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Design
OPA172, OPA2172, OPA4172
SBOS618I – DECEMBER 2013 – REVISED MAY 2018
OPAx172 36-V, Single-Supply, 10-MHz, Rail-to-Rail Output Operational Amplifiers
1 Features
3 Description
•
The OPA172, OPA2172 and OPA4172 (OPAx172)
are a family of 36-V, single-supply, low-noise
operational amplifiers capable of operating on
supplies ranging from +4.5 V (±2.25 V) to +36 V
(±18 V). This latest addition of high-voltage CMOS
operational amplifiers, in conjunction with the
OPAx171 and OPAx170, provide a family of
bandwidth, noise, and power options to meet the
needs of a wide variety of applications. The OPAx172
are available in micropackages, and offer low offset,
drift, and quiescent current. These devices also offer
wide bandwidth, fast slew rate, and high output
current drive capability. The single, dual, and quad
versions all have identical specifications for maximum
design flexibility.
1
•
•
•
•
•
•
•
•
•
•
•
•
•
Wide Supply Range:
+4.5 V to +36 V, ±2.25 V to ±18 V
Low Offset Voltage: ±0.2 mV
Low Offset Drift: ±0.3 µV/°C
Gain Bandwidth: 10 MHz
Low Input Bias Current: ±8 pA
Low Quiescent Current: 1.6 mA per Amplifier
Low Noise: 7 nV/√Hz
EMI and RFI Filtered Inputs
Input Range Includes the Negative Supply
Input Range Operates to Positive Supply
Rail-to-Rail Output
High Common-Mode Rejection: 120 dB
Industry-Standard Packages:
– SOIC-8, VSSOP-8, SOIC-14, TSSOP-14
microPackages: Single in SC70, SOT-23,
Dual in WSON-8
2 Applications
•
•
•
•
•
•
•
•
Tracking Amplifier in Power Modules
Merchant Power Supplies
Transducer Amplifiers
Bridge Amplifiers
Temperature Measurements
Strain Gauge Amplifiers
Precision Integrators
Test Equipment
Unlike most op amps, which are specified at only one
supply voltage, the OPAx172 family is specified from
+4.5 V to +36 V. Input signals beyond the supply rails
do not cause phase reversal. The input can operate
100 mV below the negative rail and within 2 V of the
top rail during normal operation. Note that these
devices can operate with full rail-to-rail input 100 mV
beyond the top rail, but with reduced performance
within 2 V of the top rail.
The OPAx172 series of op amps are specified from
–40°C to +125°C.
Device Information(1)
PART NUMBER
PACKAGE
OPA172
OPA2172
OPA4172
BODY SIZE (NOM)
SC70 (5)
2.00 mm × 1.25 mm
SOT-23 (5)
2.90 mm × 1.60 mm
SOIC (8)
4.90 mm × 3.91 mm
SOIC (8)
4.90 mm × 3.91 mm
VSSOP (8)(2)
3.00 mm × 3.00 mm
WSON (8)
3.00 mm × 3.00 mm
SOIC (14)
8.65 mm × 3.91 mm
TSSOP (14)
4.40 mm × 5.00 mm
(1) For all available packages, see the package option addendum
at the end of the data sheet.
(2) The VSSOP package is the same as the MSOP package.
JFET-Input Low-Noise Amplifier
Superior THD Performance
V1
15 V
VEE
V2
15 V
R1
3.9 kŸ
R2
3.9 kŸ
VEE
OPA172
++
LSK489
Q1
VCC
VOUT
R3
1.13 kŸ
Q2
VCC
R6
27.4 kŸ
Q3
R4
11.5 Ÿ
Total Harmonic Distortion + Noise (%)
VCC
-80
G = +1 V/V, RL = 10 k
G = +1 V/V, RL = 2 k
G = +1 V/V, RL = 600
G = -1 V/V, RL = 10 k
0.001
-100
G = -1 V/V, RL = 2 k
G = -1 V/V, RL = 600
0.0001
-120
VOUT = 3.5 VRMS
BW = 80 kHz
0.00001
MMBT4401
-140
10
Q4
MMBT4401
Total Harmonic Distortion + Noise (dB)
0.01
VCC
100
1k
Frequency (Hz)
10k
C007
R5
300 Ÿ
VEE
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
OPA172, OPA2172, OPA4172
SBOS618I – DECEMBER 2013 – REVISED MAY 2018
www.ti.com
Table of Contents
1
2
3
4
5
Features ..................................................................
Applications ...........................................................
Description .............................................................
Revision History.....................................................
Device Comparison ...............................................
1
1
1
2
4
5.1 Device Comparison................................................... 4
5.2 Device Family Comparison ....................................... 4
6
7
Pin Configuration and Functions ......................... 5
Specifications......................................................... 7
7.1
7.2
7.3
7.4
7.5
7.6
7.7
7.8
7.9
8
Absolute Maximum Ratings ..................................... 7
ESD Ratings.............................................................. 7
Recommended Operating Conditions....................... 7
Thermal Information: OPA172 .................................. 8
Thermal Information: OPA2172 ................................ 8
Thermal Information: OPA4172 ................................ 8
Electrical Characteristics........................................... 9
Typical Characteristics: Table of Graphs ................ 11
Typical Characteristics ............................................ 12
Detailed Description ............................................ 19
8.1 Overview ................................................................. 19
8.2 Functional Block Diagram ....................................... 19
8.3 Feature Description................................................. 20
8.4 Device Functional Modes........................................ 22
9
Applications and Implementation ...................... 25
9.1 Application Information............................................ 25
9.2 Typical Applications ................................................ 25
10 Power-Supply Recommendations ..................... 28
11 Layout................................................................... 29
11.1 Layout Guidelines ................................................. 29
11.2 Layout Example .................................................... 29
12 Device and Documentation Support ................. 30
12.1
12.2
12.3
12.4
12.5
12.6
12.7
Device Support......................................................
Documentation Support ........................................
Related Links ........................................................
Community Resources..........................................
Trademarks ...........................................................
Electrostatic Discharge Caution ............................
Glossary ................................................................
30
30
30
30
31
31
31
13 Mechanical, Packaging, and Orderable
Information ........................................................... 31
4 Revision History
Changes from Revision H (September 2015) to Revision I
•
Page
Changed supply voltage values within Absolute Maximum Ratings table ............................................................................. 7
Changes from Revision G (June 2015) to Revision H
Page
•
Added DRG package to OPA2172 device ............................................................................................................................ 1
•
Added WSON to last Features bullet .................................................................................................................................... 1
•
Added OPA2172 WSON row to Device Information table...................................................................................................... 1
•
Added WSON-8 to OPA2172 row of Device Comparison table ............................................................................................ 4
•
Added DRG pinout drawing ................................................................................................................................................... 6
•
Added DRG column to OPA2172 and OPA4172 Pin Functions table .................................................................................. 6
•
Added DRG column to OPA2172 Thermal Information table ................................................................................................ 8
Changes from Revision F (June 2015) to Revision G
•
Page
Added input bias current (IB) values for DGK and PW packages. ......................................................................................... 9
Changes from Revision E (December 2014) to Revision F
Page
•
Changed device status to Production Data from Mixed Status.............................................................................................. 1
•
Changed OPA2172 DGK and OPA4172 PW packages to Production Data.......................................................................... 1
•
Added OPA2172 VSSOP and OPA4172 TSSOP rows to Device Information table ............................................................. 1
•
Deleted footnote from Device Comparison table.................................................................................................................... 4
•
Deleted footnote from OPA2172 DGK and OPA4172 PW pin out drawings ........................................................................ 6
•
Added OPA2172 DGK thermal information ........................................................................................................................... 8
2
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SBOS618I – DECEMBER 2013 – REVISED MAY 2018
Changes from Revision D (September 2014) to Revision E
Page
•
Changed OPA2172 D package from product preview to production data ............................................................................. 1
•
Changed Device Information table ......................................................................................................................................... 1
•
Changed Device Comparison table note (1) to show preview packages............................................................................... 4
•
Changed Handling Ratings table to ESD Ratings table ......................................................................................................... 7
Changes from Revision C (July 2014) to Revision D
Page
•
Changed low-noise features bullet value from 6 nV/√Hz to 7 ................................................................................................ 1
•
Changed MSOP to VSSOP in features bullet ........................................................................................................................ 1
•
Added packages and new note 2 to Device Information table ............................................................................................... 1
•
Changed OPAx172 voltage noise density from 6 nV/√Hz to 7 in Device Family Comparison table ..................................... 4
•
Changed OPA4172 package from DGK to PW in Pin Functions table .................................................................................. 6
•
Added OPA2172 Thermal Information table........................................................................................................................... 8
•
Changed input voltage noise value in Electrical Characteristics from 1.2 µVPP to 2.5 µVPP .................................................. 9
•
Changed input voltage noise density value at 100 Hz in Electrical Characteristics from 8.6 nV/√Hz to 12 .......................... 9
•
Changed input voltage noise density value at 1 kHz in Electrical Characteristics from 6 nV/√Hz to 7.................................. 9
•
Changed voltage output swing values in the Electrical Characteristics ............................................................................... 10
•
Changed Figure 13 .............................................................................................................................................................. 13
•
Changed Figure 14............................................................................................................................................................... 13
•
Added new note to Applications and Implementation section ............................................................................................. 25
Changes from Revision B (May 2014) to Revision C
Page
•
Changed OPA4172 D package (SOIC-14) from product preview to production data............................................................ 1
•
Added OPA4172-D Thermal information ............................................................................................................................... 8
•
Added Channel separation parameter to the Electrical Characteristics ................................................................................. 9
•
Added Channel Separation vs Frequency plot .................................................................................................................... 17
Changes from Revision A (April 2014) to Revision B
•
Page
Changed DCK (SC70) package from product preview to production data............................................................................. 1
Changes from Original (December 2013) to Revision A
Page
•
Changed document format to meet latest data sheet standards; added Handling Ratings Recommended Operating
Conditions, and Device and Documentation Support sections, and moved existing sections............................................... 1
•
Changed DCK package pin names from IN+ and IN– to +IN and –IN, respectively ............................................................. 5
•
Changed DBV package from product preview to production data ......................................................................................... 5
•
Changed Figure 9................................................................................................................................................................. 12
•
Added Functional Block Diagram section............................................................................................................................. 19
•
Added Capacitive Load Drive Solution Using an Isolation Resistor section ........................................................................ 25
•
Added Power-Supply Recommendations section ................................................................................................................ 28
•
Changed Layout Guidelines section..................................................................................................................................... 29
Copyright © 2013–2018, Texas Instruments Incorporated
Product Folder Links: OPA172 OPA2172 OPA4172
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OPA172, OPA2172, OPA4172
SBOS618I – DECEMBER 2013 – REVISED MAY 2018
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5 Device Comparison
5.1 Device Comparison
DEVICE
PACKAGE
OPA172 (single)
SC70-5, SOT-23-5, SOIC-8
OPA2172 (dual)
SOIC-8, VSSOP-8, WSON-8
OPA4172 (quad)
SOIC-14, TSSOP-14
5.2 Device Family Comparison
4
DEVICE
QUIESCENT CURRENT
(IQ)
OPAx172
1600 µA
10 MHz
7 nV/√Hz
OPAx171
475 µA
3.0 MHz
14 nV/√Hz
OPAx170
110 µA
1.2 MHz
19 nV/√Hz
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GAIN BANDWIDTH PRODUCT
(GBP)
VOLTAGE NOISE DENSITY
(en)
Copyright © 2013–2018, Texas Instruments Incorporated
Product Folder Links: OPA172 OPA2172 OPA4172
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SBOS618I – DECEMBER 2013 – REVISED MAY 2018
6 Pin Configuration and Functions
DCK Package: OPA172
SC70-5
Top View
+IN
1
V-
2
-IN
3
D Package: OPA172
SOIC-8
Top View
V+
5
DBV Package: OPA172
SOT-23-5
Top View
1
V-
2
+IN
3
1
8
NC(1)
-IN
2
7
V+
+IN
3
6
OUT
V-
4
5
NC(1)
OUT
4
OUT
NC(1)
5
V+
4
-IN
(1)
No internal connection.
Pin Functions: OPA172
PIN
OPA172
NAME
D (SOIC)
DBV (SOT)
DCK (SC70)
I/O
+IN
3
3
1
I
Noninverting input
DESCRIPTION
–IN
2
4
3
I
Inverting input
NC
1, 5, 8
—
—
—
No internal connection
OUT
6
1
4
O
Output
V+
7
5
5
—
Positive (highest) power supply
V–
4
2
2
—
Negative (lowest) power supply
Copyright © 2013–2018, Texas Instruments Incorporated
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OPA172, OPA2172, OPA4172
SBOS618I – DECEMBER 2013 – REVISED MAY 2018
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D and DGK Packages: OPA2172
SOIC-8 and VSSOP-8
Top View
OUT A
1
8
V+
-IN A
2
7
OUT B
+IN A
3
6
-IN B
V-
4
5
+IN B
D and PW Packages: OPA4172
SO-14 and TSSOP-14
Top View
DRG Package: OPA2172
WSON-8
Top View
+IN A 1
A
V+ 2
V- 3
8
-IN A
7
OUT A
6
OUT B
5
-IN B
OUT A
1
14
OUT D
-IN A
2
13
-IN D
+IN A
3
12
+IN D
V+
4
11
V-
+IN B
5
10
+IN C
-IN B
6
9
-IN C
OUT B
7
8
OUT C
B
+IN B 4
Pin Functions: OPA2172 and OPA4172
PIN
OPA2172
NAME
+IN A
OPA4172
D (SOIC),
DGK
(VSSOP)
DRG
(WSON)
D (SOIC),
PW (TSSOP)
I/O
3
1
3
I
Noninverting input, channel A
DESCRIPTION
+IN B
5
4
5
I
Noninverting input, channel B
+IN C
—
—
10
I
Noninverting input, channel C
+IN D
—
—
12
I
Noninverting input, channel D
–IN A
2
8
2
I
Inverting input, channel A
–IN B
6
5
6
I
Inverting input, channel B
–IN C
—
—
9
I
Inverting input,,channel C
–IN D
—
—
13
I
Inverting input, channel D
OUT A
1
7
1
O
Output, channel A
OUT B
7
6
7
O
Output, channel B
OUT C
—
—
8
O
Output, channel C
OUT D
—
—
14
O
Output, channel D
V+
8
2
4
—
Positive (highest) power supply
V–
4
3
11
—
Negative (lowest) power supply
6
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SBOS618I – DECEMBER 2013 – REVISED MAY 2018
7 Specifications
7.1 Absolute Maximum Ratings (1)
over operating free-air temperature range (unless otherwise noted)
MIN
MAX
Supply voltage, [(V+) – (V-)]
Voltage (2)
Signal input pins
Signal input pins
Output short circuit
Common-mode
(V–) – 0.5
±10
mA
+150
°C
+150
°C
+150
°C
Continuous
–55
Junction temperature, TJ
Storage temperature, Tstg
(2)
(3)
(4)
V
±0.5
Current
(4)
V
(V+) + 0.5
Differential (3)
Operating temperature
(1)
UNIT
40
–65
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
Transient conditions that exceed these voltage ratings must be current limited to 10 mA or less.
Refer to the Electrical Overstress section for more information.
Short-circuit to ground, one amplifier per package.
7.2 ESD Ratings
VALUE
V(ESD)
(1)
(2)
Electrostatic discharge
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001 (1)
±4000
Charged-device model (CDM), per JEDEC specification JESD22-C101 (2)
±1000
UNIT
V
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
7.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
Supply voltage (V+ – V–)
Specified temperature
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MIN
MAX
4.5 (±2.25)
36 (±18)
UNIT
V
–40
125
°C
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7
OPA172, OPA2172, OPA4172
SBOS618I – DECEMBER 2013 – REVISED MAY 2018
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7.4 Thermal Information: OPA172
OPA172
THERMAL METRIC (1)
D (SOIC)
DBV (SOT-23)
DCK (SC70)
8 PINS
5 PINS
5 PINS
UNIT
RθJA
Junction-to-ambient thermal resistance
126.5
227.9
285.2
°C/W
RθJC(top)
Junction-to-case(top) thermal resistance
80.6
115.7
60.5
°C/W
RθJB
Junction-to-board thermal resistance
67.1
65.9
78.9
°C/W
ψJT
Junction-to-top characterization parameter
31.0
10.7
0.8
°C/W
ψJB
Junction-to-board characterization parameter
66.6
65.3
77.9
°C/W
RθJC(bot)
Junction-to-case(bottom) thermal resistance
N/A
N/A
N/A
°C/W
(1)
For more information about traditional and new thermal metrics, see the Semiconductor and IC package Thermal Metrics application
report.
7.5 Thermal Information: OPA2172
OPA2172
THERMAL METRIC (1)
D (SOIC)
DGK (VSSOP)
DRG (WSON)
UNIT
8 PINS
8 PINS
8 PINS
RθJA
Junction-to-ambient thermal resistance
116.1
158
63.2
°C/W
RθJC(top)
Junction-to-case (top) thermal resistance
69.8
48.6
63.5
°C/W
RθJB
Junction-to-board thermal resistance
56.6
78.7
36.5
°C/W
ψJT
Junction-to-top characterization parameter
22.5
3.9
1.4
°C/W
ψJB
Junction-to-board characterization parameter
56.1
77.3
36.6
°C/W
RθJC(bot)
Junction-to-case (bottom) thermal resistance
N/A
N/A
6.3
°C/W
(1)
For more information about traditional and new thermal metrics, see the Semiconductor and IC package Thermal Metrics application
report.
7.6 Thermal Information: OPA4172
OPA4172
THERMAL METRIC (1)
D (SOIC)
PW (TSSOP)
UNIT
14 PINS
14 PINS
RθJA
Junction-to-ambient thermal resistance
82.7
111.1
°C/W
RθJC(top)
Junction-to-case (top) thermal resistance
42.3
40.8
°C/W
RθJB
Junction-to-board thermal resistance
37.3
54.1
°C/W
ψJT
Junction-to-top characterization parameter
8.9
3.8
°C/W
ψJB
Junction-to-board characterization parameter
37
53.3
°C/W
RθJC(bot)
Junction-to-case (bottom) thermal resistance
N/A
N/A
°C/W
(1)
8
For more information about traditional and new thermal metrics, see the Semiconductor and IC package Thermal Metrics application
report.
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SBOS618I – DECEMBER 2013 – REVISED MAY 2018
7.7 Electrical Characteristics
At TA = +25°C, VS = ±2.25 V to ±18 V, VCM = VOUT = VS / 2, and RL = 10 kΩ connected to VS / 2 (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
OFFSET VOLTAGE
±0.2
VOS
Input offset voltage
dVOS/dT
Drift
PSRR
vs power supply
TA = –40°C to +125°C
Channel separation, dc
At dc
±1
mV
TA = –40°C to +125°C
±1.15
OPA172, OPA4172
TA = –40°C to +125°C
±0.3
±1.5
µV/°C
OPA2172
±1.8
±1
±3
µV/V
5
µV/V
INPUT BIAS CURRENT
±8
IB
Input bias current
TA = –40°C to +125°C
pA
±14
OPA2172IDGK
TA = –40°C to +125°C
nA
±18
OPA41721PW
±2
IOS
±15
Input offset current
TA = –40°C to +125°C
±15
OPA172, OPA4172
±1
OPA2172
±3
pA
nA
NOISE
En
Input voltage noise
en
Input voltage noise density
in
Input current noise density
f = 0.1 Hz to 10 Hz
2.5
f = 100 Hz
12
µVPP
nV/√Hz
f = 1 kHz
7
f = 1 kHz
1.6
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fA/√Hz
9
OPA172, OPA2172, OPA4172
SBOS618I – DECEMBER 2013 – REVISED MAY 2018
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Electrical Characteristics (continued)
At TA = +25°C, VS = ±2.25 V to ±18 V, VCM = VOUT = VS / 2, and RL = 10 kΩ connected to VS / 2 (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
INPUT VOLTAGE
Common-mode voltage range (1)
VCM
CMRR
Common-mode rejection ratio
(V–) – 0.1 V
VS = ±2.25 V, (V–) – 0.1 V < VCM < (V+) – 2 V,
TA = –40°C to +125°C
(V+) – 2 V
90
104
110
120
V
dB
VS = ±18 V, (V–) – 0.1 V < VCM < (V+) – 2 V,
TA = –40°C to +125°C
INPUT IMPEDANCE
Differential
100 || 4
Common-mode
MΩ || pF
6 || 4
1013Ω || pF
OPEN-LOOP GAIN
AOL
(V–) + 0.35 V < VO < (V+) – 0.35 V, RL =
10 kΩ, TA = –40°C to +125°C
OPA172, OPA4172
110
130
OPA2172
107
115
(V–) + 0.5 V < VO < (V+) – 0.5 V,
RL = 2 kΩ, TA = –40°C to +125°C
OPA172, OPA4172
116
OPA2172
107
Open-loop voltage gain
dB
FREQUENCY RESPONSE
GBP
Gain bandwidth product
SR
Slew rate
tS
Settling time
G = +1
To 0.1%, VS = ±18 V, G = +1, 10-V step
MHz
10
V/µs
2
µs
To 0.01% (12 bit), VS = ±18 V, G = +1, 10-V step
THD+N
10
Overload recovery time
VIN × Gain > VS
Total harmonic distortion + noise
VS = +36 V, G = +1, f = 1 kHz, VO = 3.5 VRMS
3.2
200
ns
0.00005%
OUTPUT
VS = +36 V
VS = +36 V,
TA = –40°C to +125°C
VO
Voltage output swing from rail
VS = +4.5V
VS = +4.5 V,
TA = –40°C to +125°C
ISC
Short-circuit current
CLOAD
Capacitive load drive
ZO
Open-loop output impedance
RL = 10 kΩ
70
90
RL = 2 kΩ
330
400
RL = 10 kΩ
95
120
RL = 2 kΩ
470
530
RL = 10 kΩ
10
20
RL = 2 kΩ
40
50
RL = 10 kΩ
10
25
RL = 2 kΩ
55
70
mV
±75
mA
See Typical Characteristics
f = 1 MHz, IO = 0 A
pF
60
Ω
POWER SUPPLY
VS
IQ
Specified voltage range
Quiescent current per amplifier
+4.5
IO = 0 A
+36
1.6
V
1.8
mA
IO = 0 A, TA = –40°C to +125°C
2
TEMPERATURE
Specified range
(1)
10
–40
+125
°C
The input range can be extended beyond (V+) – 2 V up to (V+) + 0.1 V. For additional information, see the Typical Characteristics and
Application Information sections.
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7.8 Typical Characteristics: Table of Graphs
Table 1. List of Typical Characteristics
DESCRIPTION
FIGURE
Offset Voltage Production Distribution
Figure 1
Offset Voltage Drift Distribution
Figure 2
Offset Voltage vs Temperature (VS = ±18 V)
Figure 3
Offset Voltage vs Common-Mode Voltage (VS = ±18 V)
Figure 4
Offset Voltage vs Common-Mode Voltage (Upper Stage)
Figure 5
Offset Voltage vs Power Supply
Figure 6
IB vs Common-Mode Voltage
Figure 7
Input Bias Current vs Temperature
Figure 8
Output Voltage Swing vs Output Current (Maximum Supply)
Figure 9
CMRR and PSRR vs Frequency (Referred-to Input)
Figure 10
CMRR vs Temperature
Figure 11
PSRR vs Temperature
Figure 12
0.1-Hz to 10-Hz Noise
Figure 13
Input Voltage Noise Spectral Density vs Frequency
Figure 14
THD+N Ratio vs Frequency
Figure 15
THD+N vs Output Amplitude
Figure 16
Quiescent Current vs Temperature
Figure 17
Quiescent Current vs Supply Voltage
Figure 18
Open-Loop Gain and Phase vs Frequency
Figure 19
Closed-Loop Gain vs Frequency
Figure 20
Open-Loop Gain vs Temperature
Figure 21
Open-Loop Output Impedance vs Frequency
Figure 22
Small-Signal Overshoot vs Capacitive Load (100-mV Output Step)
Figure 23, Figure 24
Positive Overload Recovery
Figure 25, Figure 26
Negative Overload Recovery
Figure 27, Figure 28
Small-Signal Step Response (10 mV)
Figure 29, Figure 30
Small-Signal Step Response (100 mV)
Figure 31, Figure 32
Large-Signal Step Response (1 V)
Figure 33, Figure 34
Large-Signal Settling Time (10-V Positive Step)
Figure 35
Large-Signal Settling Time (10-V Negative Step)
Figure 36
No Phase Reversal
Figure 37
Short-Circuit Current vs Temperature
Figure 38
Maximum Output Voltage vs Frequency
Figure 39
EMIRR vs Frequency
Figure 40
Channel Separation vs Frequency
Figure 41
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7.9 Typical Characteristics
At VS = ±18 V, VCM = VS / 2, RLOAD = 10 kΩ connected to VS / 2, and CL = 100 pF, unless otherwise noted.
25
Distribution Taken From 47 Amplifiers
Offset Voltage Drift (µV/ƒC)
Offset Voltage (mV)
C013
C013
Figure 1. Offset Voltage Production Distribution
Figure 2. Offset Voltage Drift Production Distribution
250
225
5 Typical Units Shown
VS = ±18 V
200
100
VOS ( V)
0
±50
VCM =16V
VCM = -18.1V
75
50
VOS ( V)
5 Typical Units Shown
VS = ±18 V
150
150
0
±75
±100
±150
±150
±200
±250
±75
±50
±25
±225
0
25
50
75
100
125
Temperature (ƒC)
150
±20
±15
±10
0
±5
5
10
15
VCM (V)
C001
Figure 3. Offset Voltage vs Temperature
(VS = ±18 V)
20
C001
Figure 4. Offset Voltage vs Common-Mode Voltage
(VS = ±18 V)
500
20
5 Typical Units Shown
VS = ±18 V
10
400
Vs = ±2.25V
300
0
5 Typical Units Shown
VS = ±2.25V to “18V
200
VOS ( V)
VOS (mV)
1.00
0.90
0.80
0.70
0.60
0.50
0.40
5
0
1.00
0.80
0.60
0.40
0.20
0.00
-0.20
-0.40
-0.60
0
-0.80
5
10
0.30
10
15
0.20
15
Temperature = -40ƒC to 125ƒC
20
0.10
20
0.00
Percentage of Amplifiers (%)
Distribution Taken From 5185 Amplifiers
-1.00
Percentage of Amplifiers (%)
25
-10
-20
100
0
±100
±200
-30
±300
-40
±400
±500
-50
14
15
16
VCM (V)
17
18
Figure 5. Offset Voltage vs Common-Mode Voltage
(Upper Stage)
12
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0.0
2.0
4.0
6.0
8.0
10.0 12.0 14.0 16.0 18.0
VSUPPLY (V)
C001
C001
Figure 6. Offset Voltage vs Power Supply
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Typical Characteristics (continued)
At VS = ±18 V, VCM = VS / 2, RLOAD = 10 kΩ connected to VS / 2, and CL = 100 pF, unless otherwise noted.
12
8000
8
6
IbN
4
2
0
±2
6000
Input Bias Current (pA)
Input Bias Current (pA)
IB+
IB Ios
IbP
10
4000
2000
0
Ios
TA = 25°C
±4
±18.0 ±13.5
±2000
±9.0
0.0
±4.5
4.5
9.0
13.5
VCM (V)
±50
18.0
25
50
75
100
125
150
C001
Figure 8. Input Bias Current vs Temperature
160.0
Common-Mode Rejection Ratio (dB),
Power-Supply Rejection Ratio (dB)
Output Voltage (V)
0
Temperature (ƒC)
Figure 7. Input Bias Current vs Common-Mode Voltage
(V+) +1
(V+)
(V+) -1
(V+) -2
(V+) -3
(V+) -4
(V+) -5
(V-) +5
(V-) +4
(V-) +3
(V-) +2
(V-) +1
(V-)
(V-) -1
25ƒC
±40ƒC
125ƒC
85ƒC
85ƒC
125ƒC
±40ƒC
25ƒC
140.0
120.0
100.0
80.0
60.0
+PSRR
40.0
-PSRR
20.0
CMRR
0.0
0
10
20
30
40
50
60
70
80
90
Output Current (mA)
100
1
10
100
1k
10k
100k
Frequency (Hz)
C011
Figure 9. Output Voltage Swing vs Output Current
(Maximum Supply)
1M
C012
Figure 10. CMRR and PSRR vs Frequency
(Referred-To-Input)
30
10
20
9 ” 9CM ”
VS = ±2.25V, -
Power-Supply Rejection Ratio (µV/V)
Common-Mode Rejection Ratio (µV/V)
±25
C001
9
10
0
VS = “18 V, -
9 ” 9CM ”
9
±10
8
6
4
2
0
±2
±75
±50
±25
0
25
50
75
100
Temperature (ƒC)
Figure 11. CMRR vs Temperature
125
150
±75
±50
±25
0
25
50
75
100
125
Temperature (ƒC)
C001
150
C001
Figure 12. PSRR vs Temperature
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Typical Characteristics (continued)
500 nV/div
Noise Spectral Density (nV/rtHz)
At VS = ±18 V, VCM = VS / 2, RLOAD = 10 kΩ connected to VS / 2, and CL = 100 pF, unless otherwise noted.
100
10
1
Time (1 s/div)
1
10
100
Figure 13. 0.1-Hz to 10-Hz Noise
G = -1 V/V, RL = 10 k
-100
G = -1 V/V, RL = 2 k
G = -1 V/V, RL = 600
0.0001
-120
VOUT = 3.5 VRMS
BW = 80 kHz
0.00001
-140
1k
10k
Frequency (Hz)
0.1
Total Harmonic Distortion + Noise (%)
Total Harmonic Distortion + Noise (%)
G = +1 V/V, RL = 600
100
100k
C001
-60
G = +1 V/V, RL = 10 k
G = +1 V/V, RL = 2 k
G = +1 V/V, RL = 600
G = -1 V/V, RL = 10 k
G = -1 V/V, RL = 2 k
G = -1 V/V, RL = 600
0.01
-80
0.001
-100
0.0001
-120
f = 1 kHz
BW = 80 kHz
0.00001
0.01
0.1
-140
1
10
Output Amplitude (VRMS)
C007
Figure 15. THD+N Ratio vs Frequency
Total Harmonic Distortion + Noise (dB)
G = +1 V/V, RL = 2 k
Total Harmonic Distortion + Noise (dB)
-80
G = +1 V/V, RL = 10 k
10
10k
Figure 14. Input Voltage Noise Spectral Density vs
Frequency
0.01
0.001
1k
Frequency (Hz)
C002
C008
Figure 16. THD+N vs Output Amplitude
2.0
1.8
1.7
1.8
1.6
1.5
IQ (mA)
IQ (mA)
Vs = ±18V
1.6
Vs = ±2.25V
1.4
1.3
1.4
1.2
1.1
1.2
1.0
±75
±50
±25
0
25
50
75
100
125
Temperature (ƒC)
Figure 17. Quiescent Current vs Temperature
14
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150
0
4
8
12
16
20
24
28
32
Supply Voltage (V)
C001
36
C001
Figure 18. Quiescent Current vs Supply Voltage
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Typical Characteristics (continued)
At VS = ±18 V, VCM = VS / 2, RLOAD = 10 kΩ connected to VS / 2, and CL = 100 pF, unless otherwise noted.
180
140
25.0
CLOAD = 15 pF
20.0
120
15.0
135
Open-Loop Gain
Phase
60
90
40
Gain (dB)
10.0
80
Phase (ƒ)
Gain (dB)
100
5.0
0.0
±5.0
20
45
±10.0
0
G = +1
G = -10
G = -1
±15.0
±20
0
1
10
100
1k
10k
100k
1M
±20.0
1000
10M
Frequency (Hz)
100k
1M
10M
Frequency (Hz)
Figure 19. Open-Loop Gain and Phase vs Frequency
C003
Figure 20. Closed-Loop Gain vs Frequency
1000
2.0
1.5
AOL (µV/V)
10k
C004
100
ZO ( )
1.0
Vs = 4.5 V
10
0.5
Vs = 36 V
1
0.0
RL = 10kŸ
±0.5
±75
±50
0
±25
0
25
50
75
100
125
Temperature (ƒC)
RI = 1 k
+
1M
10M
100M
C016
Figure 22. Open-Loop Output Impedance vs Frequency
G = +1
ROUT
OPA172
40
CL
± 18 V
40
Overshoot (%)
Overshoot (%)
100k
G = -1
+
±
10k
50
±
VIN = 100mV
1k
Frequency (Hz)
RF = 1 k
+ 18 V
50
100
C001
Figure 21. Open-Loop Gain vs Temperature
60
10
150
30
20
20
+ 18 V
ROUT = 0
10
30
ROUT= 0
10
R
25
RO
OUT==25
±
ROUT
OPA172
R
RO
= 25
25
OUT=
+
VIN = 100mV
+
RL
CL
± 18 V
±
R
50
RO
OUT==50
0
0p
100p
200p
300p
Capacitive Load (F)
400p
RO
= 50
50
R
OUT=
0
500p
0p
100p
Figure 23. Small-Signal Overshoot vs Capacitive Load
(100-mV Output Step)
200p
300p
400p
Capacitive Load (F)
C013
500p
C013
Figure 24. Small-Signal Overshoot vs Capacitive Load
(100-mV Output Step)
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Typical Characteristics (continued)
At VS = ±18 V, VCM = VS / 2, RLOAD = 10 kΩ connected to VS / 2, and CL = 100 pF, unless otherwise noted.
RI = 1 k
RF = 10 k
+ 18 V
±
+
OPA172
VIN = 2V
VOUT
+
±
VOUT
± 18 V
5 V/div
5 V/div
RI = 1 k
VOUT
RF = 10 k
+ 18 V
±
+
OPA172
VIN = 2V
VOUT
+
±
± 18 V
VIN
VIN
Time (1 s/div)
Time (1 s/div)
C009
Figure 25. Positive Overload Recovery
C009
Figure 26. Positive Overload Recovery (Zoomed In)
VIN
RI = 1 k
VIN
RF = 10 k
5 V/div
5 V/div
+ 18 V
VOUT
RI = 1 k
±
+
OPA172
VIN = 2V
VOUT
+
±
± 18 V
RF = 10 k
+ 18 V
VOUT
±
+
OPA172
VIN = 2V
VOUT
+
±
± 18 V
Time (1 s/div)
Time (1 s/div)
C010
Figure 27. Negative Overload Recovery
C010
Figure 28. Negative Overload Recovery (Zoomed In)
RL
NŸ
CL = 10pF
+ 18 V
CL = 10pF
±
OPA172
+
VIN = 10mV
+
CL
± 18 V
2 mV/div
2 mV/div
±
RI = 1 k
RF = 1 k
+ 18 V
+
VIN = 10mV
±
OPA172
+
±
RL
CL
± 18 V
Time (200 ns/div)
Time (200 ns/div)
C006
Figure 29. Small-Signal Step Response (10 mV, G = –1)
16
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C014
Figure 30. Small-Signal Step Response (10 mV, G = +1)
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Typical Characteristics (continued)
At VS = ±18 V, VCM = VS / 2, RLOAD = 10 kΩ connected to VS / 2, and CL = 100 pF, unless otherwise noted.
+ 18 V
CL = 10pF
RL
NŸ
CL = 10pF
±
OPA172
+
+
VIN = 100mV
20 mV/div
20 mV/div
CL
± 18 V
±
RI = 1 k
RF = 1 k
+ 18 V
±
+
OPA172
VIN = 100mV
+
±
RL
CL
± 18 V
Time (200 ns/div)
Time (200 ns/div)
C006
Figure 31. Small-Signal Step Response (100 mV, G = –1)
C014
Figure 32. Small-Signal Step Response (100 mV, G = +1)
RL
NŸ
CL = 10 pF
+ 18 V
CL = 10pF
±
OPA172
+
+
VIN = 10V
2 V/div
2 V/div
CL
± 18 V
±
RI = 1 k
RF = 1 k
+ 18 V
±
+
OPA172
VIN = 10V
+
±
RL
CL
± 18 V
Time (500 ns/div)
Time (500 ns/div)
C014
Figure 33. Large-Signal Step Response (10 V, G = –1)
Figure 34. Large-Signal Step Response (10 V, G = +1)
20
20
G = +1
CL = 10 pF
15
Output Delta from Final Value (mV)
Output Delta from Final Value (mV)
C005
10
5
0
-5
0.1% Settling = ±10 mV
-10
-15
-20
G = +1
CL = 10 pF
15
10
5
0
-5
0.1% Settling = ±10 mV
-10
-15
-20
0
0.5
1
1.5
2
2.5
3
3.5
Time ( s)
4
4.5
5
0
0.5
1
Figure 35. Large-Signal Settling Time (10-V Positive Step)
1.5
2
2.5
3
3.5
4
4.5
Time ( s)
C034
5
C034
Figure 36. Large-Signal Settling Time (10-V Negative Step)
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Typical Characteristics (continued)
At VS = ±18 V, VCM = VS / 2, RLOAD = 10 kΩ connected to VS / 2, and CL = 100 pF, unless otherwise noted.
100
+ 18 V
±
+
±
37 VPP ± 18 V
Sine Wave
(±18.5V)
VOUT
VOUT
OPA172
+
75
ISC (mA)
5 V/div
ISC, Sink “18V
50
ISC, Source ±18V
25
VIN
0
Time (200 s/div)
±75
±50
±25
0
Figure 37. No Phase Reversal
50
75
100
125
150
C001
Figure 38. Short-Circuit Current vs Temperature
160.0
30
VS = ±15 V
EMIRR IN+ (dB)
120.0
20
15
VS = ±5 V
10
100.0
80.0
60.0
40.0
VS = ±2.25 V
5
PRF = -10 dBm
VSUPPLY = ±18 V
VCM = 0 V
140.0
Maximum output voltage without
slew-rate induced distortion.
25
Output Voltage (VPP)
25
Temperature (ƒC)
C011
20.0
0
0.0
10k
100k
1M
10M
Frequency (Hz)
10M
100M
1G
Frequency (Hz)
C033
Figure 39. Maximum Output Voltage vs Frequency
10G
C017
Figure 40. EMIRR vs Frequency
Channel Separation (dB)
0
±20
±40
±60
±80
±100
±120
10
100
1k
10k
100k
1M
Frequency (Hz)
10M
C041
Figure 41. Channel Separation vs Frequency
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8 Detailed Description
8.1 Overview
The OPAx172 family of operational amplifiers provide high overall performance, making them ideal for many
general-purpose applications. The excellent offset drift of only 1.5 µV/°C (max) provides excellent stability over
the entire temperature range. In addition, the device offers very good overall performance with high CMRR,
PSRR, AOL, and superior THD.
The Functional Block Diagram section shows the simplified diagram of the OPA172 design. The design topology
is a highly-optimized, three-stage amplifier with an active-feedforward gain stage.
8.2 Functional Block Diagram
OPA172
PCH
FF Stage
Ca
Cb
+IN
PCH
Input Stage
2nd Stage
Output
Stage
OUT
-IN
NCH
Input Stage
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8.3 Feature Description
8.3.1 EMI Rejection
The OPAx172 uses integrated electromagnetic interference (EMI) filtering to reduce the effects of EMI from
sources such as wireless communications and densely-populated boards with a mix of analog signal chain and
digital components. EMI immunity can be improved with circuit design techniques; the OPAx172 benefits from
these design improvements. Texas Instruments has developed the ability to accurately measure and quantify the
immunity of an operational amplifier over a broad frequency spectrum extending from 10 MHz to 6 GHz.
Figure 42 shows the results of this testing on the OPAx172. Table 2 shows the EMIRR IN+ values for the
OPAx172 at particular frequencies commonly encountered in real-world applications. Applications listed in
Table 2 can be centered on or operated near the particular frequency shown. Detailed information can also be
found in Application Report SBOA128, EMI Rejection Ratio of Operational Amplifiers, available for download
from www.ti.com.
160.0
140.0
PRF = -10 dBm
VSUPPLY = ±18 V
VCM = 0 V
EMIRR IN+ (dB)
120.0
100.0
80.0
60.0
40.0
20.0
0.0
10M
100M
1G
10G
Frequency (Hz)
C017
Figure 42. EMIRR Testing
Table 2. OPAx172 EMIRR IN+ for Frequencies of Interest
FREQUENCY
20
APPLICATION OR ALLOCATION
EMIRR IN+
400 MHz
Mobile radio, mobile satellite, space operation, weather, radar, ultrahigh frequency (UHF)
applications
47.6 dB
900 MHz
Global system for mobile communications (GSM) applications, radio communication, navigation,
GPS (to 1.6 GHz), GSM, aeronautical mobile, UHF applications
58.5 dB
1.8 GHz
GSM applications, mobile personal communications, broadband, satellite, L-band (1 GHz to 2 GHz)
2.4 GHz
802.11b, 802.11g, 802.11n, Bluetooth®, mobile personal communications, industrial, scientific and
medical (ISM) radio band, amateur radio and satellite, S-band (2 GHz to 4 GHz)
69.2 dB
3.6 GHz
Radiolocation, aero communication and navigation, satellite, mobile, S-band
82.9 dB
5.0 GHz
802.11a, 802.11n, aero communication and navigation, mobile communication, space and satellite
operation, C-band (4 GHz to 8 GHz)
114 dB
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68 dB
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8.3.2 Phase-Reversal Protection
The OPAx172 family has internal phase-reversal protection. Many op amps exhibit a phase reversal when the
input is driven beyond the linear common-mode range. This condition is most often encountered in noninverting
circuits when the input is driven beyond the specified common-mode voltage range, causing the output to
reverse into the opposite rail. The input of the OPAx172 prevents phase reversal with excessive common-mode
voltage. Instead, the appropriate rail limits the output voltage. This performance is shown in Figure 43.
+ 18 V
±
±
37 VPP ± 18 V
Sine Wave
(±18.5V)
5 V/div
+
VOUT
VOUT
OPA172
+
VIN
Time (200 s/div)
C011
Figure 43. No Phase Reversal
8.3.3 Capacitive Load and Stability
The dynamic characteristics of the OPAx172 are optimized for commonly-used operating conditions. The
combination of low closed-loop gain and high capacitive loads decreases the phase margin of the amplifier and
may lead to gain peaking or oscillations. As a result, heavier capacitive loads must be isolated from the output.
The simplest way to achieve this isolation is to add a small resistor (for example, ROUT = 50 Ω) in series with the
output. Figure 44 and Figure 45 show graphs of small-signal overshoot versus capacitive load for several values
of ROUT. Refer to Application Bulletin SBOA015 (AB-028), Feedback Plots Define Op Amp AC Performance,
available for download from www.ti.com, for details of analysis techniques and application circuits.
60
RI = 1 k
50
RF = 1 k
50
±
+
ROUT
OPA172
VIN = 100mV
40
+
±
CL
± 18 V
40
Overshoot (%)
Overshoot (%)
G = +1
G = -1
+ 18 V
30
20
20
+ 18 V
ROUT = 0
10
30
ROUT= 0
10
R
25
RO
OUT==25
±
ROUT
OPA172
R
RO
= 25
25
OUT=
+
VIN = 100mV
+
RL
CL
± 18 V
±
R
50
RO
OUT==50
0
0p
100p
200p
300p
Capacitive Load (F)
400p
RO
= 50
50
R
OUT=
0
500p
0p
100p
Figure 44. Small-Signal Overshoot vs Capacitive Load
(100-mV Output Step)
200p
300p
400p
Capacitive Load (F)
C013
500p
C013
Figure 45. Small-Signal Overshoot vs Capacitive Load
(100-mV Output Step)
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8.4 Device Functional Modes
8.4.1 Common-Mode Voltage Range
The input common-mode voltage range of the OPAx172 series extends 100 mV below the negative rail and
within 2 V of the top rail for normal operation.
This device can operate with full rail-to-rail input 100 mV beyond the top rail, but with reduced performance within
2 V of the top rail. The typical performance in this range is summarized in Table 3.
Table 3. Typical Performance Range (VS = ±18 V)
PARAMETER
MIN
Input Common-Mode Voltage
TYP
(V+) – 2
MAX
(V+) + 0.1
Offset voltage
UNIT
V
5
mV
Offset voltage vs temperature (TA = –40°C to +125°C)
10
µV/°C
Common-mode rejection
70
dB
Open-loop gain
60
dB
4
MHz
Gain bandwidth product (GBP)
Slew rate
Noise at f = 1 kHz
4
V/µs
22
nV/√Hz
8.4.2 Electrical Overstress
Designers often ask questions about the capability of an operational amplifier to withstand electrical overstress.
These questions tend to focus on the device inputs, but may involve the supply voltage terminals or even the
output terminal. Each of these different terminal functions have electrical stress limits determined by the voltage
breakdown characteristics of the particular semiconductor fabrication process and specific circuits connected to
the terminal. Additionally, internal electrostatic discharge (ESD) protection is built into these circuits to protect
them from accidental ESD events both before and during product assembly.
A good understanding of this basic ESD circuitry and its relevance to an electrical overstress event is helpful.
Figure 46 illustrates the ESD circuits contained in the OPAx172 (indicated by the dashed line area). The ESD
protection circuitry involves several current-steering diodes connected from the input and output terminals and
routed back to the internal power-supply lines, where the diodes meet at an absorption device internal to the
operational amplifier. This protection circuitry is intended to remain inactive during normal circuit operation.
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TVS
+
±
RF
+VS
R1
IN±
RS
IN+
2.5 NŸ
2.5 NŸ
+
Power-Supply
ESD Cell
ID
VIN
RL
+
±
+
±
±VS
TVS
Figure 46. Equivalent Internal ESD Circuitry Relative to a Typical Circuit Application
An ESD event produces a short-duration, high-voltage pulse that is transformed into a short-duration, highcurrent pulse while discharging through a semiconductor device. The ESD protection circuits are designed to
provide a current path around the operational amplifier core to prevent damage. The energy absorbed by the
protection circuitry is then dissipated as heat.
When an ESD voltage develops across two or more amplifier device terminals, current flows through one or more
steering diodes. Depending on the path that the current takes, the absorption device may activate. The
absorption device has a trigger, or threshold voltage, that is above the normal operating voltage of the OPAx172
but below the device breakdown voltage level. When this threshold is exceeded, the absorption device quickly
activates and clamps the voltage across the supply rails to a safe level.
When the operational amplifier connects into a circuit (as shown in Figure 46), the ESD protection components
are intended to remain inactive and do not become involved in the application circuit operation. However,
circumstances may arise where an applied voltage exceeds the operating voltage range of a given terminal. If
this condition occurs, there is a risk that some internal ESD protection circuits can turn on and conduct current.
Any such current flow occurs through steering-diode paths and rarely involves the absorption device.
Figure 46 shows a specific example where the input voltage (VIN) exceeds the positive supply voltage (+VS) by
500 mV or more. Much of what happens in the circuit depends on the supply characteristics. If +VS can sink the
current, one of the upper input steering diodes conducts and directs current to +VS. Excessively high current
levels can flow with increasingly higher VIN. As a result, the data sheet specifications recommend that
applications limit the input current to 10 mA.
If the supply is not capable of sinking the current, VIN can begin sourcing current to the operational amplifier, and
then take over as the source of positive supply voltage. The danger in this case is that the voltage can rise to
levels that exceed the operational amplifier absolute maximum ratings.
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Another common question involves what happens to the amplifier if an input signal is applied to the input while
the power supplies +VS or –VS are at 0 V. Again, this question depends on the supply characteristic while at 0 V,
or at a level below the input-signal amplitude. If the supplies appear as high impedance, then the input source
supplies the operational amplifier current through the current-steering diodes. This state is not a normal bias
condition; most likely, the amplifier will not operate normally. If the supplies are low impedance, then the current
through the steering diodes can become quite high. The current level depends on the ability of the input source
to deliver current, and any resistance in the input path.
If there is any uncertainty about the ability of the supply to absorb this current, add external zener diodes to the
supply terminals; see Figure 46. Select the zener voltage so that the diode does not turn on during normal
operation. However, the zener voltage must be low enough so that the zener diode conducts if the supply
terminal begins to rise above the safe-operating, supply-voltage level.
The OPAx172 input terminals are protected from excessive differential voltage with back-to-back diodes; see
Figure 46. In most circuit applications, the input protection circuitry has no effect. However, in low-gain or G = 1
circuits, fast-ramping input signals can forward-bias these diodes because the output of the amplifier cannot
respond rapidly enough to the input ramp. If the input signal is fast enough to create this forward-bias condition,
limit the input signal current to 10 mA or less. If the input signal current is not inherently limited, an input series
resistor can be used to limit the input signal current. This input series resistor degrades the low-noise
performance of the OPAx172. Figure 46 illustrates an example configuration that implements a current-limiting
feedback resistor.
8.4.3 Overload Recovery
Overload recovery is defined as the time it takes for the op amp output to recover from the saturated state to the
linear state. The output devices of the op amp enter the saturation region when the output voltage exceeds the
rated operating voltage, either due to the high input voltage or the high gain. After the device enters the
saturation region, the charge carriers in the output devices need time to return back to the normal state. After the
charge carriers return back to the equilibrium state, the device begins to slew at the normal slew rate. Thus, the
propagation delay in case of an overload condition is the sum of the overload recovery time and the slew time.
The overload recovery time for the OPAx172 is approximately 200 ns.
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9 Applications and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
9.1 Application Information
The OPAx172 family of amplifiers is specified for operation from 4.5 V to 36 V (±2.25 V to ±18 V). Many of the
specifications apply from –40°C to +125°C. Parameters that can exhibit significant variance with regard to
operating voltage or temperature are presented in the Typical Characteristics.
9.2 Typical Applications
The following application examples highlight only a few of the circuits where the OPAx172 can be used.
9.2.1 Capacitive Load Drive Solution Using an Isolation Resistor
The OPA172 can be used capacitive loads such as cable shields, reference buffers, MOSFET gates, and diodes.
The circuit uses an isolation resistor (RISO) to stabilize the output of an op amp. RISO modifies the open-loop gain
of the system to ensure the circuit has sufficient phase margin.
+VS
VOUT
RISO
+
VIN
+
±
CLOAD
-VS
Figure 47. Unity-Gain Buffer with RISO Stability Compensation
9.2.1.1 Design Requirements
The design requirements are:
•
•
•
Supply voltage: 30 V (±15 V)
Capacitive loads: 100 pF, 1000 pF, 0.01 μF, 0.1 μF, and 1 μF
Phase margin: 45° and 60°
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Typical Applications (continued)
9.2.1.2 Detailed Design Procedure
Figure 47 depicts a unity-gain buffer driving a capacitive load. Equation 1 shows the transfer function for the
circuit in Figure 47. Not depicted in Figure 47 is the open-loop output resistance of the op amp, Ro.
1 + CLOAD × RISO × s
T(s) =
1 + Ro + RISO × CLOAD × s
(1)
The transfer function in Equation 1 has a pole and a zero. The frequency of the pole (fp) is determined by (Ro +
RISO) and CLOAD. Components RISO and CLOAD determine the frequency of the zero (fz). A stable system is
obtained by selecting RISO such that the rate of closure (ROC) between the open-loop gain (AOL) and 1 / β is
20 dB per decade. Figure 48 shows the concept. Note that the 1 / β curve for a unity-gain buffer is 0 dB.
120
AOL
100
1
fp
2 u Πu RISO
Gain (dB)
80
60
Ro
u CLOAD
40 dB
fz
40
1
2 u Πu RISO u CLOAD
1 dec
1/
20
ROC
20 dB
dec
0
10
100
1k
10k
100k
1M
10M
100M
Frequency (Hz)
Figure 48. Unity-Gain Amplifier with RISO Compensation
ROC stability analysis is typically simulated. The validity of the analysis depends on multiple factors, especially
the accurate modeling of Ro. In addition to simulating the ROC, a robust stability analysis includes a
measurement of overshoot percentage and ac gain peaking of the circuit using a function generator,
oscilloscope, and gain and phase analyzer. Phase margin is then calculated from these measurements. Table 4
shows the overshoot percentage and ac gain peaking that correspond to phase margins of 45° and 60°. For
more details on this design and other alternative devices that can be used in place of the OPA172, refer to the
precision design, Capacitive Load Drive Solution using an Isolation Resistor (TIPD128).
Table 4. Phase Margin versus Overshoot and AC Gain Peaking
26
PHASE MARGIN
OVERSHOOT
AC GAIN PEAKING
45°
23.3%
2.35 dB
60°
8.8%
0.28 dB
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9.2.1.3 Application Curve
The OPA172 meets the supply voltage requirements of 30 V. The OPA172 is tested for various capacitive loads
and RISO is adjusted to get an overshoot corresponding to Table 4. The results of the these tests are summarized
in Figure 49.
1000
60° Phase Margin
45° Phase Margin
RISO (Ÿ)
100
10
1
0.01
0.1
1
10
100
1000
CLOAD (nF)
C041
Figure 49. RISO vs CLOAD
9.2.2 Bidirectional Current Source
The improved Howland current-pump topology shown in Figure 50 provides excellent performance because of
the extremely tight tolerances of the on-chip resistors of the INA132. By buffering the output using an OPA172,
the output current the circuit is able to deliver is greatly extended.
The circuit dc transfer function is shown in Equation 2:
IOUT = VIN / R1
(2)
The OPA172 can also be used as the feedback amplifier because the low bias current minimizes error voltages
produced across R1. However, for improved performance, select a FET-input device with extremely low offset,
such as the OPA192, OPA140, or OPA188 as the feedback amplifier.
INA132
±IN
40 NŸ
40 NŸ
SENSE
VCC
OUTPUT
VIN
+
+
+IN
40 NŸ
40 NŸ
+ +
OPA172
REF
VEE
VCC
OPA172
R1
+ +
VEE
IOUT
Figure 50. Bidirectional Current Source
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9.2.3 JFET-Input Low-Noise Amplifier
Figure 51 shows a low-noise composite amplifier built by adding a low noise JFET pair (Q1 and Q2) as an input
preamplifier for the OPA172. Transistors Q3 and Q4 form a 2-mA current sink that biases each JFET with 1 mA
of drain current. Using 3.9-kΩ drain resistors produces a gain of approximately 10 in the input amplifier, making
the extremely-low, broadband-noise spectral density of the JFET pair, Q1 and Q2, the dominant noise source of
the amplifier. The output impedance of the input differential amplifier is large enough that a FET-input amplifier
such as the OPA172 provides superior noise performance over bipolar-input amplifiers.
The gain of the composite amplifier is given by Equation 3:
AV = (1 + R3 / R4)
(3)
The resistances shown are standard 1% resistor values that produce a gain of approximately 100 (99.26) with
68° of phase margin. Gains less than 10 may require additional compensation methods to provide stability.
Select low resistor values to minimize the resistor thermal noise contribution to the total output noise.
VCC
VCC
VEE
V1
15 V
V2
15 V
R1
3.9 kŸ
R2
3.9 kŸ
VEE
OPA172
++
LSK489
Q1
VCC
VOUT
R3
1.13 kŸ
Q2
VCC
R6
27.4 kŸ
Q3
R4
11.5 Ÿ
MMBT4401
Q4
MMBT4401
R5
300 Ÿ
VEE
Figure 51. JFET-Input Low-Noise Amplifier
10 Power-Supply Recommendations
The OPA172 is specified for operation from 4.5 V to 36 V (±2.25 V to ±18 V); many specifications apply from
–40°C to +125°C. Parameters that can exhibit significant variance with regard to operating voltage or
temperature are presented in the Typical Characteristics.
CAUTION
Supply voltages larger than 40 V can permanently damage the device; see the
Absolute Maximum Ratings.
Place 0.1-μF bypass capacitors close to the power-supply terminals to reduce errors coupling in from noisy or
high-impedance power supplies. For more detailed information on bypass capacitor placement, see the Layout
section.
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11 Layout
11.1 Layout Guidelines
For best operational performance of the device, use good printed circuit board (PCB) layout practices, including:
• Noise can propagate into analog circuitry through the power pins of the circuit as a whole and op amp
itself. Bypass capacitors are used to reduce the coupled noise by providing low-impedance power
sources local to the analog circuitry.
– Connect low-ESR, 0.1-µF ceramic bypass capacitors between each supply pin and ground, placed as
close to the device as possible. A single bypass capacitor from V+ to ground is applicable for singlesupply applications.
• Separate grounding for analog and digital portions of circuitry is one of the simplest and most-effective
methods of noise suppression. One or more layers on multilayer PCBs are usually devoted to ground
planes. A ground plane helps distribute heat and reduces EMI noise pickup. Make sure to physically
separate digital and analog grounds paying attention to the flow of the ground current. For more detailed
information refer to SLOA089, Circuit Board Layout Techniques.
• In order to reduce parasitic coupling, run the input traces as far away from the supply or output traces as
possible. If these traces cannot be kept separate, crossing the sensitive trace perpendicular as opposed
to in parallel with the noisy trace is preferable.
• Place the external components as close to the device as possible. As shown in Figure 52, keeping RF
and RG close to the inverting input minimizes parasitic capacitance.
• Keep the length of input traces as short as possible. Always remember that the input traces are the most
sensitive part of the circuit.
• Consider a driven, low-impedance guard ring around the critical traces. A guard ring can significantly
reduce leakage currents from nearby traces that are at different potentials.
11.2 Layout Example
Run the input traces
as far away from
the supply lines
as possible
Place components close
to device and to each
other to reduce parasitic
errors
VS+
RF
NC
NC
GND
±IN
V+
VIN
+IN
OUTPUT
V±
NC
Use a low-ESR,
ceramic bypass
capacitor
RG
GND
VS±
GND
VOUT
Ground (GND) plane on another layer
Use low-ESR,
ceramic bypass
capacitor
Figure 52. Operational Amplifier Board Layout for Noninverting Configuration
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12 Device and Documentation Support
12.1 Device Support
12.1.1 Development Support
12.1.1.1 TINA-TI™ (Free Software Download)
TINA™ is a simple, powerful, and easy-to-use circuit simulation program based on a SPICE engine. TINA-TI is a
free, fully-functional version of the TINA software, preloaded with a library of macro models in addition to a range
of both passive and active models. TINA-TI provides all the conventional dc, transient, and frequency domain
analysis of SPICE, as well as additional design capabilities.
Available as a free download from the Analog eLab Design Center, TINA-TI offers extensive post-processing
capability that allows users to format results in a variety of ways. Virtual instruments offer the ability to select
input waveforms and probe circuit nodes, voltages, and waveforms, creating a dynamic quick-start tool.
NOTE
These files require that either the TINA software (from DesignSoft™) or TINA-TI software
be installed. Download the free TINA-TI software from the TINA-TI folder.
12.2 Documentation Support
12.2.1 Related Documentation
SBOA015 (AB-028) — Feedback Plots Define Op Amp AC Performance.
SLOA089 — Circuit Board Layout Techniques.
SLOD006 — Op Amps for Everyone.
SBOA128 — EMI Rejection Ratio of Operational Amplifiers.
TIPD128 — Capacitive Load Drive Solution using an Isolation Resistor.
12.3 Related Links
Table 5 lists quick access links. Categories include technical documents, support and community resources,
tools and software, and quick access to sample or buy.
Table 5. Related Links
PARTS
PRODUCT FOLDER
SAMPLE & BUY
TECHNICAL
DOCUMENTS
TOOLS &
SOFTWARE
SUPPORT &
COMMUNITY
OPA172
Click here
Click here
Click here
Click here
Click here
OPA2172
Click here
Click here
Click here
Click here
Click here
OPA4172
Click here
Click here
Click here
Click here
Click here
12.4 Community Resources
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
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12.5 Trademarks
E2E is a trademark of Texas Instruments.
TINA-TI is a trademark of Texas Instruments, Inc and DesignSoft, Inc.
Bluetooth is a registered trademark of Bluetooth SIG, Inc.
TINA, DesignSoft are trademarks of DesignSoft, Inc.
All other trademarks are the property of their respective owners.
12.6 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
12.7 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
13 Mechanical, Packaging, and Orderable Information
The following pages include mechanical packaging and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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PACKAGE OPTION ADDENDUM
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10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
(4/5)
(6)
OPA172ID
ACTIVE
SOIC
D
8
75
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 125
OPA172
OPA172IDBVR
ACTIVE
SOT-23
DBV
5
3000
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 125
OUWQ
OPA172IDBVT
ACTIVE
SOT-23
DBV
5
250
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 125
OUWQ
OPA172IDCKR
ACTIVE
SC70
DCK
5
3000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
SIU
OPA172IDCKT
ACTIVE
SC70
DCK
5
250
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
SIU
OPA172IDR
ACTIVE
SOIC
D
8
2500
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 125
OPA172
OPA2172ID
ACTIVE
SOIC
D
8
75
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 125
O2172A
OPA2172IDGK
ACTIVE
VSSOP
DGK
8
80
RoHS & Green
NIPDAUAG
Level-2-260C-1 YEAR
-40 to 125
OVJQ
OPA2172IDGKR
ACTIVE
VSSOP
DGK
8
2500
RoHS & Green
NIPDAUAG
Level-2-260C-1 YEAR
-40 to 125
OVJQ
OPA2172IDR
ACTIVE
SOIC
D
8
2500
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 125
O2172A
OPA2172IDRGR
ACTIVE
SON
DRG
8
3000
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 125
OP2172
OPA2172IDRGT
ACTIVE
SON
DRG
8
250
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 125
OP2172
OPA4172ID
ACTIVE
SOIC
D
14
50
RoHS & Green
NIPDAU
Level-3-260C-168 HR
-40 to 125
OPA4172
OPA4172IDR
ACTIVE
SOIC
D
14
2500
RoHS & Green
NIPDAU
Level-3-260C-168 HR
-40 to 125
OPA4172
OPA4172IPW
ACTIVE
TSSOP
PW
14
90
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 125
OPA4172
OPA4172IPWR
ACTIVE
TSSOP
PW
14
2000
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 125
OPA4172
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
Addendum-Page 1
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of
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