OPA684
OPA
684
OPA68
4
SBOS219D – OCTOBER 2001 – REVISED JUNE 2009
Low-Power, Current Feedback
OPERATIONAL AMPLIFIER With Disable
FEATURES
APPLICATIONS
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MINIMAL BANDWIDTH CHANGE VERSUS GAIN
> 120MHz BANDWIDTH TO GAIN > +10
LOW DISTORTION: < –78dBc at 5MHz
HIGH OUTPUT CURRENT: 120mA
SINGLE +5V TO +12V SUPPLY OPERATION
DUAL ±2.5 TO ±6.0V SUPPLY OPERATION
LOW SUPPLY CURRENT: 1.7mA
LOW SHUTDOWN CURRENT: 100µA
DESCRIPTION
The OPA684 provides a new level of performance in low-power,
wideband, current-feedback (CFB) amplifiers. This CFBplus amplifier is the first to use an internally closed-loop input buffer stage that
enhances performance significantly over earlier low-power CFB
amplifiers. While retaining the benefits of very low power operation,
this new architecture provides many of the benefits of a more ideal
CFB amplifier. The closed-loop input stage buffer gives a very low
and linearized impedance path at the inverting input to sense the
feedback error current. This improved inverting input impedance
retains exceptional bandwidth to much higher gains and improves
harmonic distortion over earlier solutions limited by inverting input
linearity. Beyond simple high-gain applications, the OPA684 CFBplus
amplifier permits the gain setting element to be set with considerable freedom from amplifier bandwidth interaction. This allows
frequency response peaking elements to be added, multiple input
inverting summing circuits to have greater bandwidth, and low-
LOW-POWER BROADCAST VIDEO DRIVERS
EQUALIZING FILTERS
SAW FILTER HIGH GAIN POST AMPLIFIERS
MULTICHANNEL SUMMING AMPLIFIERS
PROFESSIONAL CAMERAS
ADC INPUT DRIVERS
power line drivers to meet the demanding requirements of studio
cameras and broadcast video.
The output capability of the OPA684 also sets a new mark in
performance for low-power current feedback amplifiers. Delivering
a full ±4VPP swing on ±5V supplies, the OPA684 also has the
output current to support this swing into a 100Ω load. This minimal
output headroom requirement is complemented by a similar 1.2V
input stage headroom giving exceptional capability for single +5V
operation.
The OPA684’s low 1.7mA supply current is precisely trimmed at
25°C. This trim, along with low shift over temperature and supply
voltage, gives a very robust design over a wide range of operating
conditions. System power may be further reduced by using the
optional disable control pin. Leaving this disable pin open, or holding
it HIGH, gives normal operation. If pulled LOW, the OPA684 supply
current drops to less than 100µA while the I/O pins go to a high
impedance state.
BW (MHz) vs GAIN
V+
G=2
G=5
3
Normalized Gain
0
+
VO
Z(S) IERR
V–
IERR
–3
–6
–9
–12
G = 10
–15
G = 20
G = 50
–18
RF
–21
RF = 1kΩ
10
RG
Low-Power
G = 100
100
200
Amplifier
Patent Pending
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
All trademarks are the property of their respective owners.
Copyright © 2001-2009, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
www.ti.com
ELECTROSTATIC
DISCHARGE SENSITIVITY
ABSOLUTE MAXIMUM RATINGS(1)
Power Supply ............................................................................... ±6.5VDC
Internal Power Dissipation ................................. See Thermal Information
Differential Input Voltage .................................................................. ±1.2V
Input Voltage Range ............................................................................ ±VS
Storage Temperature Range: ID, IDBV ......................... –65°C to +125°C
Junction Temperature (TJ ) ........................................................... +175°C
NOTE: (1) Stresses above these ratings may cause permanent damage.
Exposure to absolute maximum conditions for extended periods may degrade
device reliability.
OPA684 RELATED PRODUCTS
SINGLES
OPA684
OPA691
OPA695
DUALS
TRIPLES
FEATURES
OPA2684
OPA2691
OPA2695
OPA3684
OPA3691
OPA3695
Low-Power CFBplus
High Slew Rate CFB
> 500MHz CFB
This integrated circuit can be damaged by ESD. Texas
Instruments recommends that all integrated circuits be handled
with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits
may be more susceptible to damage because very small
parametric changes could cause the device not to meet its
published specifications.
PACKAGE/ORDERING INFORMATION(1)
PRODUCT
PACKAGE-LEAD
PACKAGE
DESIGNATOR
SPECIFIED
TEMPERATURE
RANGE
PACKAGE
MARKING
ORDERING
NUMBER
TRANSPORT
MEDIA, QUANTITY
SO-8
D
–40°C to +85°C
OPA684D
"
"
"
"
OPA684ID
OPA684IDR
Rails, 100
Tape and Reel, 2500
SOT23-6
DBV
–40°C to +85°C
B84
OPA684IDBVT
Tape and Reel, 250
"
"
"
"
OPA684IDBVR
Tape and Reel, 3000
OPA684
"
OPA684
"
NOTE: (1) For the most current package and ordering information, see the Package Option Addendum located at the end of this document, or see the TI website
at www.ti.com.
PIN CONFIGURATION
Top View
SO
NC
1
8
DIS
Inverting Input
2
7
+VS
Noninverting Input
3
6
Output
–VS
4
5
NC
Top View
SOT23
Output
1
6
+VS
–VS
2
5
DIS
Noninverting Input
3
4
Inverting Input
6
5
4
B84
NC = No Connection
1
2
3
Pin Orientation/Package Marking
2
OPA684
www.ti.com
SBOS219D
ELECTRICAL CHARACTERISTICS: VS = ±5V
RF = 1kΩ, RL = 100Ω, and G = +2, (See Figure 1 for AC performance only), unless otherwise noted.
OPA684ID, IDBV
TYP
PARAMETER
AC PERFORMANCE (See Figure 1)
Small-Signal Bandwidth (VO = 0.5VPP)
Bandwidth for 0.1dB Gain Flatness
Peaking at a Gain of +1
Large-Signal Bandwidth
Slew Rate
Rise-and-Fall Time
Harmonic Distortion
2nd-Harmonic
3rd-Harmonic
Input Voltage Noise
Non-inverting Input Current Noise
Inverting Input Current Noise
Differential Gain
Differential Phase
DC PERFORMANCE(4)
Open-Loop Transimpedance Gain (ZOL)
Input Offset Voltage
Average Offset Voltage Drift
Non-inverting Input Bias Current
Average Non-inverting Input Bias Current Drift
Inverting Input Bias Current
Average Inverting Input Bias Current Drift
INPUT
Common-Mode Input Range(5) (CMIR)
Common-Mode Rejection Ratio (CMRR)
Non-inverting Input Impedance
Inverting Input Resistance (RI)
OUTPUT
Voltage Output Swing
Current Output, Sourcing
Current Output, Sinking
Closed-Loop Output Impedance
DISABLE (Disabled Low)
Power-Down Supply Current (+VS)
Disable Time
Enable Time
Off Isolation
Output Capacitance in Disable
Enable Voltage
Disable Voltage
Control Pin Input Bias Current (DIS)
POWER SUPPLY
Specified Operating Voltage
Maximum Operating Voltage Range
Minimum Operating Voltage Range
Max Quiescent Current
Min Quiescent Current
Power-Supply Rejection Ratio (–PSRR)
TEMPERATURE RANGE
Specification: ID, IDBV
Thermal Resistance, θJA
D
SO-8
DBV SOT-23-6
+25°C
CONDITIONS
G = +1, RF = 1kΩ
G = +2, RF = 1kΩ
G = +5, RF = 1kΩ
G = +10, RF = 1kΩ
G = +20, RF = 1kΩ
G = +2, VO = 0.5VPP, RF = 1kΩ
RF = 1kΩ, VO = 0.5VPP
G = +2, VO = 4VPP
G = –1, VO = 4V Step
G = +2,VO = 4V Step
G = +2, VO = 0.5V Step
G = +2, VO = 4VStep
G = +2, f = 5MHz, VO = 2VPP
RL = 100Ω
RL ≥ 1kΩ
RL = 100Ω
RL ≥ 1kΩ
f > 1MHz
f > 1MHz
f > 1MHz
G = +2, NTSC, VO = 1.4Vp, RL = 150Ω
G = +2, NTSC, VO = 1.4Vp, RL = 150Ω
VO = 0V, RL = 1kΩ
VCM = 0V
VCM = 0V
VCM = 0V
VCM = 0V
VCM = 0V
VCM = 0V
210
160
134
120
104
19
1.4
90
820
750
3
6.8
MIN/MAX OVER TEMPERATURE
+25°C(1)
0°C to
70°C(2)
–40°C to
+85°C(2)
112
110
104
16
4.8
14
5.9
14
6.3
675
650
650
620
575
590
–59
–64
–66
–82
4.1
11
18
–59
–64
–65
–81
4.2
12
18.5
160
typ
min
typ
typ
typ
min
max
typ
min
min
typ
typ
C
B
C
C
C
B
B
C
B
B
C
C
–58
–63
–65
–81
4.4
12.5
19
dBc
dBc
dBc
dBc
nV/√Hz
pA/√Hz
pA/√Hz
%
deg
max
max
max
max
max
max
max
typ
typ
B
B
B
B
B
B
B
C
C
155
±4.1
±12
±11.5
±25
±17.5
±35
153
±4.3
±12
±12
±30
±18.5
±40
kΩ
mV
µV/°C
µA
nA/°C
µA
nA°/C
min
max
max
max
max
max
max
A
A
B
A
B
A
B
±3.65
52
±3.6
52
V
dB
kΩ || pF
Ω
min
min
typ
typ
A
A
C
C
140
–110
±4.0
135
–105
±3.9
130
–100
V
mA
mA
Ω
min
min
min
typ
A
A
A
C
–150
–170
–180
3.5
1.7
120
3.6
1.6
130
3.7
1.5
135
µA
ms
ns
dB
pF
V
V
µA
max
typ
typ
typ
typ
min
max
max
A
C
C
C
C
A
A
A
±6
±6
±6
1.8
1.6
54
1.85
1.55
53
1.85
1.45
53
V
V
V
mA
mA
dB
typ
max
min
max
min
typ
C
A
C
A
A
A
–40 to +85
°C
typ
C
125
150
°C/W
°C/W
typ
typ
C
C
–67
–78
–70
–89
3.7
9.4
17
0.04
0.02
±3.5
±5.0
±10
±5.0
±16
±3.65
Open-Loop, DC
±3.75
60
50 || 2
2.5
1kΩ Load
VO = 0
VO = 0
G = +2, f = 100kHz
±4.1
160
–120
0.006
±4.0
VDIS = 0
VIN = +1V, G = +2
VIN = +1V, G = +2
G = +2, 5MHz
–100
4
40
70
1.7
3.4
1.8
80
VDIS = 0V
±5
VS = ±5V
VS = ±5V
Input Referred
MIN/ TEST
MAX LEVEL(3)
MHz
MHz
MHz
MHz
MHz
MHz
dB
MHz
V/µs
V/µs
ns
ns
355
±1.5
VCM = 0V
UNITS
±1.4
1.7
1.7
60
Junction-to-Ambient
53
NOTES: (1) Junction temperature = ambient for 25°C tested specifications. (2) Junction temperature = ambient at low temperature limit, junction temperature = ambient
+2°C at high temperature limit for over temperature tested specifications. (3) Test levels: (A) 100% tested at 25°C. Over temperature limits by characterization and
simulation. (B) Limits set by characterization and simulation. (C) Typical value only for information. (4) Current is considered positive out-of-node. VCM is the input
common-mode voltage. (5) Tested < 3dB below minimum specified CMR at ±CMIR limits.
OPA684
SBOS219D
www.ti.com
3
ELECTRICAL CHARACTERISTICS: VS = +5V
RF = 1.3kΩ, RL = 100Ω, and G = +2, (See Figure 3 for AC performance only), unless otherwise noted.
OPA684ID, IDBV
TYP
PARAMETER
AC PERFORMANCE (See Figure 3)
Small-Signal Bandwidth (VO = 0.5VPP)
Bandwidth for 0.1dB Gain Flatness
Peaking at a Gain of +1
Large-Signal Bandwidth
Slew Rate
Rise-and-Fall Time
Harmonic Distortion
2nd-Harmonic
3rd-Harmonic
Input Voltage Noise
Non-inverting Input Current Noise
Inverting Input Current Noise
Differential Gain
Differential Phase
DC PERFORMANCE(4)
Open-Loop Transimpedance Gain (ZOL)
Input Offset Voltage
Average Offset Voltage Drift
Non-inverting Input Bias Current
Average Non-inverting Input Bias Current Drift
Inverting Input Bias Current
Average Inverting Input Bias Current Drift
INPUT
Least Positive Input Voltage(5)
Most Positive Input Voltage(5)
Common-Mode Refection Ratio (CMRR)
Non-inverting Input Impedance
Inverting Input Resistance (RI)
OUTPUT
Most Positive Output Voltage
Least Positive Output Voltage
Current Output, Sourcing
Current Output, Sinking
Closed-Loop Output Impedance
DISABLE (Disabled LOW)
Power-Down Supply Current (+VS)
Off Isolation
Output Capacitance in Disable
Turn On Glitch
Turn Off Glitch
Enable Voltage
Disable Voltage
Control Pin Input Bias Current (DIS)
POWER SUPPLY
Specified Single-Supply Operating Voltage
Max Single-Supply Operating Voltage Range
Min Single-Supply Operating Voltage Range
Max Quiescent Current
Min Quiescent Current
Power-Supply Rejection Ratio (+PSRR)
TEMPERATURE RANGE
Specification: ID, IDBV
Thermal Resistance, θJA Junction-to-Ambient
D
SO-8
DBV SOT23-6
+25°C
CONDITIONS
G = +1, RF = 1.3kΩ
G = +2, RF = 1.3kΩ
G = +5, RF = 1.3kΩ
G = +10, RF = 1.3kΩ
G = +20, RF = 1.3kΩ
G = +2, VO < 0.5VPP, RF = 1.3kΩ
RF = 1.3kΩ, VO < 0.5VPP
G = 2, VO = 2VPP
G = 2, VO = 2V Step
G = 2, VO = 0.5V Step
G = 2, VO = 2VStep
G = 2, f = 5MHz, VO = 2VPP
RL = 100Ω to VS/2
RL ≥ 1kΩ to VS/2
RL = 100Ω to VS/2
RL ≥ 1kΩ to VS/2
f > 1MHz
f > 1MHz
f > 1MHz
G = +2, NTSC, VO = 1.4Vp, RL = 150Ω
G = +2, NTSC, VO = 1.4Vp, RL = 150Ω
VO = VS/2, RL = 100Ω to VS/2
VCM = VS/2
VCM = VS/2
VCM = VS/2
VCM = VS/2
VCM = VS/2
VCM = VS/2
146
105
95
87
79
21
0.5
86
300
4.3
5.3
65
65
65
71
3.7
9.4
17
0.04
0.07
MIN/MAX OVER TEMPERATURE
+25°C(1)
0°C to
70°C(2)
–40°C to
+85°C(2)
79
76
69
12
2.6
11
3.4
10
3.7
240
235
225
57
58
64
70
4.1
11
18
57
57
63
70
4.2
12
18.5
160
UNITS
MIN/ TEST
MAX LEVEL(3)
MHz
MHz
MHz
MHz
MHz
MHz
dB
MHz
V/µs
ns
ns
typ
min
min
typ
typ
min
max
typ
min
typ
typ
C
B
C
C
C
B
B
C
B
C
C
56
57
63
69
4.4
12.5
19
dBc
dBc
dBc
dBc
nV/√Hz
pA/√Hz
pA/√Hz
%
deg
max
max
max
max
max
max
max
typ
typ
B
B
B
B
B
B
B
C
C
155
±3.6
±12
±11.5
±25
±13.5
±25
153
±3.8
±12
±12
±30
±15
±30
kΩ
mV
µV/°C
µA
nA/°C
µA
nA°/C
min
max
max
max
max
max
max
A
A
B
A
B
A
B
325
±1.0
±3.0
±5
±10
±5
±12
1.32
3.68
52
1.35
3.65
51
1.38
3.62
51
Open-Loop
1.25
3.75
58
50 || 1
2.5
V
V
dB
kΩ || pF
Ω
max
min
min
typ
typ
A
A
A
C
C
RL = 1kΩ to VS/2
RL = 1kΩ to VS/2
VO = VS/2
VO = VS/2
G = +2, f = 100kHz
4.10
0.9
80
70
0.006
4.0
1.0
70
58
4.0
1.0
65
53
3.9
1.1
60
48
V
V
mA
mA
Ω
min
max
min
min
typ
A
A
A
A
C
VDIS = 0
F = 5.0MHz
–90
70
1.7
µA
dB
pF
mV
mV
V
V
µA
typ
typ
typ
typ
typ
min
max
max
C
C
C
C
C
A
A
A
V
V
V
mA
mA
dB
typ
max
min
max
min
typ
C
A
C
A
A
C
–40 to +85
°C
typ
C
125
150
°C/W
°C/W
typ
typ
C
C
VCM = VS/2
G = +2, RL = 150Ω, VIN = VS/2
G = +2, RL = 150Ω, VIN = VS/2
3.4
1.8
80
VDIS = 0V
3.5
1.7
120
3.6
1.6
130
3.7
1.5
135
12
12
12
1.55
1.30
1.55
1.20
1.55
1.15
5
VS = +5V
VS = +5V
Input Referred
2.8
1.44
1.44
65
NOTES: (1) Junction temperature = ambient for 25°C tested specifications. (2) Junction temperature = ambient at low temperature limit, junction temperature = ambient
+1°C at high temperature limit for over temperature tested specifications. (3) Test levels: (A) 100% tested at 25°C. Over temperature limits by characterization and
simulation. (B) Limits set by characterization and simulation. (C) Typical value only for information. (4) Current is considered positive out-of-node. VCM is the input
common-mode voltage. (5) Tested < 3dB below minimum specified CMR at ± CMIR limits.
4
OPA684
www.ti.com
SBOS219D
TYPICAL CHARACTERISTICS: VS = ±5V
At TA = +25°C, G = +2, RF = 1kΩ, RL = 100Ω, unless otherwise noted.
NONINVERTING SMALL-SIGNAL
FREQUENCY RESPONSE
VO = 0.5Vp-p
RF = 1kΩ
Normalized Gain (3dB/div)
3
INVERTING SMALL-SIGNAL FREQUENCY RESPONSE
+3
G = 50
G = 100
G=1
G=2
0
Normalized Gain (3dB/div)
6
–3
–6
–9
G=5
–12
VO = 0.5Vp-p
RF = 1kΩ
G = –10
G = –5
G = –20
0
G = –1
–3
G = –2
–6
–9
–15
See Figure 1
G = 10
See Figure 2
–12
–18
1
10
100
200
1
10
Frequency (MHz)
NONINVERTING LARGE-SIGNAL
FREQUENCY RESPONSE
9
VO = 0.5Vp-p
VO = 0.5Vp-p
2Vp-p
Gain (dB)
VO = 1Vp-p
3
2Vp-p
1Vp-p
–3
5Vp-p
–6
5Vp-p
0
–9
See Figure 1
–3
1
See Figure 2
–12
10
100
200
1
10
Frequency (MHz)
NONINVERTING PULSE RESPONSE
0.8
0.8
G = +2
0.4
0.8
0.4
Small-Signal Left Scale
0
0
–0.2
–0.4
–0.4
–0.8
–0.6
–1.2
0.6
1.2
0.4
0.8
0.2
0.4
0
0
Small-Signal Left Scale
–0.2
–0.4
Large-Signal Right Scale
–0.4
–0.6
See Figure 1
–0.8
–1.2
See Figure 2
–0.8
–1.6
Time (10ns/div)
–0.8
–1.6
Time (10ns/div)
OPA684
SBOS219D
1.6
G = –1
Output Voltage (200mV/div)
1.2
Output Voltage (400mV/div)
0.6
Large-Signal Right Scale
200
INVERTING PULSE RESPONSE
1.6
0.2
100
Frequency (MHz)
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5
Output Voltage (400mV/div)
Gain (dB)
G = –1
RL = 100Ω
0
6
Output Voltage (200mV/div)
200
INVERTING LARGE-SIGNAL FREQUENCY RESPONSE
3
G = +2
RL = 100Ω
100
Frequency (MHz)
TYPICAL CHARACTERISTICS: VS = ±5V (Cont.)
At TA = +25°C, G = +2, RF = 1kΩ, RL = 100Ω, unless otherwise noted.
HARMONIC DISTORTION vs LOAD RESISTANCE
HARMONIC DISTORTION vs FREQUENCY
–50
–50
VO = 2Vp-p
f = 5MHz
G = +2
–60
VO = 2Vp-p
RL = 100Ω
Harmonic Distortion (dBc)
Harmonic Distortion (dBc)
–55
–65
2nd-Harmonic
–70
–75
3rd-Harmonic
–80
–60
2nd-Harmonic
–70
3rd-Harmonic
–80
–85
See Figure 1
–90
See Figure 1
–90
100
0.1
1k
1
Load Resistance (Ω)
HARMONIC DISTORTION vs OUTPUT VOLTAGE
f = 5MHz
RL = 100Ω
Harmonic Distortion (dBc)
Harmonic Distortion (dBc)
–50
–60
2nd-Harmonic
–70
3rd-Harmonic
–80
VO = 2Vp-p
RL = 100Ω
–60
2nd-Harmonic
–70
3rd-Harmonic
–80
See Figure 1
See Figure 1
–90
0.5
1
–90
±2.5
5
±3
Output Voltage (Vp-p)
±4
±4.5
±5
Supply Voltage (±V)
±5.5
±6
–50
–60
VO = 2Vp-p
f = 5MHz
RL = 100Ω
–55
2nd-Harmonic
Harmonic Distortion (dBc)
VO = 2Vp-p
f = 5MHz
RL = 100Ω
–55
Harmonic Distortion (dBc)
±3.5
HARMONIC DISTORTION vs INVERTING GAIN
HARMONIC DISTORTION vs NONINVERTING GAIN
–50
–65
–70
–75
3rd-Harmonic
–80
–60
2nd-Harmonic
–65
–70
–75
3rd-Harmonic
–80
–85
–85
See Figure 2
See Figure 1
–90
1
10
1
20
Gain (V/V)
6
20
5MHz HARMONIC DISTORTION vs SUPPLY VOLTAGE
–50
–90
10
Frequency (MHz)
10
20
Inverting Gain (V/V)
OPA684
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SBOS219D
TYPICAL CHARACTERISTICS: VS = ±5V (Cont.)
At TA = +25°C, G = +2, RF = 1kΩ, RL = 100Ω, unless otherwise noted.
2-TONE, 3RD-ORDER
INTERMODULATION DISTORTION
INPUT VOLTAGE AND CURRENT NOISE DENSITY
–50
100
20MHz
3rd-Order Spurious Level (dBc)
Voltage Noise (nV/√Hz)
Current Noise (pA/√Hz)
Inverting Current Noise
17pA/√Hz
Noninverting Current Noise
9.4pA/√Hz
10
Voltage Noise
3.7nV/√Hz
–60
10MHz
–70
+5V
PI
PO
50Ω
–5V
1kΩ
–80
1MHz
1kΩ
1
–90
100
1k
10k
100k
1M
10M
–8 –7 –6 –5 –4 –3 –2 –1 0 1 2 3 4 5
Power at Load (each tone, dBm)
Frequency (Hz)
DISABLE TIME
–40
VDIS
4
VIN = 1VDC
See Figure 1
3
VOUT
2
7
8
G = +2
VDIS = 0
–50
–60
Feedthru (dB)
5
6
DISABLED FEEDTHRU
6
VOUT and VDIS (V)
5MHz
50Ω
50Ω OPA684
–70
–80
1
–90
0
–100
See Figure 1
0
2
4
6
8
10
12
14
16
0.1
1
Time (ms)
10
100
Frequency (MHz)
SMALL-SIGNAL BANDWIDTH vs CLOAD
RS vs CLOAD
60
9
0.5dB Peaking
10pF
50
Normalized Gain (dB)
6
RS (Ω)
40
30
20
3
+5V
0
VO
50Ω OPA684
250Ω
CL
1kΩ
47pF
–5V
1.1kΩ
–3
10
100pF
RS
VI
1.1kΩ
22pF
0
–6
1
10
100
1
CLOAD (pF)
OPA684
SBOS219D
10
100
200
Frequency (MHz)
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7
TYPICAL CHARACTERISTICS: VS = ±5V (Cont.)
At TA = +25°C, G = +2, RF = 1kΩ, RL = 100Ω, unless otherwise noted.
OPEN-LOOP TRANSIMPEDANCE GAIN AND PHASE
CMRR and PSRR vs FREQUENCY
CMRR
60
50
+PSRR
40
–PSRR
30
20
10
0
102
103
104
105
106
Frequency (Hz)
107
120
0
20log (ZOL)
100
–30
80
–60
60
40
–120
20
–150
0
108
–180
102
103
0.07
2
dG
0.05
0Ω
3
VO (V)
108
109
=
RL
50
Ω
1
0
–1
0.04
–2
0.03
dP
–3
0.01
–4
0
–5
1
RL = 500Ω
2
3
4
1W Power
Limit
Number of 150Ω Video Loads
–150
0
IO (MA)
TYPICAL DC DRIFT OVER TEMPERATURE
SUPPLY AND OUTPUT CURRENT
vs TEMPERATURE
4
–100
–50
50
100
150
200
2
Sourcing Output Current
3
1.9
Output Current (mA)
2
1
Noninverting Input Bias Current
Input Offset Voltage
0
–1
–2
175
1.8
Sinking Output Current
150
1.7
Supply Current
125
Inverting Input Bias Current
1.6
Right Scale
–3
–4
100
–50
–25
0
25
50
75
100
125
Ambient Temperature (°C)
Supply Current (mA)
Differential Gain (%)
Differential Phase (°)
4
0.08
Input Bias Currents (µA)
and Offset Voltage (mV)
107
1W Power
Limit
L =1
0
Gain = +2
NTSC, Positive Video
0.02
8
105
106
Frequency (Hz)
R
5
0.06
104
OUTPUT CURRENT AND VOLTAGE LIMITATIONS
COMPOSITE VIDEO DIFFERENTIAL GAIN/PHASE
0.10
0.09
–90
∠ ZOL
Open-Loop Phase (°)
Open-Loop Transimpedance Gain (dBΩ)
Common-Mode Rejection Ratio (dB)
70
1.5
–25
0
25
50
75
Ambient Temperature (°C)
100
125
OPA684
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SBOS219D
TYPICAL CHARACTERISTICS: VS = ±5V (Cont.)
At TA = +25°C, G = +2, RF = 1kΩ, RL = 100Ω, unless otherwise noted.
SETTLING TIME
DISABLED SUPPLY CURRENT vs TEMPERATURE
0.05
120
Disabled Supply Current (µA)
2V Step
See Figure 1
0.04
0.02
0.01
0
–0.01
–0.02
–0.03
110
100
90
80
70
–0.04
+VS Current
–0.05
60
0
10
20
30
Time (ns)
40
50
60
–50
0
25
50
75
Ambient Temperature (°C)
125
INVERTING OVERDRIVE RECOVERY
8.0
8.0
3.2
6.4
6.4
6.4
2.4
4.8
4.8
4.8
1.6
3.2
0.8
1.6
0
0
Output Voltage
Right Scale
–0.8
–1.6
See Figure 1
–1.6
–2.4
–3.2
–4.8
Input Voltage
Left Scale
–4.0
Input Voltage (1.6V/div)
8.0
–3.2
3.2
3.2
Output Voltage
Right Scale
1.6
1.6
0
0
–1.6
–1.6
–3.2
–3.2
–4.8
–6.4
–6.4
–8.0
–8.0
–4.8
Input Voltage
Left Scale
–6.4
See Figure 2
–8.0
Time (100ns/div)
Time (100ns/div)
CLOSED-LOOP OUTPUT IMPEDANCE vs FREQUENCY
INPUT AND OUTPUT RANGE vs SUPPLY VOLTAGE
100
6
5
4
3
2
1
0
–1
–2
–3
–4
–5
–6
Input
Voltage
Range
10
Output Impedance (Ω)
Input and Output Voltage Range
100
4.0
Output Voltage (1.6V/div)
Input Voltage (0.8V/div)
NONINVERTING OVERDRIVE RECOVERY
–25
Output
Voltage
Range
OPA684
ZO
1kΩ
1
1kΩ
0.1
0.01
0.001
±2
±3
±4
±5
±6
100
± Supply Voltage
10k
100k
1M
10M
100M
Frequency (Hz)
OPA684
SBOS219D
1k
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9
Output Voltage (1.6V/div)
% Error to Final Value
0.03
TYPICAL CHARACTERISTICS: VS = +5V
At TA = +25°C, VS = 5V, G = +2, RF = 1.3kΩ, RL = 100Ω, unless otherwise noted.
NONINVERTING SMALL-SIGNAL
FREQUENCY RESPONSE
RF = 1.3kΩ
Normalized Gain (3dB/div)
3
INVERTING SMALL-SIGNAL FREQUENCY RESPONSE
+3
G = 50
RF = 1.3kΩ
G = 100
G=1
Normalized Gain (3dB/div)
6
0
G=2
–3
–6
–9
–12
G=5
0
–3
–6
G = –1
G = –2
G = –5
G = –10
G = –20
–9
–15
See Figure 3
G = 10
–18
See Figure 4
–12
1
10
100
200
1
10
Frequency (MHz)
100
NONINVERTING LARGE-SIGNAL
FREQUENCY RESPONSE
INVERTING LARGE-SIGNAL FREQUENCY RESPONSE
9
3
VO = 0.5Vp-p
0.5Vp-p
0
Gain (dB)
0.2Vp-p
6
Gain (dB)
200
Frequency (MHz)
1Vp-p
3
2Vp-p
VO = 2Vp-p
–3
VO = 1Vp-p
VO = 2Vp-p
–6
0
–9
See Figure 3
–3
See Figure 4
–12
10
100
200
1
10
Frequency (MHz)
200
INVERTING PULSE RESPONSE
1.6
0.4
1.6
0.3
1.2
0.3
1.2
0.2
0.8
0.1
0.4
0.2
Large-Signal Right Scale
0.1
0.8
0.4
Small-Signal Left Scale
0
0
–0.1
–0.4
–0.2
–0.8
–0.3
Output Voltage (200mV/div)
0.4
Output Voltage (400mV/div)
Output Voltage (200mV/div)
NONINVERTING PULSE RESPONSE
–1.2
0
0
Small-Signal Left Scale
–0.1
–0.4
Large-Signal Right Scale
–0.2
–0.3
See Figure 3.
–0.8
–1.2
See Figure 4
–0.4
–1.6
Time (10ns/div)
10
100
Frequency (MHz)
–0.4
–1.6
Time (10ns/div)
OPA684
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SBOS219D
Output Voltage (400mV/div)
1
TYPICAL CHARACTERISTICS: VS = +5V (Cont.)
At TA = +25°C, VS = 5V, G = +2, RF = 1.3kΩ, RL = 100Ω, unless otherwise noted.
HARMONIC DISTORTION vs FREQUENCY
HARMONIC DISTORTION vs LOAD RESISTANCE
–50
–50
Harmonic Distortion (dBc)
Harmonic Distortion (dBc)
VO = 2Vp-p
RL = 100Ω
VO = 2Vp-p
f = 5MHz
–55
–60
3rd-Harmonic
–65
–70
–75
2nd-Harmonic
–80
2nd-Harmonic
–60
–70
3rd-Harmonic
–80
–85
See Figure 3
100
0.1
1k
HARMONIC DISTORTION vs OUTPUT VOLTAGE
2-TONE, 3RD-ORDER
INTERMODULATION DISTORTION
20
–50
3rd-Order Spurious Level (dBc)
G = +2
RL = 100Ω
f = 5MHz
–60
2nd-Harmonic
–70
–80
See Figure 3
0.5
20MHz
–60
10MHz
–70
5MHz
–80
1MHz
See Figure 3
–90
1
2
3
–15 –14 –13 –12 –11 –10 –9
Output Voltage (Vp-p)
–7
–6
–5
–4 –3
COMPOSITE VIDEO DIFFERENTIAL GAIN/PHASE
100
1.5
0.16
Supply Current
G = +2
NTSC, Positive Video
0.14
1.2
Left Scale
Sinking Output Current
Differential Gain (%)
Differential Phase (°)
1.3
Left Scale
Sourcing Output Current
Supply Current (mA)
1.4
Right Scale
75
–8
Power at Load (each tone, dBm)
SUPPLY AND OUTPUT CURRENT
vs TEMPERATURE
Output Current (mA)
10
Frequency (MHz)
3rd-Harmonic
–90
1
Load Resistance (Ω)
–50
Harmonic Distortion (dBc)
See Figure 3
–90
–90
1.1
0.12
0.10
dP
0.08
0.06
0.04
dG
0.02
1.0
50
–25
0
25
50
75
Ambient Temperature (°C)
100
125
1
2
3
4
Number of 150Ω Video Loads
OPA684
SBOS219D
0
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11
APPLICATIONS INFORMATION
LOW-POWER, CURRENT-FEEDBACK OPERATION
The OPA684 gives a new level of performance in low-power,
current-feedback op amps. Using a new input stage buffer
architecture, the OPA684 CFBplus amplifier holds nearly
constant AC performance over a wide gain range. This
closed-loop internal buffer gives a very low and linearized
impedance at the inverting node, isolating the amplifier’s AC
performance from gain element variations. This allows both
the bandwidth and distortion to remain nearly constant over
gain, moving closer to the ideal current feedback performance of gain bandwidth independence. This low power
amplifier also delivers exceptional output power—its ±4V
swing on ±5V supplies with >100mA output drive gives
excellent performance into standard video loads or doublyterminated 50Ω cables. Single +5V supply operation is also
supported with similar bandwidths but with reduced output
power capability. For lower quiescent power in a CFBplus
amplifier, consider the OPA683, while for higher output
power, consider the OPA691.
Figure 1 shows the DC coupled, gain of +2, dual powersupply circuit used as the basis of the ±5V Electrical and
Typical Characteristics. For test purposes, the input impedance is set to 50Ω with a resistor to ground, and the output
impedance is set to 50Ω with a series output resistor. Voltage
swings reported in the characteristics are taken directly at the
input and output pins while load powers (dBm) are defined at
a matched 50Ω load. For the circuit of Figure 1, the total
effective load will be 100Ω || 2000Ω = 95Ω. Gain changes are
most easily accomplished by simply resetting the RG value,
holding RF constant at its recommended value of 1kΩ. The
disable control line (DIS) is typically left open to give normal
amplifier operation. It may, however, be asserted LOW to
reduce the amplifier supply current to 100µA typically.
Figure 2 shows the DC coupled, gain of –1V/V, dual powersupply circuit used as the basis of the Inverting Typical
Characteristics. Inverting operation offers several performance benefits. Since there is no common-mode signal
across the input stage, the slew rate for inverting operation
is higher and the distortion performance is slightly improved.
An additional input resistor, RM, is included in Figure 2 to set
the input impedance equal to 50Ω. The parallel combination
of RM and RG set the input impedance. As the desired gain
increases for the inverting configuration, RG is adjusted to
achieve the desired gain, while RM is also adjusted to hold a
50Ω input match. A point will be reached where RG will equal
50Ω, RM is removed, and the input match is set by RG only.
With RG fixed to achieve an input match to 50Ω, increasing
RF will increase the gain. This will, however, quickly reduce
the achievable bandwidth as the feedback resistor increases
from its recommended value of 1kΩ. If the source does not
require an input match of 50Ω, either adjust RM to the get the
desired load, or remove it and let the RG resistor alone
provide the input load.
These circuits show ±5V operation. The same circuits can be
applied with bipolar supplies from ±2.5V to ±6V. Internal
supply independent biasing gives nearly the same performance for the OPA684 over this wide range of supplies.
Generally, the optimum feedback resistor value (for nominally flat frequency response at G = +2) will increase in value
as the total supply voltage across the OPA684 is reduced.
+5V
0.1µF
+
6.8µF
50Ω
OPA684
50Ω Load
DIS
RF
1kΩ
+5V
50Ω Source
0.1µF
+
RG
1kΩ
VI
6.8µF
RM
52.3Ω
0.1µF
VI
50Ω Source
RM
50Ω
50Ω
6.8µF
–5V
OPA684
50Ω Load
FIGURE 2. DC Coupled, G = –1V/V, Bipolar Supply, Specification and Test Circuit.
DIS
RF
1kΩ
RG
1kΩ
0.1µF
+
6.8µF
–5V
FIGURE 1. DC Coupled, G = +2V/V, Bipolar Supply Specifications and Test Circuit.
12
+
Figure 3 shows the AC-coupled, single +5V supply, gain of
+2V/V circuit configuration used as a basis only for the +5V
Electrical and Typical Characteristics. The key requirement
of broadband single-supply operation is to maintain input and
output signal swings within the usable voltage ranges at both
the input and the output. The circuit of Figure 3 establishes
an input midpoint bias using a simple resistive divider from
the +5V supply (two 10kΩ resistors) to the non-inverting
input. The input signal is then AC coupled into this midpoint
OPA684
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SBOS219D
voltage bias. The input voltage can swing to within 1.25V of
either supply pin, giving a 2.5VPP input signal range centered
between the supply pins. The input impedance of Figure 3 is
set to give a 50Ω input match. If the source does not require
a 50Ω match, remove RM and drive directly into the blocking
capacitor. The source will then see the 5kΩ load of the
biasing network. The gain resistor (RG) is AC coupled, giving
the circuit a DC gain of +1, which puts the non-inverting input
DC bias voltage (2.5V) on the output as well. The feedback
resistor value has been adjusted from the bipolar supply
condition to re-optimize for a flat frequency response in +5V
only, gain of +2, operation. On a single +5V supply, the
output voltage can swing to within 1.0V of either supply pin
while delivering more than 70mA output current giving 3V
output swing into 100Ω (8dBm maximum at a matched 50Ω
load). The circuit of Figure 3 shows a blocking capacitor
driving into a 50Ω output resistor then into a 50Ω load.
Alternatively, the blocking capacitor could be removed if the
load is tied to a supply midpoint or to ground if the DC current
+5V
0.1µF
+
6.8µF
10kΩ
0.1µF
0.1µF
10kΩ
50Ω
OPA684
50Ω Load
50Ω Source
0.1µF
DIS
RF
1.3kΩ
RG
1.3kΩ
VI
RM
52.3Ω
FIGURE 4. Inverting Single-Supply Test and Characterization Circuit.
required by the load is acceptable.
The circuits of Figure 3 and 4 show single-supply operation
at +5V. These same circuits may be used up to single
supplies of +12V with minimal change in the performance of
the OPA684.
+5V
0.1µF
50Ω Source
+
6.8µF
10kΩ
LOW-POWER VIDEO LINE DRIVER APPLICATIONS
0.1µF
VI
0.1µF
RM
50Ω
10kΩ
50Ω
OPA684
50Ω Load
DIS
RF
1.3kΩ
RG
1.3kΩ
0.1µF
FIGURE 3. Non-inverting Single-Supply Test and Characterization Circuit.
Figure 4 shows the AC coupled, single +5V supply, gain of
–1V/V circuit configuration used as a basis for the +5V
Typical Characteristics. In this case, the midpoint DC bias on
the non-inverting input is also decoupled with an additional
0.1µF decoupling capacitor. This reduces the source impedance at higher frequencies for the non-inverting input bias
current noise. This 2.5V bias on the non-inverting input pin
appears on the inverting input pin and, since RG is DC
blocked by the input capacitor, will also appear at the output
pin. One advantage to inverting operation is that since there
is no signal swing across the input stage, higher slew rates
and operation to even lower supply voltages is possible. To
retain a 1VPP output capability, operation down to a 3V
supply is allowed. At a +3V supply, the input stage is
saturated, but for the inverting configuration of a current
feedback amplifier, wideband operation is retained even
under this condition.
For low-power, video line driving, the OPA684 provides the
output current and linearity to support multiple load composite video signals. Figure 5 shows a typical ±5V supply video
line driver application. The improved 2nd-harmonic distortion
of the CFBplus architecture, along with the OPA684’s high
output current and voltage, gives exceptional differential gain
and phase performance for a low-power solution. As the
Typical Characteristics show, a single video load shows a
dG/dP of 0.04%/0.02°. Multiple loads may also be driven with
< 0.1%/0.1° dG/dP for up to 4 parallel video loads, where the
amplifier is driving an equivalent load of 37.5Ω.
+5V
VIDEOIN
Supply Decoupling not shown.
75Ω
75Ω
Coax 75Ω Load
OPA684
1kΩ
1kΩ
–5V
FIGURE 5. Gain of +2 Video Cable Driver.
OPA684
SBOS219D
DIS
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13
INVERTING SUMMING APPLICATIONS
SAW FILTER POST- AMPLIFIER
The OPA684 provides one of the most robust summing
operations available in a wideband op amp. Figure 6 shows
a typical inverting summing application where, in this case, 4
sources are summed through 500Ω gain resistors while also
including an 88.9Ω terminating impedance to present a 75Ω
input impedance to each source. The gain for each channel
is –2 to the output pin and –1 to the matched load. The
extremely low inverting input impedance of the CFBplus
architectures ensures noninteractive summing for all of the
channels. The amplifier bandwidth is largely independent of
variations in the gain setting elements, depending primarily
on the feedback resistor value instead. This type of circuit
may be used to sum numerous signals together or, where the
prior stages can be disabled, allow multiple channels to be
brought together with only the active channel passing on to
the output.
While SAW filters provide unmatched selectivity in a passive
filter element, this comes at the cost of significant insertion loss
for the desired signal. The OPA684 can provide a low-cost and
low-power post-amplifier over a wide range of gains due to the
CFBplus internal architecture. Figure 7 shows a 44MHz SAW
filter with 20dB insertion loss followed by an OPA684 operating
at a gain of 20V/V (26dB) providing a net gain of 1 (0dB) from
the input of the SAW filter to a matched 50Ω load. The circuit
shown also includes a simple bandpass around 44MHz to
reduce out-of-band noise. The gain for the circuit of Figure 7
ranges from 0dB at DC to 28dB at 44MHz and then back to
< 0dB above 200MHz. The LC elements in the gain circuit peak
the response slightly above a gain of 26dB—removing those
would give a broadband gain of 26dB.
+5V
DIS
500Ω
Supply Decoupling not shown.
IN1
75Ω
88.9Ω
75Ω Load
OPA684
500Ω
–2(IN1 + IN2 + IN3 + IN4)
IN2
1kΩ
88.9Ω
500Ω
IN3
–5V
88.9Ω
500Ω
IN4
88.9Ω
FIGURE 6. Gain of –2 Video Summing Amplifier.
+VS
+5V to +12V
PI
SAW
Filter
44MHz
20dB
Insertion
Loss
20kΩ
DIS
1000pF
1000pF
20kΩ
50Ω
OPA684
50Ω
PO
50Ω Load
1000pF
950Ω
PO
= 0dB at 44MHz
PI
50Ω
100pF
160nH
FIGURE 7. Single-Supply, High-Gain SAW Post-Amplifier.
14
OPA684
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SBOS219D
Figure 8 shows the small-signal frequency response for the
amplifier portion of this circuit, from the non-inverting input to
the output pin. This particular example is configured as a
single-supply circuit that will operate over a supply range from
+5V to +12V. Where higher frequencies or 3rd-order intercepts
are required, consider the OPA685, a very high bandwidth
(> 500MHz) current-feedback op amp.
BANDPASS SAW FILTER POST AMPLIFIER
30
27
the non-inverting converter input and the amplifier noninverting input. With an AC-coupled gain path, this +2.5V has
a gain of +1 to the output, putting the output at the DC
midpoint for the converter. The output then drives through an
isolating resistor (50Ω) to the inverting input of the converter,
which is further de-coupled by a 10pF external capacitance
to add to its 5pF input capacitance. This coupling network
provides a high frequency cutoff, while also giving a low
source impedance at high frequencies for the converter. The
gain for this circuit is set by adjusting RG to the desired value.
For a 2VPP maximum output driving the light load of Figure
9, the OPA684 will provide > 75dB SFDR through 5MHz (see
the Typical Characteristics).
Gain (dB)
44MHz
24
DESIGN-IN TOOLS
21
DEMONSTRATION FIXTURES
Two printed circuit boards (PCBs) are available to assist in
the initial evaluation of circuit performance using the OPA684
in its two package options. Both of these are offered free of
charge as unpopulated PCBs, delivered with a user's guide.
The summary information for these fixtures is shown in
Table I.
18
15
10
100
Frequency (MHz)
FIGURE 8. Bandpass SAW Filter Post-Amplifier.
PRODUCT
LOW POWER, ADC DRIVER
Where a low-power, single-supply, interface to a singleended input +5V ADC is required, the circuit of Figure 9 can
provide a very flexible, higher performance solution. Running
in an AC-coupled inverting mode allows the non-inverting
input to be used for the CM (Common-Mode) voltage from
the ADS825 converter. This midpoint reference biases both
PACKAGE
ORDERING
NUMBER
LITERATURE
NUMBER
SO-8
SOT23-6
DEM-OPA-SO-1A
DEM-OPA-SOT-1A
SBOU009
SBOU010
OPA684ID
OPA684IDBQ
TABLE I. Demonstration Fixtures by Package.
The demonstration fixtures can be requested at the Texas
Instruments web site (www.ti.com) through the OPA684
product folder.
RI
1.3kΩ
+5V
DIS
RG
2.5VDC
VI
50Ω
OPA684
VO
IN
ADS825
10-Bit
40MSPS
10pF
VO = –
1.3kΩ
RG
VI
50Ω
2Vp-p
Max
IN
+2.5V
CM
0.1µF
FIGURE 9. Low-Power, Single-Supply, ADC Driver.
OPA684
SBOS219D
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15
OPERATING SUGGESTIONS
SETTING RESISTOR VALUES TO OPTIMIZE BANDWIDTH
Any current-feedback op amp like the OPA684 can hold high
bandwidth over signal-gain settings with the proper adjustment of the external resistor values. A low-power part like the
OPA684 typically shows a larger change in bandwidth due to
the significant contribution of the inverting input impedance
to loop-gain changes as the signal gain is changed. Figure
10 shows a simplified analysis circuit for any current-feedback amplifier.
α
VO
iERR
Z(S) iERR
RF
RG
FIGURE 10. Current Feedback Transfer Function Analysis
Circuit.
The key elements of this current-feedback op amp model
are:
α ⇒ Buffer gain from the non-inverting input to the inverting input.
RI ⇒ Buffer output impedance.
iERR ⇒ Feedback error current signal.
Z(S) ⇒ Frequency dependent open loop transimpedance gain from iERR to VO .
The buffer gain is typically very close to 1.00 and is normally
neglected from signal gain considerations. It will, however, set
the CMRR for a single op amp differential amplifier configuration. For the buffer gain α < 1.0, the CMRR = –20 • log(1 – α).
The closed-loop input stage buffer used in the OPA684 gives
a buffer gain more closely approaching 1.00 and this shows up
in a slightly higher CMRR than any previous current feedback
op amp.
RI, the buffer output impedance, is a critical portion of the
bandwidth control equation. The OPA684 reduces this element to approximately 2.5Ω, using the loop gain of the local
input buffer stage. This significant reduction in output impedance, on very low power, contributes significantly to extending the bandwidth at higher gains.
A current-feedback op amp senses an error current in the
inverting node (as opposed to a differential input error voltage for a voltage-feedback op amp) and passes this on to the
output through an internal frequency dependent
transimpedance gain. The Typical Characteristics show this
open-loop transimpedance response. This is analogous to
16
R
α 1 + F
R
VO
α NG
G
=
=
VI
RF 1 + RF + RI NG
RF + RI 1 +
Z (S )
RG
1+
Z (S )
R
NG = 1 + F
R G
This is written in a loop-gain analysis format where the errors
arising from a non-infinite open-loop gain are shown in the
denominator. If Z(S) were infinite over all frequencies, the
denominator of Equation 1 would reduce to 1 and the ideal
desired signal gain shown in the numerator would be achieved.
The fraction in the denominator of Equation 1 determines the
frequency response. Equation 2 shows this as the loop-gain
equation.
(2)
Z (S )
= Loop Gain
RF + RI NG
VI
RI
the open-loop voltage gain curve for a voltage-feedback
op amp. Developing the transfer function for the circuit of
Figure 10 gives Equation 1:
(1)
If 20 • log(RF + NG • RI) were drawn on top of the open-loop
transimpedance plot, the difference between the two would
be the loop gain at a given frequency. Eventually, Z(S) rolls off
to equal the denominator of Equation 2, at which point the
loop gain has reduced to 1 (and the curves have intersected).
This point of equality is where the amplifier’s closed-loop
frequency response given by Equation 1 will start to roll off,
and is exactly analogous to the frequency at which the noise
gain equals the open-loop voltage gain for a voltage-feedback op amp. The difference here is that the total impedance
in the denominator of Equation 2 may be controlled separately from the desired signal gain (or NG).
The OPA684 is internally compensated to give a maximally
flat frequency response for RF = 1kΩ at NG = 2 on ±5V
supplies. That optimum value goes to 1.3kΩ on a single +5V
supply. Normally, with a current-feedback amplifier, it is
possible to adjust the feedback resistor to hold this bandwidth up as the gain is increased. The CFBplus architecture
has reduced the contribution of the inverting input impedance
to provide exceptional bandwidth to higher gains without
adjusting the feedback resistor value. The Typical Characteristics show the small-signal bandwidth over gain with a fixed
feedback resistor.
At very high gains, 2nd-order effects in the inverting output
impedance cause the overall response to peak up. If desired,
it is possible to retain a flat frequency response at higher
gains by adjusting the feedback resistor to higher values as
the gain is increased. See Figure 11 for the empirically
determined feedback resistor and resulting –3dB bandwidth
from gains of +2 to +100 to hold a < 0.5dB peaked response.
See Figure 12 for the measured frequency response curves
with the adjusted feedback resistor value. While the bandwidth for this low-power part does reduce at higher gains,
OPA684
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detailed view of the OPA684’s output drive capabilities.
Superimposing resistor load lines onto the plot shows the
available output voltage and current for specific loads.
BANDWIDTH AND RF OPTIMIZED vs GAIN
2000
200
Feedback Resistor (Ω)
1500
150
1250
RF
Left Scale
1000
100
Bandwidth (MHz)
Bandwidth
Right Scale
1750
750
500
50
2
5
10
20
50
100
Voltage Gain (V/V)
FIGURE 11. Bandwidth and RF Optimized vs Gain.
SMALL-SIGNAL RESPONSE WITH OPTIMIZED RF
3
G=5
Normalized Gain (dB)
0
G = 10
G=2
–3
G = 100
–6
G = 50
–9
G = 20
–1.2
10
100
200
Frequency (MHz)
FIGURE 12. Small-Signal Frequency Response with Optimized RF.
going over a 50:1 gain range gives only a factor of 3.5
bandwidth reduction. The 50MHz bandwidth at a gain of
100V/V is equivalent to a 5GHz gain-bandwidth product
voltage-feedback amplifier capability.
OUTPUT CURRENT AND VOLTAGE
The OPA684 provides output voltage and current capabilities
that can support the needs of driving doubly-terminated 50Ω
lines. For a 100Ω load at the gain of +2, (see Figure 1), the total
load is the parallel combination of the 100Ω load and the 2kΩ
total feedback network impedance. This 95Ω load will require
no more than 40mA output current to support the ±3.8V
minimum output voltage swing for 100Ω loads. This is well
under the specified minimum +130/–100mA specifications
over the full temperature range.
The specifications described above, though familiar in the
industry, consider voltage and current limits separately. In
many applications, it is the voltage • current, or V-I product,
which is more relevant to circuit operation. Refer to the
Output Current and Voltage Limitations curve in the Typical
Characteristics. The X and Y axes of this graph show the
zero-voltage output current limit and the zero-current output
voltage limit, respectively. The four quadrants give a more
The minimum specified output voltage and current over
temperature are set by worst-case simulations at the cold
temperature extreme. Only at cold startup will the output
current and voltage decrease to the numbers shown in the
Electrical Characteristic tables. As the output transistors
deliver power, their junction temperatures will increase, decreasing their VBEs (increasing the available output voltage
swing) and increasing their current gains (increasing the
available output current). In steady-state operation, the available output voltage and current will always be greater than
that shown in the over-temperature specifications since the
output stage junction temperatures will be higher than the
minimum specified operating ambient.
To maintain maximum output stage linearity, no output shortcircuit protection is provided. Normally, this will not be a
problem since most applications include a series-matching
resistor at the output that will limit the internal power dissipation if the output side of this resistor is shorted to ground.
However, shorting the output pin directly to the adjacent
positive power-supply pin (8-pin packages) will, in most
cases, destroy the amplifier. If additional short-circuit protection is required, consider a small-series resistor in the powersupply leads. This will, under heavy output loads, reduce the
available output voltage swing. A 5Ω series resistor in each
power-supply lead will limit the internal power dissipation to
less than 1W for an output short-circuit, while decreasing the
available output voltage swing only 0.25V for up to 50mA
desired load currents. Always place the 0.1µF power-supply
decoupling capacitors after these supply current limiting
resistors directly on the supply pins.
DRIVING CAPACITIVE LOADS
One of the most demanding and yet very common load
conditions for an op amp is capacitive loading. Often, the
capacitive load is the input of an Analog-to-Digital Converter
(ADC), including additional external capacitance which may
be recommended to improve ADC linearity. A high-speed,
high open-loop gain, amplifier like the OPA684 can be very
susceptible to decreased stability and closed-loop response
peaking when a capacitive load is placed directly on the
output pin. When the amplifier’s open-loop output resistance
is considered, this capacitive load introduces an additional
pole in the signal path that can decrease the phase margin.
Several external solutions to this problem have been suggested. When the primary considerations are frequency
response flatness, pulse response fidelity, and/or distortion,
the simplest and most effective solution is to isolate the
capacitive load from the feedback loop by inserting a series
isolation resistor between the amplifier output and the capacitive load. This does not eliminate the pole from the loop
response, but rather shifts it and adds a zero at a higher
frequency. The additional zero acts to cancel the phase lag
from the capacitive load pole, thus increasing the phase
margin and improving stability.
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17
The Typical Characteristics show the recommended RS vs
CLOAD and the resulting frequency response at the load. To
reduce the required value of RS, those curves show a slight
increase in the feedback resistor value and an added load of
250Ω to ground. The 1kΩ resistor shown in parallel with the
load capacitor is a measurement path and may be omitted.
Parasitic capacitive loads greater than 5pF can begin to
degrade the performance of the OPA684. Long PC board
traces, unmatched cables, and connections to multiple devices can easily cause this value to be exceeded. Always
consider this effect carefully, and add the recommended
series resistor as close as possible to the OPA684 output pin
(see Board Layout Guidelines).
DISTORTION PERFORMANCE
The OPA684 provides very low distortion in a low-power part.
The CFBplus architecture also gives two significant areas of
distortion improvement. First, in operating regions where the
2nd-harmonic distortion due to output stage nonlinearities is
very low (frequencies < 1MHz, low output swings into light
loads), the linearization at the inverting node provided by the
CFBplus design gives 2nd-harmonic distortions that extend
into the –90dBc region. Previous current-feedback amplifiers
have been limited to approximately –85dBc due to the
nonlinearities at the inverting input. The 2nd-area of distortion improvement comes in a distortion performance that is
largely gain independent. To the extent that the distortion at
a particular output power is output stage dependent, 3rdharmonics particularly, and to a lesser extent 2nd-harmonic
distortion, are constant as the gain is increased. This is due
to the constant loop gain versus signal gain provided by the
CFBplus design. As shown in the Typical Characteristics,
while the 3rd-harmonic is constant with gain, the 2nd-harmonic degrades at higher gains. This is largely due to board
parasitic issues. Slightly imbalanced load return currents will
couple into the gain resistor to cause a portion of the 2ndharmonic distortion. At high gains, this imbalance has more
gain to the output giving increased 2nd-harmonic distortion.
Relative to alternative amplifiers with < 2mA supply current,
the OPA684 holds much lower distortion at higher frequencies (> 5MHz) and to higher gains. Generally, until the
fundamental signal reaches very high frequency or power
levels, the 2nd-harmonic will dominate the distortion with a
lower 3rd-harmonic component. Focusing then on the 2nd
harmonic, increasing the load impedance improves distortion
directly. Remember that the total load includes the feedback
network—in the non-inverting configuration (see Figure 1)
this is the sum of RF + RG, while in the inverting configuration
it is just RF. Also, providing an additional supply decoupling
capacitor (0.1µF) between the supply pins (for bipolar operation) improves the 2nd-order distortion slightly (3dB to 6dB).
In most op amps, increasing the output voltage swing increases harmonic distortion directly. A low-power part like
the OPA684 includes quiescent boost circuits to provide the
full-power bandwidth shown in the Typical Characteristics.
These act to increase the bias in a very linear fashion only
when high slew rate or output power are required. This also
acts to actually reduce the distortion slightly at higher output
18
power levels. The Typical Characteristics show the 2ndharmonic holding constant from 500mVPP to 5VPP outputs,
while the 3rd harmonics actually decrease with increasing
output power.
The OPA684 has an extremely low 3rd-order harmonic
distortion, particularly for light loads and at lower frequencies. This also gives low 2-tone 3rd-order intermodulation
distortion, as shown in the Typical Characteristics. Since the
OPA684 includes internal power boost circuits to retain good
full-power performance at high frequencies and outputs, it
does not show a classical 2-tone, 3rd-order intermodulation
intercept characteristic. Instead, it holds relatively low and
constant 3rd-order intermodulation spurious levels over power.
The Typical Characteristics show this spurious level as a dBc
below the carrier at fixed center frequencies swept over
single-tone power at a matched 50Ω load. These spurious
levels drop significantly (> 12dB) for lighter loads than the
100Ω used in the 2-tone 3rd-order intermodulation plot.
Converter inputs for instance will see < –82dBc 3rd-order
spurious to 10MHz for full-scale inputs. For even lower 3rdorder intermodulation distortion to much higher frequencies,
consider the OPA685.
NOISE PERFORMANCE
Wideband current-feedback op amps generally have a higher
output noise than comparable voltage-feedback op amps.
The OPA684 offers an excellent balance between voltage
and current noise terms to achieve low output noise in a low
power amplifier. The inverting current noise (17pA/√Hz) is
lower than most other current-feedback op amps, while the
input voltage noise (3.7nV/√Hz) is lower than any unity-gain
stable, comparable slew rate, voltage-feedback op amp. This
low input voltage noise was achieved at the price of higher
non-inverting input current noise (9.4pA/√Hz). As long as the
AC source impedance looking out of the non-inverting node
is less than 200Ω, this current noise will not contribute
significantly to the total output noise. The op amp input
voltage noise and the two input current noise terms combine
to give low output noise under a wide variety of operating
conditions. Figure 13 shows the op amp noise analysis
model with all the noise terms included. In this model, all
noise terms are taken to be noise voltage or current density
terms in either nV/√Hz or pA/√Hz.
ENI
EO
OPA684
RS
IBN
ERS
RF
√ 4kTRS
4kT
RG
RG
IBI
√ 4kTRF
4kT = 1.6E –20J
at 290°K
FIGURE 13. Op Amp Noise Analysis Model.
OPA684
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The total output spot noise voltage can be computed as the
square root of the sum of all squared output noise voltage
contributors. Equation 3 shows the general form for the
output noise voltage using the terms shown in Figure 13.
(3)
2
2
EO = ENI2 + (IBNR S ) + 4kTRS GN2 + (IBIRF ) + 4kTRF GN
Dividing this expression by the noise gain (GN = (1 + RF/RG))
will give the equivalent input referred spot noise voltage at
the non-inverting input, as shown in Equation 4.
(4)
2
I R
4kTRF
2
EN = ENI2 + (IBNR S ) + 4kTRS + BI F +
GN
GN
Evaluating these two equations for the OPA684 circuit and
component values (see Figure 1) will give a total output spot
noise voltage of 13.3nV/√Hz and a total equivalent input spot
noise voltage of 6.7nV/√Hz. This total input referred spot
noise voltage is higher than the 3.7nV/√Hz specification for
the op amp voltage noise alone. This reflects the noise
added to the output by the inverting current noise times the
feedback resistor. As the gain is increased, this fixed output
noise power term contributes less to the total output noise
and the total input referred voltage noise given by Equation
3 will approach just the 3.7nV/√Hz of the op amp itself. For
example, going to a gain of +20 in the circuit of Figure 1,
adjusting only the gain resistor to 52.3Ω, will give a total input
referred noise of 3.9nV/√Hz . A more complete description of
op amp noise analysis can be found in the TI application note
SBOA066, Noise Analysis for High Speed Op Amps, located
at www.ti.com.
While the last term, the inverting bias current error, is
dominant in this low-gain circuit, the input offset voltage will
become the dominant DC error term as the gain exceeds
5V/V. Where improved DC precision is required in a highspeed amplifier, consider the OPA642 single and OPA2822
dual voltage-feedback amplifiers.
DISABLE OPERATION
The OPA684 provides an optional disable feature that may
be used to reduce system power when amplifier operation is
not required. If the VDIS control pin is left unconnected, the
OPA684 will operate normally. To disable, the VDIS control
pin must be asserted LOW. Figure 14 shows a simplified
internal circuit for the disable control feature.
In normal operation, base current to Q1 is provided through
the 250kΩ resistor, while the emitter current through the
40kΩ resistor sets up a voltage drop that is inadequate to
turn on the two diodes in Q1’s emitter. As VDIS is pulled LOW,
additional current is pulled through the 40kΩ resistor eventually turning on these two diodes. At this point, any further
current pulled out of VDIS goes through those diodes holding
the emitter-base voltage of Q1 at approximately 0V. This
shuts off the collector current out of Q1, turning the amplifier
off. The supply current in the disable mode is only what is
required to operate the circuit of Figure 14.
+VS
40kΩ
Q1
DC ACCURACY AND OFFSET CONTROL
A current-feedback op amp like the OPA684 provides exceptional bandwidth in high gains, giving fast pulse settling but
only moderate DC accuracy. The Electrical Characteristics
show an input offset voltage comparable to high slew rate
voltage-feedback amplifiers. The two input bias currents,
however, are somewhat higher and are unmatched. Whereas
bias current cancellation techniques are very effective with
most voltage-feedback op amps, they do not generally reduce the output DC offset for wideband current-feedback op
amps. Since the two input bias currents are unrelated in both
magnitude and polarity, matching the source impedance
looking out of each input to reduce their error contribution to
the output is ineffective. Evaluating the configuration of
Figure 1, using worst case +25°C input offset voltage and the
two input bias currents, gives a worst case output offset
range equal to:
±(GN • VOS) + (IBN • RS/2 • GN) ± (IBI • RF)
= ±(2 • 3.5mV) ± (10µA • 25Ω • 2) ± (1kΩ • 16µA)
= ±7mV + 0.5mV ± 16mV
= ±23.5mV
25kΩ
VDIS
250kΩ
IS
Control
–VS
FIGURE 14. Simplified Disable Control Circuit.
When disabled, the output and input nodes go to a high
impedance state. If the OPA684 is operating at a gain of +1
(with a 1kΩ feedback resistor still required for stability), it will
show a very high impedance (1.7pF || 1MΩ) at the output and
exceptional signal isolation. If operating at a gain greater
than +1, the total feedback network resistance (RF + RG) will
appear as the impedance looking back into the output, but
the circuit will still show very high forward and reverse
isolation. If configured as an inverting amplifier, the input and
output will be connected through the feedback network
resistance (RF + RG) giving relatively poor input to output
isolation.
where GN = non-inverting signal gain
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19
The OPA684 provides very high power gain on low quiescent
current levels. When disabled, internal high impedance nodes
discharge slowly that, with the exceptional power gain provided, give a self-powering characteristic that leads to a slow
turn-off characteristic. Typical turn-off times to rated 100µA
disabled supply current are 4ms. Turn-on times are very
fast—less than 40ns.
b)
Minimize the distance (< 0.25") from the power-supply
pins to high-frequency 0.1µF decoupling capacitors. At
the device pins, the ground and power plane layout
should not be in close proximity to the signal I/O pins.
Avoid narrow power and ground traces to minimize
inductance between the pins and the decoupling capacitors. The power-supply connections should always be
decoupled with these capacitors. An optional supply decoupling capacitor across the two power supplies (for
bipolar operation) will improve 2nd-harmonic distortion
performance. Larger (2.2µF to 6.8µF) decoupling capacitors, effective at lower frequencies, should also be
used on the main supply pins. These may be placed
somewhat farther from the device and may be shared
among several devices in the same area of the PC
board.
c)
Careful selection and placement of external components will preserve the high-frequency performance
of the OPA684. Resistors should be a very low reactance type. Surface-mount resistors work best and allow
a tighter overall layout. Metal film and carbon composition axially-leaded resistors can also provide good highfrequency performance. Again, keep their leads and PC
board trace length as short as possible. Never use
wirewound type resistors in a high-frequency application. Since the output pin and inverting input pin are the
most sensitive to parasitic capacitance, always position
the feedback and series output resistors, if any, as close
as possible to the output pin. Other network components, such as non-inverting input termination resistors,
should also be placed close to the package. Where
double-side component mounting is allowed, place the
feedback resistor directly under the package on the
other side of the board between the output and inverting
input pins. The frequency response is primarily determined by the feedback resistor value, as described
previously. Increasing its value will reduce the peaking
at higher gains, while decreasing it will give a more
peaked frequency response at lower gains. The 1kΩ
feedback resistor used in the electrical characteristics at
a gain of +2 on ±5V supplies is a good starting point for
design. Note that a 1kΩ feedback resistor, rather than a
direct short, is required for the unity-gain follower application. A current-feedback op amp requires a feedback
resistor even in the unity gain follower configuration to
control stability.
d)
Connections to other wideband devices on the board
may be made with short direct traces or through onboard transmission lines. For short connections, consider the trace and the input to the next device as a
lumped capacitive load. Relatively wide traces (50mils to
100mils) should be used, preferably with ground and
power planes opened up around them. Estimate the
total capacitive load and set RS from the plot of recommended RS vs CLOAD. Low parasitic capacitive loads
(< 5pF) may not need an RS since the OPA684 is
THERMAL ANALYSIS
The OPA684 will not require external heatsinking for most
applications. Maximum desired junction temperature will set
the maximum allowed internal power dissipation as described below. In no case should the maximum junction
temperature be allowed to exceed 175°C.
Operating junction temperature (TJ) is given by TA + PD • θJA.
The total internal power dissipation (PD) is the sum of
quiescent power (PDQ) and additional power dissipated in the
output stage (PDL) to deliver load power. Quiescent power is
simply the specified no-load supply current times the total
supply voltage across the part. PDL will depend on the
required output signal and load but would, for a grounded
resistive load, be at a maximum when the output is fixed at
a voltage equal to 1/2 of either supply voltage (for equal
bipolar supplies). Under this condition PDL = VS2/(4 • RL),
where RL includes feedback network loading.
Note that it is the power in the output stage and not into the
load that determines internal power dissipation.
As an absolute worst-case example, compute the maximum
TJ using an OPA684IDBV (SOT23-6 package) in the circuit
of Figure 1 operating at the maximum specified ambient
temperature of +85°C and driving a grounded 100Ω load.
PD = 10V • 1.85mA + 52 /(4 • (100Ω || 2kΩ)) = 84mW
Maximum TJ = +85°C + (0.084W • 150°C/W) = 98°C.
This maximum operating junction temperature is well below
most system level targets. Most applications will be lower
than this since an absolute worst-case output stage power
was assumed in this calculation.
BOARD LAYOUT GUIDELINES
Achieving optimum performance with a high-frequency amplifier like the OPA684 requires careful attention to board
layout parasitics and external component types. Recommendations that will optimize performance include:
a)
20
Minimize parasitic capacitance to any AC ground for
all of the signal I/O pins. Parasitic capacitance on the
output and inverting input pins can cause instability; on
the non-inverting input, it can react with the source
impedance to cause unintentional bandlimiting. To reduce unwanted capacitance, a window around the signal I/O pins should be opened in all of the ground and
power planes around those pins. Otherwise, ground and
power planes should be unbroken elsewhere on the
board.
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nominally compensated to operate with a 2pF parasitic
load. If a long trace is required, and the 6dB signal loss
intrinsic to a doubly-terminated transmission line is acceptable, implement a matched impedance transmission line using microstrip or stripline techniques (consult
an ECL design handbook for microstrip and stripline
layout techniques). A 50Ω environment is normally not
necessary onboard, and in fact a higher impedance
environment will improve distortion, as shown in the
distortion versus load plots. With a characteristic board
trace impedance defined based on board material and
trace dimensions, a matching series resistor into the
trace from the output of the OPA684 is used, as well as
a terminating shunt resistor at the input of the destination device. Remember also that the terminating impedance will be the parallel combination of the shunt resistor
and the input impedance of the destination device; this
total effective impedance should be set to match the
trace impedance. The high output voltage and current
capability of the OPA684 allows multiple destination
devices to be handled as separate transmission lines,
each with their own series and shunt terminations. If the
6dB attenuation of a doubly-terminated transmission line
is unacceptable, a long trace can be series-terminated
at the source end only. Treat the trace as a capacitive
load in this case and set the series resistor value as
shown in the plot of RS vs CLOAD. This will not preserve
signal integrity as well as a doubly-terminated line. If the
input impedance of the destination device is low, there
will be some signal attenuation due to the voltage divider
formed by the series output into the terminating impedance.
e)
INPUT AND ESD PROTECTION
The OPA684 is built using a very high-speed complementary
bipolar process. The internal junction breakdown voltages
are relatively low for these very small geometry devices.
These breakdowns are reflected in the Absolute Maximum
Ratings table where an absolute maximum 13V across the
supply pins is reported. All device pins have limited ESD
protection using internal diodes to the power supplies, as
shown in Figure 15.
These diodes provide moderate protection to input overdrive
voltages above the supplies as well. The protection diodes
can typically support 30mA continuous current. Where higher
currents are possible (e.g. in systems with ±15V supply parts
driving into the OPA684), current limiting series resistors
should be added into the two inputs. Keep these resistor
values as low as possible since high values degrade both
noise performance and frequency response.
+V CC
External
Pin
Internal
Circuitry
–V CC
FIGURE 15. Internal ESD Protection.
Socketing a high-speed part like the OPA684 is not
recommended. The additional lead length and pin-topin capacitance introduced by the socket can create an
extremely troublesome parasitic network which can make
it almost impossible to achieve a smooth, stable frequency response. Best results are obtained by soldering
the OPA684 onto the board.
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21
Revision History
DATE
6/09
7/08
REVISION
D
C
PAGE
SECTION
DESCRIPTION
2
Related Products
4
Electrical Characteristics
Replaced OPA685 (obsolete) with OPA695 family.
8
Typical Characteristics
Changed Open-Loop Transimpedance Gain and Phase plot to fix typo.
9
Typical Characteristics
Changed Closed-Loop Output Impedance vs Frequency plot to fix typo.
2
Abs Max Ratings
3, 4
Electrical Characteristics
Added missing value (0.006) to Closed-Loop Output Impedance parameter.
Changed Storage Temperature Range from −40°C to +125C to
−65°C to +125C.
Added Minimum Operating Voltage Range to Power-Supply subsection.
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
22
OPA684
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SBOS219D
PACKAGE OPTION ADDENDUM
www.ti.com
14-Oct-2022
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
Samples
(4/5)
(6)
OPA684ID
ACTIVE
SOIC
D
8
75
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 85
OPA
684
Samples
OPA684IDBVR
ACTIVE
SOT-23
DBV
6
3000
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 85
B84
Samples
OPA684IDBVT
ACTIVE
SOT-23
DBV
6
250
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 85
B84
Samples
OPA684IDR
ACTIVE
SOIC
D
8
2500
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 85
OPA
684
Samples
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of
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