SN65HVDA100-Q1
SLIS128D – NOVEMBER 2011 – REVISED APRIL 2022
SN65HVDA100-Q1 LIN Physical Interface
1 Features
3 Description
•
The SN65HVDA100-Q1 device is a Local
Interconnect Network (LIN) physical interface, which
integrates the serial transceiver with wakeup and
protection features. The LIN bus is a single-wire
bidirectional bus typically used for low-speed invehicle networks using data rates from 2.4 kbps to
20 kbps. The LIN protocol output data stream on
TXD is converted by the SN65HVDA100-Q1 into
the LIN bus signal through a current-limited waveshaping driver as outlined by the LIN Physical Layer
Specification and ISO 17987. The receiver converts
the data stream from the LIN bus and outputs the data
stream through RXD. The LIN bus has two states:
dominant state (voltage near ground) and recessive
state (voltage near battery). In the recessive state, the
LIN bus is pulled high by the internal pullup resistor
(30 kΩ) and series diode, so no external pullup
components are required for responder applications.
Commander applications require an external pullup
resistor (1 kΩ) plus a series diode per the LIN
specification.
•
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•
AEC-Q100 (Grade 1) qualified for automotive
applications
Compliant with LIN 2.0, LIN 2.1, LIN 2.2, LIN
2.2A, and ISO/DIS 17987-4 electrical physical
layer (EPL) specification
Extended operation with supply from 5 V to 27 V
DC
LIN Transmits speed up to 20-kbps (LIN specified
maximum), high-speed receive capable
Sleep mode: ultra-low current consumption allows
wake-up events from:
– LIN bus
– wake-up through EN
Wake-up request on RXD pin
Wake-up source recognition on TXD pin
Interfaces to MCU with 5-V or 3.3-V I/O pins
High electromagnetic compatibility (EMC)
Control of external voltage regulator (INH Pin)
Supports ISO9141 (K-line)
ESD protection to ±12 kV (human body model) on
LIN pin
LIN pin handles voltage from –27 V to 45 V (short
to battery or ground)
Survives transient damage in automotive
environment (ISO 7637)
Undervoltage protection on VSUP
TXD dominant state time-out protection
Prevention of false wakeups with false wake-up
lockout
Thermal shutdown
Unpowered node or ground disconnection failsafe
at system level, node does not disturb bus (no load
on bus)
2 Applications
•
•
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Automotive
Industrial sensing
White goods distributed control
Device Information
PART NUMBER
SN65HVDA100-Q1
(1)
PACKAGE(1)
BODY SIZE (NOM)
SOIC (8)
4.90 mm × 3.91 mm
For all available packages, see the orderable addendum at
the end of the data sheet.
VSUP
RXD
1
8
INH
7
VSUP
6
LIN
5
GND
VSUP/2
Receiver
EN
2
Filter
Wake up
State
INH Control
NWAKE 3
TXD 4
30lQ
Filter
Fault Detection
and Protection
Dominant State
Timeout
Driver with
Slope Control
SN65HVDA100-Q1 Block Diagram
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
SN65HVDA100-Q1
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SLIS128D – NOVEMBER 2011 – REVISED APRIL 2022
Table of Contents
1 Features............................................................................1
2 Applications..................................................................... 1
3 Description.......................................................................1
4 Description (continued).................................................. 2
5 Revision History.............................................................. 3
6 Pin Configuration and Functions...................................4
7 Specifications.................................................................. 5
7.1 Absolute Maximum Ratings(1) (2) ................................5
7.2 ESD Ratings............................................................... 5
7.3 Recommended Operating Conditions.........................5
7.4 Thermal Information....................................................6
7.5 Electrical Characteristics.............................................6
7.6 Switching Characteristics............................................8
7.7 Dissipation Ratings..................................................... 9
7.8 Typical Characteristics.............................................. 12
8 Parameter Measurement Information.......................... 13
9 Detailed Description......................................................14
9.1 Overview................................................................... 14
9.2 Functional Block Diagram......................................... 14
9.3 Feature Description...................................................14
9.4 Device Functional Modes..........................................18
10 Application and Implementation................................ 21
10.1 Application Information........................................... 21
10.2 Typical Application.................................................. 21
11 Power Supply Recommendations..............................22
12 Layout...........................................................................23
12.1 Layout Guidelines................................................... 23
12.2 Layout Example...................................................... 24
13 Device and Documentation Support..........................25
13.1 Documentation Support.......................................... 25
13.2 Receiving Notification of Documentation Updates..25
13.3 Support Resources................................................. 25
13.4 Trademarks............................................................. 25
13.5 Electrostatic Discharge Caution..............................25
13.6 Glossary..................................................................25
14 Mechanical, Packaging, and Orderable
Information.................................................................... 25
4 Description (continued)
In sleep mode, low quiescent current is needed even though the wake-up circuits remain active and allow for
remote wake up through the LIN bus or local wake up through the NWake or EN pins.
The SN65HVDA100-Q1 has been designed for operation in the harsh automotive environment. The device
also prevents back-feed current through LIN to the supply input in case of a ground shift or supply voltage
disconnection. The device also features undervoltage, overtemperature, and loss-of-ground protection. In the
event of a fault condition, the transmitter is immediately switched off and remains off until the fault condition is
removed.
2
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5 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision C (July 2015) to Revision D (April 2022)
Page
• Changed the Features list ..................................................................................................................................1
• Changed all instances of legacy terminology to commander and responder where mentioned.........................1
• Replaced LIN 2.1 with ISO 17987-4 in the Absolute Maximum Ratings table....................................................5
• Added HBM and CDM classification levels to the ESD Ratings table ............................................................... 5
• Replaced LIN 2.1 with ISO 17987-4 in the Recommended Operating Conditions table.................................... 5
• Replaced LIN 2.1 with ISO 17987-4 in the Electrical Characteristics table........................................................ 6
• Deleted test Conditions for VSUP in the Electrical Characteristics table............................................................. 6
• Replaced LIN 2.1 with ISO 17987-4 in the Switching Characteristics table....................................................... 8
• Changed the Application hint to a Note in the TXD Dominant State Timeout section...................................... 16
• Changed the Application hint to a Note in the Standby Mode section..............................................................19
• Changed the Application hint to a Note in the Mode Transitions section..........................................................20
Changes from Revision B (January 2014) to Revision C (July 2015)
Page
• Added Pin Configuration and Functions section, ESD Ratings table, Feature Description section, Device
Functional Modes, Application and Implementation section, Power Supply Recommendations section, Layout
section, Device and Documentation Support section, and Mechanical, Packaging, and Orderable Information
section ............................................................................................................................................................... 1
Changes from Revision A (January 2013) to Revision B (January 2014)
Page
• Added new Mode Transitions section, including a new figure.......................................................................... 20
• Revised the application schematic diagram..................................................................................................... 21
Changes from Revision * (November 2011) to Revision A (January 2013)
Page
• Deleted -03V to 45V from the 1.5 row in the abs max table, units column......................................................... 5
• Changed added Delta and corrected Hysteresis in Electrical Characteristics table, row 4.4 and changed the
TYP column from 4.5 to 0.2................................................................................................................................ 6
• Deleted rows 9.1 and 9.2 from the Electrical Characteristics table.................................................................... 6
• Added Minimum to the statement in parens in front of dominant, row 11.9 of the Switching Characteristics
table.................................................................................................................................................................... 8
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6 Pin Configuration and Functions
RXD
EN
NWake
TXD
1
8
2
7
3
6
4
5
INH
VSUP
LIN
GND
Figure 6-1. D Package, 8-Pin SOIC
(Top View)
Table 6-1. Pin Functions
PIN
NAME
4
NO.
TYPE
DESCRIPTION
EN
2
I
GND
5
GND
Enable input
INH
8
O
Inhibit controls external voltage regulator with inhibit input
LIN
6
I/O
LIN bus single-wire transmitter and receiver
NWake
3
I
High-voltage input for device wake up
RXD
1
O
RXD output (open-drain) interface reporting state of LIN bus voltage
TXD
4
I
TXD input interface to control state of LIN output
VSUP
7
Supply
Ground
Device supply voltage (connected to battery in series with external reverse blocking diode)
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7 Specifications
7.1 Absolute Maximum Ratings(1) (2)
MIN
MAX
UNIT
–0.3
45
V
LIN input voltage
–27
45
V
NWake input voltage (through serial resistor ≥ 2 kΩ)
–0.3
45
V
–50
2
mA
–0.3
Vsup + 0.3
V
VSUP
Supply line supply voltage (ISO 17987-4 Param 11)
VLIN
VNWAKE
IO
Output current
VINH
INH voltage
VLogic
Logic pin voltage
–0.3
5.5
V
TA
Operational free-air (ambient) temperature
–40
125
°C
TJ
Junction temperature
–40
150
°C
TLEAD
Lead temperature (soldering, 10 seconds)
260
°C
Tstg
Storage temperature
150
°C
(1)
(2)
RXD, TXD, EN
–65
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress
ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under
Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device
reliability.
All voltage values are with respect to GND.
7.2 ESD Ratings
VALUE
V(ESD)
Electrostatic discharge
All pins
HBM ESD classification level
3A
±4000
LIN bus pin(2)
Human body model (HBM), per AEC
HBM ESD classification level
Q100-002(1)
3B
±12000
NWake pin(3)
HBM ESD classification level
3B
±11000
Charged device model (CDM), per AEC Q100-011(1)
CDM ESD classification level C6
(1)
(2)
(3)
UNIT
V
±1500
AEC Q100-002 indicates that HBM stressing shall be in accordance with the ANSI/ESDA/JEDEC JS-001 specification.
Test method based upon AEC-Q100-002, LIN bus pin stressed with respect to GND.
Test method based upon AEC-Q100-002, NWake pin stressed with respect to GND.
7.3 Recommended Operating Conditions
MIN
MAX
VSUP
Supply line supply voltage (ISO 17987-4 Param 10)
5
27
UNIT
V
VLIN
LIN input voltage
0
18
V
VNWake
NWake input voltage
0
27
V
VINH
INH voltage
0
27
V
VLogic
Logic voltage
0
5.25
V
TA
Operational free-air temperature (see Section 7.4)
–40
125
°C
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7.4 Thermal Information
SN65HVDA100-Q1
THERMAL
METRIC(1)
D (SOIC)
UNIT
8 PINS
RθJA
Junction-to-ambient thermal resistance
112.5
°C/W
RθJC(top)
Junction-to-case (top) thermal resistance
66.3
°C/W
RθJB
Junction-to-board thermal resistance
52.9
°C/W
ψJT
Junction-to-top characterization parameter
19.3
°C/W
ψJB
Junction-to-board characterization parameter
52.4
°C/W
(1)
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report, SPRA953.
7.5 Electrical Characteristics
VSUP = 5V to 27 V, TJ = –40°C to 150°C (unless otherwise noted)
MIN
TYP(1)
MAX
5
14
27
Normal and standby modes
7
14
18
Sleep mode
7
12
18
PARAMETER
TEST CONDITIONS
UNIT
VSUP SUPPLY
VSUP
Operational supply
voltage (ISO 17987-4
Param 10)(2)
VSUP
Nominal supply
voltage (ISO 17987-4
Param 10)
UVSUP
Undervoltage VSUP threshold
UVHYS
Delta hysteresis voltage for VSUP undervoltage threshold
ISUP
Supply current
4.35
4.65
0.2
V
V
V
V
Normal mode, EN = high, Bus dominant (total
bus load where RLIN ≥ 500 Ω and CLIN ≤ 10
nF (see Figure 8-1 )(3), INH = VSUP, NWake =
VSUP
1.2
7.5
mA
Standby mode, EN = low, Bus dominant (total
bus load where RLIN ≥ 500 Ω and CLIN ≤ 10
nF (see Figure 8-1)(3), INH = VSUP, NWake =
VSUP
1
2.1
mA
Normal mode, EN = high, Bus recessive, LIN
= VSUP, INH = VSUP, NWake = VSUP
450
775
μA
Standby mode, EN = low, Bus recessive, LIN
= VSUP, INH = VSUP, NWake = VSUP
450
775
μA
10
20
μA
30
μA
5.5
V
Sleep mode, 7 V < VSUP ≤ 14 V,
LIN = VSUP, NWake = VSUP, EN = 0 V, TXD
and RXD floating
Sleep mode, 14 V < VSUP < 27 V,
LIN = VSUP, NWake = VSUP, EN = 0 V, TXD
and RXD floating
RXD OUTPUT PIN (OPEN DRAIN)
VO
Output voltage(4)
IOL
Low-level output
current, open drain
LIN = 0 V, RXD = 0.4 V
3.5
IIKG
Leakage current, highLIN = VSUP, RXD = 5 V
level
–5
–0.3
mA
0
5
μA
TXD INPUT/OUTPUT PIN
6
VIL
Low-level input voltage
–0.3
0.8
V
VIH
High-level input voltage
2
5.5
V
VIT
Input threshold hysteresis voltage
30
500
mV
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7.5 Electrical Characteristics (continued)
VSUP = 5V to 27 V, TJ = –40°C to 150°C (unless otherwise noted)
PARAMETER
TEST CONDITIONS
Pulldown resistor
IIL
Low-level input
leakage current
TXD = Low
ITXD_Wake
Local wake up source
re recognition TXD
open drain drive
Standby mode after a local wake up event,
VLIN = VSUP, NWake = 0 V,
TXD = 1 V
MIN
TYP(1)
MAX
UNIT
125
350
800
kΩ
–5
0
5
μA
1.3
4.6
8
mA
LIN PIN (REFERENCED TO VSUP)
VOH
High-level output
voltage
LIN recessive, TXD = high, IO = 0 mA,
VSUP = 14 V
VOL
Low-level output
voltage
LIN dominant, TXD = low, IO = 40 mA,
VSUP = 14 V
IL
Limiting current (ISO
17987-4 Param 12)
TXD = 0 V, VLIN = 7 V to 27 V
ILKG
ILKG
Leakage current, loss
of supply (ISO
17987-4 Param 16)
VIL
Low-level input voltage
LIN dominant (including LIN dominant for
(ISO 17987-4 Param
wake up)
17)
VIH
High-level input
voltage (ISO 17987-4
Param 18)
LIN recessive
VBUS_CNT
Receiver center
threshold (ISO
17987-4 Param 19)
VBUS_CNT = (VIL + VIH) / 2
VHYS
Hysteresis voltage
(ISO 17987-4 Param
20)
VHYS = (VIL - VIH)
Serial diode in LIN
termination pull up
path (ISO 17987-4
Param 21)
By design and characterization
DIODE
40
Pullup current source
to VSUP
200
V
mA
mA
20
GND = VSUP , VSUP = 12 V,
0 V < VLIN < 18 V
–5
5
–1
1
7 V < LIN ≤ 12 V, VSUP = GND
5
12 V < LIN ≤ 18 V, VSUP = GND
10
0.4 × VSUP
0.6 × VSUP
0.475 x VSUP
Sleep mode, VSUP = 14 V, LIN = GND
μA
mA
μA
V
V
0.5 × VSUP
0.05 × VSUP
Pullup resistor to VSUP
RRESPONDER (ISO 17987-4 Param
Normal and standby modes
26)
RSLEEP
90
–1
Receiver leakage
LIN ≥ VSUP, 7 ≤ VSUP ≤18 V, Driver off
current, recessive (ISO
LIN = VSUP, driver off
17987-4 Param 14)
Leakage current, loss
of ground (ISO
17987-4 Param 15)
V
0.2 × VSUP
Receiver leakage
current, dominant (ISO LIN = 0 V, 7 V ≤VSUP ≤ 18 V, Driver off
17987-4 Param 13)
ILKG
VSERIAL_
VSUP – 1
0.525 x VSUP
V
0.175 × VSUP
V
0.4
0.7
1.0
V
20
30
60
kΩ
–2
–20
μA
–0.3
0.8
V
2
5.5
V
30
500
mV
EN INPUT PIN
VIL
Low-level input voltage
VIH
High-level input
voltage
Vhys
Hysteresis voltage
By design and characterization
Pulldown resistor
IIL
Low-level input current EN = Low
125
350
800
kΩ
–5
0
5
μA
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7.5 Electrical Characteristics (continued)
VSUP = 5V to 27 V, TJ = –40°C to 150°C (unless otherwise noted)
PARAMETER
TEST CONDITIONS
TYP(1)
MAX
25
50
Ω
0
5
μA
–0.3
VSUP – 3.3
V
VSUP – 1
VSUP + 0.3
V
MIN
UNIT
INH OUTPUT PIN
RDS(on)
ON-state resistance
Between VSUP and INH, INH = 2-mA drive,
Normal or standby mode
IIKG
Leakage current
Low-power mode, 0 < INH < VSUP
–5
NWAKE INPUT PIN
VIL
Low-level input voltage
VIH
High-level input
voltage
IIKG
Pullup current
NWake = 0 V
Leakage current
VSUP = NWake
–45
–10
–2
μA
–5
0
5
μA
AC CHARACTERISTICS
Duty cycle 1(5) (ISO
17987-4 Param 27)
D1
2(5)
Duty cycle
(ISO
17987-4 Param 28)
D2
3(5)
Duty cycle
(ISO
17987-4 Param 29)
D3
4(5)
Duty cycle
(ISO
17987-4 Param 30)
D4
(1)
(2)
(3)
(4)
(5)
THREC(max) = 0.744 × VSUP, THDOM(maximum) =
0.581 × VSUP,
VSUP = 7 V to 18 V, tBIT = 50 μs (20 kbps),
D1 = tBus_rec(min)/ (2 × tBIT) (see Figure 7-1)
0.396
THREC(min) = 0.422 × VSUP,
THDOM(min) = 0.284 × VSUP,
VSUP = 7.6 V to 18 V,
tBIT = 50 μs (20 kbps),
D2 = tBus_rec(max)/ (2 × tBIT) (see Figure 7-1)
THREC(max) = 0.778 × VSUP,
THDOM(max) = 0.616 × VSUP,
VSUP = 7 V to 18 V,
tBIT = 96 μs (10.4 kbps),
D3 = tBus_rec(min)/ (2 × tBIT) (see Figure 7-1)
0.581
0.417
THREC(min) = 0.389 × VSUP,
THDOM(min) = 0.251 × VSUP,
VSUP = 7.6 V to 18 V,
tBIT = 96 μs (10.4 kbps),
D4 = tBus_rec(max)/ (2 × tBIT) (see Figure 7-1)
0.59
Typical values are given for VSUP = 14 V at 25°C, except for low power mode where typical values are given for VSUP = 12 V at 25°C.
All voltages are defined with respect to ground; positive currents flow into the SN65HVDA100-Q1 device.
In the dominant state, the supply current increases as the supply voltage increases due to the integrated LIN responder termination
resistance. At higher voltages the majority of supply current is through the termination resistance. The minimum resistance of the
LIN responder termination is 20 kΩ, so the maximum supply current attributed to the termination is:ISUP (dom) max termination ≉ (VSUP –
(VLIN_Dominant + 0.7 V) / 20 kΩ.
RXD pin output is open drain. Output voltage is through external pullup resistance to logic supply of the system and impedance of the
RXD pin.
Duty cycles: LIN driver bus load conditions (CLINBUS, RLINBUS): Load1 = 1 nF, 1 kΩ; Load2 = 10 nF, 500 Ω. Duty cycles 3 and 4 are
defined for 10.4-kbps operation. The SN65HVDA100-Q1 also meets these lower data rate requirements, while it is capable of the
higher speed 20-kbps operation as specified by duty cycles 1 and 2. SAEJ2602 derives propagation delay equations from the LIN 2.0
duty cycle definitions, for details see the SAEJ2602 specification.
7.6 Switching Characteristics
over operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
AC CHARACTERISTICS
8
trx_pdr
Receiver rising propagation delay
time (ISO 17987-4 Param 31)
RRXD = 2.4 kΩ, CRXD = 20 pF
(see Figure 7-2 and Figure 8-1)
6
μs
trx_pdf
Receiver falling propagation delay
time (ISO 17987-4 Param 31)
RRXD = 2.4 kΩ, CRXD = 20 pF
(see Figure 7-2 and Figure 8-1)
6
μs
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7.6 Switching Characteristics (continued)
over operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
trx_sym
Symmetry of receiver propagation
delay time (ISO 17987-4 Param 32)
Rising edge with respect to falling
edge
(trx_sym = trx_pdf - trx_pdr) RRXD = 2.4
kΩ,
CRXD = 20 pF (see Figure 7-2 and
Figure 8-1)
tNWake
NWake filter time for local wakeup
See Figure 7-6
25
tLINBUS
LIN wake-up time (Minimum
dominant time on LIN bus for
wakeup)
See Figure 9-2, Figure 9-3, and
Figure 7-5
tCLEAR
Time to clear false wake-up
prevention logic if LIN Bus had
bus stuck dominant fault (recessive
time on LIN bus to clear bus stuck
dominant fault)
See Figure 9-3
tDST
Dominant state time-out(1)
tMODE_
CHANGE
(1)
–2
TYP
MAX
2
μs
50
150
μs
25
100
150
μs
8
17
50
μs
20
34
80
ms
5
μs
Time to change from standby mode
to normal mode or normal mode to
sleep mode through EN pin
Mode change delay time
UNIT
TXD Dominant state timeout limits the minimum data rate to 650 bps. The minimum datarates may be calculated by the following
forumulas. DataRateCommander(min) = tSYNC_DOM(max) / tDST(min) and DataRateResponder(min) = 9 + nmargin / tDST(min) where nmargin is a safety
margin. For responder node cases where nmargin ≤ 4, the commander node case will be the limiting calculation.
7.7 Dissipation Ratings
TYP
PD
MAX
UNIT
Thermal shutdown temperature
180
°C
Thermal shutdown hysteresis
15
°C
230
mW
Power Dissipation in normal mode (dominant)
tBit
17
tBit
RECESSIVE
D = 0.5
TXD (Input)
DOMINANT
THRec(max)
LIN Bus
Signal
Thresholds
:
Worst case 1
THDom(max)
Vsup
THRec(min)
Thresholds
:
Worst case 2
THDom(min)
tBus_dom(max)
tBus_rec(max)
D = tBus_rec(min)/(2 x tBit)
RXD
D1 (20 kbps) and
D3 (10 kbps) case
tBus_dom(min)
tBus_rec(min)
D = tBus_rec(max)/(2 x tBit)
RXD
D2 (20 kbps) and
D4 (10 kbps) case
Figure 7-1. Definition of Bus Timing Parameters
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LIN Bus
0.6 VSUP
VSUP
0.4 VSUP
trx_pdf
trx_pdr
RXD
50%
50%
Figure 7-2. Propagation Delay
Wake Event
tMODE_CHANGE
EN
MODE
RXD
Normal
Transition
Mirrors Bus
Indeterminate
Ignore
tMODE_CHANGE
Sleep
Floating
Standby
Transition
Normal
Wake Request
RXD = low
Indeterminate
Ignore
Mirrors Bus
Figure 7-3. Mode Transitions
EN
INH
TXD
Vsup
High impedance
Weak internal pulldown
Weak internal pulldown
Vsup
LIN
RXD
MODE
Floating
Sleep
Normal
Figure 7-4. Wakeup Through EN
10
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LIN
0.6 × VSUP
0.6 × VSUP
0.4 × VSUP
Vsup
0.4 × VSUP
t < tLINBUS
tLINBUS
Vsup
INH
TXD
High impedance
Weak internal pulldown
EN
RXD
MODE
Floating
Standby
Sleep
Normal
Figure 7-5. Wakeup Through LIN
NWake VIH
NWake VIL
NWake VIL
NWake
VSUP
tNWake
t < tNWake
INH
TXD
VSUP
High impedance
Weak internal pulldown
Wake-up source recognition:
Strong pulldown
EN
RXD
Floating
VSUP
LIN
MODE
Sleep
Standby
Normal
Figure 7-6. Wakeup Through NWake
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7.8 Typical Characteristics
30
1000
900
25
800
VOL (mV)
VOH
20
15
10
5
700
600
500
VOHLIN -40°C
400
VOHLIN 25°C
300
VOLLIN (mV) -40°C
VOLLIN (mV) 25°C
VOLLIN (mV) 125°C
VOHLIN 125°C
200
0
5
10
15
20
25
VSUP
5
10
15
20
25
VSUP
C002
Figure 7-7. VOH vs VSUPPLY and Temperature
12
30
30
C001
Figure 7-8. VOL vs VSUPPLY and Temperature
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8 Parameter Measurement Information
Figure 8-1. Test Circuit for AC Characteristics
8.1
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9 Detailed Description
9.1 Overview
The SN65HVDA100-Q1 LIN transceiver is a LIN (Local Interconnect Network) physical layer transceiver which
integrates a serial transceiver with wake up and protection features. The LIN bus is a single wire, bi-directional
bus that typically is used in low speed in vehicle networks with data rates that range from 2.4 kbps to 20 kbps.
9.2 Functional Block Diagram
VSUP
INH
RXD
VSUP
VSUP/2
Receiver
EN
Filter
Wake up
State
INH Control
NWAKE
TXD
Filter
Fault Detection
and Protection
Dominant State
Timeout
30lQ
LIN
Driver with
Slope Control
9.3 Feature Description
9.3.1 LIN (Local Interconnect Network) Bus
This I/O pin is the single-wire LIN bus transmitter and receiver. The LIN pin can survive excessive DC and
transient voltages. There are no reverse currents from the LIN to supply (VSUP), even in the event of a ground
shift or loss of supply (VSUP).
9.3.1.1 LIN Transmitter Characteristics
The transmitter has thresholds and AC parameters according to the LIN specification. The transmitter is a
low-side transistor with internal current limitation and thermal shutdown. During a thermal shutdown condition,
the transmitter is disabled to protect the device. There is an internal pullup resistor with a serial diode structure
to VSUP, so no external pullup components are required for LIN responder mode applications. An external pullup
resistor and a series diode to VSUP must be added when the device is used for commander node applications.
9.3.1.2 LIN Receiver Characteristics
The receiver’s characteristic thresholds are ratiometric with the device supply pin according to the LIN
specification.
The receiver is capable of receiving higher data rates (>100 kbps) than supported by LIN or SAEJ2602
specifications. This allows the SN65HVDA100-Q1 to be used for high-speed downloads at end-of-line production
or other applications. The actual data rates achievable depend on system time constants (bus capacitance and
pullup resistance) and driver characteristics used in the system.
9.3.1.2.1 Termination
There is an internal pullup resistor with a serial diode structure from LIN to VSUP, so no external pullup
components are required for LIN responder mode applications. An external pullup resistor (1 kΩ) and a
series diode to VSUP must be added when the device is used for commander node applications per the LIN
specification.
14
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VBattery
(KL30)
Voltage drop across the
diodes in the pullup path
VLIN_BUS
Simplified Transceiver
VSUP
VBattery
VSUP
VSUP
RXD
VLIN_Recessive
VSUP/2
Commander
node
pullup
Receiver
LIN
Driver
with slope control
LIN Bus
GND
TXD
VLIN_Dominant
t
VBattery = Vehicle battery supply
VSUP = Electronic module supply (reverse battery diode blocked VBattery)
Figure 9-1. Definition of Voltage Levels
9.3.2 TXD (Transmit Input / Output)
TXD is the interface to the MCU’s LIN protocol controller or SCI/UART that is used to control the state of the
LIN output. When TXD is low, the LIN output is dominant (near ground). When TXD is high, the LIN output is
recessive (near battery). The TXD input structure is compatible with microcontrollers with 3.3-V and 5-V I/O. TXD
has an internal pulldown resistor. The LIN bus is protected from being stuck dominant through a system failure
driving TXD low through the dominant state time-out timer. The TXD pin is pulled down strongly in standby mode
after a wake-up event on the NWake pin.
9.3.3 RXD (Receive Output)
RXD is the interface to the MCU’s LIN protocol controller or SCI/UART, which reports the state of the LIN bus
voltage. LIN recessive (near battery) is represented by a high level on RXD and LIN dominant (near ground)
is represented by a low level on RXD. The RXD output structure is an open-drain output stage. This allows
the device to be used with 3.3-V and 5-V I/O microcontrollers. If the microcontroller’s RXD pin does not have
an integrated pullup, an external pullup resistor to the microcontroller I/O supply voltage is required. In standby
mode the RXD pin is driven low to indicate a wake-up request from LIN or NWake.
9.3.4 VSUP (Supply Voltage)
VSUP is the power supply pin. VSUP is connected to the battery through an external reverse battery blocking
diode. If there is a loss of power at the ECU level, the device has extremely low leakage from the LIN pin, which
does not load the bus down. This is optimal for LIN systems in which some of the nodes are unpowered (ignition
supplied) while the rest of the network remains powered (battery supplied).
9.3.5 GND (Ground)
GND is the device ground connection. The device can operate with a ground shift as long as the ground shift
does not reduce VSUP below the minimum operating voltage. If there is a loss of ground at the ECU level, the
device has extremely low leakage from the LIN pin, which does not load the bus down. This is optimal for LIN
systems in which some of the nodes are unpowered (ignition supplied) while the rest of the network remains
powered (battery supplied).
9.3.6 EN (Enable Input)
EN controls the operational modes of the device. When EN is high, the device is in normal mode, allowing a
transmission path from TXD to LIN and from LIN to RXD. When EN is low, the device is put into sleep mode
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and there are no transmission paths available. The device can enter normal mode only after wake up. EN has an
internal pull-down resistor to make sure the device remains in low-power mode even if EN floats.
9.3.7 NWake (High Voltage Wake Up Input)
NWake is a high-voltage input used to wake up from sleep mode. NWake is usually connected to an external
switch in the application. A low on NWake that is asserted longer than the filter time (tNWAKE) results in a local
wakeup. NWake provides an internal pullup source to VSUP.
9.3.8 INH (Inhibit Output)
INH is used to control an external voltage regulator that has an inhibit or enable input. When the device is in
normal operating mode, the inhibit switch is enabled and the external voltage regulator is activated. When device
is in sleep mode, the inhibit switch is disabled, which turns off the system voltage regulator. A wake-up event
transitions the device to standby by mode and re-enables INH which, in turn, restarts the system by turning on
the voltage regulators. INH can also drive an external transistor connected to an MCU interrupt input.
9.3.9 TXD Dominant State Timeout
During normal mode, if TXD is inadvertently driven permanently low by a hardware or software application
failure, the LIN bus is protected by the dominant state timeout timer. This timer is triggered by a falling edge on
TXD. If the low signal remains on TXD for longer than tDST, the transmitter is disabled, thus allowing the LIN bus
to return to the recessive state and communication to resume on the bus. The protection is cleared and the tDST
timer is reset by a rising edge on TXD. The TXD pin has an internal pull-down to make sure the device fails to
a known state if TXD is disconnected. During this fault, the transceiver remains in normal mode (assuming no
change of state request on EN), the transmitter is disabled, the RXD pin reflects the LIN bus, INH remains on,
and the LIN bus pullup termination remains on.
Note
The maximum dominant TXD time allowed by the TXD Dominant state time-out limits the minimum
possible data rate of the device. The LIN protocol has different constraints for commander and
responder applications thus there are different maximum consecutive dominant bits for each
application case and thus different minimum data rates.
Commander node: The maximum continuous dominant is the maximum dominant of the SYNC
BREAK FIELD, tSYNC_DOM(max). The SYNC BREAK FIELD notifies the 'start of frame' to all LIN
responders. It consists of 13 to 26 dominant bits (low phase) followed by a delimiter. Thus
the minimum TXD dominant time out, tDST(min) and the maximum SYNC BREAK FIELD for the
commander determine the minimum data rate for a commander node, which may be calculated using
Equation 1.
DataRateCommander(min) = tSYNC_DOM(max) / tDST(min)
(1)
Responder node: sends the response part of the LIN message frame which has a maximum
consecutive dominant length of 9 bits (start bit + 8 data bits). As a result the minimum baud rate
of a responder can be calculated using Equation 2.
DataRateResponder(min) = (9 + nmargin) / tDST(min) where nmargin is a saftey margin.
(2)
9.3.10 Thermal Shutdown
The LIN transmitter is protected through a current limit, however, if the junction temperature of the
device exceeds the thermal shutdown threshold, the device turns off the LIN transmitter circuit. Once the
overtemperature fault condition has been removed and the junction temperature has cooled beyond the
hysteresis temperature, the transmitter is re-enabled, assuming the device remained in the normal mode. During
this fault, the transceiver remains in normal mode (assuming no change of state request on EN), the transmitter
is disabled, the RXD pin reflects the LIN bus, INH remains on, and the LIN bus pullup termination remains on.
16
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9.3.11 Bus Stuck Dominant System Fault: False Wake-Up Lockout
The device contains logic to detect bus stuck dominant system faults and prevent the device from waking up
falsely during this system fault. Upon entering sleep mode, the device detects the state of the LIN bus. If the bus
is dominant, the wake-up logic is locked out until a valid recessive on the bus "clears" the bus stuck dominant
condition. This logic prevents the potential for a cyclical false wakeup of the system if the bus is stuck dominant,
preventing excessive current use. Figure 9-2 and Figure 9-3 show the behavior of this protection feature.
EN
LIN Bus
tLINBUS
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