SN74HC373AN

SN54HC373, SN74HC373 SCLS140F – DECEMBER 1982 – REVISED APRIL 2022 SNx4HC373 Octal Transparent D-Type Latches With 3-State Outputs 1 Features 2 Description • • These 8-bit latches feature 3-state outputs designed specifically for driving highly capacitive or relatively low-impedance loads. They are particularly suitable for implementing buffer registers, I/O ports, bidirectional bus drivers, and working registers. • • • • • • Wide operating voltage range of 2 V to 6 V High-current 3-state true outputs can drive up to 15 LSTTL loads Low power consumption, 80-µA max ICC Typical tpd = 13 ns ±6-mA output drive at 5 V Low input current of 1 µA max Eight high-current latches in a single package Full parallel access for loading The eight latches of the ’HC373 devices are transparent D-type latches. While the latch-enable (LE) input is high, the Q outputs follow the data (D) inputs. When LE is taken low, the Q outputs are latched at the levels that were set up at the D inputs. Device Information (1) PART NUMBER PACKAGE BODY SIZE (NOM) SN74HC373DW SOIC (20) 12.80 mm × 7.50 mm SN74HC373DBR SSOP (20) 7.20 mm × 5.30 mm SN74HC373N PDIP (20) 25.40 mm × 6.35 mm SN74HC373NSR SO (20) 15.00 mm × 5.30 mm SN74HC373PW TSSOP (20) 6.50 mm × 4.40 mm SN54HC373J CDIP (20) 26.92 mm × 6.92 mm SNJ54HC373FK LCCC (20) 8.89 mm × 8.45 mm SNJ54HC373W CFP (20) 13.72 mm × 6.92 mm (1) For all available packages, see the orderable addendum at the end of the data sheet. Logic Diagram (Positive Logic) An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. PRODUCTION DATA. SN54HC373, SN74HC373 www.ti.com SCLS140F – DECEMBER 1982 – REVISED APRIL 2022 Table of Contents 1 Features............................................................................1 2 Description.......................................................................1 3 Revision History.............................................................. 2 4 Pin Configuration and Functions...................................3 5 Specifications.................................................................. 4 5.1 Absolute Maximum Ratings........................................ 4 5.2 Recommended Operating Conditions(1) .................... 4 5.3 Thermal Information....................................................4 5.4 Electrical Characteristics.............................................5 5.5 Timing Requirements.................................................. 5 5.6 Switching Characteristics............................................6 5.7 Switching Characteristics............................................6 5.8 Operating Characteristics........................................... 6 6 Parameter Measurement Information............................ 7 7 Detailed Description........................................................8 7.1 Overview..................................................................... 8 7.2 Functional Block Diagram........................................... 8 7.3 Device Functional Modes............................................8 8 Power Supply Recommendations..................................9 9 Layout...............................................................................9 9.1 Layout Guidelines....................................................... 9 10 Device and Documentation Support..........................10 10.1 Receiving Notification of Documentation Updates..10 10.2 Support Resources................................................. 10 10.3 Trademarks............................................................. 10 10.4 Electrostatic Discharge Caution..............................10 10.5 Glossary..................................................................10 11 Mechanical, Packaging, and Orderable Information.................................................................... 11 3 Revision History NOTE: Page numbers for previous revisions may differ from page numbers in the current version. Changes from Revision E (January 2022) to Revision F (April 2022) Page • Junction-to-ambient thermal resistance values increased. DW was 58 is now 109.1, DB was 70 is now 122.7, N was 69 is now 84.6, NS was 60 is now 113.4, PW was 83 is now 131.8........................................................ 4 Changes from Revision D (August 2003) to Revision E (January 2022) Page • Updated the numbering, formatting, tables, figures, and cross-references throughout the document to reflect modern data sheet standards............................................................................................................................. 1 2 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: SN54HC373 SN74HC373 SN54HC373, SN74HC373 www.ti.com SCLS140F – DECEMBER 1982 – REVISED APRIL 2022 4 Pin Configuration and Functions OE 1 20 1Q 2 19 8Q 1D 3 18 8D 7D VCC 2D 4 17 2Q 5 16 7Q 3Q 6 15 6Q 6D 3D 7 14 4D 8 13 5D 4Q 9 12 5Q 10 11 LE GND J, W, FK, DB, DW, N, NS, or PW package 20--Pin CDIP, CFP, LCCC, SSOP, SOIC, PDIP, SO, or TSSOP Top View FK package 20-Pin LCCC Top View Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: SN54HC373 SN74HC373 3 SN54HC373, SN74HC373 www.ti.com SCLS140F – DECEMBER 1982 – REVISED APRIL 2022 5 Specifications 5.1 Absolute Maximum Ratings over operating free-air temperature range (unless otherwise noted)(1) VCC Supply voltage range current(2) MIN MAX –0.5 7 UNIT V IIK Input clamp VI < 0 or VI > VCC ±20 mA IOK Output clamp current(2) VO < 0 or VO > VCC ±20 mA IO Continuous output current VO = 0 to VCC ±35 mA ±70 mA 150 °C 150 °C Continuous current through VCC or GND TJ Junction temperature Tstg Storage temperature range (1) (2) –65 Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “Section 5.2” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. The input and output voltage ratings may be exceeded if the input and output current ratings are observed. 5.2 Recommended Operating Conditions(1) SN54HC373 VCC Supply voltage VCC = 2 V VIH High-level input voltage VCC = 4.5 V VCC = 6 V NOM MAX 2 5 6 Low-level input voltage VI Input voltage VO Output voltage TA (1) MAX 2 5 6 3.15 3.15 4.2 4.2 VCC = 4.5 V 0 0.5 0.5 1.35 1.35 0 VCC 0 V VCC V VCC = 4.5 V 500 500 VCC = 6 V 400 400 125 V VCC 1000 –55 V 1.8 VCC 1000 Operating free-air temperature UNIT V 1.8 0 VCC = 2 V Input transition rise and fall time NOM 1.5 VCC = 6 V ∆t/∆v MIN 1.5 VCC = 2 V VIL SN74HC373 MIN –40 ns 85 °C All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report, Implications of Slow or Floating CMOS Inputs, literature number SCBA004. 5.3 Thermal Information SN74HC373 THERMAL METRIC 4 DW (SOIC) DB (SSOP) N (PDIP) NS (SO) PW (TSSOP) 20 PINS 20 PINS 20 PINS 20 PINS 20 PINS UNIT 109.1 122.7 84.6 113.4 131.8 °C/W 76 81.6 72.5 78.6 72.2 °C/W RθJA Junction-to-ambient thermal (1) resistance RθJC (top) Junction-to-case (top) thermal resistance RθJB Junction-to-board thermal resistance 77.6 77.5 65.3 78.4 82.8 °C/W ΨJT Junction-to-top characterization parameter 51.5 46.1 55.3 47.1 21.5 °C/W ΨJB Junction-to-board characterization parameter 77.1 77.1 65.2 78.1 82.4 °C/W Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: SN54HC373 SN74HC373 SN54HC373, SN74HC373 www.ti.com SCLS140F – DECEMBER 1982 – REVISED APRIL 2022 5.3 Thermal Information (continued) SN74HC373 DW (SOIC) DB (SSOP) N (PDIP) NS (SO) PW (TSSOP) 20 PINS 20 PINS 20 PINS 20 PINS 20 PINS UNIT N/A N/A N/A N/A N/A °C/W THERMAL METRIC RθJC(bot) (1) Junction-to-case (bottom) thermal resistance For more information about traditional and new thermal metrics, see the Semiconductor and IC package thermal metrics application report. 5.4 Electrical Characteristics over recommended operating free-air temperature range (unless otherwise noted) PARAMETER VOH TEST CONDITIONS VI = VCC or 0, MIN 1.998 1.9 1.9 4.499 4.4 4.4 6V 5.9 5.999 5.9 5.9 IOH = –6 mA 4.5 V 3.98 4.3 3.7 3.84 6V 5.48 IOL = 7.8 mA VO = VCC or 0 SN74HC373 MAX 4.4 IOL = 6 mA IOZ MIN 1.9 IOL = 20 µA ICC SN54HC373 MAX 2V VI = VIH or VIL VI = VCC or 0 TYP 4.5 V VI = VIH or VIL II MIN IOH = –20 µA IOH = –7.8 mA VOL TA = 25°C VCC IO = 0 5.8 5.2 UNIT V 5.34 2V 0.002 0.1 0.1 0.1 4.5 V 0.001 0.1 0.1 0.1 6V 0.001 0.1 0.1 0.1 4.5 V 0.17 0.26 0.4 0.33 6V 0.15 0.26 0.4 0.33 6V ±0.1 ±100 ±1000 ±1000 nA 6V ±0.01 ±0.5 ±10 ±5 µA 8 160 80 µA 10 10 10 pF 6V 2 V to 6V Ci MAX 3 V 5.5 Timing Requirements over recommended operating free-air temperature range (unless otherwise noted) VCC tw tsu th Pulse duration, LE high Setup time, data before LE↓ Hold time, data after LE↓ TA = 25°C MIN SN54HC373 MAX MIN SN74HC373 MAX MIN 2V 80 120 100 4.5 V 16 24 20 6V 14 20 17 2V 50 75 63 4.5 V 10 15 13 6V 9 13 11 2V 20 26 24 4.5 V 10 13 12 6V 10 13 12 MAX UNIT ns ns ns Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: SN54HC373 SN74HC373 5 SN54HC373, SN74HC373 www.ti.com SCLS140F – DECEMBER 1982 – REVISED APRIL 2022 5.6 Switching Characteristics over recommended operating free-air temperature range, CL = 50 pF (unless otherwise noted) (see Figure 6-1) PARAMETER FROM (INPUT) TO (OUTPUT) D Q tpd LE ten Any Q OE tdis Any Q OE Any Q tt Any Q VCC TA = 25°C MIN SN54HC373 MIN SN74HC373 TYP MAX MAX MIN MAX 2V 58 150 225 190 4.5 V 15 30 45 38 6V 13 26 38 32 2V 73 175 265 220 4.5 V 18 35 53 44 6V 15 30 45 38 2V 65 150 225 190 4.5 V 17 30 45 38 6V 14 26 38 32 2V 50 150 225 190 4.5 V 15 30 45 38 6V 13 26 38 32 2V 28 60 90 75 4.5 V 8 12 18 15 6V 6 10 15 13 UNIT ns ns ns ns 5.7 Switching Characteristics over recommended operating free-air temperature range, CL = 150 pF (unless otherwise noted) (see Figure 6-1) PARAMETER FROM (INPUT) TO (OUTPUT) VCC D Q tpd LE ten Any Q OE Any Q tt Any Q TA = 25°C MIN SN54HC373 MIN SN74HC373 TYP MAX MAX MIN MAX 2V 82 200 300 250 4.5 V 22 40 60 50 6V 19 34 51 43 2V 100 225 335 285 4.5 V 24 45 67 57 6V 20 38 57 48 2V 90 200 300 250 4.5 V 23 40 60 50 6V 19 34 51 43 2V 45 210 315 265 4.5 V 17 42 63 53 6V 13 36 53 45 UNIT ns ns ns 5.8 Operating Characteristics TA = 25°C PARAMETER Cpd 6 Power dissipation capacitance per latch TEST CONDITIONS TYP UNIT No load 100 pF Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: SN54HC373 SN74HC373 SN54HC373, SN74HC373 www.ti.com SCLS140F – DECEMBER 1982 – REVISED APRIL 2022 6 Parameter Measurement Information VCC From Output Under Test CL (see Note A) PARAMETER tPZH S1 Test Point RL 1 kΩ ten RL tPZL tPHZ tdis S2 tPLZ Reference Input VCC 50% Data Input VCC 50% 10% 50% 50% 0V In-Phase Output 50% 10% tPHL 90% 90% tr tPHL Out-ofPhase Output 90% tf VOH 50% 10% V OL tf C. D. E. F. G. Closed Open Open Open VCC th 90% 90% VCC 50% 10% 0 V tf 50% 10% Output Control (Low-Level Enabling) VCC 50% 50% 0V Output Waveform 1 (See Note B) tPLZ ≈VCC 50% 90% VOL Output Waveform 2 (See Note B) ≈VCC 10% tPZH VOH VOL tPHZ 50% 90% VOH ≈0 V tr VOLTAGE WAVEFORMS PROPAGATION DELAY AND OUTPUT TRANSITION TIMES A. B. Closed tPZL tPLH 50% 10% Open VOLTAGE WAVEFORMS SETUP AND HOLD AND INPUT RISE AND FALL TIMES VCC tPLH Open tr VOLTAGE WAVEFORMS PULSE DURATIONS 50% Closed 0V 0V Input Closed tsu 0V 50% Open 50% 50% tw Low-Level Pulse S2 50 pF or 150 pF −− LOAD CIRCUIT High-Level Pulse S1 50 pF 1 kΩ tpd or tt CL 50 pF or 150 pF VOLTAGE WAVEFORMS ENABLE AND DISABLE TIMES FOR 3-STATE OUTPUTS CL includes probe and test-fixture capacitance. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control. Phase relationships between waveforms were chosen arbitrarily. All input pulses are supplied by generators having the following characteristics: PRR ≤ 1 MHz, ZO = 50 Ω, tr = 6 ns, tf = 6 ns. The outputs are measured one at a time with one input transition per measurement. tPLZ and tPHZ are the same as tdis. tPZL and tPZH are the same as ten. tPLH and tPHL are the same as tpd. Figure 6-1. Load Circuit and Voltage Waveforms Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: SN54HC373 SN74HC373 7 SN54HC373, SN74HC373 www.ti.com SCLS140F – DECEMBER 1982 – REVISED APRIL 2022 7 Detailed Description 7.1 Overview These 8-bit latches feature 3-state outputs designed specifically for driving highly capacitive or relatively lowimpedance loads. They are particularly suitable for implementing buffer registers, I/O ports, bidirectional bus drivers, and working registers. The eight latches of the ’HC373 devices are transparent D-type latches. While the latch-enable (LE) input is high, the Q outputs follow the data (D) inputs. When LE is taken low, the Q outputs are latched at the levels that were set up at the D inputs. An output-enable (OE) input places the eight outputs in either a normal logic state (high or low logic levels) or the high-impedance state. In the high-impedance state, the outputs neither load nor drive the bus lines significantly. The high-impedance state and increased drive provide the capability to drive bus lines without interface or pullup components. OE does not affect the internal operations of the latches. Old data can be retained or new data can be entered while the outputs are off. 7.2 Functional Block Diagram 7.3 Device Functional Modes Function Table (Each Latch) INPUTS 8 OE LE D OUTPUT Q L H H H L H L L L L X Q0 H X X Z Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: SN54HC373 SN74HC373 SN54HC373, SN74HC373 www.ti.com SCLS140F – DECEMBER 1982 – REVISED APRIL 2022 8 Power Supply Recommendations The power supply can be any voltage between the minimum and maximum supply voltage rating located in the Recommended Operating Conditions. Each VCC terminal should have a good bypass capacitor to prevent power disturbance. A 0.1-μF capacitor is recommended for this device. It is acceptable to parallel multiple bypass caps to reject different frequencies of noise. The 0.1-μF and 1-μF capacitors are commonly used in parallel. The bypass capacitor should be installed as close to the power terminal as possible for best results. 9 Layout 9.1 Layout Guidelines When using multiple-input and multiple-channel logic devices inputs must not ever be left floating. In many cases, functions or parts of functions of digital logic devices are unused; for example, when only two inputs of a triple-input AND gate are used or only 3 of the 4 buffer gates are used. Such unused input pins must not be left unconnected because the undefined voltages at the outside connections result in undefined operational states. All unused inputs of digital logic devices must be connected to a logic high or logic low voltage, as defined by the input voltage specifications, to prevent them from floating. The logic level that must be applied to any particular unused input depends on the function of the device. Generally, the inputs are tied to GND or VCC, whichever makes more sense for the logic function or is more convenient. Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: SN54HC373 SN74HC373 9 SN54HC373, SN74HC373 www.ti.com SCLS140F – DECEMBER 1982 – REVISED APRIL 2022 10 Device and Documentation Support TI offers an extensive line of development tools. Tools and software to evaluate the performance of the device, generate code, and develop solutions are listed below. 10.1 Receiving Notification of Documentation Updates To receive notification of documentation updates, navigate to the device product folder on ti.com. Click on Subscribe to updates to register and receive a weekly digest of any product information that has changed. For change details, review the revision history included in any revised document. 10.2 Support Resources TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight from the experts. Search existing answers or ask your own question to get the quick design help you need. Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of Use. 10.3 Trademarks TI E2E™ is a trademark of Texas Instruments. All trademarks are the property of their respective owners. 10.4 Electrostatic Discharge Caution This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. 10.5 Glossary TI Glossary 10 This glossary lists and explains terms, acronyms, and definitions. Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: SN54HC373 SN74HC373 SN54HC373, SN74HC373 www.ti.com SCLS140F – DECEMBER 1982 – REVISED APRIL 2022 11 Mechanical, Packaging, and Orderable Information The following pages include mechanical, packaging, and orderable information. This information is the most current data available for the designated devices. This data is subject to change without notice and revision of this document. For browser-based versions of this data sheet, refer to the left-hand navigation. Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: SN54HC373 SN74HC373 11 PACKAGE OPTION ADDENDUM www.ti.com 14-Oct-2022 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan (2) Lead finish/ Ball material MSL Peak Temp Op Temp (°C) Device Marking (3) Samples (4/5) (6) 5962-8407201VRA ACTIVE CDIP J 20 1 Non-RoHS & Green SNPB N / A for Pkg Type -55 to 125 5962-8407201VR A SNV54HC373J 5962-8407201VSA ACTIVE CFP W 20 1 Non-RoHS & Green SNPB N / A for Pkg Type -55 to 125 5962-8407201VS A SNV54HC373W 84072012A ACTIVE LCCC FK 20 1 Non-RoHS & Green SNPB N / A for Pkg Type -55 to 125 84072012A SNJ54HC 373FK 8407201RA ACTIVE CDIP J 20 1 Non-RoHS & Green SNPB N / A for Pkg Type -55 to 125 8407201RA SNJ54HC373J Samples 8407201SA ACTIVE CFP W 20 1 Non-RoHS & Green SNPB N / A for Pkg Type -55 to 125 8407201SA SNJ54HC373W Samples JM38510/65403B2A ACTIVE LCCC FK 20 1 Non-RoHS & Green SNPB N / A for Pkg Type -55 to 125 JM38510/ 65403B2A Samples JM38510/65403BRA ACTIVE CDIP J 20 1 Non-RoHS & Green SNPB N / A for Pkg Type -55 to 125 JM38510/ 65403BRA Samples M38510/65403B2A ACTIVE LCCC FK 20 1 Non-RoHS & Green SNPB N / A for Pkg Type -55 to 125 JM38510/ 65403B2A Samples M38510/65403BRA ACTIVE CDIP J 20 1 Non-RoHS & Green SNPB N / A for Pkg Type -55 to 125 JM38510/ 65403BRA Samples SN54HC373J ACTIVE CDIP J 20 1 Non-RoHS & Green SNPB N / A for Pkg Type -55 to 125 SN54HC373J Samples SN74HC373DBR ACTIVE SSOP DB 20 2000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 HC373 Samples SN74HC373DW ACTIVE SOIC DW 20 25 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 HC373 Samples SN74HC373DWR ACTIVE SOIC DW 20 2000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 HC373 Samples SN74HC373DWRE4 ACTIVE SOIC DW 20 2000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 HC373 Samples SN74HC373N ACTIVE PDIP N 20 20 RoHS & Green NIPDAU N / A for Pkg Type -40 to 85 SN74HC373N Samples SN74HC373NE4 ACTIVE PDIP N 20 20 RoHS & Green NIPDAU N / A for Pkg Type -40 to 85 SN74HC373N Samples Addendum-Page 1 Samples Samples Samples PACKAGE OPTION ADDENDUM www.ti.com Orderable Device 14-Oct-2022 Status (1) Package Type Package Pins Package Drawing Qty Eco Plan (2) Lead finish/ Ball material MSL Peak Temp Op Temp (°C) Device Marking (3) Samples (4/5) (6) SN74HC373NSR ACTIVE SO NS 20 2000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 HC373 Samples SN74HC373NSRE4 ACTIVE SO NS 20 2000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 HC373 Samples SN74HC373PW ACTIVE TSSOP PW 20 70 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 HC373 Samples SN74HC373PWR ACTIVE TSSOP PW 20 2000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 HC373 Samples SN74HC373PWRE4 ACTIVE TSSOP PW 20 2000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 HC373 Samples SN74HC373PWT ACTIVE TSSOP PW 20 250 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 HC373 Samples SNJ54HC373FK ACTIVE LCCC FK 20 1 Non-RoHS & Green SNPB N / A for Pkg Type -55 to 125 84072012A SNJ54HC 373FK SNJ54HC373J ACTIVE CDIP J 20 1 Non-RoHS & Green SNPB N / A for Pkg Type -55 to 125 8407201RA SNJ54HC373J Samples SNJ54HC373W ACTIVE CFP W 20 1 Non-RoHS & Green SNPB N / A for Pkg Type -55 to 125 8407201SA SNJ54HC373W Samples (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of