TAS5708
www.ti.com ........................................................................................................................................................................................... SLOS570 – DECEMBER 2008
20-W STEREO DIGITAL AUDIO POWER AMPLIFIER WITH EQ/DRC and FEEDBACK
FEATURES
1
•
•
Audio Input/Output
– 20-W Into an 8-Ω Load From an 18-V Supply
– Wide PVCC Range (10 V to 26 V); 3.3 V
Digital Supply
– Supports One Serial Audio Input (8 kHz - 48
kHz Sample Rates) (LJ/RJ/I2S)
– Power-Stage Feedback Allows Operation
From Poorly Regulated Power Supplies
Audio/PWM Processing
– Factory-Trimmed Internal Oscillator for
Automatic Rate Detection
– High-End 32-Bit Data Path Audio Processor
– 14 Biquads for Speaker EQ
– Dynamic Range Control (DRC)
•
Benefits
– EQ: Speaker Equalization Improves Audio
Performance
– DRC: Enables Speaker Protection and
Night-Mode Listening.
– Autobank Switching: Preloaded
Coefficients for Three Different Sample
Rates Eliminates the Need to Update
Coefficients When Sample Rate Changes
– Autodetect: Automatically Detects
Sample-Rate Changes Eliminating the Need
for External Microprocessor Intervention
– Closed-Loop Power Stage: Enables Wide
PVCC Operating Range and Reduced
Power Supply Ripple Distortion
DESCRIPTION
The TAS5708 is a 20-W, efficient, digital audio power amplifier for driving stereo bridge-tied speakers. A 32-bit
datapath eliminates the need for pre-scaling before processing and preserves signal integrity without sacrificing
dynamic range. A digital audio processor with fully programmable digital filters allows designers to custom tune
speakers for optimum sound in small enclosures. A programmable DRC can adjust power levels for a scaleable
design while also enabling night-mode listening modes.
The closed-loop architecture allows the device to operate from poorly regulated supplies. Figure 1 below shows
the benefit of the feedback architecture when a noisy supply (1kHz, 500mVpp ripple) modulates a 10kHz audio
input. The figure shows a 40dB improvement in sideband suppression when compared to an open-loop design.
This correlates directly to a 24dB improvement in distortion as seen in Figure 2.
20
10
0
THD+N − Total Harmonic Distortion + Noise − %
Fundamental
Audio Input
Closest Open-Loop
Competitor
TI Closed-Loop
−20
nd
Amplitude − dB
2 Order
Sideband
−40
40 dB
Inprovement
rd
3 Order
Sideband
−60
−80
−100
−120
Audio Input = 10 kHz
Supply Ripple = 1 kHz, 500 mVpp
−140
Closest Open-Loop
Competitor
TI Closed-Loop
1
0.1
PO = 3 W
Supply Ripple = 1 kHz, 500 mVpp
0.01
5k
6k
7k
8k 9k 10k
12k
15k
20k
f − Frequency − Hz
G018
Figure 1. Supply Ripple Intermod Distortion
20
100
1k
10k 20k
f − Frequency − Hz
G019
Figure 2. THD+N vs Frequency
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2008, Texas Instruments Incorporated
TAS5708
SLOS570 – DECEMBER 2008 ........................................................................................................................................................................................... www.ti.com
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
SIMPLIFIED APPLICATION DIAGRAM
3.3 V
10 V–26 V
AVDD/DVDD
AVCC/PVCC
OUT_A
LRCLK
Digital
Audio
Source
SCLK
BST_A
MCLK
LC
Left
LC
Right
BST_B
SDIN
OUT_B
2
I C
Control
SDA
OUT_C
SCL
BST_C
Control
Inputs
RESET
BST_D
PDN
OUT_D
PLL_FLTP
Loop
Filter*
PLL_FLTM
B0264-07
*Refer to user's guide for Loop Filter details.
2
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FUNCTIONAL VIEW
L
SDIN
OUT_A
7 BQ
V
O
L
U
M
E
Serial
Audio
Port
R
7 BQ
th
DRC
S
R
C
4
Order
Noise
Shaper
and
PWM
2´ HB
FET Out
OUT_B
OUT_C
2´ HB
FET Out
OUT_D
mDAP
Protection
Logic
MCLK
SCLK
LRCLK
SDA
SCL
Click and Pop
Control
Sample Rate
Autodetect
and PLL
Serial
Control
Microcontroller
Based
System
Control
Terminal Control
B0262-02
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B0341-01
DAP Process Flow
46[D0]
DRC
ON/ OFF
Attack
DRC1 Decay
Vol2
30-36
R
50[D7]
7 BQ EQ
´
ealpha
3A
3A
ealpha
29-2F
´
Vol1
7 BQ EQ
L
Hex numbers refer to I2C subaddresses
[Di] = bit "i" of subaddress
3B-3C 1
´
´
To PWM
Energy
MAXMUX
Input Muxing
4
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48-PIN, HTQFP PACKAGE (TOP VIEW)
BST_C
PVCC_C
BST_D
VCLAMP_CD
AGND
BYPASS
HIZ
AVCC
BST_A
BST_B
VCLAMP_AB
PVCC_B
PHP Package
(Top View)
48 47 46 45 44 43 42 41 40 39 38 37
OUT_B
1
36
OUT_C
PGND_B
2
35
PGND_C
PGND_B
3
34
PGND_C
OUT_A
4
33
OUT_D
PGND_A
5
32
PGND_D
PGND_A
6
31
PGND_D
PVCC_A
7
30
PVCC_D
PVCC_A
8
29
PVCC_D
AVSS
9
28
DVSS
PLL_FLTM
10
27
DVDD
PLL_FLTP
11
26
STEST
VR_ANA
12
25
RESET
TAS5708
SCL
SDA
SDIN
SCLK
PDN
LRCLK
VR_DIG
DVSSO
OSC_RES
AVDD
FAULT
MCLK
13 14 15 16 17 18 19 20 21 22 23 24
P0075-03
PIN FUNCTIONS
PIN
NAME
TYPE
NO.
(1)
5-V
TOLERANT
TERMINATION
DESCRIPTION
(2)
AGND
42
P
Analog ground for power stage
AVCC
43
P
Analog power supply for power stage. Connect externally to same
potential as PVCC.
AVDD
13
P
3.3-V analog power supply
AVSS
9
P
Analog 3.3-V supply ground
BST_A
45
P
High-side bootstrap supply for half-bridge A
BST_B
47
P
High-side bootstrap supply for half-bridge B
BST_C
38
P
High-side bootstrap supply for half-bridge C
BST_D
40
P
High-side bootstrap supply for half-bridge D
BYPASS
41
AO
DVDD
27
P
3.3-V digital power supply
DVSS
28
P
Digital ground
DVSSO
17
P
HIZ
44
DI
(1)
(2)
Nominally equal to VCC/8. Internal reference voltage for analog cells
Oscillator Ground
Pullup
Enable high-impedance (Hi-Z) mode (active low)
TYPE: A = analog; D = 3.3-V digital; P = power/ground/decoupling; I = input; O = output
All pullups are weak pullups and all pulldowns are weak pulldowns. The pullups and pulldowns are included to assure proper input logic
levels if the pins are left unconnected (pullups → logic 1 input; pulldowns → logic 0 input).
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PIN FUNCTIONS (continued)
PIN
NAME
NO.
TYPE
(1)
5-V
TOLERANT
TERMINATION
DESCRIPTION
(2)
LRCLK
20
DI
5-V
Pulldown
Input serial audio data left/right clock (sample rate clock)
MCLK
15
DI
5-V
Pulldown
Master Clock Input
OSC_RES
16
AO
OUT_A
4
O
Output, half-bridge A
OUT_B
1
O
Output, half-bridge B
OUT_C
36
O
Output, half-bridge C
OUT_D
33
O
PDN
19
DI
PGND_A
5, 6
P
Power ground for half-bridge A
PGND_B
2, 3
P
Power ground for half-bridge B
PGND_C
34, 35
P
Power ground for half-bridge C
PGND_D
31, 32
P
Power ground for half-bridge D
PLL_FLTM
10
AO
PLL negative loop filter terminal
PLL_FLTP
11
AO
PLL positive loop filter terminal
PVCC_A
7, 8
P
Power supply input for half-bridge output A
PVCC_B
48
P
Power supply input for half-bridge output B
PVCC_C
37
P
Power supply input for half-bridge output C
PVCC_D
Oscillator trim resistor. Connect an 18.2-kΩ 1% resistor to DVSSO.
Output, half-bridge D
5-V
Pullup
Power down, active-low. PDN prepares the device for loss of power
supplies by shutting down the Noise Shaper and initiating PWM stop
sequence.
29, 30
P
RESET
25
DI
5-V
SCL
24
DI
5-V
SCLK
21
DI
5-V
SDA
23
DIO
5-V
SDIN
22
DI
5-V
STEST
26
DI
Factory test pin. Connect directly to DVSS.
FAULT
14
DO
Backend error indicator. Asserted LOW for over current errors.
De-asserted upon recovery from error condition.
VR_ANA
12
P
Internally regulated 1.8-V analog supply voltage. This pin must not be
used to power external devices.
VR_DIG
18
P
Internally regulated 1.8-V digital supply voltage. This pin must not be
used to power external devices.
VCLAMP_AB
46
AO
Internally generated voltage supply for channel A and B gate
drive.This pin must not be used to power external devices.Connect
only to external decoupling capacitor
VCLAMP_CD
39
AO
Internally generated voltage supply for channel C and D gate
drive.This pin must not be used to power external devices.Connect
only to external decoupling capacitor
6
Power supply input for half-bridge output D
Pullup
Reset, active-low. A system reset is generated by applying a logic low
to this pin. RESET is an asynchronous control signal that restores the
DAP to its default conditions, and places the PWM in the hard mute
state (tristated).
I2C serial control clock input
Pulldown
Serial audio data clock (shift clock). SCLK is the serial audio port input
data bit clock.
I2C serial control data interface input/output
Pulldown
Serial audio data input. SDIN supports three discrete (stereo) data
formats.
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ABSOLUTE MAXIMUM RATINGS
over operating free-air temperature range (unless otherwise noted)
Supply voltage
Input voltage
(1) (2)
VALUE
UNIT
DVDD, AVDD
–0.3 to 3.6
V
PVCC_X, AVCC
–0.3 to 30
V
3.3-V digital inputs (except HIZ)
–0.5 to DVDD + 0.5
V
3.3-V HIZ input
–0.3 to AVDD + 0.3
V
–0.5 to DVDD + 2.5 (2)
V
(2)
V
5-V tolerant (3) digital inputs (except MCLK)
5-V tolerant MCLK input
–0.5 to AVDD + 2.5
OUT_x to PGND_X
32 (4)
V
BST_x to PGND_X
43 (4)
V
Operating free-air temperature
0 to 85
°C
Operating junction temperature range
0 to 150
°C
–40 to 125
°C
Storage temperature range, Tstg
(1)
Stresses beyond those listed under absolute ratings may cause permanent damage to the device. These are stress ratings only and
functional operation of the device at these or any other conditions beyond those indicated under recommended operation conditions are
not implied. Exposure to absolute-maximum conditions for extended periods may affect device reliability.
Maximum pin voltage should not exceed 6.0V
5-V tolerant inputs are PDN, RESET, SCLK, LRCLK, MCLK, SDIN, SDA, and SCL.
DC voltage + peak ac waveform measured at the pin should be below the allowed limit for all conditions.
(2)
(3)
(4)
DISSIPATION RATINGS (1)
PACKAGE
DERATING FACTOR
ABOVE TA = 25°C
TA ≤ 25°C
POWER RATING
TA = 45°C
POWER RATING
TA = 70°C
POWER RATING
7-mm × 7-mm HTQFP
40 mW/°C
5W
4.2 W
3.2 W
(1)
This data was taken using 1 oz trace and copper pad that is soldered directly to a JEDEC standard high-k PCB. The thermal pad must
be soldered to a thermal land on the printed-circuit board. See TI Technical Briefs SLMA002 for more information about using the
HTQFP thermal pad
RECOMMENDED OPERATING CONDITIONS
Digital/analog supply voltage
DVDD, AVDD
Half-bridge supply voltage
PVCC_X, AVCC
VIH
High-level input voltage
Digital Inputs
VIL
Low-level input voltage
Digital Inputs
TA
TJ
(1)
MIN
NOM
MAX
3
3.3
3.6
V
26
V
10
UNIT
2
V
0.8
V
Operating ambient temperature range
0
85
°C
Operating junction temperature range
0
125
°C
RL (BTL)
Load impedance
Output filter: L = 33 µH, C = 1 µF.
6
8
Ω
RL (PBTL)
Load impedance
Output filter: L = 33 µH, C = 1 µF.
3.2
4
Ω
LO (BTL)
Output-filter inductance
Minimum output inductance under
short-circuit condition
10
µH
LO (PBTL)
Output-filter inductance
Minimum output inductance under
short-circuit condition
10
µH
(1)
Continuous operation above the recommended junction temperature may result in reduced reliability and/or lifetime of the device.
PWM OPERATION AT RECOMMENDED OPERATING CONDITIONS
PARAMETER
Output sample rate
TEST CONDITIONS
VALUE
UNIT
11.025/22.05/44.1-kHz data rate ±2%
352.8
kHz
48/24/12/8/16/32-kHz data rate ±2%
384
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PLL INPUT PARAMETERS AND EXTERNAL FILTER COMPONENTS
PARAMETER
fMCLKI
tr /
tf(MCLK)
TEST CONDITIONS
MIN
MCLK Frequency
2.8224
MCLK duty cycle
40%
TYP
50%
MAX
UNIT
24.576
MHz
60%
Rise/fall time for MCLK
LRCLK allowable drift before LRCLK reset
External PLL filter capacitor C1
SMD 0603 Y5V
External PLL filter capacitor C2
External PLL filter resistor R
5
ns
4
MCLKs
47
nF
SMD 0603 Y5V
4.7
nF
SMD 0603, metal film
470
Ω
ELECTRICAL CHARACTERISTICS
DC Characteristics, BD BTL Mode, FS = 48 kHz, TA = 25°C, PVCC_X = AVCC = 18 V, DVDD=AVDD= 3.3V, RL = 8 Ω (unless
otherwise noted)
PARAMETER
TEST CONDITIONS
VOH
High-level output voltage
FAULT and SDA
IOH = –4 mA ,
DVDD=AVDD=3.0 V
VOL
Low-level output voltage
FAULT and SDA
IOL = 4 mA ,
DVDD=AVDD=3.0 V
|VOS|
Class-D output offset voltage
VBYPASS
PVCC/8 reference for analog section
TYP MAX
2.4
No load
0.5
2.1
UNIT
V
26
2.26
V
mV
2.4
V
Digital Inputs
VI ≤ VIL
DVDD = AVDD = 3.6 V
75
µA
Digital Inputs
VI ≥ VIH
DVDD = AVDD = 3.6 V
75
µA
IIL
Low-level input current
IIH
High-level input current
IDD
3.3-V supply current
ICC
Half-Bridge supply current No Load (PVCC + AVCC)
Drain-to-source resistance, high-side
rDS(on) (1)
MIN
3.3V Supply voltage (DVDD +
AVDD)
Drain-to-source resistance, low-side
Normal mode
43
77
Reset (RESET = low, PDN
= high)
19
24
mA
Normal Mode
34
60
mA
Reset (RESET = low, PDN
= high)
54
310
µA
VCC = 18 V , IO = 500 mA,
TJ = 25°C, includes
metallization resistance
240
240
mΩ
Protection
Vuvp
Undervoltage protection
limit
PVCC_X = AVCC falling
Vuvp,hyst
Undervoltage protection
limit
PVCC_X = AVCC rising
Vovp
Over-voltage protection
limit
PVCC_X = AVCC rising
Vovp,hyst
Over-voltage protection
limit
PVCC_X = AVCC falling
OTE (2)
OTEHYST
(1)
(2)
8
(2)
8.4
8.5
27.5
27.2
V
V
V
V
Over temperature error (output shutdown, unlatched)
150
°C
Extra temperature drop required to recover from error
15
°C
This does not include bond-wire or pin resistance.
Specified by design
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AC Characteristics, PVCC_x = AVCC = 18V, BTL BD Mode, FS=48KHz, TA = 25°C, AVDD = DVDD
= 3.3 V, RL = 8 Ω, CBST = 220 nF, Audio Frequency = 1 kHz, AES17 filter (unless otherwise
noted). All performance is in accordance with recommended operating conditions, unless
otherwise specified.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
KSVR
Supply ripple rejection
200-mVpp ripple at 1 kHz, no audio input
–80
dB
PO
Continuous output
power
THD+N = 10%, f = 1 kHz
20.2
W
18.8
W
THD+N
Total harmonic distortion f = 1 kHz, PO = 1 W
+ noise
Vn
Output integrated noise
(rms)
Crosstalk
SNR
(1)
Signal-to-noise ratio (1)
THD+N = 7%, f = 1 kHz
0.03%
A-weighted
105
µV
PO= 1 W, f = 1 kHz
–63
dB
Maximum Power at THD+N < 1%, f = 1 kHz,
A-weighted
100
dB
SNR is calculated relative to 0-dbFS Input Level
AC Characteristics, PVCC_x = AVCC = 12V, BTL BD Mode, FS=48KHz, TA = 25°C, AVDD = DVDD
= 3.3 V, RL = 8 Ω, CBST = 220 nF, Audio Frequency = 1 kHz, AES17 filter (unless otherwise
noted). All performance is in accordance with recommended operating conditions, unless
otherwise specified.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
KSVR
Supply ripple rejection
200-mVpp ripple at 1 kHz, no audio input
–80
dB
PO
Continuous output power
THD+N = 10%, f = 1 kHz
8.8
W
8.4
W
THD+N
Total harmonic distortion
+ noise
f = 1 kHz, PO = 1 W
Vn
Output integrated noise
(rms)
A-weighted
106
µV
f = 1 kHz, PO = 1 W
–63
dB
97
dB
THD+N = 7%, f = 1 kHz
Crosstalk
SNR
(1)
Signal-to-noise ratio (1)
Maximum Power at THD+N < 1%,
f = 1 kHz, A-weighted
0.04%
SNR is calculated relative to 0-dbFS Input Level
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SERIAL AUDIO PORTS SLAVE MODE
over recommended operating conditions (unless otherwise noted)
TEST
CONDITIONS
PARAMETER
MIN
CL = 30 pF
TYP
1.024
MAX
UNIT
12.288
MHz
fSCLKIN
Frequency, SCLK 32 × fS, 48 × fS, 64 × fS
tsu1
Setup time, LRCLK to SCLK rising edge
10
ns
th1
Hold time, LRCLK from SCLK rising edge
10
ns
tsu2
Setup time, SDIN to SCLK rising edge
10
ns
th2
Hold time, SDIN from SCLK rising edge
10
LRCLK frequency
ns
8
48
48
SCLK duty cycle
40%
50%
60%
LRCLK duty cycle
40%
50%
60%
SCLK rising edges between LRCLK rising edges
t(edge)
LRCLK clock edge with respect to the falling edge of SCLK
tr /
tf(SCLK/LRCLK)
Rise/fall time for SCLK/LRCLK
kHz
32
64
SCLK
edges
–1/4
1/4
SCLK
period
8
tr
ns
tf
SCLK
(Input)
t(edge)
th1
tsu1
LRCLK
(Input)
th2
tsu2
SDIN
T0026-04
Figure 3. Slave Mode Serial Data Interface Timing
10
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I2C SERIAL CONTROL PORT OPERATION
Timing characteristics for I2C Interface signals over recommended operating conditions (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
No wait states
MAX
UNIT
400
kHz
fSCL
Frequency, SCL
tw(H)
Pulse duration, SCL high
0.6
tw(L)
Pulse duration, SCL low
1.3
tr
Rise time, SCL and SDA
300
ns
tf
Fall time, SCL and SDA
300
ns
tsu1
Setup time, SDA to SCL
th1
Hold time, SCL to SDA
t(buf)
µs
µs
100
ns
0
ns
Bus free time between stop and start condition
1.3
µs
tsu2
Setup time, SCL to start condition
0.6
µs
th2
Hold time, start condition to SCL
0.6
µs
tsu3
Setup time, SCL to stop condition
0.6
CL
Load capacitance for each bus line
µs
400
tw(H)
tw(L)
pF
tf
tr
SCL
tsu1
th1
SDA
T0027-01
Figure 4. SCL and SDA Timing
SCL
t(buf)
th2
tsu2
tsu3
SDA
Start
Condition
Stop
Condition
T0028-01
Figure 5. Start and Stop Conditions Timing
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RESET TIMING (RESET)
Control signal parameters over recommended operating conditions (unless otherwise noted). Please refer to Recommended
Use Model section on usage of all terminals.
PARAMETER
tw(RESET)
Pulse duration, RESET active
td(I2C_ready)
Time to enable I2C
MIN
TYP
MAX
UNIT
13.5
ms
100
us
RESET
tw(RESET)
2
2
I C Active
I C Active
td(I2C_ready)
System Initialization.
2
Enable via I C.
T0421-01
NOTE: On power up, it is recommended that the TAS5708 RESET be held LOW for at least 100 µs after DVDD has reached
3.0 V
NOTE: If the RESET is asserted LOW while PDN is LOW, then the RESET must continue to be held LOW for at least 100 µs
after PDN is deasserted (HIGH).
Figure 6. Reset Timing
TYPICAL CHARACTERISTICS, BTL CONFIGURATION
TOTAL HARMONIC DISTORTION + NOISE
vs
FREQUENCY
TOTAL HARMONIC DISTORTION + NOISE
vs
FREQUENCY
10
THD+N − Total Harmonic Distortion + Noise − %
THD+N − Total Harmonic Distortion + Noise − %
10
PVCC = 12 V
RL = 8 Ω
1
PO = 4 W
0.1
0.01
0.001
20
PO = 2 W
100
PO = 0.5 W
1k
10k 20k
PVCC = 18 V
RL = 8 Ω
1
PO = 10 W
PO = 5 W
0.1
0.01
0.001
20
f − Frequency − Hz
PO = 1 W
100
1k
G001
Figure 7.
12
10k 20k
f − Frequency − Hz
G002
Figure 8.
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TYPICAL CHARACTERISTICS, BTL CONFIGURATION (continued)
TOTAL HARMONIC DISTORTION + NOISE
vs
FREQUENCY
TOTAL HARMONIC DISTORTION + NOISE
vs
OUTPUT POWER
10
THD+N − Total Harmonic Distortion + Noise − %
THD+N − Total Harmonic Distortion + Noise − %
10
PVCC = 24 V
RL = 8 Ω
1
PO = 10 W
PO = 5 W
0.1
0.01
PO = 1 W
0.001
20
100
1k
PVCC = 12 V
RL = 8 Ω
Volume = 6 dB
1
f = 1 kHz
f = 10 kHz
0.1
0.01
f = 20 Hz
0.001
0.01
10k 20k
0.1
f − Frequency − Hz
G003
TOTAL HARMONIC DISTORTION + NOISE
vs
OUTPUT POWER
TOTAL HARMONIC DISTORTION + NOISE
vs
OUTPUT POWER
10
THD+N − Total Harmonic Distortion + Noise − %
THD+N − Total Harmonic Distortion + Noise − %
50
G004
Figure 10.
PVCC = 18 V
RL = 8 Ω
Volume = 6 dB
1
f = 1 kHz
f = 10 kHz
0.01
f = 20 Hz
0.001
0.01
10
Figure 9.
10
0.1
1
PO − Output Power − W
0.1
1
PO − Output Power − W
10
50
PVCC = 24 V
RL = 8 Ω
Volume = 6 dB
1
f = 1 kHz
f = 10 kHz
0.1
0.01
f = 20 Hz
0.001
0.01
G005
Figure 11.
0.1
1
10
PO − Output Power − W
50
G006
Figure 12.
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TYPICAL CHARACTERISTICS, BTL CONFIGURATION (continued)
OUTPUT POWER
vs
SUPPLY VOLTAGE
EFFICIENCY
vs
OUTPUT POWER
40
100
RL = 8 Ω
90
35
30
70
Efficiency − %
PO − Output Power − W
80
THD+N = 10%
25
20
THD+N = 1%
PVCC = 24 V
PVCC = 12 V
60
PVCC = 18 V
50
40
30
15
20
10
Power represented by
dashed lines may require
additional heat sinking.
10
5
RL = 8 Ω
0
10
12
14
16
18
20
22
24
26
0
2
PVCC − Supply Voltage − V
G008
10
12
Figure 14.
CROSSTALK
vs
FREQUENCY
CROSSTALK
vs
FREQUENCY
PO = 1 W
PVCC = 12 V
RL = 8 Ω
−50
Left to Right
−70
16
18
20
G010
Right to Left
Right to Left
−80
−80
−90
−90
100
1k
Left to Right
−70
10k 20k
−100
20
f − Frequency − Hz
100
1k
10k 20k
f − Frequency − Hz
G013
Figure 15.
14
14
PO = 1 W
PVCC = 18 V
RL = 8 Ω
−60
Crosstalk − dB
Crosstalk − dB
8
−40
−60
−100
20
6
Figure 13.
−40
−50
4
PO − Output Power (Per Channel) − W
G014
Figure 16.
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TYPICAL CHARACTERISTICS, BTL CONFIGURATION (continued)
CROSSTALK
vs
FREQUENCY
−40
−50
PO = 1 W
PVCC = 24 V
RL = 8 Ω
Crosstalk − dB
−60
Left to Right
−70
Right to Left
−80
−90
−100
20
100
1k
10k 20k
f − Frequency − Hz
G015
Figure 17.
DETAILED DESCRIPTION
POWER SUPPLY
To facilitate system design, the TAS5708 needs only a 3.3-V supply in addition to the 10-V to 26-V power-stage
supply. An internal voltage regulator provides suitable voltage levels for the gate drive circuitry. Additionally, all
circuitry requiring a floating voltage supply, e.g., the high-side gate drive, is accommodated by built-in bootstrap
circuitry requiring only a few external capacitors.
In order to provide good electrical and acoustical characteristics, the PWM signal path for the output stage is
designed as identical, independent half-bridges. For this reason, each half-bridge has separate bootstrap pins
(BST_X), and power-stage supply pins (PVCC_X). The gate drive voltages (VCLAMP_AB and VCLAMP_CD) are
derived from the PVCC voltage. Special attention should be paid to placing all decoupling capacitors as close to
their associated pins as possible. In general, inductance between the power-supply pins and decoupling
capacitors must be avoided.
For a properly functioning bootstrap circuit, a small ceramic capacitor must be connected from each bootstrap pin
(BST_X) to the power-stage output pin (OUT_X). When the power-stage output is low, the bootstrap capacitor is
charged through an internal diode connected between the gate-drive regulator output pin (VCLAMP_X) and the
bootstrap pin. When the power-stage output is high, the bootstrap capacitor potential is shifted above the output
potential and thus provides a suitable voltage supply for the high-side gate driver. In an application with PWM
switching frequencies in the range from 352 kHz to 384 kHz, it is recommended to use 220-nF ceramic
capacitors, size 0603 or 0805, for the bootstrap supply. These 220-nF capacitors ensure sufficient energy
storage, even during minimal PWM duty cycles, to keep the high-side power stage FET (LDMOS) fully turned on
during the remaining part of the PWM cycle.
Special attention should be paid to the power-stage power supply; this includes component selection, PCB
placement, and routing. As indicated, each half-bridge has independent power-stage supply pins (PVCC_X). For
optimal electrical performance, EMI compliance, and system reliability, it is important that each PVCC_X pin is
decoupled with a 100-nF ceramic capacitor placed as close as possible to each supply pin.
The TAS5708 is fully protected against erroneous power-stage turnon due to parasitic gate charging.
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ERROR REPORTING
Any fault resulting in device shutdown is signaled by the FAULT pin going low (see Table 1). A sticky version of
this pin is available on D1 of register 0X02.
Table 1. FAULT Output States
FAULT
DESCRIPTION
0
Overcurrent (OC) ERROR
1
No faults (normal operation)
DEVICE PROTECTION SYSTEM
Overcurrent (OC) Protection
The device has independent, fast-reacting current detectors on all high-side and low-side power-stage FETs,
which protects against shorts across the load, to GND, or to PVCC. The protection system triggers a latching
shutdown, resulting in the power stage being set in the high-impedance (Hi-Z) state and FAULT being asserted
low. The device returns to normal operation once the fault condition (i.e., a short circuit on the output) is
removed. Current limiting and overcurrent protection are not independent for half-bridges. That is, if the
bridge-tied load between half-bridges A and B causes an overcurrent fault, half-bridges A, B, C, and D are shut
down.
Overtemperature Protection
The TAS5708 has an over-temperature protection system. If the device junction temperature exceeds 150°C
(nominal), the device is put into thermal shutdown, resulting in all half-bridge outputs being set in the
high-impedance (Hi-Z) state. The TAS5708 recovers automatically once the temperature drops approximately
15°.
Undervoltage Protection (UVP) and Overvoltage Protection (OVP)
THE UVP circuits of the TAS5708 fully protect the device in any power-up/down and brownout situation. The
UVP engages if PVCC_X = AVCC drops below 8.4-V (typical) and disengages when PVCC_X = AVCC exceeds
8.5-V. The OVP circuits protect aganist voltage spikes and engage when PVCC_X = AVCC exceeds 27.5-V
(typical). The OVP circuits disengage when PVCC_X = AVCC drops below 27.2-V. When the protection circuits
engage, all half-bridge outputs are immediately placed in the high-impedance (Hi-Z) state.
SERIAL DATA INTERFACE
Serial data is input on SDIN. The PWM outputs are derived from SDIN. The TAS5708 DAP accepts serial data in
16-, 20-, or 24-bit left-justified, right-justified, and I2S serial data formats.
CLOCK, AUTO DETECTION, and PLL
The TAS5708 is a slave device. It accepts MCLK, SCLK, and LRCLK. The digital audio processor (DAP)
supports all the sample rates and MCLK rates that are defined in the clock control register.
The TAS5708 checks to verify that SCLK is a specific value of 32 fS, 48 fS, or 64 fS. The DAP only supports a 1 ×
fS LRCLK. The timing relationship of these clocks to SDIN is shown in subsequent sections. The clock section
uses MCLK or the internal oscillator clock (when MCLK is unstable, out of range, or absent) to produce the
internal clock (DCLK) running at 512 times the PWM switching frequency.
The DAP can autodetect and set the internal clock control logic to the appropriate settings for all supported clock
rates as defined in the clock control register.
TAS5708 has robust clock error handling that uses the bulit-in trimmed oscillator clock to quickly detect
changes/errors. Once the system detects a clock change/error, it will mute the audio (through a single step mute)
and then force PLL to limp using the internal oscillator as a reference clock. Once the clocks are stable, the
system will auto detect the new rate and revert to normal operation. During this process, the default volume will
be restored in a single step (also called hard unmute). The ramp process can be programmed to ramp back
slowly (also called soft unmute) as defined in volume register (0X0E).
16
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PWM Section
The TAS5708 DAP device uses noise-shaping and sophisticated non-linear correction algorithms to achieve high
power efficiency and high-performance digital audio reproduction. The DAP uses a fourth-order noise shaper to
increase dynamic range and SNR in the audio band. The PWM section accepts 24-bit PCM data from the DAP
and outputs two BTL PWM audio output channels.
The PWM section has individual channel dc blocking filters that can be enabled and disabled. The filter cutoff
frequency is less than 1 Hz. Individual channel de-emphasis filters for 44.1- and 48-kHz are included and can be
enabled and disabled.
Finally, the PWM section has an adjustable maximum modulation limit of 93.8% to 99.2%.
For detailed description of using audio processing features like DRC and EQ, please refer to User's Guide and
TAS570X GDE software development tool documentation. Also refer to GDE software development tool for
device data path.
I2C COMPATIBLE SERIAL CONTROL INTERFACE
The TAS5708 DAP has an I2C serial control slave interface to receive commands from a system controller. The
serial control interface supports both normal-speed (100-kHz) and high-speed (400-kHz) operations without wait
states. As an added feature, this interface operates even if MCLK is absent.
The serial control interface supports both single-byte and multi-byte read and write operations for status registers
and the general control registers associated with the PWM.
SERIAL INTERFACE CONTROL AND TIMING
I2S Timing
I2S timing uses LRCLK to define when the data being transmitted is for the left channel and when it is for the
right channel. LRCLK is low for the left channel and high for the right channel. A bit clock running at 32, 48, or
64 × fS is used to clock in the data. There is a delay of one bit clock from the time the LRCLK signal changes
state to the first bit of data on the data lines. The data is written MSB first and is valid on the rising edge of bit
clock. The DAP masks unused trailing data bit positions.
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2
2-Channel I S (Philips Format) Stereo Input
32 Clks
LRCLK (Note Reversed Phase)
32 Clks
Right Channel
Left Channel
SCLK
SCLK
MSB
24-Bit Mode
23 22
LSB
9
8
5
4
5
4
1
0
1
0
1
MSB
0
LSB
23 22
9
8
5
4
19 18
5
4
1
0
15 14
1
0
1
0
20-Bit Mode
19 18
16-Bit Mode
15 14
T0034-01
NOTE: All data presented in 2s-complement form with MSB first.
Figure 18. I2S 64-fS Format
2
2-Channel I S (Philips Format) Stereo Input/Output (24-Bit Transfer Word Size)
LRCLK
24 Clks
24 Clks
Left Channel
Right Channel
SCLK
SCLK
MSB
24-Bit Mode
23 22
MSB
LSB
17 16
9
8
5
4
13 12
5
4
1
0
9
1
0
3
2
1
0
LSB
23 22
17 16
9
8
5
4
19 18
13 12
5
4
1
0
15 14
9
1
0
3
2
1
20-Bit Mode
19 18
16-Bit Mode
15 14
8
8
T0092-01
NOTE: All data presented in 2s-complement form with MSB first.
Figure 19. I2S 48-fS Format
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2
2-Channel I S (Philips Format) Stereo Input
LRCLK
16 Clks
16 Clks
Left Channel
Right Channel
SCLK
SCLK
MSB
16-Bit Mode
MSB
LSB
15 14 13 12
11 10
9
5
8
4
3
2
1
0
LSB
15 14 13 12
11 10
9
5
8
4
3
2
1
T0266-01
NOTE: All data presented in 2s-complement form with MSB first.
Figure 20. I2S 32-fS Format
Left-Justified
Left-justified (LJ) timing uses LRCLK to define when the data being transmitted is for the left channel and when it
is for the right channel. LRCLK is high for the left channel and low for the right channel. A bit clock running at 32,
48, or 64 × fS is used to clock in the data. The first bit of data appears on the data lines at the same time LRCLK
toggles. The data is written MSB first and is valid on the rising edge of the bit clock. The DAP masks unused
trailing data bit positions.
2-Channel Left-Justified Stereo Input
32 Clks
32 Clks
Left Channel
Right Channel
LRCLK
SCLK
SCLK
MSB
24-Bit Mode
23 22
LSB
9
8
5
4
5
4
1
0
1
0
1
0
MSB
LSB
23 22
9
8
5
4
19 18
5
4
1
0
15 14
1
0
1
0
20-Bit Mode
19 18
16-Bit Mode
15 14
T0034-02
NOTE: All data presented in 2s-complement form with MSB first.
Figure 21. Left-Justified 64-fS Format
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2-Channel Left-Justified Stereo Input (24-Bit Transfer Word Size)
24 Clks
24 Clks
Left Channel
Right Channel
LRCLK
SCLK
SCLK
MSB
24-Bit Mode
23 22
21
LSB
17 16
9
8
5
4
13 12
5
4
1
0
9
1
0
1
0
MSB
LSB
21
17 16
9
8
5
4
19 18 17
13 12
5
4
1
0
15 14 13
9
1
0
23 22
1
0
20-Bit Mode
19 18 17
16-Bit Mode
15 14 13
8
8
T0092-02
NOTE: All data presented in 2s-complement form with MSB first.
Figure 22. Left-Justified 48-fS Format
2-Channel Left-Justified Stereo Input
16 Clks
16 Clks
Left Channel
Right Channel
LRCLK
SCLK
SCLK
MSB
16-Bit Mode
15 14 13 12
LSB
11 10
9
8
5
4
3
2
1
0
MSB
15 14 13 12
LSB
11 10
9
8
5
4
3
2
1
0
T0266-02
NOTE: All data presented in 2s-complement form with MSB first.
Figure 23. Left-Justified 32-fS Format
Right-Justified
Right-justified (RJ) timing uses LRCLK to define when the data being transmitted is for the left channel and when
20
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it is for the right channel. LRCLK is high for the left channel and low for the right channel. A bit clock running at
32, 48, or 64 × fS is used to clock in the data. The first bit of data appears on the data 8 bit-clock periods (for
24-bit data) after LRCLK toggles. In RJ mode the LSB of data is always clocked by the last bit clock before
LRCLK transitions. The data is written MSB first and is valid on the rising edge of bit clock. The DAP masks
unused leading data bit positions.
2-Channel Right-Justified (Sony Format) Stereo Input
32 Clks
32 Clks
Left Channel
Right Channel
LRCLK
SCLK
SCLK
MSB
24-Bit Mode
LSB
23 22
19 18
15 14
1
0
19 18
15 14
1
0
15 14
1
0
MSB
LSB
23 22
19 18
15 14
1
0
19 18
15 14
1
0
15 14
1
0
20-Bit Mode
16-Bit Mode
T0034-03
Figure 24. Right Justified 64-fS Format
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2-Channel Right-Justified Stereo Input (24-Bit Transfer Word Size)
24 Clks
24 Clks
Left Channel
Right Channel
LRCLK
SCLK
SCLK
MSB
24-Bit Mode
23 22
LSB
19 18
15 14
6
5
2
1
0
19 18
15 14
6
5
2
1
0
15 14
6
5
2
1
0
MSB
23 22
LSB
19 18
15 14
6
5
2
1
0
19 18
15 14
6
5
2
1
0
15 14
6
5
2
1
0
20-Bit Mode
16-Bit Mode
T0092-03
Figure 25. Right Justified 48-fS Format
Figure 26. Right Justified 32-fS Format
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I2C SERIAL CONTROL INTERFACE
The TAS5708 DAP has a bidirectional I2C interface that compatible with the I2C (Inter IC) bus protocol and
supports both 100-kHz and 400-kHz data transfer rates for single and multiple byte write and read operations.
This is a slave only device that does not support a multimaster bus environment or wait state insertion. The
control interface is used to program the registers of the device and to read device status.
The DAP supports the standard-mode I2C bus operation (100 kHz maximum) and the fast I2C bus operation
(400 kHz maximum). The DAP performs all I2C operations without I2C wait cycles.
General I2C Operation
The I2C bus employs two signals; SDA (data) and SCL (clock), to communicate between integrated circuits in a
system. Data is transferred on the bus serially one bit at a time. The address and data can be transferred in byte
(8-bit) format, with the most significant bit (MSB) transferred first. In addition, each byte transferred on the bus is
acknowledged by the receiving device with an acknowledge bit. Each transfer operation begins with the master
device driving a start condition on the bus and ends with the master device driving a stop condition on the bus.
The bus uses transitions on the data pin (SDA) while the clock is high to indicate a start and stop conditions. A
high-to-low transition on SDA indicates a start and a low-to-high transition indicates a stop. Normal data bit
transitions must occur within the low time of the clock period. These conditions are shown in Figure 27. The
master generates the 7-bit slave address and the read/write (R/W) bit to open communication with another
device and then waits for an acknowledge condition. The TAS5708 holds SDA low during the acknowledge clock
period to indicate an acknowledgment. When this occurs, the master transmits the next byte of the sequence.
Each device is addressed by a unique 7-bit slave address plus R/W bit (1 byte). All compatible devices share the
same signals via a bidirectional bus using a wired-AND connection. An external pullup resistor must be used for
the SDA and SCL signals to set the high level for the bus.
SDA
R/
A
W
7-Bit Slave Address
7
6
5
4
3
2
1
0
8-Bit Register Address (N)
7
6
5
4
3
2
1
0
8-Bit Register Data For
Address (N)
A
7
6
5
4
3
2
1
8-Bit Register Data For
Address (N)
A
0
7
6
5
4
3
2
1
A
0
SCL
Start
Stop
T0035-01
2
Figure 27. Typical I C Sequence
There is no limit on the number of bytes that can be transmitted between start and stop conditions. When the last
word transfers, the master generates a stop condition to release the bus. A generic data transfer sequence is
shown in Figure 27.
The 7-bit address for TAS5708 is 0011 011 (0x36).
TAS5708 address can be changed from 0x36 to 0x38 by writing 0x38 to device address register 0xF9.
Single- and Multiple-Byte Transfers
The serial control interface supports both single-byte and multiple-byte read/write operations for subaddresses
0x00 to 0x1F. However, for the subaddresses 0x20 to 0xFF, the serial control interface supports only
multiple-byte read/write operations (in multiples of 4 bytes).
During multiple-byte read operations, the DAP responds with data, a byte at a time, starting at the subaddress
assigned, as long as the master device continues to respond with acknowledges. If a particular subaddress does
not contain 32 bits, the unused bits are read as logic 0.
During multiple-byte write operations, the DAP compares the number of bytes transmitted to the number of bytes
that are required for each specific subaddress. For example, if a write command is received for a biquad
subaddress, the DAP expects to receive five 32-bit words. If fewer than five 32-bit data words have been
received when a stop command (or another start command) is received, the data received is discarded.
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Supplying a subaddress for each subaddress transaction is referred to as random I2C addressing. The TAS5708
also supports sequential I2C addressing. For write transactions, if a subaddress is issued followed by data for
that subaddress and the 15 subaddresses that follow, a sequential I2C write transaction has taken place, and the
data for all 16 subaddresses is successfully received by the TAS5708. For I2C sequential write transactions, the
subaddress then serves as the start address, and the amount of data subsequently transmitted, before a stop or
start is transmitted, determines how many subaddresses are written. As was true for random addressing,
sequential addressing requires that a complete set of data be transmitted. If only a partial set of data is written to
the last subaddress, the data for the last subaddress is discarded. However, all other data written is accepted;
only the incomplete data is discarded.
Single-Byte Write
As shown in Figure 28, a single-byte data write transfer begins with the master device transmitting a start
condition followed by the I2C device address and the read/write bit. The read/write bit determines the direction of
the data transfer. For a write data transfer, the read/write bit will be a 0. After receiving the correct I2C device
address and the read/write bit, the DAP responds with an acknowledge bit. Next, the master transmits the
address byte or bytes corresponding to the TAS5708 internal memory address being accessed. After receiving
the address byte, the TAS5708 again responds with an acknowledge bit. Next, the master device transmits the
data byte to be written to the memory address being accessed. After receiving the data byte, the TAS5708 again
responds with an acknowledge bit. Finally, the master device transmits a stop condition to complete the
single-byte data write transfer.
Start
Condition
Acknowledge
A6
A5
A4
A3
A2
A1
A0
Acknowledge
R/W ACK A7
A6
A5
2
A4
A3
A2
A1
Acknowledge
A0 ACK D7
D6
Subaddress
I C Device Address and
Read/Write Bit
D5
D4
D3
D2
D1
D0 ACK
Stop
Condition
Data Byte
T0036-01
Figure 28. Single-Byte Write Transfer
Multiple-Byte Write
A multiple-byte data write transfer is identical to a single-byte data write transfer except that multiple data bytes
are transmitted by the master device to the DAP as shown in Figure 29. After receiving each data byte, the
TAS5708 responds with an acknowledge bit.
Start
Condition
Acknowledge
A6
A5
A1
A0 R/W ACK A7
2
I C Device Address and
Read/Write Bit
A6
A5
A4
A3
Subaddress
A1
Acknowledge
Acknowledge
Acknowledge
Acknowledge
A0 ACK D7
D0 ACK D7
D0 ACK D7
D0 ACK
First Data Byte
Other Data Bytes
Last Data Byte
Stop
Condition
T0036-02
Figure 29. Multiple-Byte Write Transfer
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Single-Byte Read
As shown in Figure 30, a single-byte data read transfer begins with the master device transmitting a start
condition followed by the I2C device address and the read/write bit. For the data read transfer, both a write
followed by a read are actually done. Initially, a write is done to transfer the address byte or bytes of the internal
memory address to be read. As a result, the read/write bit becomes a 0. After receiving the TAS5708 address
and the read/write bit, TAS5708 responds with an acknowledge bit. In addition, after sending the internal memory
address byte or bytes, the master device transmits another start condition followed by the TAS5708 address and
the read/write bit again. This time the read/write bit becomes a 1, indicating a read transfer. After receiving the
address and the read/write bit, the TAS5708 again responds with an acknowledge bit. Next, the TAS5708
transmits the data byte from the memory address being read. After receiving the data byte, the master device
transmits a not acknowledge followed by a stop condition to complete the single byte data read transfer.
Repeat Start
Condition
Start
Condition
Acknowledge
A6
A5
A1
A0 R/W ACK A7
Acknowledge
A6
2
A5
A4
A0 ACK
A6
A5
A1
A0 R/W ACK D7
D6
2
Subaddress
I C Device Address and
Read/Write Bit
Not
Acknowledge
Acknowledge
D1
D0 ACK
Stop
Condition
Data Byte
I C Device Address and
Read/Write Bit
T0036-03
Figure 30. Single-Byte Read Transfer
Multiple-Byte Read
A multiple-byte data read transfer is identical to a single-byte data read transfer except that multiple data bytes
are transmitted by the TAS5708 to the master device as shown in Figure 31. Except for the last data byte, the
master device responds with an acknowledge bit after receiving each data byte.
Repeat Start
Condition
Start
Condition
Acknowledge
A6
2
A0 R/W ACK A7
I C Device Address and
Read/Write Bit
Acknowledge
A6
A5
Subaddress
A6
A0 ACK
2
Acknowledge
Acknowledge
Acknowledge
Not
Acknowledge
A0 R/W ACK D7
D0 ACK D7
D0 ACK D7
D0 ACK
I C Device Address and
Read/Write Bit
First Data Byte
Other Data Bytes
Last Data Byte
Stop
Condition
T0036-04
Figure 31. Multiple Byte Read Transfer
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Dynamic Range Control (DRC)
The DRC scheme has a single threshold, offset, and slope (all programmable). There is one ganged DRC for the
left/right channels.
Output Level (dB)
The DRC input/output diagram is shown in Figure 32.
K
1:1 Transfer Function
O
Implemented Transfer Function
T
Input Level (dB)
M0091-02
Professional-quality dynamic range compression automatically adjusts volume to flatten volume level.
• One DRC for left/right
• The DRC has adjustable threshold, offset, and compression levels
• Programmable energy, attack, and decay time constants
• Transparent compression: compressors can attack fast enough to avoid apparent clipping before engaging,
and decay times can be set slow enough to avoid pumping.
Figure 32. Dynamic Range Control
Audio Input
DRC
Energy
Filter
Compression
Control
Attack
and
Decay
Filters
a, w
T, K, O
aa, wa / ad, wd
0x3A
0x40, 0x41, 0x42
0x3B / 0x3C
DRC Coefficient
Alpha Filter Structure
S
a
w
–1
Z
NOTE:
w=1–α
B0265-03
Figure 33. DRC Structure
26
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BiQuad Structure
All biquads use a 2nd order IIR filter structure as shown below. Each biquad has 3 coefficients on the direct path
(b0,b1,b2) and 2 coefficients on feedback path (a1 and a2) as shown in the diagram.
b0
x(n)
S
b1
z
a1
–1
z
b2
z
y(n)
Magnitude
Truncation
–1
a2
–1
z
–1
M0012-02
Figure 34. Biquad Filter
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BANK SWITCHING
The TAS5708 uses an approach called bank switching together with automatic sample-rate detection. All
processing features that must be changed for different sample rates are stored internally in three banks. The
user can program which sample rates map to each bank. By default, bank 1 is used in 32kHz mode, bank 2 is
used in 44.1/48 kHz mode, and bank 3 is used for all other rates. Combined with the clock-rate autodetection
feature, bank switching allows the TAS5708 to detect automatically a change in the input sample rate and switch
to the appropriate bank without any MCU intervention.
An external controller configures bankable locations (0x29-0x36 and 0x3A-0x3C) for all three banks during the
initialization sequence.
If auto bank switching is enabled (register 0x50, bits 2:0) , then the TAS5708 automatically swaps the coefficients
for subsequent sample rate changes, avoiding the need for any external controller intervention for a sample rate
change.
By default, bits 2:0 have the value 000; indicating that bank switching is disabled. In that state, updates to
bankable locations take immediate effect. A write to register 0x50 with bits 2:0 being 001, 010, or 011 brings the
system into the coefficient-bank-update state update bank1, update bank2, or update bank3, respectively. Any
subsequent write to bankable locations updates the coefficient banks stored outside the DAP. After updating all
the three banks, the system controller should issue a write to register 0x50 with bits 2:0 being 100; this changes
the system state to automatic bank switching mode. In automatic bank switching mode, the TAS5708
automatically swaps banks based on the sample rate.
Command sequences for updating DAP coefficients can be summarized as follows:
1. Bank switching disabled (default): DAP coefficient writes take immediate effect and are not
influenced by subsequent sample rate changes.
OR
Bank switching enabled:
a. Update bank-1 mode: Write "001" to bits 2:0 of reg 0x50. Load the 32 kHz coefficients.
b. Update bank-2 mode: Write "010" to bits 2:0 of reg 0x50. Load the 48 kHz coefficients.
c. Update bank-3 mode: Write "011" to bits 2:0 of reg 0x50. Load the other coefficients.
d. Enable automatic bank switching by writing "100" to bits 2:0 of reg 0x50.
26-Bit 3.23 Number Format
All mixer gain coefficients are 26-bit coefficients using a 3.23 number format. Numbers formatted as 3.23
numbers means that there are 3 bits to the left of the decimal point and 23 bits to the right of the decimal point.
This is shown in Figure 35 .
2
–23
2
2
–5
–1
Bit
Bit
Bit
0
2 Bit
1
2 Bit
Sign Bit
S_xx.xxxx_xxxx_xxxx_xxxx_xxxx_xxx
M0125-01
Figure 35. 3.23 Format
28
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The decimal value of a 3.23 format number can be found by following the weighting shown in Figure 35. If the
most significant bit is logic 0, the number is a positive number, and the weighting shown yields the correct
number. If the most significant bit is a logic 1, then the number is a negative number. In this case every bit must
be inverted, a 1 added to the result, and then the weighting shown in Figure 36 applied to obtain the magnitude
of the negative number.
0
1
2 Bit
2 Bit
1
2
–1
Bit
0
2
(1 or 0) ´ 2 + (1 or 0) ´ 2 + (1 or 0) ´ 2
–1
–4
Bit
2
+ ....... (1 or 0) ´ 2
–4
–23
Bit
+ ....... (1 or 0) ´ 2
–23
M0126-01
Figure 36. Conversion Weighting Factors—3.23 Format to Floating Point
Gain coefficients, entered via the I2C bus, must be entered as 32-bit binary numbers. The format of the 32-bit
number (4-byte or 8-digit hexadecimal number) is shown in Figure 37
Fraction
Digit 6
Sign
Bit
Fraction
Digit 1
Integer
Digit 1
Fraction
Digit 2
Fraction
Digit 3
Fraction
Digit 4
Fraction
Digit 5
u u u u
u u S x
x. x x x
x x x x
x x x x
x x x x
x x x x
x x x x 0
Coefficient
Digit 8
Coefficient
Digit 7
Coefficient
Digit 6
Coefficient
Digit 5
Coefficient
Digit 4
Coefficient
Digit 3
Coefficient
Digit 2
Coefficient
Digit 1
u = unused or don’t care bits
Digit = hexadecimal digit
M0127-01
Figure 37. Alignment of 3.23 Coefficient in 32-Bit I2C Word
Sample calculation for 3.23 format
db
Linear
Decimal
0
1
8388608
Hex (3.23 Format)
00800000
5
1.7782794
14917288
00E39EA8
-5
0.5623413
4717260
0047FACC
X
L = 10(X/20)
D = 8388608 × L
H = dec2hex (D, 8)
Sample calculation for 9.17 format
db
Linear
Decimal
Hex (9.17 Format)
0
1
131072
00020000
5
1.7782794
233082.6
00038E7A
-5
0.5623413
73707.2
00011FEB
X
L = 10(X/20)
D = 131072 × L
H = dec2hex (D, 8)
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APPLICATION INFORMATION
Calculation of Output Signal Level of TAS5708 Feedback Power Stage
(Gain Is independent of PVCC)
The gain of the TAS5708 is the total digital gain of the controller multiplied by the gain of the power stage.
For a half-bridge channel of the TAS5708 power stage, the gain is simply:
Power stage gain = 13 × VRMS / Modulation Level
Modulation level = fraction of full-scale modulation of the PWM signal at the input of the power stage.
VRMS(SE) = Audio voltage level at the output of the power stage = 13 × Modulation Level
VRMS(BTL) = 2 × Audio voltage level at the output of the power stage = 26 × Modulation Level
For the TAS5708 controller, the gain is the programmed digital gain multiplied by a scaling factor, called the
maximum modulation level. The maximum modulation level is derived from the modulation limit programmed in
the controller, which limits duty cycle to a set number of percent above 0% and below 100%. Setting the
modulation limit to 97.7% (default) limits the duty cycle between 2.3% and 97.7%.
Controller gain = digital gain × maximum modulation level × (modulation level/digital FFS)
Digital FFS = digital input fraction of full scale
Modulation limit = 97.7%
Maximum modulation level = 2 × modulation limit – 1 = 0.954
The output signal level of the TAS5708 can now be calculated:
VRMS(SE) = digital FFS × digital gain × maximum modulation level × 13
VRMS(BTL) = 2 × VRMS(SE)
With the modulation limit set at the default level of 97.7%, this becomes:
VRMS (BTL) = digital FFS × digital gain × 24.8
Example: Input = –20 dbFS; volume = 0 dB; biquads = ALL PASS; modulation index = 97.7%; mode = BTL
Output VRMS (BTL) = 24.8 × 0.1 × 1 = 2.48 V.
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PVCC/AVCC
RESET
HIZ
SCL
SDA
I C
2
MCLK
LRCLK
SCLK
SDIN
2
I S
PDN
AVDD/DVDD
3V
10 V
7.5 V
tVDDH-PVCCL
tDV-RH
tVDDH-DL
tPVCCH-I2C
tRH-I2C
Trim
tPOR
Other
Config
tautodetect
DAP
Config
Stable and Valid Clocks
Initialization
Exit
SD
texitSD
texitSD
tPOR
(Reconfigure DAP After Shutdown)
tRL-PVCCH
Powerdown
tDL-VDDH
10 V
7.5 V
tPVCCL-VDDH
tRL-DV
tenterSD
Stable and Valid Clocks
Shutdown
Enter
SD
(Return to Normal Operation After Shutdown)
Volume and Mute Commands
tautodetect
Clock Errors and
Rate Changes OK
Normal Operation
T0419-02
3V
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Recommended Use Model
Figure 38. Recommended Command Sequence
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PARAMETER DESCRIPTION
MIN
MAX
UNIT
tVDDH-DL
Time digital inputs must remain low after AVDD/DVDD goes above 3V
0
µs
tDL-VDDH
Time digital inputs must be low before AVDD/DVDD goes below 3V
0
µs
100
µs
tVDDH-PVCCL
Time PVCC/AVCC remains below 7.5V after AVDD/DVDD goes above 3V
tPVCCL-VDDH
Time PVCC/AVCC must be below 7.5V before AVDD/DVDD goes below
3V
0
µs
tPVCCH-I2C
Time PVCC/AVCC must be above 10V before I2C commands may
address device
10
µs
tRL-PVCCH
Time PVCC/AVCC must remain above 10V after RESET goes low
2
µs
tRH-I2C
Time RESET must be high before I2C commands may address device
13.5
ms
tDV-RH
Time digital inputs must be valid (driven as recommended) before RESET
goes high
100
µs
tRL-DV
Time digital inputs must remain valid (driven as recommended) after
RESET goes low
2
µs
Autodetect completion wait time (given stable and valid clocks) before
issuing further commands
50
ms
tautodetect
texitSD
Exit shutdown wait time before issuing further commands to device (tstart
given by register 0x1A)
1+1.3*tstart
ms
tenterSD
Enter shutdown wait time before issuing further commands to device (tstop
given by register 0x1A)
1+1.3*tstop
ms
tPOR
Power-on-reset wait time after 1st trim following AVDD/DVDD power-up
(tstart given by register 0x1A) (does not apply to trim commands following
subsequent resets)
240+1.3*tstart
ms
Sudden Power Loss
(AD BTL)
Sudden Power Loss
(BD BTL)
3V
AVDD/DVDD
3V
AVDD/DVDD
tDL-VDDH
tDL-VDDH
PDN
PDN
2
I S
2
TYP
I C
MCLK
LRCLK
SCLK
SDIN
I S
SCL
SDA
I C
2
2
MCLK
LRCLK
SCLK
SDIN
SCL
SDA
tPL-HL
tPL-HL
HIZ
HIZ
tHL-RL
tHL-DV
tRL-DV
RESET
RESET
tRL-PVCCH
tHL-PVCCH
tPVCCL-VDDH
tPVCCL-VDDH
PVCC/AVCC
10 V
7.5 V
PVCC\AVCC
10 V
7.5 V
T0420-03
T0420-02
Figure 39. BD BTL Power Loss Sequence
32
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Figure 40. AD BTL Power Loss Sequence
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PARAMETER
DESCRIPTION
MIN
TYP
MAX
UNIT
tPL-HL
Time HIZ must remain high after PDN goes low
2
ms
tHL-RL
Time RESET must remain high after HIZ goes low
4
µs
tHL-DV
Time digital inputs must remain valid (driven as recommended) after HIZ
goes low
4
µs
tRL-DV
Time digital inputs must remain valid (driven as recommended) after
RESET goes low
2
µs
tDL-VDDH
Time digital inputs must be low before AVDD/DVDD goes below 3V
0
µs
tHL-PVCCH
Time PVCC/AVCC must remain above 10V after HIZ goes low
4
µs
tRL-PVCCH
Time PVCC/AVCC must remain above 10V after RESET goes low
2
µs
Time PVCC/AVCC must be below 7.5V before AVDD/DVDD goes below
3V
0
µs
tPVCCL-VDDH
Recommended Command Sequences
The DAP has two groups of commands. One set is for configuration and is intended for use only during
initialization. The other set has built-in click and pop protection and may be used during normal operation while
audio is streaming. The following supported command sequences illustrate how to initialize, operate, and
shutdown the device.
Initialization Sequence
Use the following sequence to power-up and initialize the device:
1. Hold all digital inputs low and ramp up AVDD/DVDD to at least 3V.
2. Initialize digital inputs and PVCC/AVCC supply as follows:
•
Drive RESET=0, PDN=1, HIZ=1, and other digital inputs to their desired state, observing
absolute maximum ratings relative to AVDD/DVDD. Provide stable and valid I2S clocks (MCLK,
LRCLK, and SCLK). Wait at least 100us, drive RESET=1, and wait at least another 13.5ms.
•
Ramp up PVCC/AVCC to at least 10V while ensuring it remains below 7.5V for at least 100us
after AVDD/DVDD reaches 3V. Then wait at least another 10us.
3. Trim oscillator (write 0x00 to register 0x1B) and wait at least 50ms.
4. Configure the DAP via I2C (see Users's Guide for typical values):
Biquads (0x29-36)
DRC parameters (0x3A-3C, 0x40-42, and 0x46)
Bank select (0x50)
5. Configure remaining registers
6. Exit shutdown (sequence defined below).
Normal Operation
The following are the only events supported during normal operation:
(a) Writes to master/channel volume registers
(b) Writes to soft mute register
(c) Enter and exit shutdown (sequence defined below)
(d) Clock errors and rate changes
Note: Events (c) and (d) are not supported for 240ms+1.3*tstart after trim following AVDD/DVDD powerup
ramp (where tstart is specified by register 0x1A).
Shutdown Sequence
Enter:
1. Ensure I2S clocks have been stable and valid for at least 50ms.
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2. Write 0x40 to register 0x05.
3. Wait at least 1ms+1.3*tstop (where tstop is specified by register 0x1A).
4. Once in shutdown, stable clocks are not required while device remains idle.
5. If desired, reconfigure by ensuring that clocks have been stable and valid for at least 50ms before
returning to step 4 of initialization sequence.
Exit:
1. Ensure I2S clocks have been stable and valid for at least 50ms.
2. Write 0x00 to register 0x05 (exit shutdown command may not be serviced for as much as 240ms
after trim following AVDD/DVDD powerup ramp).
3. Wait at least 1ms+1.3*tstart (where tstart is specified by register 0x1A).
4. Proceed with normal operation.
Controlled Powerdown Sequence
Use the following sequence to powerdown the device and its supplies when time permits a controlled
shutdown:
1. Enter shutdown (sequence defined above).
2. Assert RESET=0.
3. Drive digital inputs low and ramp down PVCC/AVCC supply as follows:
•
Drive all digital inputs low after RESET has been low for at least 2us.
•
Ramp down PVCC/AVCC while ensuring that it remains above 10V until RESET has been low
for at least 2us.
4. Ramp down AVDD/DVDD while ensuring that it remains above 3V until PVCC/AVCC is below 7.5V
and observing absolute maximum ratings for digital inputs.
Power Loss Sequence (BD BTL)
Use the following sequence to powerdown a BD BTL device and its supplies in case of sudden power loss
when time does not permit a controlled shutdown:
1. Assert PDN = 0 and wait at least 2ms.
2. Assert HIZ = 0.
3. Drive digital inputs low and ramp down PVCC/AVCC supply as follows:
•
Drive all digital inputs low after HIZ has been low for at least 4µs.
•
Ramp down PVCC/AVCC while ensuring that it remains above 10V until HIZ has been low for at
least 4µs.
4. Ramp down AVDD/DVDD while ensuring that it remains above 3V until PVCC/AVCC is below 7.5V
and observing absolute maximum ratings for digital inputs.
Power Loss Sequence (AD BTL)
Use the following sequence to powerdown an AD BTL device and its supplies in case of sudden power loss
when time does not permit a controlled shutdown:
1. Assert PDN = 0 and wait at least 2ms then assert HIZ = 0 and wait at least 4µs.
2. Assert RESET = 0.
3. Drive digital inputs low and ramp down PVCC/AVCC supply as follows:
34
•
Drive all digital inputs low after RESET has been low for at least 2µs.
•
Ramp down PVCC/AVCC while ensuring that it remains above 10V until RESET has been low
for at least 2µs.
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4. Ramp down AVDD/DVDD while ensuring that it remains above 3V until PVCC/AVCC is below 7.5V
and observing absolute maximum ratings for digital inputs.
Table 2. Serial Control Interface Register Summary (1)
SUBADDRESS
REGISTER NAME
NO. OF
BYTES
INITIALIZATION
VALUE
CONTENTS
A u indicates unused bits.
0x00
Clock control register
1
Description shown in subsequent section
0x6C
0x01
Device ID register
1
Description shown in subsequent section
0x68
0x02
Error status register
1
Description shown in subsequent section
0x00
0x03
System control register 1
1
Description shown in subsequent section
0xA0
0x04
Serial data interface
register
1
Description shown in subsequent section
0x05
0x05
System control register 2
1
Description shown in subsequent section
0x40
0x06
Soft mute register
1
Description shown in subsequent section
0x00
0x07
Master volume
1
Description shown in subsequent section
0xFF (mute)
0x08
Channel 1 vol
1
Description shown in subsequent section
0x30 (0 dB)
0x09
Channel 2 vol
1
Description shown in subsequent section
0x30 (0 dB)
0x0A
Fine master volume
1
Description shown in subsequent section
0x00 (0 dB)
0x0B - 0X0D
0x0E
Volume configuration
register
0x0F
1
Reserved
1
Description shown in subsequent section
1
Reserved (2)
0x91
0x10
Modulation limit register
1
Description shown in subsequent section
0x02
0x11
IC delay channel 1
1
Description shown in subsequent section
0x4C
0x12
IC delay channel 2
1
Description shown in subsequent section
0x34
0x13
IC delay channel 3
1
Description shown in subsequent section
0x1C
0x14
IC delay channel 4
1
Description shown in subsequent section
0x64
1
Reserved (2)
0x15-0x19
0x1A
Start/stop period register
1
Description shown in subsequent section
0x0A
0x1B
Oscillator trim register
1
Description shown in subsequent section
0x82
0x1C
BKND_ERR register
1
Description shown in subsequent section
0x02
0x1D–0x1F
0x20
Input MUX register
0x21-0x24
0x25
PWM MUX register
0x26-0x28
0x29
0x2A
(1)
(2)
(2)
ch1_bq[0]
ch1_bq[1]
(2)
1
Reserved
4
Description shown in subsequent section
4
Reserved (2)
4
Description shown in subsequent section
0x 0089 777A
0x0102 1345
(2)
4
Reserved
20
u[31:26], b0[25:0]
0x0080 0000
u[31:26], b1[25:0]
0x0000 0000
u[31:26], b2[25:0]
0x0000 0000
u[31:26], a1[25:0]
0x0000 0000
u[31:26], a2[25:0]
0x0000 0000
u[31:26], b0[25:0]
0x0080 0000
u[31:26], b1[25:0]
0x0000 0000
u[31:26], b2[25:0]
0x0000 0000
u[31:26], a1[25:0]
0x0000 0000
u[31:26], a2[25:0]
0x0000 0000
20
Reserved registers should not be accessed.
Reserved registers should not be accessed.
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Table 2. Serial Control Interface Register Summary (continued)
SUBADDRESS
0x2B
0x2C
0x2D
0x2E
0x2F
0x30
0x31
0x32
0x33
36
REGISTER NAME
ch1_bq[2]
ch1_bq[3]
ch1_bq[4]
ch1_bq[5]
ch1_bq[6]
ch2_bq[0]
ch2_bq[1]
ch2_bq[2]
ch2_bq[3]
NO. OF
BYTES
20
20
20
20
20
20
20
20
20
CONTENTS
INITIALIZATION
VALUE
u[31:26], b0[25:0]
0x0080 0000
u[31:26], b1[25:0]
0x0000 0000
u[31:26], b2[25:0]
0x0000 0000
u[31:26], a1[25:0]
0x0000 0000
u[31:26], a2[25:0]
0x0000 0000
u[31:26], b0[25:0]
0x0080 0000
u[31:26], b1[25:0]
0x0000 0000
u[31:26], b2[25:0]
0x0000 0000
u[31:26], a1[25:0]
0x0000 0000
u[31:26], a2[25:0]
0x0000 0000
u[31:26], b0[25:0]
0x0080 0000
u[31:26], b1[25:0]
0x0000 0000
u[31:26], b2[25:0]
0x0000 0000
u[31:26], a1[25:0]
0x0000 0000
u[31:26], a2[25:0]
0x0000 0000
u[31:26], b0[25:0]
0x0080 0000
u[31:26], b1[25:0]
0x0000 0000
u[31:26], b2[25:0]
0x0000 0000
u[31:26], a1[25:0]
0x0000 0000
u[31:26], a2[25:0]
0x0000 0000
u[31:26], b0[25:0]
0x0080 0000
u[31:26], b1[25:0]
0x0000 0000
u[31:26], b2[25:0]
0x0000 0000
u[31:26], a1[25:0]
0x0000 0000
u[31:26], a2[25:0]
0x0000 0000
u[31:26], b0[25:0]
0x0080 0000
u[31:26], b1[25:0]
0x0000 0000
u[31:26], b2[25:0]
0x0000 0000
u[31:26], a1[25:0]
0x0000 0000
u[31:26], a2[25:0]
0x0000 0000
u[31:26], b0[25:0]
0x0080 0000
u[31:26], b1[25:0]
0x0000 0000
u[31:26], b2[25:0]
0x0000 0000
u[31:26], a1[25:0]
0x0000 0000
u[31:26], a2[25:0]
0x0000 0000
u[31:26], b0[25:0]
0x0080 0000
u[31:26], b1[25:0]
0x0000 0000
u[31:26], b2[25:0]
0x0000 0000
u[31:26], a1[25:0]
0x0000 0000
u[31:26], a2[25:0]
0x0000 0000
u[31:26], b0[25:0]
0x0080 0000
u[31:26], b1[25:0]
0x0000 0000
u[31:26], b2[25:0]
0x0000 0000
u[31:26], a1[25:0]
0x0000 0000
u[31:26], a2[25:0]
0x0000 0000
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TAS5708
www.ti.com ........................................................................................................................................................................................... SLOS570 – DECEMBER 2008
Table 2. Serial Control Interface Register Summary (continued)
SUBADDRESS
0x34
0x35
0x36
REGISTER NAME
ch2_bq[4]
ch2_bq[5]
ch2_bq[6]
NO. OF
BYTES
20
20
20
0x37 - 0x39
0x3A
0x3B
0x3C
DRC (1 – ae)
DRC aa
DRC (1 – aa)
DRC ad
DRC (1 – ad)
8
8
8
0x0080 0000
u[31:26], b1[25:0]
0x0000 0000
u[31:26], b2[25:0]
0x0000 0000
u[31:26], a1[25:0]
0x0000 0000
u[31:26], a2[25:0]
0x0000 0000
u[31:26], b0[25:0]
0x0080 0000
u[31:26], b1[25:0]
0x0000 0000
u[31:26], b2[25:0]
0x0000 0000
u[31:26], a1[25:0]
0x0000 0000
u[31:26], a2[25:0]
0x0000 0000
u[31:26], b0[25:0]
0x0080 0000
u[31:26], b1[25:0]
0x0000 0000
u[31:26], b2[25:0]
0x0000 0000
u[31:26], a1[25:0]
0x0000 0000
u[31:26], a2[25:0]
0x0000 0000
(3)
u[31:26], ae[25:0]
0x0080 0000
u[31:26], (1 – ae)[25:0]
0x0000 0000
u[31:26], aa[25:0]
0x0080 0000
u[31:26], (1 – aa)[25:0]
0x0000 0000
u[31:26], ad[25:0]
0x0080 0000
u[31:26], (1 – ad)[25:0]
0x0000 0000
(2)
0x3D–0x3F
Reserved
0x40
DRC-T
4
T[31:0] (9.23 format)
0xFDA2 1490
0x41
DRC-K
4
u[31:26], K[25:0]
0x0384 2109
0x42
DRC-O
4
u[31:26], O[25:0]
0x0008 4210
Reserved(2)
0x43–0x45
0x46
DRC control
4
0x50
Bank switch control
4
0x0000 0000
Description shown in subsequent section
0x0F70 8000
Reserved(2)
0x51–0xF8
0xF9
Description shown in subsequent section
Reserved(2)
0x47–0x4F
Update Device Address
0xFA-0xFF
(3)
(4)
u[31:26], b0[25:0]
Reserved
DRC ae (4)
INITIALIZATION
VALUE
CONTENTS
4
u[31:8],New Dev Id[7:0] (New Dev Id = 0x38)
0x00000036
(2)
Reserved
Reserved registers should not be accessed.
"ae" stands for ∝ of energy filter, "aa" stands for ∝ of attack filter and "ad" stands for ∝ of decay filter and 1- ∝ = ω.
Note: All DAP coefficients are 3.23 format unless specified otherwise
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TAS5708
SLOS570 – DECEMBER 2008 ........................................................................................................................................................................................... www.ti.com
CLOCK CONTROL REGISTER (0x00)
The clocks and data rates are automatically determined by the TAS5708. The clock control register contains the
auto-detected clock status. Bits D7–D5 reflect the sample rate. Bits D4–D2 reflect the MCLK frequency.TAS5708
accepts a 64 Fs or 32 Fs SCLK rate for all MCLK ratios, but accepts a 48Fs SCLK rate only for MCLK ratios of
192 Fs and 384 Fs.
Table 3. Clock Control Register (0x00)
D7
D6
D5
D4
D3
D2
D1
D0
0
0
0
–
–
–
–
–
fS = 32-kHz sample rate
0
0
1
–
–
–
–
–
Reserved (1)
0
1
0
–
–
–
–
–
Reserved (1)
0
1
1
–
–
–
–
–
fS = 44.1/48-kHz sample rate
1
0
0
–
–
–
–
–
fs = 16-kHz sample rate
1
0
1
–
–
–
–
–
fs = 22.05/24 -kHz sample rate
1
1
0
–
–
–
–
–
fs = 8-kHz sample rate
1
1
1
–
–
–
–
–
fs = 11.025/12 -kHz sample rate
–
–
–
0
0
0
–
–
MCLK frequency = 64 × fS (3)
–
–
–
0
0
1
–
–
MCLK frequency = 128 × fS (3)
–
–
–
0
1
0
–
–
MCLK frequency = 192 × fS
–
–
–
0
1
1
–
–
MCLK frequency = 256 × fS
–
–
–
1
0
0
–
–
MCLK frequency = 384 × fS
–
–
–
1
0
1
–
–
MCLK frequency = 512 × fS
–
–
–
1
1
0
–
–
Reserved (1)
–
–
–
1
1
1
–
–
Reserved (1)
–
–
–
–
–
–
0
–
Reserved (1)
–
–
–
–
–
–
–
0
Reserved (1)
(1)
(2)
(3)
(4)
(5)
FUNCTION
(2)
(4)
(2) (5)
Reserved registers should not be accessed.
Default values are in bold.
Only available for 44.1 kHz and 48 kHz rates.
Rate only available for 32/44.1/48 KHz sample rates
Not available at 8 kHz
DEVICE ID REGISTER (0x01)
The device ID register contains the ID code for the firmware revision.
Table 4. General Status Register (0x01)
D7
D6
D5
D4
D3
D2
D1
D0
X
–
–
–
–
–
–
–
Reserved
–
1
1
0
1
0
0
0
Identification code
38
FUNCTION
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TAS5708
www.ti.com ........................................................................................................................................................................................... SLOS570 – DECEMBER 2008
ERROR STATUS REGISTER (0x02)
The error bits are sticky and are not cleared by the hardware. This means that the software must clear the
register (write zeroes) and then read them to determine if they are persistent errors.
Error Definitions:
• MCLK Error : MCLK frequency is changing. The number of MCLKs per LRCLK is changing.
• SCLK Error: The number of SCLKs per LRCLK is changing.
• LRCLK Error: LRCLK frequency is changing.
• Frame Slip: LRCLK phase is drifting with respect to internal Frame Sync.
Table 5. Error Status Register (0x02)
D7
D6
D5
D4
D3
D2
D1
D0
1
-
–
–
–
–
–
–
MCLK error
–
1
–
–
–
–
–
–
PLL autolock error
–
–
1
–
–
–
–
–
SCLK error
–
–
–
1
–
–
–
–
LRCLK error
–
–
–
–
1
–
–
–
Frame slip
–
–
–
–
–
–
1
–
Over current error
0
0
0
0
0
0
0
-
No errors
(1)
FUNCTION
(1)
Default values are in bold.
SYSTEM CONTROL REGISTER 1 (0x03)
The system control register 1 has several functions:
Bit D7:
If 0, the dc-blocking filter for each channel is disabled.
If 1, the dc-blocking filter (–3 dB cutoff
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