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TAS5727
SLOS670B – NOVEMBER 2010 – REVISED DECEMBER 2016
TAS5727 25-W Digital Audio Power Amplifier With EQ and DRC
1 Features
•
1
•
•
Audio Input and Output
– 25 W Into an 8-Ω Load From a 20-V Supply
– Wide PVDD Range, From 8 V to 26 V
– Supports BTL Configuration With 4-Ω Load
– Efficient Class-D Operation Eliminates Need
for Heatsinks
– One Serial Audio Input (Two Audio Channels)
– I2C Address Selection Pin (Chip Select)
– Single Output Filter PBTL Support
– Supports 44.1-kHz to 48-kHz Sample Rate
(LJ/RJ/I2S)
Audio and PWM Processing
– Independent Channel Volume Controls With
Gain of 24 dB to Mute With 0.125-dB
Resolution Steps
– Programmable Two-Band Dynamic-Range
Control
– 18 Programmable Biquads for Speaker EQ
and Other Audio-Processing Features
– Programmable Coefficients for DRC Filters
– DC Blocking Filters
General Features
– I2C Serial Control Interface Operational
Without MCLK
– Requires Only 3.3 V and PVDD
– No External Oscillator: Internal Oscillator for
Automatic Rate Detection
– Surface-Mount, 48-Pin HTQFP Package
– Thermal and Short-Circuit Protection
– 106-dB SNR, A-Weighted
•
– AD, BD, and Ternary Modulation
– Up to 90% Efficient
– PWM Level Meter to Measure the Digital
Power Profile
Benefits
– EQ: Speaker Equalization Improves Audio
Performance
– Two-Band DRC: Dynamic Range
Compression. Can Be Used As Power Limiter.
Enables Speaker Protection, Easy Listening,
Night-Mode Listening
– Autodetect: Automatically Detects SampleRate Changes. No Need for External
Microprocessor Intervention
2 Applications
•
LCD TV, LED TV, Soundbar
3 Description
The TAS5727 is a 25-W, efficient, digital-audio power
amplifier for driving stereo bridge-tied speakers. One
serial data input allows processing of up to two
discrete audio channels and seamless integration to
most digital audio processors and MPEG decoders.
The device accepts a wide range of input data and
data rates. A fully programmable data path routes
these channels to the internal speaker drivers.
Device Information(1)
PART NUMBER
TAS5727
PACKAGE
HTQFP (48)
BODY SIZE (NOM)
7.00 mm × 7.00 mm
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
Functional View
SDIN
Serial
Audio
Port
Digital Audio Processor
(DAP)
S
R
C
4th
Order
Noise
Shaper
and
PWM
2´ HB
FET Out
2´ HB
FET Out
OUT_A
OUT_B
OUT_C
OUT_D
Protection
Logic
MCLK
SCLK
LRCLK
SDA
SCL
Click and Pop
Control
Sample Rate
Autodetect
and PLL
Serial
Control
Microcontroller
Based
System
Control
Terminal Control
B0262-06
Copyright © 2016 Texas Instruments Incorporated
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
TAS5727
SLOS670B – NOVEMBER 2010 – REVISED DECEMBER 2016
www.ti.com
Table of Contents
1
2
3
4
5
6
7
8
Features ..................................................................
Applications ...........................................................
Description .............................................................
Revision History.....................................................
Description (continued).........................................
Device Comparison Table.....................................
Pin Configuration and Functions .........................
Specifications.........................................................
1
1
1
2
3
3
4
6
8.1
8.2
8.3
8.4
8.5
8.6
8.7
Absolute Maximum Ratings ...................................... 6
ESD Ratings.............................................................. 6
Recommended Operating Conditions....................... 6
Thermal Information .................................................. 7
DC Electrical Characteristics .................................... 7
AC Electrical Characteristics (BTL, PBTL)................ 8
PLL Input Parameters and External Filter
Components............................................................... 8
8.8 Serial Audio Ports Slave Mode ................................. 8
8.9 I2C Serial Control Port Operation.............................. 9
8.10 Reset Timing (RESET) ........................................... 9
8.11 Typical Characteristics .......................................... 11
9 Parameter Measurement Information ................ 12
10 Detailed Description ........................................... 13
10.1 Overview ............................................................... 13
10.2
10.3
10.4
10.5
10.6
Functional Block Diagrams ...................................
Feature Description...............................................
Device Functional Modes......................................
Programming ........................................................
Register Maps ......................................................
13
15
28
29
31
11 Application and Implementation........................ 54
11.1 Application Information.......................................... 54
11.2 Typical Applications .............................................. 54
12 Power Supply Recommendations ..................... 59
12.1 DVDD and AVDD Supplies ................................... 59
12.2 PVDD Power Supply ............................................. 59
13 Layout................................................................... 60
13.1 Layout Guidelines ................................................. 60
13.2 Layout Example .................................................... 60
14 Device and Documentation Support ................. 61
14.1
14.2
14.3
14.4
14.5
14.6
14.7
Device Support......................................................
Documentation Support ........................................
Receiving Notification of Documentation Updates
Community Resources..........................................
Trademarks ...........................................................
Electrostatic Discharge Caution ............................
Glossary ................................................................
61
61
61
61
61
61
61
15 Mechanical, Packaging, and Orderable
Information ........................................................... 61
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision A (May 2016) to Revision B
•
Page
Added Note 1 to PVDD_x in the Recommended Operating Conditions table ....................................................................... 6
Changes from Original (November 2010) to Revision A
Page
•
Added ESD Ratings table, Feature Description section, Device Functional Modes, Application and Implementation
section, Power Supply Recommendations section, Layout section, Device and Documentation Support section, and
Mechanical, Packaging, and Orderable Information section. ................................................................................................. 1
•
Changed Section: Overcurrent (OC) Protection With Current Limiting ................................................................................ 16
•
Changed Section: Overcurrent (OC) Protection With Current Limiting and Overload Detection ......................................... 16
2
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SLOS670B – NOVEMBER 2010 – REVISED DECEMBER 2016
5 Description (continued)
The TAS5727 is a slave-only device receiving all clocks from external sources. The TAS5727 operates with a
PWM carrier between a 384-kHz switching rate and a 288-KHz switching rate, depending on the input sample
rate. Oversampling combined with a fourth-order noise shaper provides a flat noise floor and excellent dynamic
range from 20 Hz to 20 kHz.
6 Device Comparison Table
TAS5727
TAS5729MD
Maximum power to single-ended load
TAS5731M
TAS5721
18
10
Maximum power to bridge tied load
35
20
37
15
Maximum power to parallel bridge tied load
70
40
70
30
2
4
4
8
Minimum supported single-ended load
Minimum supported bridge tied load
Minimum supported parallel bridge tied load
Closed- or open-loop
Maximum speaker outputs (#)
Headphone channels
Architecture
Dynamic range control (DRC)
Biquads (EQ)
4
4
2
4
2
4
Open
Open
Open
Open
2
2
3
3
No
Yes
No
Yes
Class D
Class D
Class D
Class D
2-Band AGL
2-Band AGL
2-Band DRC
2-Band DRC
28
28
21
21
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TAS5727
SLOS670B – NOVEMBER 2010 – REVISED DECEMBER 2016
www.ti.com
7 Pin Configuration and Functions
PGND_AB
PGND_AB
OUT_B
NC
NC
BST_B
BST_C
NC
NC
OUT_C
PGND_CD
PGND_CD
48
47
46
45
44
43
42
41
40
39
38
37
PHP Package
48-Pin HTQFP
Top View
OUT_A
1
36
OUT_D
PVDD_AB
2
35
PVDD_CD
PVDD_AB
3
34
PVDD_CD
BST_A
4
33
BST_D
NC
5
32
GVDD_OUT
SSTIMER
6
NC
7
PBTL
AVSS
31
VREG
30
AGND
8
29
GND
9
28
DVSS
PLL_FLTM
10
27
DVDD
PLL_FLTP
11
26
STEST
VR_ANA
12
25
RESET
18
19
20
21
22
23
24
PDN
LRCLK
SCLK
SDIN
SDA
SCL
16
OSC_RES
VR_DIG
15
MCLK
17
14
A_SEL_FAULT
DVSSO
13
AVDD
Thermal
Pad
Pin Functions
PIN
TYPE (1)
5-V
TERMINATION (2)
TOLERANT
DESCRIPTION
NAME
NO.
AGND
30
P
A_SEL_FAULT
14
DIO
AVDD
13
P
3.3-V analog power supply
AVSS
9
P
Analog 3.3-V supply ground
BST_A
4
P
High-side bootstrap supply for half-bridge A
BST_B
43
P
High-side bootstrap supply for half-bridge B
(1)
(2)
4
Local analog ground for power stage
This pin is monitored on the rising edge of RESET. A value of 0 (15kΩ pulldown) sets the I2C device address to 0x54 and a value of 1
(15-kΩ pullup) sets it to 0x56. this dual-function pin can be
programmed to output internal power-stage errors.
TYPE: A = analog; D = 3.3-V digital; P = power/ground/decoupling; I = input; O = output
All pullups are weak pullups and all pulldowns are weak pulldowns. The pullups and pulldowns are included to assure proper input logic
levels if the pins are left unconnected (pullups → logic 1 input; pulldowns → logic 0 input).
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Pin Functions (continued)
PIN
TYPE (1)
5-V
TERMINATION (2)
TOLERANT
DESCRIPTION
NAME
NO.
BST_C
42
P
High-side bootstrap supply for half-bridge C
BST_D
33
P
High-side bootstrap supply for half-bridge D
DVDD
27
P
3.3-V digital power supply
DVSS
28
P
Digital ground
DVSSO
17
P
Oscillator ground
GND
29
P
Analog ground for power stage
GVDD_OUT
32
P
LRCLK
20
DI
5-V
Pulldown
Input serial audio data left and right clock (sample-rate clock)
MCLK
15
DI
5-V
Pulldown
Master clock input
Gate drive internal regulator output
5, 7,
40,
41,
44, 45
–
OSC_RES
16
AO
OUT_A
1
O
Output, half-bridge A
OUT_B
46
O
Output, half-bridge B
OUT_C
39
O
Output, half-bridge C
OUT_D
36
O
Output, half-bridge D
PBTL
8
DI
Low means BTL mode; high means PBTL mode. Information goes
directly to power stage.
PDN
19
DI
PGND_AB
47, 48
P
Power ground for half-bridges A and B
PGND_CD
37, 38
P
Power ground for half-bridges C and D
PLL_FLTM
10
AO
PLL negative loop-filter terminal
PLL_FLTP
11
AO
PLL positive loop-filter terminal
PVDD_AB
2, 3
P
Power-supply input for half-bridge output A
PVDD_CD
34, 35
P
Power-supply input for half-bridge output D
Reset, active-low. A system reset is generated by applying a logic
low to this pin. RESET is an asynchronous control signal that
restores the DAP to its default conditions and places the PWM in the
hard-mute (high-impedance) state.
NC
No connect
Oscillator trim resistor. Connect an 18.2-kΩ, 1% resistor to DVSSO.
5-V
Pullup
Pullup
Power down, active-low. PDN prepares the device for loss of power
supplies by shutting down the noise shaper and initiating the PWM
stop sequence.
RESET
25
DI
5-V
SCL
24
DI
5-V
SCLK
21
DI
5-V
SDA
23
DIO
5-V
SDIN
22
DI
5-V
SSTIMER
6
AI
Controls ramp time of OUT_x to minimize pop. Leave this pin
floating for BD mode. Requires capacitor of 2.2 nF to GND in AD
mode. The capacitor determines the ramp time.
STEST
26
DI
Factory test pin. Connect directly to DVSS.
VR_ANA
12
P
Internally regulated 1.8-V analog supply voltage. This pin must not
be used to power external devices.
VR_DIG
18
P
Internally regulated 1.8-V digital supply voltage. This pin must not be
used to power external devices.
VREG
31
P
Digital regulator output. Not to be used for powering external
circuitry.
I2C serial control clock input
Pulldown
Serial audio-data clock (shift clock). SCLK is the serial-audio-port
input-data bit clock.
I2C serial control data interface input/output
Pulldown
Serial audio data input. SDIN supports three discrete (stereo) data
formats.
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SLOS670B – NOVEMBER 2010 – REVISED DECEMBER 2016
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8 Specifications
8.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted) (1)
Supply
voltage
Input voltage
MIN
MAX
UNIT
DVDD, AVDD
–0.3
3.6
V
PVDD_x
–0.3
30
V
3.3-V digital input
–0.5
DVDD + 0.5
5-V tolerant (2) digital input (except MCLK)
–0.5
DVDD + 2.5 (3)
–0.5
(3)
5-V tolerant MCLK input
AVDD + 2.5
V
OUT_x to PGND_x
32 (4)
V
BST_x to PGND_x
43 (4)
V
Input clamp current, IIK
±20
mA
Output clamp current, IOK
±20
mA
Operating free-air temperature
0
85
°C
Operating junction temperature
0
150
°C
–40
125
°C
Storage temperature, Tstg
(1)
(2)
(3)
(4)
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating
Conditions is not implied. Exposure to absolute-maximum conditions for extended periods may affect device reliability.
5-V tolerant inputs are PDN, RESET, SCLK, LRCLK, MCLK, SDIN, SDA, and SCL.
Maximum pin voltage should not exceed 6 V.
DC voltage + peak ac waveform measured at the pin should be below the allowed limit for all conditions.
8.2 ESD Ratings
VALUE
V(ESD)
(1)
(2)
Electrostatic discharge
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001
(1)
UNIT
±1000
Charged-device model (CDM), per JEDEC specification JESD22-C101 (2)
V
±250
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
8.3 Recommended Operating Conditions
MIN
NOM
MAX
UNIT
3
3.3
3.6
V
26
V
Digital/analog supply voltage
DVDD, AVDD
Half-bridge supply voltage
PVDD_x
(1)
8
VIH
High-level input voltage
5-V tolerant
2
VIL
Low-level input voltage
5-V tolerant
TA
Operating ambient temperature
TJ (2)
Operating junction temperature
RL (BTL)
Load impedance
Output filter: L = 15 μH, C = 680 nF
4
8
Ω
RL (PBTL)
Load impedance
Output filter: L = 15 μH, C = 680 nF
2
4
Ω
Output-filter inductance
Minimum output inductance under shortcircuit condition
LO (BTL)
Output sample rate
(1)
(2)
6
V
0.8
V
0
85
°C
0
125
°C
10
μH
11.025/22.05/44.1-kHz data rate ±2%
288
48/24/12/8/16/32-kHz data rate ±2%
384
kHz
For operation at PVDD_x levels greater than 18 V, the modulation limit must be set to 93.8% through the control port register 0x10.
Continuous operation above the recommended junction temperature may result in reduced reliability and/or lifetime of the device.
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8.4 Thermal Information
TAS5727
THERMAL METRIC (1)
PHP (HTQFP)
UNIT
48 PINS
RθJA
Junction-to-ambient thermal resistance
27.9
°C/W
RθJC(top)
RθJB
Junction-to-case (top) thermal resistance
13
°C/W
Junction-to-board thermal resistance
1.1
°C/W
ψJT
Junction-to-top characterization parameter
20.7
°C/W
ψJB
Junction-to-board characterization parameter
0.3
°C/W
RθJC(bot)
Junction-to-case (bottom) thermal resistance
6.7
°C/W
(1)
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
8.5 DC Electrical Characteristics
TA = 25°, PVCC_x = 18 V, DVDD = AVDD = 3.3 V, RL= 8 Ω, BTL AD mode, fS = 48 kHz (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
VOH
High-level output voltage
A_SEL_FAULT and SDA
IOH = –4 mA
DVDD = 3 V
VOL
Low-level output voltage
A_SEL_FAULT and SDA
IOL = 4 mA
DVDD = 3 V
0.5
V
IIL
Low-level input current
VI < VIL ; DVDD = AVDD
= 3.6 V
75
μA
IIH
High-level input current
VI > VIH ; DVDD =
AVDD = 3.6 V
75 (1)
μA
IDD
3.3-V supply current
3.3-V supply voltage (DVDD,
AVDD)
IPVDD
Supply current
No load (PVDD_x)
Drain-to-source resistance, LS
TJ = 25°C, includes metallization resistance
75
Drain-to-source resistance, HS
TJ = 25°C, includes metallization resistance
75
rDS(on)
(2)
2.4
V
Normal mode
49
68
Reset (RESET = low,
PDN = high)
23
38
Normal mode
32
50
3
8
Reset (RESET = low,
PDN = high)
mA
mA
mΩ
I/O Protection
Vuvp
Undervoltage protection limit
PVDD falling
7.2
V
Vuvp,hyst
Undervoltage protection limit
PVDD rising
7.6
V
150
°C
30
°C
OTE
(3)
OTEHYST
Overtemperature error
(3)
Extra temperature drop
required to recover from error
IOC
Overcurrent limit protection
4.5
A
IOCT
Overcurrent response time
150
ns
RPD
Internal pulldown resistor at the Connected when drivers are in the high-impedance state
output of each half-bridge
to provide bootstrap capacitor charge.
3
kΩ
(1)
(2)
(3)
IIH for the PBTL pin has a maximum limit of 200 µA due to an internal pulldown on the pin.
This does not include bond-wire or pin resistance.
Specified by design
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8.6 AC Electrical Characteristics (BTL, PBTL)
PVDD_x = 18 V, BTL AD mode, fS = 48 KHz, RL = 8 Ω, ROCP = 22 kΩ, CBST = 33 nF, audio frequency = 1 kHz, AES17 filter,
fPWM = 384 kHz, TA = 25°C (unless otherwise specified). All performance is in accordance with recommended operating
conditions (unless otherwise specified).
PARAMETER
TEST CONDITIONS
MIN
TYP
PVDD = 18 V,10% THD, 1-kHz input signal
21.5
PVDD = 18 V, 7% THD, 1-kHz input signal
20.3
PVDD = 12 V, 10% THD, 1-kHz input signal
9.6
PVDD = 12 V, 7% THD, 1-kHz input signal
9.1
PVDD = 8 V, 10% THD, 1-kHz input signal
4.2
PVDD = 8 V, 7% THD, 1-kHz input signal
PO
Power output per channel
THD+N
Total harmonic distortion + noise
Vn
Output integrated noise (rms)
SNR
(1)
Signal-to-noise ratio
(1)
UNIT
4
PBTL mode, PVDD = 12 V, RL = 4 Ω,
10% THD, 1-kHz input signal
18.7
PBTL mode, PVDD = 12 V, RL = 4 Ω,
7% THD, 1-kHz input signal
17.7
PBTL mode, PVDD = 18 V, RL = 4 Ω,
10% THD, 1-kHz input signal
41.5
PBTL mode, PVDD = 18 V, RL = 4 Ω,
7% THD, 1-kHz input signal
39
PVDD = 18 V, PO = 1 W
0.07%
PVDD = 12 V, PO = 1 W
0.03%
PVDD = 8 V, PO = 1 W
0.1%
A-weighted
Crosstalk
MAX
W
56
μV
PO = 0.25 W, f = 1 kHz (BD Mode)
–82
dB
PO = 0.25 W, f = 1 kHz (AD Mode)
–69
dB
A-weighted, f = 1 kHz, maximum power at
THD < 1%
106
dB
SNR is calculated relative to 0-dBFS input level.
8.7 PLL Input Parameters and External Filter Components
PARAMETER
fMCLKI
tr /
tf(MCLK)
TEST CONDITIONS
MIN
MCLK frequency
2.8224
MCLK duty cycle
40%
TYP
50%
Rise/fall time for MCLK
LRCLK allowable drift before LRCLK reset
MAX
UNIT
24.576
MHz
60%
5
ns
4
MCLKs
External PLL filter capacitor C1
SMD 0603 X7R
47
nF
External PLL filter capacitor C2
SMD 0603 X7R
4.7
nF
External PLL filter resistor R
SMD 0603, metal film
470
Ω
8.8 Serial Audio Ports Slave Mode
over recommended operating conditions (unless otherwise noted)
PARAMETER
TEST CONDITIONS
CL = 30 pF
MIN
NOM
MAX
UNIT
MHz
Frequency, SCLK 32 × fS, 48 × fS, 64 × fS
tsu1
Setup time, LRCLK to SCLK rising edge
10
ns
th1
Hold time, LRCLK from SCLK rising edge
10
ns
tsu2
Setup time, SDIN to SCLK rising edge
10
ns
th2
Hold time, SDIN from SCLK rising edge
10
LRCLK frequency
8
1.024
12.288
fSCLKIN
ns
8
48
48
SCLK duty cycle
40%
50%
60%
LRCLK duty cycle
40%
50%
60%
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Serial Audio Ports Slave Mode (continued)
over recommended operating conditions (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
SCLK rising edges between LRCLK rising edges
t(edge)
LRCLK clock edge with respect to the falling
edge of SCLK
tr/tf
Rise/fall time for SCLK/LRCLK
NOM
MAX
UNIT
32
64
SCLK
edges
–1/4
1/4
SCLK
period
8
ns
8.9 I2C Serial Control Port Operation
Timing characteristics for I2C Interface signals over recommended operating conditions (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
fSCL
Frequency, SCL
tw(H)
Pulse duration, SCL high
No wait states
0.6
tw(L)
Pulse duration, SCL low
1.3
tr
Rise time, SCL and SDA
tf
Fall time, SCL and SDA
tsu1
Setup time, SDA to SCL
th1
Hold time, SCL to SDA
t(buf)
tsu2
MAX
UNIT
400
kHz
μs
μs
300
ns
300
ns
100
ns
0
ns
Bus free time between stop and start conditions
1.3
μs
Setup time, SCL to start condition
0.6
μs
th2
Hold time, start condition to SCL
0.6
μs
tsu3
Setup time, SCL to stop condition
0.6
CL
Load capacitance for each bus line
μs
400
pF
8.10 Reset Timing (RESET)
Control signal parameters over recommended operating conditions (unless otherwise noted). Please refer to Recommended
Use Model section on usage of all terminals.
PARAMETER
tw(RESET)
Pulse duration, RESET active
td(I2C_ready)
Time to enable I2C
MIN
NOM
MAX
100
μs
12
tr
UNIT
ms
tf
SCLK
(Input)
t(edge)
th1
tsu1
LRCLK
(Input)
th2
tsu2
SDIN
T0026-04
Figure 1. Slave-Mode Serial Data-Interface Timing
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tw(H)
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tw(L)
tf
tr
SCL
tsu1
th1
SDA
T0027-01
Figure 2. SCL and SDA Timing
SCL
t(buf)
th2
tsu3
tsu2
SDA
Start
Condition
Stop
Condition
T0028-01
Figure 3. Start and Stop Conditions Timing
RESET
tw(RESET)
2
2
I C Active
I C Active
td(I2C_ready)
System Initialization.
2
Enable via I C.
T0421-01
NOTES: On power up, TI recommends that the TAS5727 RESET be held LOW for at least 100 μs after DVDD has reached 3
V.
If RESET is asserted LOW while PDN is LOW, then RESET must continue to be held LOW for at least 100 μs after
PDN is deasserted (HIGH).
Figure 4. Reset Timing
10
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8.11 Typical Characteristics
BTL Configuration, 8 Ω
10
10
PVDD = 12V
RL = 8Ω
TA = 25°C
PVDD = 18V
RL = 8Ω
TA = 25°C
1
THD+N (%)
THD+N (%)
1
0.1
0.01
0.1
0.01
PO = 1W
PO = 2.5W
PO = 5W
0.001
20
100
PO = 1W
PO = 5W
PO = 10W
1k
Frequency (Hz)
10k
0.001
20k
Figure 5. Total Harmonic Distortion + Noise vs Frequency
100
1k
Frequency (Hz)
PVDD = 12V
RL = 8Ω
TA = 25°C
1
THD+N (%)
1
0.1
0.01
0.1
0.01
PO = 1W
PO = 5W
PO = 10W
20
100
f = 20Hz
f = 1kHz
f = 10kHz
1k
Frequency (Hz)
10k
0.001
0.01
20k
Figure 7. Total Harmonic Distortion + Noise vs Frequency
0.1
1
Output Power (W)
10
40
Figure 8. Total Harmonic Distortion + Noise vs Output
Power
10
10
PVDD = 18V
RL = 8Ω
TA = 25°C
PVDD = 24V
RL = 8Ω
TA = 25°C
1
THD+N (%)
1
THD+N (%)
20k
10
PVDD = 24V
RL = 8Ω
TA = 25°C
0.001
10k
Figure 6. Total Harmonic Distortion + Noise vs Frequency
10
THD+N (%)
20
0.1
0.01
0.1
0.01
f = 20Hz
f = 1kHz
f = 10kHz
0.001
0.01
0.1
1
Output Power (W)
10
40
Figure 9. Total Harmonic Distortion + Noise vs Output
Power
f = 20Hz
f = 1kHz
f = 10kHz
0.001
0.01
0.1
1
Output Power (W)
10
40
Figure 10. Total Harmonic Distortion + Noise vs Output
Power
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Typical Characteristics (continued)
BTL Configuration, 8 Ω
0
0
VO = 1W
PVDD = 12V
RL = 8Ω
TA = 25°C
−10
−20
Right to Left
Left to Right
−20
−40
−50
−60
−40
−50
−60
−70
−70
−80
−80
−90
−90
−100
−100
20
100
1k
Frequency (Hz)
10k
20k
20
Figure 11. Crosstalk vs Frequency
100
1k
Frequency (Hz)
10k
20k
Figure 12. Crosstalk vs Frequency
100
0
VO = 1W
PVDD = 24V
RL = 8Ω
TA = 25°C
−10
−20
Right to Left
Left to Right
90
80
70
Efficiency (%)
−30
Crosstalk (dB)
Right to Left
Left to Right
−30
Crosstalk (dB)
−30
Crosstalk (dB)
VO = 1W
PVDD = 18V
RL = 8Ω
TA = 25°C
−10
−40
−50
−60
60
50
40
30
−70
PVDD = 12V
PVDD = 18V
PVDD = 24V
20
−80
10
RL = 8Ω
TA = 25°C
−90
0
−100
20
100
1k
Frequency (Hz)
10k
20k
Figure 13. Crosstalk vs Frequency
0
5
10
15
20
25
30
Total Output Power (W)
35
40
Dashed lines represent thermally limited region.
Figure 14. Efficiency vs Total Output Power
9 Parameter Measurement Information
All parameters are measured according to the conditions described in the Specifications.
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10 Detailed Description
10.1 Overview
The TAS5727 is an efficient stereo I2S input Class-D audio power amplifier with a digital audio processor. The
digital audio processor of the device uses noise shaping and customized correction algorithms to achieve a great
power efficiency and high audio performance. Also, the device has up to eighteen equalizers and two-band
advanced Automatic Gain Limiting (AGL).
The device needs only a single DVDD supply in addition to the higher-voltage PVDD power supply. An internal
voltage regulator provides suitable voltage levels for the gate drive circuit. The wide PVDD power supply range of
the device enables its use in a multitude of applications.
The TAS5727 is a slave-only device that is controlled by a bidirectional I2C interface that supports both 100-kHz
and 400-kHz data transfer rates for single- and multiple-byte write and read operations. This control interface is
used to program the registers of the device and read the device status. The PWM of this device operates with a
carrier frequency between 384 kHz and 354 kHz, depending the sampling rate. This device allows the use of the
same clock signal for both MCLK and BCLK (64xFs) when using a sampling frequency of 44.1 kHz or 48 kHz.
This amplifier can be configured in two different modes, stereo and mono single filter configuration is supported
in mono mode.
10.2 Functional Block Diagrams
OUT_A
th
SDIN
Serial
Audio
Port
S
R
C
Digital Audio Processor
(DAP)
4
Order
Noise
Shaper
and
PWM
2´ HB
FET Out
OUT_B
OUT_C
2´ HB
FET Out
OUT_D
Protection
Logic
MCLK
SCLK
LRCLK
SDA
SCL
Click and Pop
Control
Sample Rate
Autodetect
and PLL
Serial
Control
Microcontroller
Based
System
Control
Terminal Control
B0262-06
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Figure 15. Functional View
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Functional Block Diagrams (continued)
FAULT
Undervoltage
Protection
FAULT
4
4
Power
On
Reset
Protection
and
I/O Logic
AGND
Temp.
Sense
GND
VALID
Overcurrent
Protection
Isense
BST_D
PVDD_D
PWM
Rcv
Ctrl
Timing
PWM Controller
PWM_D
Gate
Drive
OUT_D
Pulldown Resistor
PGND_CD
GVDD
Regulator
GVDD_OUT
BST_C
PVDD_C
PWM_C
PWM
Rcv
Ctrl
Timing
Gate
Drive
OUT_C
Pulldown Resistor
PGND_CD
BST_B
PVDD_B
PWM_B
PWM
Rcv
Ctrl
Timing
Gate
Drive
OUT_B
Pulldown Resistor
GVDD
Regulator
PGND_AB
BST_A
PVDD_A
PWM_A
PWM
Rcv
Ctrl
Timing
Gate
Drive
OUT_A
Pulldown Resistor
PGND_AB
B0034-06
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Figure 16. Power-Stage Functional Block Diagram
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Functional Block Diagrams (continued)
2
I C Subaddress in Red
2
58, 59
27–2F
26
L
9BQ
0x70
32
24
clip24
2BQ
Vol1
1BQ
0x73
0x71
0x46[0]
AGL
5C, 5D
31–39
30
0x51[0]
0x52[1]
0x76
R
I C:56
VDISTA
0x51[1]
0x72
9BQ
Vol2
0x74 v2im1
32
24
clip24
2BQ
1BQ
2
Level
Meter
I C:57
VDISTB
0x77
0x75
0x52[0]
5E, 5F
32
32
2BQ
2
Vol
I C:0x6B (32Bit-Left Level)
2
I C:0x6C (32 Bit-Right Level)
0x46[1]
AGL
5A, 5B
Vol
2BQ
Vol Config Reg 0x0E
B0321-11
Copyright © 2016 Texas Instruments Incorporated
Figure 17. DAP Process Structure
10.3 Feature Description
10.3.1 Power Supply
To facilitate system design, the TAS5727 needs only a 3.3-V supply in addition to the (typical) 18-V power-stage
supply. An internal voltage regulator provides suitable voltage levels for the gate drive circuitry. Additionally, all
circuitry requiring a floating voltage supply, for example, the high-side gate drive, is accommodated by built-in
bootstrap circuitry requiring only a few external capacitors.
To provide good electrical and acoustical characteristics, the PWM signal path for the output stage is designed
as identical, independent half-bridges. For this reason, each half-bridge has separate bootstrap pins (BST_x),
and power-stage supply pins (PVDD_x). The gate-drive voltage (GVDD_OUT) is derived from the PVDD voltage.
Place all decoupling capacitors as close to their associated pins as possible. Inductance between the powersupply pins and decoupling capacitors must be avoided.
For a properly functioning bootstrap circuit, a small ceramic capacitor must be connected from each bootstrap pin
(BST_x) to the power-stage output pin (OUT_x). When the power-stage output is low, the bootstrap capacitor is
charged through an internal diode connected between the gate-drive regulator output pin (GVDD_OUT) and the
bootstrap pin. When the power-stage output is high, the bootstrap capacitor potential is shifted above the output
potential and thus provides a suitable voltage supply for the high-side gate driver. In an application with PWM
switching frequencies in the range from 288 kHz to 384 kHz, TI recommends using 33-nF, X7R ceramic
capacitors, size 0603 or 0805, for the bootstrap supply. These 33-nF capacitors ensure sufficient energy storage,
even during minimal PWM duty cycles, to keep the high-side power-stage FET (LDMOS) fully turned on during
the remaining part of the PWM cycle.
Pay special attention to the power-stage power supply; this includes component selection, PCB placement, and
routing. As indicated, each half-bridge has independent power-stage supply pins (PVDD_x). For optimal electrical
performance, EMI compliance, and system reliability, it is important that each PVDD_x pin is decoupled with a
100-nF, X7R ceramic capacitor placed as close as possible to each supply pin.
The TAS5727 is fully protected against erroneous power-stage turnon due to parasitic gate charging.
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Feature Description (continued)
10.3.2 I2C Address Selection and Fault Output
10.3.2.1 I2C Chip Select
A_SEL_FAULT is an input pin during power up. It can be pulled high (15-kΩ pullup) or low (15-kΩ pulldown).
High indicates an I2C subaddress of 0x56, and low a subaddress of 0x54.
10.3.2.2 I2C Device Address Change Procedure
• Write to device address change enable register, 0xF8 with a value of 0xF9A5 A5A5.
• Write to device register 0xF9 with a value of 0x0000 00XX, where XX is the new address.
• Any writes after that should use the new device address XX.
10.3.2.3 Fault Indication
A_SEL_FAULT is an input pin during power up. This pin can be programmed after RESET to be an output by
writing 1 to bit 0 of I2C register 0x05. In that mode, the A_SEL_FAULT pin has the definition shown in Table 1.
Any fault resulting in device shutdown is signaled by the A_SEL_FAULT pin going low (see Table 1). A latched
version of this pin is available on D1 of register 0x02. This bit can be reset only by an I2C write.
Table 1. A_SEL_FAULT Output States
A_SEL_FAULT
DESCRIPTION
0
Overcurrent (OC) or undervoltage (UVP) error or overtemperature error (OTE) or overvoltage
error
1
No faults (normal operation)
10.3.3 Device Protection Systems
10.3.3.1 Overcurrent (OC) Protection With Current Limiting
The device has independent, fast-reacting current detectors on all high-side and low-side power-stage FETs. The
detector outputs are closely monitored by two protection systems. The first protection system controls the power
stage to prevent the output current further increasing, that is, the protection system performs a cycle-by-cycle
current-limiting function, rather than prematurely shutting down during combinations of high-level music transients
and extreme speaker load-impedance drops. If the high-current condition situation persists, that is, the power
stage is being overloaded, a second protection system triggers a latching shutdown, resulting in the power stage
being set in the high-impedance (Hi-Z) state. The device returns to normal operation once the fault condition (that
is, a short circuit on the output) is removed. Current-limiting and overcurrent protection are not independent for
half-bridges. That is, if the bridge-tied load between half-bridges A and B causes an overcurrent fault, halfbridges A, B, C, and D are shut down.
10.3.3.2 Overtemperature Protection
The TAS5727 has an overtemperature-protection system. If the device junction temperature exceeds 150°C
(nominal), the device is put into thermal shutdown, resulting in all half-bridge outputs being set in the highimpedance (Hi-Z) state and A_SEL_FAULT being asserted low. The TAS5727 recovers automatically once the
temperature drops approximately 30°C.
10.3.3.3 Undervoltage Protection (UVP) and Power-On Reset (POR)
The UVP and POR circuits of the TAS5727 fully protect the device in any power-up, power-down, and brownout
situation. While powering up, the POR circuit resets the overload circuit (OLP) and ensures that all circuits are
fully operational when the PVDD and AVDD supply voltages reach 7.6 V and 2.7 V, respectively. Although PVDD
and AVDD are independently monitored, a supply-voltage drop below the UVP threshold on AVDD or either
PVDD pin results in all half-bridge outputs immediately being set in the high-impedance (Hi-Z) state and
A_SEL_FAULT being asserted low.
16
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Feature Description (continued)
10.3.4 Clock, Auto Detection, and PLL
The TAS5727 is an I2S slave device. It accepts MCLK, SCLK, and LRCLK. The digital audio processor (DAP)
supports all the sample rates and MCLK rates that are defined in the Clock Control Register (0x00).
The TAS5727 checks to verify that SCLK is a specific value of 32 fS, 48 fS, or 64 fS. The DAP only supports a
1 × fS LRCLK. The timing relationship of these clocks to SDIN is shown in subsequent sections. The clock
section uses MCLK or the internal oscillator clock (when MCLK is unstable, out of range, or absent) to produce
the internal clock (DCLK) running at 512 times the PWM switching frequency.
The DAP can autodetect and set the internal clock control logic to the appropriate settings for all supported clock
rates as defined in the clock-control register.
The TAS5727 has robust clock error handling that uses the built-in trimmed oscillator clock to quickly detect
changes and errors. Once the system detects a clock change or error, it mutes the audio (through a single-step
mute) and then forces PLL to limp using the internal oscillator as a reference clock. Once the clocks are stable,
the system autodetects the new rate and reverts to normal operation. During this process, the default volume is
restored in a single step (also called hard unmute). The ramp process can be programmed to ramp back slowly
(also called soft unmute) as defined in volume register (0x0E).
10.3.5 PWM Section
The TAS5727 DAP device uses noise-shaping and customized nonlinear correction algorithms to achieve high
power efficiency and high-performance digital audio reproduction. The DAP uses a fourth-order noise shaper to
increase dynamic range and SNR in the audio band. The PWM section accepts 24-bit PCM data from the DAP
and outputs two BTL PWM audio output channels.
The PWM section has individual-channel DC-blocking filters that can be enabled and disabled. The filter cutoff
frequency is less than 1 Hz. Individual-channel de-emphasis filters for 44.1 kHz and 48 kHz are included and can
be enabled and disabled.
Finally, the PWM section has an adjustable maximum modulation limit of 93.8% to 99.2%.
For a detailed description of using audio processing features like DRC and EQ, see the User's Guide (SLOU299)
and the TAS57xx GDE.
10.3.6 SSTIMER Functionality
The SSTIMER pin uses a capacitor connected between this pin and ground to control the output duty cycle when
exiting all-channel shutdown. The capacitor on the SSTIMER pin is slowly charged through an internal current
source, and the charge time determines the rate at which the output transitions from a near-zero duty cycle to the
desired duty cycle. This allows for a smooth transition that minimizes audible pops and clicks. When the part is
shut down, the drivers are placed in the high-impedance state and transition slowly down through a 3-kΩ resistor,
similarly minimizing pops and clicks. The shutdown transition time is independent of the SSTIMER pin
capacitance. Larger capacitors increase the start-up time, while capacitors smaller than 2.2 nF decrease the
start-up time. The SSTIMER pin should be left floating for BD modulation.
10.3.7 Single-Filter PBTL Mode
The TAS5727 supports parallel BTL (PBTL) mode with OUT_A/OUT_B (and OUT_C/OUT_D) connected before
the LC filter. To put the part in PBTL configuration, drive PBTL (pin 8) HIGH. This synchronizes the turnoff of
half-bridges A and B (and similarly C/D) if an overcurrent condition is detected in either half-bridge. There is a
pulldown resistor on the PBTL pin that configures the part in BTL mode if the pin is left floating.
PWM output multiplexers should be updated to set the device in PBTL mode. Output Mux Register (0x25) should
be written with a value of 0x0110 3245. Also, the PWM shutdown register (0x19) should be written with a value
of 0x3A.
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Feature Description (continued)
10.3.8 I2C Serial Control Interface
The TAS5727 DAP has a bidirectional I2C interface that is compatible with the Inter IC (I2C) bus protocol and
supports both 100-kHz and 400-kHz data transfer rates for single- and multiple-byte write and read operations.
This is a slave-only device that does not support a multimaster bus environment or wait-state insertion. The
control interface is used to program the registers of the device and to read device status.
The DAP supports the standard-mode I2C bus operation (100 kHz maximum) and the fast I2C bus operation
(400 kHz maximum). The DAP performs all I2C operations without I2C wait cycles.
10.3.8.1 General I2C Operation
The I2C bus employs two signals, SDA (data) and SCL (clock), to communicate between integrated circuits in a
system. Data is transferred on the bus serially, one bit at a time. The address and data can be transferred in byte
(8-bit) format, with the most-significant bit (MSB) transferred first. In addition, each byte transferred on the bus is
acknowledged by the receiving device with an acknowledge bit. Each transfer operation begins with the master
device driving a start condition on the bus and ends with the master device driving a stop condition on the bus.
The bus uses transitions on the data pin (SDA) while the clock is high to indicate start and stop conditions. A
high-to-low transition on SDA indicates a start and a low-to-high transition indicates a stop. Normal data-bit
transitions must occur within the low time of the clock period. These conditions are shown in Figure 18. The
master generates the 7-bit slave address and the read/write (R/W) bit to open communication with another
device and then waits for an acknowledge condition. The TAS5727 holds SDA low during the acknowledge clock
period to indicate an acknowledgment. When this occurs, the master transmits the next byte of the sequence.
Each device is addressed by a unique 7-bit slave address plus R/W bit (1 byte). All compatible devices share the
same signals through a bidirectional bus using a wired-AND connection. An external pullup resistor must be used
for the SDA and SCL signals to set the high level for the bus.
SDA
R/
A
W
7-Bit Slave Address
7
6
5
4
3
2
1
0
8-Bit Register Address (N)
7
6
5
4
3
2
1
0
8-Bit Register Data For
Address (N)
A
7
6
5
4
3
2
1
8-Bit Register Data For
Address (N)
A
0
7
6
5
4
3
2
1
A
0
SCL
Start
Stop
T0035-01
2
Figure 18. Typical I C Sequence
There is no limit on the number of bytes that can be transmitted between start and stop conditions. When the last
word transfers, the master generates a stop condition to release the bus. A generic data transfer sequence is
shown in Figure 18.
The 7-bit address for TAS5715 is 0101 010 (0x54) or 0101 011 (0x56) defined by A_SEL (external pulldown for
0x54 and pullup for 0x56).
10.3.8.2 Single- and Multiple-Byte Transfers
The serial control interface supports both single-byte and multiple-byte read/write operations for subaddresses
0x00 to 0x1F. However, for the subaddresses 0x20 to 0xFF, the serial control interface supports only multiplebyte read/write operations (in multiples of 4 bytes).
During multiple-byte read operations, the DAP responds with data, a byte at a time, starting at the subaddress
assigned, as long as the master device continues to respond with acknowledges. If a particular subaddress does
not contain 32 bits, the unused bits are read as logic 0.
18
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Feature Description (continued)
During multiple-byte write operations, the DAP compares the number of bytes transmitted to the number of bytes
that are required for each specific subaddress. For example, if a write command is received for a biquad
subaddress, the DAP must receive five 32-bit words. If fewer than five 32-bit data words have been received
when a stop command (or another start command) is received, the received data is discarded.
Supplying a subaddress for each subaddress transaction is referred to as random I2C addressing. The TAS5727
also supports sequential I2C addressing. For write transactions, if a subaddress is issued followed by data for
that subaddress and the 15 subaddresses that follow, a sequential I2C write transaction has taken place, and the
data for all 16 subaddresses is successfully received by the TAS5727. For I2C sequential-write transactions, the
subaddress then serves as the start address, and the amount of data subsequently transmitted, before a stop or
start is transmitted, determines how many subaddresses are written. As was true for random addressing,
sequential addressing requires that a complete set of data be transmitted. If only a partial set of data is written to
the last subaddress, the data for the last subaddress is discarded. However, all other data written is accepted;
only the incomplete data is discarded.
10.3.8.3 Single-Byte Write
As shown in Figure 19, a single-byte data-write transfer begins with the master device transmitting a start
condition followed by the I2C device address and the read/write bit. The read/write bit determines the direction of
the data transfer. For a data-write transfer, the read/write bit is a 0. After receiving the correct I2C device address
and the read/write bit, the DAP responds with an acknowledge bit. Next, the master transmits the address byte or
bytes corresponding to the TAS5727 internal memory address being accessed. After receiving the address byte,
the TAS5727 again responds with an acknowledge bit. Next, the master device transmits the data byte to be
written to the memory address being accessed. After receiving the data byte, the TAS5727 again responds with
an acknowledge bit. Finally, the master device transmits a stop condition to complete the single-byte data-write
transfer.
Start
Condition
Acknowledge
A6
A5
A4
A3
A2
A1
A0
Acknowledge
R/W ACK A7
A6
A5
2
A4
A3
A2
A1
Acknowledge
A0 ACK D7
D6
Subaddress
I C Device Address and
Read/Write Bit
D5
D4
D3
D2
D1
D0 ACK
Stop
Condition
Data Byte
T0036-01
Figure 19. Single-Byte Write Transfer
10.3.8.4 Multiple-Byte Write
A multiple-byte data-write transfer is identical to a single-byte data-write transfer except that multiple data bytes
are transmitted by the master device to the DAP as shown in Figure 20. After receiving each data byte, the
TAS5727 responds with an acknowledge bit.
Start
Condition
Acknowledge
A6
A5
A1
A0 R/W ACK A7
A6
A5
2
A4
A3
Subaddress
I C Device Address and
Read/Write Bit
A1
Acknowledge
Acknowledge
Acknowledge
Acknowledge
A0 ACK D7
D0 ACK D7
D0 ACK D7
D0 ACK
First Data Byte
Other Data Bytes
Last Data Byte
Stop
Condition
T0036-02
Figure 20. Multiple-Byte Write Transfer
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Feature Description (continued)
10.3.8.5 Single-Byte Read
As shown in Figure 21, a single-byte data-read transfer begins with the master device transmitting a start
condition, followed by the I2C device address and the read/write bit. For the data read transfer, both a write
followed by a read are actually done. Initially, a write is done to transfer the address byte or bytes of the internal
memory address to be read. As a result, the read/write bit becomes a 0. After receiving the TAS5727 address
and the read/write bit, TAS5727 responds with an acknowledge bit. In addition, after sending the internal memory
address byte or bytes, the master device transmits another start condition followed by the TAS5727 address and
the read/write bit again. This time, the read/write bit becomes a 1, indicating a read transfer. After receiving the
address and the read/write bit, the TAS5727 again responds with an acknowledge bit. Next, the TAS5727
transmits the data byte from the memory address being read. After receiving the data byte, the master device
transmits a not-acknowledge followed by a stop condition to complete the single-byte data-read transfer.
Repeat Start
Condition
Start
Condition
Acknowledge
A6
A5
A1
A0 R/W ACK A7
Acknowledge
A6
2
A5
A4
A0 ACK
A6
A5
A1
A0 R/W ACK D7
D6
2
I C Device Address and
Read/Write Bit
Subaddress
I C Device Address and
Read/Write Bit
Not
Acknowledge
Acknowledge
D1
D0 ACK
Stop
Condition
Data Byte
T0036-03
Figure 21. Single-Byte Read Transfer
10.3.8.6 Multiple-Byte Read
A multiple-byte data-read transfer is identical to a single-byte data-read transfer except that multiple data bytes
are transmitted by the TAS5727 to the master device as shown in Figure 22. Except for the last data byte, the
master device responds with an acknowledge bit after receiving each data byte.
Repeat Start
Condition
Start
Condition
Acknowledge
A6
A0 R/W ACK A7
2
I C Device Address and
Read/Write Bit
Acknowledge
A6
A6
A0 ACK
A5
2
Acknowledge
Acknowledge
Acknowledge
Not
Acknowledge
A0 R/W ACK D7
D0 ACK D7
D0 ACK D7
D0 ACK
I C Device Address and
Read/Write Bit
Subaddress
First Data Byte
Other Data Bytes
Last Data Byte
Stop
Condition
T0036-04
Figure 22. Multiple-Byte Read Transfer
10.3.9 Audio Serial Interface
Serial data is input on SDIN. The PWM outputs are derived from SDIN. The TAS5727 DAP accepts serial data in
16-, 20-, or 24-bit left-justified, right-justified, and I2S serial data formats.
10.3.10 Serial Interface Control and Timing
10.3.10.1 I2S Timing
I2S timing uses LRCLK to define when the data being transmitted is for the left channel and when it is for the
right channel. LRCLK is low for the left channel and high for the right channel. A bit clock running at 32, 48, or
64 × fS is used to clock in the data. There is a delay of one bit clock from the time the LRCLK signal changes
state to the first bit of data on the data lines. The data is written MSB-first and is valid on the rising edge of bit
clock. The DAP masks unused trailing data bit positions.
20
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Feature Description (continued)
2
2-Channel I S (Philips Format) Stereo Input
32 Clks
LRCLK (Note Reversed Phase)
32 Clks
Right Channel
Left Channel
SCLK
SCLK
MSB
24-Bit Mode
23 22
LSB
9
8
5
4
5
4
1
0
1
0
1
0
MSB
LSB
23 22
9
8
5
4
19 18
5
4
1
0
15 14
1
0
1
0
20-Bit Mode
19 18
16-Bit Mode
15 14
T0034-01
NOTE: All data presented in 2s-complement form with MSB first.
Figure 23. I2S 64-fS Format
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Feature Description (continued)
2
2-Channel I S (Philips Format) Stereo Input/Output (24-Bit Transfer Word Size)
LRCLK
24 Clks
24 Clks
Left Channel
Right Channel
SCLK
SCLK
MSB
24-Bit Mode
23 22
MSB
LSB
17 16
9
8
5
4
13 12
5
4
1
0
9
1
0
3
2
1
0
LSB
23 22
17 16
9
8
5
4
19 18
13 12
5
4
1
0
15 14
9
1
0
3
2
1
20-Bit Mode
19 18
16-Bit Mode
15 14
8
8
T0092-01
NOTE: All data presented in 2s-complement form with MSB first.
Figure 24. I2S 48-fS Format
2
2-Channel I S (Philips Format) Stereo Input
LRCLK
16 Clks
16 Clks
Left Channel
Right Channel
SCLK
SCLK
MSB
16-Bit Mode
15 14 13 12
MSB
LSB
11 10
9
8
5
4
3
2
1
0
LSB
15 14 13 12
11 10
9
8
5
4
3
2
1
T0266-01
NOTE: All data presented in 2s-complement form with MSB first.
Figure 25. I2S 32-fS Format
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Feature Description (continued)
10.3.10.2 Left-Justified
Left-justified (LJ) timing uses LRCLK to define when the data being transmitted is for the left channel and when it
is for the right channel. LRCLK is high for the left channel and low for the right channel. A bit clock running at 32,
48, or 64 × fS is used to clock in the data. The first bit of data appears on the data lines at the same time LRCLK
toggles. The data is written MSB-first and is valid on the rising edge of the bit clock. The DAP masks unused
trailing data bit positions.
2-Channel Left-Justified Stereo Input
32 Clks
32 Clks
Left Channel
Right Channel
LRCLK
SCLK
SCLK
MSB
24-Bit Mode
23 22
LSB
9
8
5
4
5
4
1
0
1
0
1
0
MSB
LSB
23 22
9
8
5
4
19 18
5
4
1
0
15 14
1
0
1
0
20-Bit Mode
19 18
16-Bit Mode
15 14
T0034-02
NOTE: All data presented in 2s-complement form with MSB first.
Figure 26. Left-Justified 64-fS Format
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Feature Description (continued)
2-Channel Left-Justified Stereo Input (24-Bit Transfer Word Size)
24 Clks
24 Clks
Left Channel
Right Channel
LRCLK
SCLK
SCLK
MSB
24-Bit Mode
23 22
21
LSB
17 16
9
8
5
4
13 12
5
4
1
0
9
1
0
1
0
MSB
LSB
21
17 16
9
8
5
4
19 18 17
13 12
5
4
1
0
15 14 13
9
1
0
23 22
1
0
20-Bit Mode
19 18 17
16-Bit Mode
15 14 13
8
8
T0092-02
NOTE: All data presented in 2s-complement form with MSB first.
Figure 27. Left-Justified 48-fS Format
2-Channel Left-Justified Stereo Input
16 Clks
16 Clks
Left Channel
Right Channel
LRCLK
SCLK
SCLK
MSB
16-Bit Mode
15 14 13 12
LSB
11 10
9
8
5
4
3
2
1
0
MSB
15 14 13 12
LSB
11 10
9
8
5
4
3
2
1
0
T0266-02
NOTE: All data presented in 2s-complement form with MSB first.
Figure 28. Left-Justified 32-fS Format
24
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Feature Description (continued)
10.3.10.3 Right-Justified
Right-justified (RJ) timing uses LRCLK to define when the data being transmitted is for the left channel and when
it is for the right channel. LRCLK is high for the left channel and low for the right channel. A bit clock running at
32, 48, or 64 × fS is used to clock in the data. The first bit of data appears on the data 8 bit-clock periods (for 24bit data) after LRCLK toggles. In RJ mode, the LSB of data is always clocked by the last bit clock before LRCLK
transitions. The data is written MSB-first and is valid on the rising edge of bit clock. The DAP masks unused
leading data bit positions.
2-Channel Right-Justified (Sony Format) Stereo Input
32 Clks
32 Clks
Left Channel
Right Channel
LRCLK
SCLK
SCLK
MSB
24-Bit Mode
LSB
23 22
19 18
15 14
1
0
19 18
15 14
1
0
15 14
1
0
MSB
LSB
23 22
19 18
15 14
1
0
19 18
15 14
1
0
15 14
1
0
20-Bit Mode
16-Bit Mode
T0034-03
Figure 29. Right-Justified 64-fS Format
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Feature Description (continued)
2-Channel Right-Justified Stereo Input (24-Bit Transfer Word Size)
24 Clks
24 Clks
Left Channel
Right Channel
LRCLK
SCLK
SCLK
MSB
24-Bit Mode
23 22
LSB
19 18
15 14
6
5
2
1
0
19 18
15 14
6
5
2
1
0
15 14
6
5
2
1
0
LSB
MSB
23 22
19 18
15 14
6
5
2
1
0
19 18
15 14
6
5
2
1
0
15 14
6
5
2
1
0
20-Bit Mode
16-Bit Mode
T0092-03
Figure 30. Right-Justified 48-fS Format
Figure 31. Right-Justified 32-fS Format
10.3.11 Dynamic Range Control (DRC)
The DRC scheme has two DRC blocks. There is one ganged DRC for the high-band left and right channels and
one DRC for the low-band left and right channels.
The DRC input/output diagram is shown in Figure 32.
26
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Output Level (dB)
Feature Description (continued)
1:1 Transfer Function
Implemented Transfer Function
T
Input Level (dB)
M0091-04
Professional-quality dynamic range compression automatically adjusts volume to flatten volume level.
• Each DRC has adjustable threshold levels.
• Programmable attack and decay time constants
• Transparent compression: compressors can attack fast enough to avoid apparent clipping before engaging,
and decay times can be set slow enough to avoid pumping.
Figure 32. Dynamic Range Control
a, w
T
aa, wa / ad, wd
DRC1
0x3C
0x3B
0x40
DRC2
0x3F
0x3E
0x43
Alpha Filter Structure
S
a
w
–1
Z
B0265-04
T = 9.23 format, all other DRC coefficients are 3.23 format
Figure 33. DRC Structure
10.3.12 PWM Level Meter
The structure in Figure 34 shows the PWM level meter that can be used to study the power profile.
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Feature Description (continued)
Post-DAP Processing
1–a
–1
Z
Ch1
ABS
a
rms
32-Bit Level
ADDR = 0x6B
2
I C Registers
(PWM Level Meter)
1–a
–1
Z
Ch2
ABS
a
rms
32-Bit Level
ADDR = 0x6C
B0396-01
Figure 34. PWM Level Meter Structure
10.4 Device Functional Modes
10.4.1 Stereo BTL Mode
The classic stereo mode of operation uses the TAS5727 device to amplify two independent signals, which
represent the left and right portions of a stereo signal. These amplified left and right audio signals are presented
on differential output pairs shown as OUT_A and OUT_B for a channel and OUT_C and OUT_D for the other
one. The routing of the audio data which is presented on the OUT_x outputs can be changed according to the
PWM Output Mux Register (0x25). By default, the TAS5727 device is configured to output channel 1 to the
OUT_A and OUT_B outputs, and channel 2 to the OUT_C and OUT_D outputs. Stereo Mode operation outputs
are shown in Figure 35.
Figure 35. Stereo BTL Mode
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Device Functional Modes (continued)
10.4.2 Mono PBTL Mode
When this mode of operation is used, the two stereo outputs of the device are placed in parallel one with another
to increase the power sourcing capabilities of the device. The TAS5727 supports parallel BTL (PBTL) mode with
OUT_A/OUT_B (and OUT_C/OUT_D) connected before the LC filter. The merging of the two output channels in
this device can be done before the inductor portion of the output filter. This is called Single-Filter PBTL, and this
mono operation is shown in Figure 36. More information about this can be found in Single-Filter PBTL Mode.
Figure 36. Mono PBTL Mode
10.5 Programming
10.5.1 26-Bit 3.23 Number Format
All mixer gain coefficients are 26-bit coefficients using a 3.23 number format. Numbers formatted as 3.23
numbers means that there are 3 bits to the left of the binary point and 23 bits to the right of the binary point (see
Figure 37).
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Programming (continued)
2
–23
2
2
Bit
–5
Bit
–1
Bit
0
2 Bit
1
2 Bit
Sign Bit
S_xx.xxxx_xxxx_xxxx_xxxx_xxxx_xxx
M0125-01
Figure 37. 3.23 Format
The decimal value of a 3.23 format number can be found by following the weighting shown in Figure 37. If the
most significant bit is logic 0, the number is a positive number, and the weighting shown yields the correct
number. If the most significant bit is a logic 1, then the number is a negative number. In this case every bit must
be inverted, a 1 added to the result, and then the weighting shown in Figure 38 applied to obtain the magnitude
of the negative number.
1
0
2 Bit
2 Bit
1
2
–1
Bit
0
(1 or 0) ´ 2 + (1 or 0) ´ 2 + (1 or 0) ´ 2
2
–1
–4
Bit
+ ....... (1 or 0) ´ 2
2
–4
–23
Bit
+ ....... (1 or 0) ´ 2
–23
M0126-01
Figure 38. Conversion Weighting Factors—3.23 Format to Floating Point
Gain coefficients, entered through the I2C bus, must be entered as 32-bit binary numbers. Figure 39 shows the
format of the 32 bit number (4 byte or 8 digit hexadecimal number).
Fraction
Digit 6
Sign
Bit
Fraction
Digit 1
Integer
Digit 1
Fraction
Digit 2
Fraction
Digit 3
Fraction
Digit 4
Fraction
Digit 5
u u u u
u u S x
x. x x x
x x x x
x x x x
x x x x
x x x x
x x x x 0
Coefficient
Digit 8
Coefficient
Digit 7
Coefficient
Digit 6
Coefficient
Digit 5
Coefficient
Digit 4
Coefficient
Digit 3
Coefficient
Digit 2
Coefficient
Digit 1
u = unused or don’t care bits
Digit = hexadecimal digit
M0127-01
2
Figure 39. Alignment of 3.23 Coefficient in 32-Bit I C Word
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Table 2. Sample Calculation for 3.23 Format
db
LINEAR
DECIMAL
HEX (3.23
FORMAT)
0
1
8,388,608
80 0000
5
1.77
14,917,288
00E3 9EA8
–5
0.56
4,717,260
0047 FACC
X
L = 10(X/20)
D = 8,388,608 × L
H = dec2hex (D, 8)
Table 3. Sample Calculation for 9.17 Format
db
HEX (9.17
FORMAT)
LINEAR
DECIMAL
0
1
131,072
2 0000
5
1.77
231,997
3 8A3D
–5
0.56
73,400
1 1EB8
X
L = 10(X/20)
D = 131,072 × L
H = dec2hex (D, 8)
10.6 Register Maps
Table 4. Serial Control Interface Register Summary
SUBADDRESS
REGISTER NAME
NO. OF
BYTES
INITIALIZATION
VALUE
CONTENTS
A u indicates unused bits.
0x00
Clock control register
1
Description shown in subsequent section
0x6C
0x01
Device ID register
1
Description shown in subsequent section
0x43
0x02
Error status register
1
Description shown in subsequent section
0x00
0x03
System control register 1
1
Description shown in subsequent section
0x80
0x04
Serial data interface register
1
Description shown in subsequent section
0x05
0x05
System control register 2
1
Description shown in subsequent section
0x40
0x06
Soft mute register
1
Description shown in subsequent section
0x00
0x07
Master volume
2
Description shown in subsequent section
0xFF (mute)
0x08
Channel 1 vol
2
Description shown in subsequent section
0x30 (0 dB)
0x09
Channel 2 vol
2
Description shown in subsequent section
0x30 (0 dB)
0x0A
Channel 3 vol
2
Description shown in subsequent section
0x30 (0 dB)
1
Reserved (1)
1
Description shown in subsequent section
1
Reserved (1)
0x0B–0x0D
0x0E
Volume configuration register
0x0F
0x10
Modulation limit register
1
Description shown in subsequent section
0x02
0x11
IC delay channel 1
1
Description shown in subsequent section
0xAC
0x12
IC delay channel 2
1
Description shown in subsequent section
0x54
0x13
IC delay channel 3
1
Description shown in subsequent section
0xAC
0x14
IC delay channel 4
1
Description shown in subsequent section
0x54
0x15–0x19
1
Reserved
(1)
0x1A
Start/stop period register
1
0x0F
0x1B
Oscillator trim register
1
0x82
0x1C
BKND_ERR register
1
0x1D–0x1F
0x02
1
Reserved (1)
0x20
Input MUX register
4
Description shown in subsequent section
0x0001 7772
0x21
Ch 4 source select register
4
Description shown in subsequent section
0x0000 4303
0x22–0x24
(1)
0x90
4
Reserved
(1)
Reserved registers should not be accessed.
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Register Maps (continued)
Table 4. Serial Control Interface Register Summary (continued)
SUBADDRESS
0x25
0x26
0x27
0x28
0x29
0x2A
0x2B
0x2C
0x2D
32
REGISTER NAME
PWM MUX register
ch1_bq[0]
ch1_bq[1]
ch1_bq[2]
ch1_bq[3]
ch1_bq[4]
ch1_bq[5]
ch1_bq[6]
ch1_bq[7]
NO. OF
BYTES
4
20
20
20
20
20
20
20
20
CONTENTS
INITIALIZATION
VALUE
Description shown in subsequent section
0x0102 1345
u[31:26], b0[25:0]
0x0080 0000
u[31:26], b1[25:0]
0x0000 0000
u[31:26], b2[25:0]
0x0000 0000
u[31:26], a1[25:0]
0x0000 0000
u[31:26], a2[25:0]
0x0000 0000
u[31:26], b0[25:0]
0x0080 0000
u[31:26], b1[25:0]
0x0000 0000
u[31:26], b2[25:0]
0x0000 0000
u[31:26], a1[25:0]
0x0000 0000
u[31:26], a2[25:0]
0x0000 0000
u[31:26], b0[25:0]
0x0080 0000
u[31:26], b1[25:0]
0x0000 0000
u[31:26], b2[25:0]
0x0000 0000
u[31:26], a1[25:0]
0x0000 0000
u[31:26], a2[25:0]
0x0000 0000
u[31:26], b0[25:0]
0x0080 0000
u[31:26], b1[25:0]
0x0000 0000
u[31:26], b2[25:0]
0x0000 0000
u[31:26], a1[25:0]
0x0000 0000
u[31:26], a2[25:0]
0x0000 0000
u[31:26], b0[25:0]
0x0080 0000
u[31:26], b1[25:0]
0x0000 0000
u[31:26], b2[25:0]
0x0000 0000
u[31:26], a1[25:0]
0x0000 0000
u[31:26], a2[25:0]
0x0000 0000
u[31:26], b0[25:0]
0x0080 0000
u[31:26], b1[25:0]
0x0000 0000
u[31:26], b2[25:0]
0x0000 0000
u[31:26], a1[25:0]
0x0000 0000
u[31:26], a2[25:0]
0x0000 0000
u[31:26], b0[25:0]
0x0080 0000
u[31:26], b1[25:0]
0x0000 0000
u[31:26], b2[25:0]
0x0000 0000
u[31:26], a1[25:0]
0x0000 0000
u[31:26], a2[25:0]
0x0000 0000
u[31:26], b0[25:0]
0x0080 0000
u[31:26], b1[25:0]
0x0000 0000
u[31:26], b2[25:0]
0x0000 0000
u[31:26], a1[25:0]
0x0000 0000
u[31:26], a2[25:0]
0x0000 0000
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Register Maps (continued)
Table 4. Serial Control Interface Register Summary (continued)
SUBADDRESS
0x2E
0x2F
0x30
0x31
0x32
0x33
0x34
0x35
0x36
REGISTER NAME
ch1_bq[8]
ch1_bq[9]
ch2_bq[0]
ch2_bq[1]
ch2_bq[2]
ch2_bq[3]
ch2_bq[4]
ch2_bq[5]
ch2_bq[6]
NO. OF
BYTES
20
20
20
20
20
20
20
20
20
CONTENTS
INITIALIZATION
VALUE
u[31:26], b0[25:0]
0x0080 0000
u[31:26], b1[25:0]
0x0000 0000
u[31:26], b2[25:0]
0x0000 0000
u[31:26], a1[25:0]
0x0000 0000
u[31:26], a2[25:0]
0x0000 0000
u[31:26], b0[25:0]
0x0080 0000
u[31:26], b1[25:0]
0x0000 0000
u[31:26], b2[25:0]
0x0000 0000
u[31:26], a1[25:0]
0x0000 0000
u[31:26], a2[25:0]
0x0000 0000
u[31:26], b0[25:0]
0x0080 0000
u[31:26], b1[25:0]
0x0000 0000
u[31:26], b2[25:0]
0x0000 0000
u[31:26], a1[25:0]
0x0000 0000
u[31:26], a2[25:0]
0x0000 0000
u[31:26], b0[25:0]
0x0080 0000
u[31:26], b1[25:0]
0x0000 0000
u[31:26], b2[25:0]
0x0000 0000
u[31:26], a1[25:0]
0x0000 0000
u[31:26], a2[25:0]
0x0000 0000
u[31:26], b0[25:0]
0x0080 0000
u[31:26], b1[25:0]
0x0000 0000
u[31:26], b2[25:0]
0x0000 0000
u[31:26], a1[25:0]
0x0000 0000
u[31:26], a2[25:0]
0x0000 0000
u[31:26], b0[25:0]
0x0080 0000
u[31:26], b1[25:0]
0x0000 0000
u[31:26], b2[25:0]
0x0000 0000
u[31:26], a1[25:0]
0x0000 0000
u[31:26], a2[25:0]
0x0000 0000
u[31:26], b0[25:0]
0x0080 0000
u[31:26], b1[25:0]
0x0000 0000
u[31:26], b2[25:0]
0x0000 0000
u[31:26], a1[25:0]
0x0000 0000
u[31:26], a2[25:0]
0x0000 0000
u[31:26], b0[25:0]
0x0080 0000
u[31:26], b1[25:0]
0x0000 0000
u[31:26], b2[25:0]
0x0000 0000
u[31:26], a1[25:0]
0x0000 0000
u[31:26], a2[25:0]
0x0000 0000
u[31:26], b0[25:0]
0x0080 0000
u[31:26], b1[25:0]
0x0000 0000
u[31:26], b2[25:0]
0x0000 0000
u[31:26], a1[25:0]
0x0000 0000
u[31:26], a2[25:0]
0x0000 0000
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Register Maps (continued)
Table 4. Serial Control Interface Register Summary (continued)
SUBADDRESS
0x37
0x38
0x39
REGISTER NAME
ch2_bq[7]
ch2_bq[8]
ch2_bq[9]
0x3A
0x3B
0x3C
34
NO. OF
BYTES
20
20
20
4
DRC1 softening filter alpha
DRC1 softening filter omega
DRC1 attack rate
DRC1 release rate
8
CONTENTS
INITIALIZATION
VALUE
u[31:26], b0[25:0]
0x0080 0000
u[31:26], b1[25:0]
0x0000 0000
u[31:26], b2[25:0]
0x0000 0000
u[31:26], a1[25:0]
0x0000 0000
u[31:26], a2[25:0]
0x0000 0000
u[31:26], b0[25:0]
0x0080 0000
u[31:26], b1[25:0]
0x0000 0000
u[31:26], b2[25:0]
0x0000 0000
u[31:26], a1[25:0]
0x0000 0000
u[31:26], a2[25:0]
0x0000 0000
u[31:26], b0[25:0]
0x0080 0000
u[31:26], b1[25:0]
0x0000 0000
u[31:26], b2[25:0]
0x0000 0000
u[31:26], a1[25:0]
0x0000 0000
u[31:26], a2[25:0]
0x0000 0000
Reserved (1)
u[31:26], ae[25:0]
0x0008 0000
u[31:26], oe[25:0]
0x0078 0000
8
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0x0000 0100
0xFFFF FF00
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Register Maps (continued)
Table 4. Serial Control Interface Register Summary (continued)
SUBADDRESS
REGISTER NAME
0x3D
0x3E
0x3F
0x40
8
DRC2 softening filter alpha
DRC2 softening filter omega
DRC2 attack rate
DRC2 release rate
DRC1 attack threshold
0x41–0x42
0x43
DRC2 attack threshold
0x44–0x45
0x46
NO. OF
BYTES
DRC control
0x47–0x4E
8
8
INITIALIZATION
VALUE
CONTENTS
Reserved (1)
u[31:26], ae[25:0]
0x0008 0000
u[31:26], oe[25:0]
0xFFF8 0000
u[31:26], at[25:0]
0x0008 0000
u[31:26], rt[25:0]
0xFFF8 0000
4
T1[31:0] (9.23 format)
0x0800 0000
4
Reserved (1)
4
T2[31:0] (9.23 format)
4
Reserved (1)
4
Description shown in subsequent section
4
Reserved (1)
0x0074 0000
0x0000 0000
0x4F
PWM switching rate control
4
u[31:4], src[3:0]
0x0000 0006
0x50
Bank switch control
4
Description shown in subsequent section
0x0F70 8000
Ch 1 output mix1[1]
0x0080 0000
0x51
0x52
Ch 1 output mixer
Ch 2 output mixer
8
8
Ch 1 output mix1[0]
0x0000 0000
Ch 2 output mix2[1]
0x0080 0000
Ch 2 output mix2[0]
0x0000 0000
(1)
0x53
16
Reserved
0x54
16
Reserved (1)
0x56
Output post-scale
4
u[31:26], post[25:0]
0x0080 0000
0x57
Output pre-scale
4
u[31:26], pre[25:0] (9.17 format)
0x0002 0000
u[31:26], b0[25:0]
0x0080 0000
u[31:26], b1[25:0]
0x0000 0000
u[31:26], b2[25:0]
0x0000 0000
u[31:26], a1[25:0]
0x0000 0000
u[31:26], a2[25:0]
0x0000 0000
u[31:26], b0[25:0]
0x0080 0000
u[31:26], b1[25:0]
0x0000 0000
u[31:26], b2[25:0]
0x0000 0000
u[31:26], a1[25:0]
0x0000 0000
u[31:26], a2[25:0]
0x0000 0000
u[31:26], b0[25:0]
0x0080 0000
u[31:26], b1[25:0]
0x0000 0000
u[31:26], b2[25:0]
0x0000 0000
u[31:26], a1[25:0]
0x0000 0000
u[31:26], a2[25:0]
0x0000 0000
u[31:26], b0[25:0]
0x0080 0000
u[31:26], b1[25:0]
0x0000 0000
u[31:26], b2[25:0]
0x0000 0000
u[31:26], a1[25:0]
0x0000 0000
u[31:26], a2[25:0]
0x0000 0000
0x58
0x59
0x5A
0x5B
ch1_bq[10]
ch1_bq[11]
ch4_bq[0]
ch4_bq[1]
20
20
20
20
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Register Maps (continued)
Table 4. Serial Control Interface Register Summary (continued)
SUBADDRESS
0x5C
0x5D
0x5E
0x5F
REGISTER NAME
ch2_bq[10]
ch2_bq[11]
ch3_bq[0]
ch3_bq[1]
0x60–0x61
0x62
NO. OF
BYTES
20
20
20
20
4
IDF post scale
CONTENTS
INITIALIZATION
VALUE
u[31:26], b0[25:0]
0x0080 0000
u[31:26], b1[25:0]
0x0000 0000
u[31:26], b2[25:0]
0x0000 0000
u[31:26], a1[25:0]
0x0000 0000
u[31:26], a2[25:0]
0x0000 0000
u[31:26], b0[25:0]
0x0080 0000
u[31:26], b1[25:0]
0x0000 0000
u[31:26], b2[25:0]
0x0000 0000
u[31:26], a1[25:0]
0x0000 0000
u[31:26], a2[25:0]
0x0000 0000
u[31:26], b0[25:0]
0x0080 0000
u[31:26], b1[25:0]
0x0000 0000
u[31:26], b2[25:0]
0x0000 0000
u[31:26], a1[25:0]
0x0000 0000
u[31:26], a2[25:0]
0x0000 0000
u[31:26], b0[25:0]
0x0080 0000
u[31:26], b1[25:0]
0x0000 0000
u[31:26], b2[25:0]
0x0000 0000
u[31:26], a1[25:0]
0x0000 0000
u[31:26], a2[25:0]
0x0000 0000
Reserved (1)
4
0x0000 0080
Reserved (1)
0x63–0x6A
0x6B
Left channel PWM level meter
4
Data[31:0]
0x0000 0000
0x6C
Right channel PWM level meter
4
Data[31:0]
0x0000 0000
Reserved (1)
0x6D–0x6F
0x70
ch1 inline mixer
4
u[31:26], in_mix1[25:0]
0x0080 0000
0x71
inline_DRC_en_mixer_ch1
4
u[31:26], in_mixdrc_1[25:0]
0x0000 0000
0x72
ch1 right_channel mixer
4
u[31:26], right_mix1[25:0]
0x0000 0000
0x73
ch1 left_channel_mixer
4
u[31:26], left_mix_1[25:0]
0x0080 0000
0x74
ch2 inline mixer
4
u[31:26], in_mix2[25:0]
0x0080 0000
0x75
inline_DRC_en_mixer_ch2
4
u[31:26], in_mixdrc_2[25:0]
0x0000 0000
0x76
ch2 left_chanel mixer
4
u[31:26], left_mix1[25:0]
0x0000 0000
0x77
ch2 right_channel_mixer
4
u[31:26], right_mix_1[25:0]
0x0080 0000
0x78–0xF7
Reserved
(1)
0xF8
Update dev address key
4
Dev Id Update Key[31:0] (Key =
0xF9A5A5A5)
0x0000 0000
0xF9
Update dev address reg
4
u[31:8],New Dev Id[7:0] (New Dev Id = 0x38
for TAS5727)
0x0000 0036
4
Reserved (1)
0xFA–0xFF
All DAP coefficients are 3.23 format unless specified otherwise.
Registers 0x3B through 0x46 should be altered only during the initialization phase.
36
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10.6.1 Clock Control Register (0x00)
The clocks and data rates are automatically determined by the TAS5727. The clock control register contains the
autodetected clock status. Bits D7–D5 reflect the sample rate. Bits D4–D2 reflect the MCLK frequency.
Table 5. Clock Control Register (0x00)
D7
D6
D5
D4
D3
D2
D1
D0
0
0
0
–
–
–
–
–
fS = 32-kHz sample rate
0
0
1
–
–
–
–
–
Reserved
0
1
0
–
–
–
–
–
Reserved
0
1
1
–
–
–
–
–
fS = 44.1/48-kHz sample rate (1)
1
0
0
–
–
–
–
–
fS = 16-kHz sample rate
1
0
1
–
–
–
–
–
fS = 22.05/24-kHz sample rate
1
1
0
–
–
–
–
–
fS = 8-kHz sample rate
1
1
1
–
–
–
–
–
fS = 11.025/12-kHz sample rate
–
–
–
0
0
0
–
–
MCLK frequency = 64 × fS (2)
–
–
–
0
0
1
–
–
MCLK frequency = 128 × fS (2)
–
–
–
0
1
0
–
–
MCLK frequency = 192 × fS (3)
–
–
–
0
1
1
–
–
MCLK frequency = 256 × fS
–
–
–
1
0
0
–
–
MCLK frequency = 384 × fS
–
–
–
1
0
1
–
–
MCLK frequency = 512 × fS
–
–
–
1
1
0
–
–
Reserved
–
–
–
1
1
1
–
–
Reserved
–
–
–
–
–
–
0
–
Reserved (1)
–
–
–
–
–
–
–
0
Reserved (1)
(1)
(2)
(3)
(4)
FUNCTION
(1) (4)
Default values are in bold.
Only available for 44.1-kHz and 48-kHz rates
Rate only available for 32/44.1/48-KHz sample rates
Not available at 8 kHz
10.6.2 Device Id Register (0x01)
The device ID register contains the ID code for the firmware revision.
Table 6. General Status Register (0x01)
D7
D6
D5
D4
D3
D2
D1
D0
0
0
0
0
0
0
0
0
(1)
FUNCTION
Identification code (1)
Default values are in bold.
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10.6.3 Error Status Register (0x02)
The error bits are sticky and are not cleared by the hardware. This means that the software must clear the
register (write zeroes) and then read them to determine if they are persistent errors.
Error definitions:
• MCLK error: MCLK frequency is changing. The number of MCLKs per LRCLK is changing.
• SCLK error: The number of SCLKs per LRCLK is changing.
• LRCLK error: LRCLK frequency is changing.
• Frame slip: LRCLK phase is drifting with respect to internal frame sync.
Table 7. Error Status Register (0x02)
D7
D6
D5
D4
D3
D2
D1
D0
1
-
–
–
–
–
–
–
MCLK error
–
1
–
–
–
–
–
–
PLL autolock error
–
–
1
–
–
–
–
–
SCLK error
–
–
–
1
–
–
–
–
LRCLK error
–
–
–
–
1
–
–
–
Frame slip
–
–
–
–
–
1
–
–
Clip indicator
–
–
–
–
–
–
1
–
Overcurrent, overtemperature, overvoltage, or undervoltage error
0
0
0
0
0
0
0
0
Reserved
0
0
0
0
0
0
0
0
No errors
(1)
FUNCTION
(1)
Default values are in bold.
10.6.4 System Control Register 1 (0x03)
System control register 1 has several functions:
Bit D7:
If 0, the DC-blocking filter for each channel is disabled.
If 1, the DC-blocking filter (–3 dB cutoff
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