TAS5731
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SLOS726A – DECEMBER 2011 – REVISED SEPTEMBER 2013
2 × 20-W DIGITAL AUDIO POWER AMPLIFIER WITH DSP AND 2.1 MODE
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FEATURES
1
•
•
•
•
•
•
•
•
•
2
2-Ch I S Input; 8-kHz to 48-kHz fS
20-W Stereo, 8 Ω/18 V (THD+N = 10%)
Up to 90% Efficient Operation
Wide 8-V to- 21-V Supply Range;
3.3-V Digital Supply
Single-Device 2.1 Support (2 × SE + 1 × BTL)
70-mΩ RDS(on) Device That Can Support 2-Ω SE
and 4-Ω BTL Modes
– 12 V / 2 Ω / 8 W With SE mode
– 12 V / 4 Ω / 15 W With BTL mode
Speaker EQ (8 BQ per Channel), 2× DRCs
P2P Compatible With the TAS5727
Benefits
– Direct Connect to Digital Processor
– High Output Power From a Standard
Supply
– Eliminates Need for Heat Sink
– Advanced Processing Improves Audio
Experience
APPLICATIONS
•
•
•
LCD TV
LED TV
Sound Bar
DESCRIPTION
The TAS5731 is a 20-W, efficient, digital-audio stereo
power amplifier for driving stereo bridge-tied
speakers. One serial data input allows processing of
up to two discrete audio channels and seamless
integration to most digital audio processors and
MPEG decoders. The device accepts a wide range of
input data and data rates. A fully programmable data
path routes these channels to the internal speaker
drivers.
The TAS5731 is a slave-only device receiving all
clocks from external sources. The TAS5731 operates
with a PWM carrier between a 384-kHz switching rate
and a 352-kHz switching rate, depending on the input
sample rate. Oversampling combined with a fourthorder noise shaper provides a flat noise floor and
excellent dynamic range from 20 Hz to 20 kHz.
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2011–2013, Texas Instruments Incorporated
TAS5731
SLOS726A – DECEMBER 2011 – REVISED SEPTEMBER 2013
www.ti.com
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
SIMPLIFIED 2.1 APPLICATION DIAGRAM
3.3 V
8 V–21 V
AVDD/DVDD
PVDD
LRCLK
Digital
Audio
Source
OUT_A
LCSE
SCLK
MCLK
PVDD
BST_A
SDIN
BST_B
2
I C
Control
SDA
Control
Inputs
RESET
OUT_B
LCSE
PVDD
SCL
PDN
OUT_C
Loop
Filter
PLL_FLTP
PLL_FLTM
BST_C
LCBTL
BST_D
OUT_D
B0264-25
2
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SLOS726A – DECEMBER 2011 – REVISED SEPTEMBER 2013
FUNCTIONAL VIEW
OUT_A
2´ HB
FET Out
SDIN
Serial
Audio
Port
Digital Audio Processor
(DAP)
S
R
C
th
4 -Order
Noise Shaper
and PWM
OUT_B
OUT_C
2´ HB
FET Out
OUT_D
Protection
Logic
MCLK
SCLK
LRCLK
SDA
SCL
Sample Rate
Autodetect
and PLL
Serial
Control
Click and Pop
Control
Microcontroller
Based
System
Control
Terminal Control
B0262-14
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TAS5731
SLOS726A – DECEMBER 2011 – REVISED SEPTEMBER 2013
www.ti.com
Undervoltage
Protection
FAULT
4
4
Power
On
Reset
Protection
and
I/O Logic
AGND
Temp.
Sense
GND
VALID
Overcurrent
Protection
Isense
BST_D
PVDD_CD
PWM
Rcv
Ctrl
Timing
PWM Controller
PWM_D
Gate
Drive
OUT_D
Pulldown Resistor
PGND_CD
GVDD
Regulator
GVDD_OUT
BST_C
PVDD_CD
PWM_C
PWM
Rcv
Ctrl
Timing
Gate
Drive
OUT_C
Pulldown Resistor
PGND_CD
BST_B
PVDD_AB
PWM_B
PWM
Rcv
Ctrl
Timing
Gate
Drive
OUT_B
Pulldown Resistor
GVDD
Regulator
PGND_AB
BST_A
PVDD_AB
PWM_A
PWM
Rcv
Ctrl
Timing
Gate
Drive
OUT_A
Pulldown Resistor
PGND_AB
B0034-08
Figure 1. Power-Stage Functional Block Diagram
4
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R
L
Input Muxing
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½
61
+
31
1BQ
2A
1BQ
21 (D8, D9)
1
0
3
I2C:54 – V2IM
+
+
6BQ
5B
5A
32–36, 5C
1BQ
+
2B–2F, 58
6BQ
1BQ
1
1
+
55
+
Vol1
+
Auto-lp
(0x46 Bit 5)
0
–1
+
5E
1BQ
1BQ
5D
1BQ
59
3D
ealpha
3D
ealpha
Vol2
Vol2
ealpha
3A
3A
ealpha
Vol1
Energy
MAXMUX
R
1
1
2
I C Subaddress in Red
Attack
Decay
Attack
Decay
Master ON/OFF
(0x46[1])
Log
Math
Master ON/OFF
(0x46[0])
Log
Math
1
1
+
+
60 V6OM
+
52 V2OM
1
1
51 V1OM
I2C:56
VDISTA
B0321-14
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½
L
30
1BQ
29
1BQ
I2C:53 – V1IM
TAS5731
SLOS726A – DECEMBER 2011 – REVISED SEPTEMBER 2013
DAP Process Structure
I2C:57
VDISTB
Energy
MAXMUX
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TAS5731
SLOS726A – DECEMBER 2011 – REVISED SEPTEMBER 2013
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DEVICE INFORMATION
PGND_CD
PGND_CD
NC
OUT_C
BST_C
NC
NC
BST_B
NC
PGND_AB
OUT_B
PGND_AB
PHP Package
(Top View)
48 47 46 45 44 43 42 41 40 39 38 37
OUT_A
1
36
OUT_D
PVDD_AB
2
35
PVDD_CD
PVDD_AB
3
34
PVDD_CD
BST_A
4
33
BST_D
NC
5
32
GVDD_OUT
SSTIMER
6
31
VREG
AGND
NC
7
30
PBTL
8
29
GND
AVSS
9
28
DVSS
PLL_FLTM
10
27
DVDD
PLL_FLTP
11
26
STEST
VR_ANA
12
25
RESET
SCL
SDA
SDIN
SCLK
PDN
LRCLK
VR_DIG
DVSSO
OSC_RES
MCLK
ADR/FALULT
AVDD
13 14 15 16 17 18 19 20 21 22 23 24
P0075-25
PIN FUNCTIONS
PIN
NAME
NO.
TYPE (1)
5-V
TERMINATION (2)
TOLERANT
DESCRIPTION
AGND
30
P
Local analog ground for power stage, which should be connected to
the system ground.
ADR/FAULT
14
DIO
Dual function terminal which sets the LSB of the 7-bit I2C address to
"0" if pulled to GND and to "1" if pulled to DVDD. If configured to be
a fault output by the methods described in I²C Address Selection and
Fault Output, this terminal is pulled low when an internal fault occurs.
A pull-up or pull-down resistor is required, as is shown in the Typical
Application Circuit Diagrams. If pulled high (to DVDD), a 15kΩ
resistor should be used to minimize in-rush current at power up and
to isolate the net if the pin is used as a fault output, as described
above.
AVDD
13
P
3.3-V analog power supply
AVSS
9
P
Analog 3.3-V supply ground
BST_A
4
P
High-side bootstrap supply for half-bridge A
BST_B
43
P
High-side bootstrap supply for half-bridge B
(1)
(2)
6
TYPE: A = analog; D = 3.3-V digital; P = power/ground/decoupling; I = input; O = output
All pullups are 20-µA weak pullups and all pulldowns are 20-µA weak pulldowns. The pullups and pulldowns are included to assure
proper input logic levels if the terminals are left unconnected (pull-ups → logic 1 input; pulldowns → logic 0 input). Devices that drive
inputs with pullups must be able to sink 20 µA while maintaining a logic-0 drive level. Devices that drive inputs with pulldowns must be
able to source 20 µA while maintaining a logic-1 drive level.
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SLOS726A – DECEMBER 2011 – REVISED SEPTEMBER 2013
PIN FUNCTIONS (continued)
PIN
NAME
NO.
TYPE (1)
5-V
TERMINATION (2)
TOLERANT
DESCRIPTION
BST_C
42
P
High-side bootstrap supply for half-bridge C
BST_D
33
P
High-side bootstrap supply for half-bridge D
DVDD
27
P
3.3-V digital power supply
DVSS
28
P
Digital ground
DVSSO
17
P
Oscillator ground
GND
29
P
Analog ground for power stage
GVDD_OUT
32
P
LRCLK
20
DI
5-V
Pulldown
Input serial audio data left/right clock (sample-rate clock)
MCLK
15
DI
5-V
Pulldown
Master clock input
5, 7,
40,
41,
44, 45
–
OSC_RES
16
AO
OUT_A
1
O
Output, half-bridge A
OUT_B
46
O
Output, half-bridge B
OUT_C
39
O
Output, half-bridge C
OUT_D
36
O
PBTL
8
DI
PDN
19
DI
PGND_AB
47, 48
P
Power ground for half-bridges A and B
PGND_CD
37, 38
P
Power ground for half-bridges C and D
PLL_FLTM
10
AO
PLL negative loop-filter terminal
PLL_FLTP
11
AO
PLL positive loop-filter terminal
PVDD_AB
2, 3
P
PVDD_CD
34, 35
P
RESET
25
DI
5-V
SCL
24
DI
5-V
SCLK
21
DI
5-V
SDA
23
DIO
5-V
SDIN
22
DI
5-V
SSTIMER
6
AI
Controls ramp time of OUT_x to minimize pop. Leave this pin
floating for BD mode. Requires capacitor of 2.2 nF to GND in AD
mode. The capacitor determines the ramp time.
STEST
26
DI
Factory test pin. Connect directly to DVSS.
VR_ANA
12
P
Internally regulated 1.8-V analog supply voltage. This pin must not
be used to power external devices.
VR_DIG
18
P
Internally regulated 1.8-V digital supply voltage. This pin must not be
used to power external devices.
VREG
31
P
Digital regulator output. Not to be used for powering external
circuitry.
NC
Gate drive internal regulator output
No connect
Oscillator trim resistor. Connect an 18.2-kΩ, 1% resistor to DVSSO.
Output, half-bridge D
5-V
Pulldown
Low means BTL mode; high means PBTL mode. Information goes
directly to power stage.
Pullup
Power down, active-low. PDN prepares the device for loss of power
supplies by shutting down the noise shaper and initiating the PWM
stop sequence.
Power-supply input for half-bridge output A and B
Power-supply input for half-bridge output C and D
Pullup
Reset, active-low. A system reset is generated by applying a logic
low to this pin. RESET is an asynchronous control signal that
restores the DAP to its default conditions and places the PWM in the
hard-mute (high-impedance) state.
I2C serial control clock input
Pulldown
Serial audio-data clock (shift clock). SCLK is the serial-audio-port
input-data bit clock.
I2C serial control data interface input/output
Pulldown
Serial audio data input. SDIN supports three discrete (stereo) data
formats.
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TAS5731
SLOS726A – DECEMBER 2011 – REVISED SEPTEMBER 2013
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ABSOLUTE MAXIMUM RATINGS
over operating free-air temperature range (unless otherwise noted)
Supply voltage
(1)
VALUE
UNIT
DVDD, AVDD
–0.3 to 3.6
V
PVDD_x
–0.3 to 30
V
3.3-V digital input
–0.5 to DVDD + 0.5
5-V tolerant (2) digital input (except MCLK)
Input voltage
–0.5 to DVDD + 2.5 (3)
5-V tolerant MCLK input
–0.5 to AVDD + 2.5
V
(3)
OUT_x to PGND_x
27 (4)
V
BST_x to PGND_x
34 (4)
V
Input clamp current, IIK
±20
mA
Output clamp current, IOK
±20
mA
0 to 85
°C
0 to 150
°C
–40 to 125
°C
Operating free-air temperature
Operating junction temperature range
Storage temperature range, Tstg
(1)
(2)
(3)
(4)
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating
Conditions is not implied. Exposure to absolute-maximum conditions for extended periods may affect device reliability.
5-V tolerant inputs are PDN, RESET, SCLK, LRCLK, MCLK, SDIN, SDA, and SCL.
Maximum pin voltage should not exceed 6 V.
DC voltage + peak ac waveform measured at the pin should be below the allowed limit for all conditions.
THERMAL INFORMATION
TAS5731
THERMAL METRIC (1)
UNIT
PHP (48 PINS)
θJA
Junction-to-ambient thermal resistance
27.9
°C/W
θJB
Junction-to-board thermal resistance
13
°C/W
θJC(bottom)
Junction-to-case (bottom) thermal resistance
1.1
°C/W
θJC(top)
Junction-to-case (top) thermal resistance
20.7
°C/W
ψJT
Junction-to-top characterization parameter
0.3
°C/W
ψJB
Junction-to-board characterization parameter
6.7
°C/W
(1)
For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.
RECOMMENDED OPERATING CONDITIONS
MIN
NOM
MAX
Digital/analog supply voltage
DVDD, AVDD
3
3.3
3.6
V
Half-bridge supply voltage
PVDD_x
8
21.5 (1)
V
VIH
High-level input voltage
5-V tolerant
2
VIL
Low-level input voltage
5-V tolerant
0.8
V
TA
Operating ambient temperature range
0
85
°C
TJ (2)
Operating junction temperature range
0
125
°C
RL (PBTL)
RL (BTL)
RL (SE)
(1)
(2)
8
Load impedance
Load impedance
Load impedance
Output filter: L = 15 μH, C = 680 nF,
PVDD_x ≤ 13 V
3
Output filter: L = 15 μH, C = 680 nF,
PVDD_x > 13 V
4
Output filter: L = 15 μH, C = 680 nF
4
Output filter: L = 15 μH, C = 680 nF,
PVDD_x ≤ 13 V
2
Output filter: L = 15 μH, C = 680 nF,
PVDD_x > 13 V
4
UNIT
V
Ω
Ω
Ω
For operation at PVDD_x levels greater than 18V, the modulation limit must be set to 93.8% via the control port register 0x10.
Continuous operation above the recommended junction temperature may result in reduced reliability and/or lifetime of the device.
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SLOS726A – DECEMBER 2011 – REVISED SEPTEMBER 2013
RECOMMENDED OPERATING CONDITIONS (continued)
MIN
LO
Minimum output inductance under shortcircuit condition
Output-filter inductance
NOM
MAX
UNIT
μH
10
PWM OPERATION AT RECOMMENDED OPERATING CONDITIONS
PARAMETER
TEST CONDITIONS
Output PWM switch frequency
VALUE
11.025/22.05/44.1-kHz data rate ±2%
352.8
48/24/12/8/16/32-kHz data rate ±2%
384
UNIT
kHz
PLL INPUT PARAMETERS AND EXTERNAL FILTER COMPONENTS
PARAMETER
fMCLKI
tr /
tf(MCLK)
TEST CONDITIONS
MIN
MCLK frequency
2.8224
MCLK duty cycle
40%
TYP
50%
Rise/fall time for MCLK
LRCLK allowable drift before LRCLK reset
External PLL filter capacitor C1
SMD 0603 X7R
External PLL filter capacitor C2
External PLL filter resistor R
MAX
UNIT
24.576
MHz
60%
5
ns
4
MCLKs
47
nF
SMD 0603 X7R
4.7
nF
SMD 0603, metal film
470
Ω
ELECTRICAL CHARACTERISTICS
DC Characteristics
TA = 25°, PVCC_x = 18 V, DVDD = AVDD = 3.3 V, RL= 8 Ω, BTL AD mode, fS = 48 kHz (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
VOH
High-level output voltage
ADR/FAULTand SDA
IOH = –4 mA
DVDD = 3 V
VOL
Low-level output voltage
ADR/FAULTand SDA
IOL = 4 mA
DVDD = 3 V
0.5
V
IIL
Low-level input current
VI < VIL ; DVDD = AVDD
= 3.6V
75
μA
IIH
High-level input current
VI > VIH ; DVDD =
AVDD = 3.6V
75 (1)
μA
IDD
3.3 V supply current
3.3 V supply voltage (DVDD,
AVDD)
IPVDD
Supply current
No load (PVDD_x)
Drain-to-source resistance, LS
TJ = 25°C, includes metallization resistance
80
Drain-to-source resistance, HS
TJ = 25°C, includes metallization resistance
80
rDS(on)
(2)
2.4
V
Normal mode
49
68
Reset (RESET = low,
PDN = high)
23
38
Normal mode
32
50
3
8
Reset (RESET = low,
PDN = high)
mA
mA
mΩ
I/O Protection
Vuvp
Undervoltage protection limit
PVDD falling
6.4
V
Vuvp,hyst
Undervoltage protection limit
PVDD rising
7.1
V
150
°C
30
°C
4.5
A
150
ns
OTE
(3)
OTEHYST
Overtemperature error
(3)
Extra temperature drop
required to recover from error
IOC
Overcurrent limit protection
IOCT
Overcurrent response time
(1)
(2)
(3)
Output to output short in BTL mode
IIH for the PBTL pin has a maximum limit of 200 µA due to an internal pulldown on the pin.
This does not include bond-wire or pin resistance.
Specified by design
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AC Characteristics (BTL, PBTL)
PVDD_x = 18 V, BTL AD mode, fS = 48 KHz, RL = 8 Ω, CBST = 33 nF, audio frequency = 1 kHz, AES17 filter,
fPWM = 384 kHz, TA = 25°C (unless otherwise specified). All performance is in accordance with recommended operating
conditions (unless otherwise specified).
PARAMETER
TEST CONDITIONS
BTL mode, PVDD = 8 V, 7% THD
PO
Power output per channel
THD+N
Vn
SNR
(1)
10
Total harmonic distortion + noise
MIN
TYP
MAX
UNIT
4
BTL mode, PVDD = 8 V, 10% THD
4.2
BTL mode, PVDD = 12 V, 7% THD
9.1
BTL mode, PVDD = 12 V, 10% THD
9.6
BTL mode, PVDD = 18 V, 7% THD
19.8
BTL mode, PVDD = 18 V, 10% THD
20.9
PBTL mode, PVDD = 12 V, RL = 4 Ω,
7% THD
17.7
PBTL mode, PVDD = 12 V, RL = 4 Ω,
10% THD
18.7
PBTL mode, PVDD = 18 V, RL = 4 Ω,
7% THD
39
PBTL mode, PVDD = 18 V, RL = 4 Ω,
10% THD
41.5
SE Mode, PVDD = 12 V, RL = 4 Ω, 7% THD
4.3
SE Mode, PVDD = 12 V, RL = 4 Ω, 10%
THD
4.6
SE Mode, PVDD = 18 V, RL = 4 Ω, 7% THD
16.8
SE Mode, PVDD = 18 V, RL = 4 Ω, 10%
THD
17.8
PVDD = 8 V, PO = 1 W
0.1
PVDD = 12 V, PO = 1 W
0.07
PVDD = 18 V, PO = 1 W
0.03
W
%
Output integrated noise (rms)
A-weighted
56
μV
Cross-talk
PO = 0.25 W, f = 1 kHz (AD Mode)
–69
dB
Signal-to-noise ratio (1)
A-weighted, f = 1 kHz, maximum power at
THD < 1%
106
dB
SNR is calculated relative to 0-dBFS input level.
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SERIAL AUDIO PORTS SLAVE MODE
over recommended operating conditions (unless otherwise noted)
TEST
CONDITIONS
PARAMETER
MIN
CL = 30 pF
TYP
1.024
MAX
UNIT
12.288
MHz
fSCLKIN
Frequency, SCLK 32 × fS, 48 × fS, 64 × fS
tsu1
Setup time, LRCLK to SCLK rising edge
10
ns
th1
Hold time, LRCLK from SCLK rising edge
10
ns
tsu2
Setup time, SDIN to SCLK rising edge
10
ns
th2
Hold time, SDIN from SCLK rising edge
10
LRCLK frequency
ns
8
48
48
SCLK duty cycle
40%
50%
60%
LRCLK duty cycle
40%
50%
60%
SCLK rising edges between LRCLK rising edges
t(edge)
LRCLK clock edge with respect to the falling edge of SCLK
tr/tf
Rise/fall time for SCLK/LRCLK
kHz
32
64
SCLK
edges
–1/4
1/4
SCLK
period
8
tr
ns
tf
SCLK
(Input)
t(edge)
th1
tsu1
LRCLK
(Input)
th2
tsu2
SDIN
T0026-04
Figure 2. Slave-Mode Serial Data-Interface Timing
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I2C SERIAL CONTROL PORT OPERATION
Timing characteristics for I2C Interface signals over recommended operating conditions (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
fSCL
Frequency, SCL
tw(H)
Pulse duration, SCL high
No wait states
0.6
tw(L)
Pulse duration, SCL low
1.3
tr
Rise time, SCL and SDA
tf
Fall time, SCL and SDA
tsu1
Setup time, SDA to SCL
th1
Hold time, SCL to SDA
t(buf)
tsu2
MAX
UNIT
400
kHz
μs
μs
300
ns
300
ns
100
ns
0
ns
Bus free time between stop and start conditions
1.3
μs
Setup time, SCL to start condition
0.6
μs
th2
Hold time, start condition to SCL
0.6
μs
tsu3
Setup time, SCL to stop condition
0.6
CL
Load capacitance for each bus line
μs
400
tw(H)
tw(L)
pF
tf
tr
SCL
tsu1
th1
SDA
T0027-01
Figure 3. SCL and SDA Timing
SCL
t(buf)
th2
tsu2
tsu3
SDA
Start
Condition
Stop
Condition
T0028-01
Figure 4. Start and Stop Conditions Timing
12
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SLOS726A – DECEMBER 2011 – REVISED SEPTEMBER 2013
RESET TIMING (RESET)
Control signal parameters over recommended operating conditions (unless otherwise noted). Please refer to Recommended
Use Model section on usage of all terminals.
PARAMETER
tw(RESET)
MIN
Pulse duration, RESET active
TYP
2
td(I2C_ready)
MAX
UNIT
μs
100
Time to enable I C
12
ms
RESET
tw(RESET)
2
2
I C Active
I C Active
td(I2C_ready)
System Initialization.
2
Enable via I C.
T0421-01
NOTES: On power up, it is recommended that the TAS5731 RESET be held LOW for at least 100 μs after DVDD has
reached 3 V.
If RESET is asserted LOW while PDN is LOW, then RESET must continue to be held LOW for at least 100 μs after
PDN is deasserted (HIGH).
Figure 5. Reset Timing
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TYPICAL CHARACTERISTICS, SE CONFIGURATION, 4 Ω
TOTAL HARMONIC DISTORTION + NOISE
vs
FREQUENCY
TOTAL HARMONIC DISTORTION + NOISE
vs
FREQUENCY
10
10
PVDD = 12V
RL = 4Ω
TA = 25°C
PVDD = 18V
RL = 4Ω
TA = 25°C
1
THD+N (%)
THD+N (%)
1
0.1
0.1
0.01
0.01
PO = 1W
PO = 2.5W
PO = 5W
0.001
20
100
PO = 1W
PO = 5W
PO = 10W
1k
Frequency (Hz)
10k
20k
0.001
20
100
1k
Frequency (Hz)
10k
20k
G021
G022
Figure 6.
Figure 7.
TEXT FOR SPACING
TEXT FOR SPACING
TEXT FOR SPACING
TEXT FOR SPACING
TOTAL HARMONIC DISTORTION + NOISE
vs
OUTPUT POWER
EFFICIENCY
vs
TOTAL OUTPUT POWER
10
100
RL = 4Ω
TA = 25°C
90
80
1
Efficiency (%)
THD+N (%)
70
0.1
60
50
40
30
PVDD = 12V
PVDD = 18V
0.01
20
0.001
0.01
0.1
1
Output Power (W)
10
Device Configuration = 2.1
RL = 4,4,8Ω
TA = 25°C
10
PVDD = 12V
PVDD = 18V
40
0
0
5
10
15
20
25
30
35
Total Output Power (W)
G024
Figure 8.
14
40
45
50
G001
Figure 9.
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TYPICAL CHARACTERISTICS, BTL CONFIGURATION, 8 Ω
TOTAL HARMONIC DISTORTION
vs
FREQUENCY (BTL)
TOTAL HARMONIC DISTORTION
vs
FREQUENCY (BTL)
10
10
PVDD = 12V
RL = 8Ω
TA = 25°C
PVDD = 18V
RL = 8Ω
TA = 25°C
1
THD+N (%)
THD+N (%)
1
0.1
0.01
0.1
0.01
PO = 1W
PO = 2.5W
PO = 5W
0.001
20
100
PO = 1W
PO = 5W
PO = 10W
1k
Frequency (Hz)
10k
0.001
20k
20
100
1k
Frequency (Hz)
10k
20k
G001
G002
Figure 10.
Figure 11.
TOTAL HARMONIC DISTORTION + NOISE
vs
OUTPUT POWER (BTL)
TOTAL HARMONIC DISTORTION + NOISE
vs
OUTPUT POWER (BTL)
10
10
PVDD = 12V
RL = 8Ω
TA = 25°C
PVDD = 18V
RL = 8Ω
TA = 25°C
1
THD+N (%)
THD+N (%)
1
0.1
0.01
0.1
0.01
f = 20Hz
f = 1kHz
f = 10kHz
0.001
0.01
0.1
1
Output Power (W)
10
f = 20Hz
f = 1kHz
f = 10kHz
40
0.001
0.01
0.1
1
Output Power (W)
10
G004
Figure 12.
40
G005
Figure 13.
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TYPICAL CHARACTERISTICS, BTL CONFIGURATION, 8 Ω (continued)
CROSSTALK
vs
FREQUENCY
CROSSTALK
vs
FREQUENCY
0
0
VO = 1W
PVDD = 12V
RL = 8Ω
TA = 25°C
−10
−20
Right to Left
Left to Right
−20
Right to Left
Left to Right
−30
Crosstalk (dB)
Crosstalk (dB)
−30
−40
−50
−60
−40
−50
−60
−70
−70
−80
−80
−90
−90
−100
VO = 1W
PVDD = 18V
RL = 8Ω
TA = 25°C
−10
20
100
1k
Frequency (Hz)
10k
20k
−100
20
100
1k
Frequency (Hz)
10k
20k
G007
G008
Figure 14.
Figure 15.
EFFICIENCY
vs
OUTPUT POWER
OUTPUT POWER
vs
SUPPLY VOLTAGE (BTL)
100
40
RL = 8Ω
TA = 25°C
90
35
80
30
Output Power (W)
Efficiency (%)
70
60
50
40
25
20
15
30
PVDD = 12V
PVDD = 18V
20
10
0
10
5
RL = 8Ω
TA = 25°C
0
5
10
15
20
25
30
35
Total Output Power (W)
40
45
THD+N = 1%
THD+N = 10%
50
0
12
14
16
18
Supply Voltage (V)
G010
Figure 16.
20
21
G011
Figure 17.
DETAILED DESCRIPTION
POWER SUPPLY
To facilitate system design, the TAS5731 needs only a 3.3-V supply in addition to the (typical) 18-V power-stage
supply. An internal voltage regulator provides suitable voltage levels for the gate drive circuitry. Additionally, all
circuitry requiring a floating voltage supply, e.g., the high-side gate drive, is accommodated by built-in bootstrap
circuitry requiring only a few external capacitors.
16
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In order to provide good electrical and acoustical characteristics, the PWM signal path for the output stage is
designed as identical, independent half-bridges. For this reason, each half-bridge has separate bootstrap pins
(BST_x), and power-stage supply pins (PVDD_x). The gate-drive voltage (GVDD_OUT) is derived from the
PVDD voltage. Special attention should be paid to placing all decoupling capacitors as close to their associated
pins as possible. Inductance between the power-supply pins and decoupling capacitors must be avoided.
For a properly functioning bootstrap circuit, a small ceramic capacitor must be connected from each bootstrap pin
(BST_x) to the power-stage output pin (OUT_x). When the power-stage output is low, the bootstrap capacitor is
charged through an internal diode connected between the gate-drive regulator output pin (GVDD_OUT) and the
bootstrap pin. When the power-stage output is high, the bootstrap capacitor potential is shifted above the output
potential and thus provides a suitable voltage supply for the high-side gate driver. In an application with PWM
switching frequencies in the range from 288 kHz to 384 kHz, it is recommended to use 33-nF, X7R ceramic
capacitors, size 0603 or 0805, for the bootstrap supply. These 33-nF capacitors ensure sufficient energy storage,
even during minimal PWM duty cycles, to keep the high-side power-stage FET (LDMOS) fully turned on during
the remaining part of the PWM cycle.
Special attention should be paid to the power-stage power supply; this includes component selection, PCB
placement, and routing. As indicated, each half-bridge has independent power-stage supply pins (PVDD_x). For
optimal electrical performance, EMI compliance, and system reliability, it is important that each PVDD_x pin is
decoupled with a 100-nF, X7R ceramic capacitor placed as close as possible to each supply pin.
The TAS5731 is fully protected against erroneous power-stage turnon due to parasitic gate charging.
I2C Address Selection and Fault Output
ADR/FAULT is an input pin during power up. It can be pulled HIGH or LOW through a resistor as shown in the
Typical Application Circuit section in order to set the I2C address. Pulling this pin HIGH through the resistor
results in setting the I2C 7-bit address to 0011011 (0x36), and pulling it LOW through the resistor results in
setting the address to 0011010 (0x34).
During power up, the address of the device is latched in, freeing up the ADR/FAULT pin to be used as a fault
notification output. When configured as a fault output, the pin will go low when a fault occurs and will return to it's
default state when register 0x02 is cleared. The behavior of the pin in response to a fault condition is to be pulled
low immediately upon an error. The device then waits for a period of time determined by BKND_ERR Register
(0x1C) before attempting to resume playback. If the error has been cleared when the device attempts to resume
playback, playback will resume, the ADR/FAULT pin will remain high, and normal operation will resume. If the
error has not been removed, then the device will immediately re-enter the protected state and wait again for the
predetermined period of time to pass. The device will pull the fault pin low for over-current, over-temperature, and
under-voltage lock-out.
SINGLE-FILTER PBTL MODE
The TAS5731 supports parallel BTL (PBTL) mode with OUT_A/OUT_B (and OUT_C/OUT_D) connected before
the LC filter. In order to put the part in PBTL configuration, drive PBTL (pin 8) HIGH. This synchronizes the
turnoff of half-bridges A and B (and similarly C/D) if an overcurrent condition is detected in either half-bridge.
There is a pulldown resistor on the PBTL pin that configures the part in BTL mode if the pin is left floating.
PWM output multiplexers should be updated to set the device in PBTL mode. Output Mux Register (0x25) should
be written with a value of 0x0110 3245.
DEVICE PROTECTION SYSTEM
Overcurrent (OC) Protection With Current Limiting
The device has independent, fast-reacting current detectors on all high-side and low-side power-stage FETs. The
detector outputs are closely monitored by a protection system. If the high-current condition situation persists, i.e.,
the power stage is being overloaded, a protection system triggers a latching shutdown, resulting in the power
stage being set in the high-impedance (Hi-Z) state. The device returns to normal operation once the fault
condition (i.e., a short circuit on the output) is removed. Current-limiting and overcurrent protection are not
independent for half-bridges. That is, if the bridge-tied load between half-bridges A and B causes an overcurrent
fault, half-bridges A, B, C, and D are shut down.
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Overtemperature Protection
The TAS5731 has an overtemperature-protection system. If the device junction temperature exceeds 150°C
(nominal), the device is put into thermal shutdown, resulting in all half-bridge outputs being set in the highimpedance (Hi-Z) state. The TAS5731 recovers automatically once the temperature drops approximately 30°C.
Undervoltage Protection (UVP) and Power-On Reset (POR)
The UVP and POR circuits of the TAS5731 fully protect the device in any power-up/down and brownout situation.
While powering up, the POR circuit resets the overload circuit (OLP) and ensures that all circuits are fully
operational when the PVDD and AVDD supply voltages reach 7.6 V and 2.7 V, respectively. Although PVDD and
AVDD are independently monitored, a supply-voltage drop below the UVP threshold on AVDD or either PVDD
pin results in all half-bridge outputs immediately being set in the high-impedance (Hi-Z) state.
SSTIMER FUNCTIONALITY
The SSTIMER pin uses a capacitor connected between this pin and ground to control the output duty cycle when
exiting all-channel shutdown. The capacitor on the SSTIMER pin is slowly charged through an internal current
source, and the charge time determines the rate at which the output transitions from a near-zero duty cycle to the
desired duty cycle. This allows for a smooth transition that minimizes audible pops and clicks. When the part is
shut down, the drivers are placed in the high-impedance state and transition slowly down through a 3-kΩ resistor,
similarly minimizing pops and clicks. The shutdown transition time is independent of the SSTIMER pin
capacitance. Larger capacitors increase the start-up time, while capacitors smaller than 2.2 nF decrease the
start-up time. The SSTIMER pin should be left floating for BD modulation.
CLOCK, AUTODETECTION, AND PLL
The TAS5731 is an I2S slave device. It accepts MCLK, SCLK, and LRCLK. The digital audio processor (DAP)
supports all the sample rates and MCLK rates that are defined in the clock control register .
The TAS5731 checks to verify that SCLK is a specific value of 32 fS, 48 fS, or 64 fS. The DAP only supports a 1 ×
fS LRCLK. The timing relationship of these clocks to SDIN is shown in subsequent sections. The clock section
uses MCLK or the internal oscillator clock (when MCLK is unstable, out of range, or absent) to produce the
internal clock (DCLK) running at 512 times the PWM switching frequency.
The DAP can autodetect and set the internal clock control logic to the appropriate settings for all supported clock
rates as defined in the clock-control register.
The TAS5731 has robust clock error handling that uses the built-in trimmed oscillator clock to quickly detect
changes/errors. Once the system detects a clock change/error, it mutes the audio (through a single-step mute)
and then forces PLL to limp using the internal oscillator as a reference clock. Once the clocks are stable, the
system autodetects the new rate and reverts to normal operation. During this process, the default volume is
restored in a single step (also called hard unmute). The ramp process can be programmed to ramp back slowly
(also called soft unmute) as defined in volume register (0x0E).
SERIAL DATA INTERFACE
Serial data is input on SDIN. The PWM outputs are derived from SDIN. The TAS5731 DAP accepts serial data in
16-, 20-, or 24-bit left-justified, right-justified, and I2S serial data formats.
PWM SECTION
The TAS5731 DAP device uses noise-shaping and customized nonlinear correction algorithms to achieve high
power efficiency and high-performance digital audio reproduction. The DAP uses a fourth-order noise shaper to
increase dynamic range and SNR in the audio band. The PWM section accepts 24-bit PCM data from the DAP
and outputs two BTL PWM audio output channels.
The PWM section has individual-channel dc-blocking filters that can be enabled and disabled. The filter cutoff
frequency is less than 1 Hz. Individual-channel de-emphasis filters for 44.1 kHz and 48 kHz are included and can
be enabled and disabled.
Finally, the PWM section has an adjustable maximum modulation limit of 93.8% to 99.2%.
For a detailed description of using audio processing features like DRC and EQ, see the User's Guide and
TAS570X GDE software development tool documentation.
18
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SERIAL INTERFACE CONTROL AND TIMING
I2S Timing
I2S timing uses LRCLK to define when the data being transmitted is for the left channel and when it is for the
right channel. LRCLK is low for the left channel and high for the right channel. A bit clock running at 32, 48, or
64 × fS is used to clock in the data. There is a delay of one bit clock from the time the LRCLK signal changes
state to the first bit of data on the data lines. The data is written MSB-first and is valid on the rising edge of bit
clock. The DAP masks unused trailing data bit positions.
2
2-Channel I S (Philips Format) Stereo Input
32 Clks
LRCLK (Note Reversed Phase)
32 Clks
Right Channel
Left Channel
SCLK
SCLK
MSB
24-Bit Mode
23 22
LSB
9
8
5
4
5
4
1
0
1
0
1
0
MSB
LSB
23 22
9
8
5
4
19 18
5
4
1
0
15 14
1
0
1
0
20-Bit Mode
19 18
16-Bit Mode
15 14
T0034-01
NOTE: All data presented in 2s-complement form with MSB first.
Figure 18. I2S 64-fS Format
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2
2-Channel I S (Philips Format) Stereo Input/Output (24-Bit Transfer Word Size)
LRCLK
24 Clks
24 Clks
Left Channel
Right Channel
SCLK
SCLK
MSB
24-Bit Mode
23 22
MSB
LSB
17 16
9
8
5
4
13 12
5
4
1
0
9
1
0
3
2
1
0
LSB
23 22
17 16
9
8
5
4
19 18
13 12
5
4
1
0
15 14
9
1
0
3
2
1
20-Bit Mode
19 18
16-Bit Mode
15 14
8
8
T0092-01
NOTE: All data presented in 2s-complement form with MSB first.
Figure 19. I2S 48-fS Format
2
2-Channel I S (Philips Format) Stereo Input
LRCLK
16 Clks
16 Clks
Left Channel
Right Channel
SCLK
SCLK
MSB
16-Bit Mode
15 14 13 12
MSB
LSB
11 10
9
8
5
4
3
2
1
0
LSB
15 14 13 12
11 10
9
8
5
4
3
2
1
T0266-01
NOTE: All data presented in 2s-complement form with MSB first.
Figure 20. I2S 32-fS Format
Left-Justified
Left-justified (LJ) timing uses LRCLK to define when the data being transmitted is for the left channel and when it
is for the right channel. LRCLK is high for the left channel and low for the right channel. A bit clock running at 32,
48, or 64 × fS is used to clock in the data. The first bit of data appears on the data lines at the same time LRCLK
toggles. The data is written MSB-first and is valid on the rising edge of the bit clock. The DAP masks unused
trailing data bit positions.
20
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2-Channel Left-Justified Stereo Input
32 Clks
32 Clks
Left Channel
Right Channel
LRCLK
SCLK
SCLK
MSB
24-Bit Mode
23 22
LSB
9
8
5
4
5
4
1
0
1
0
1
0
MSB
LSB
23 22
9
8
5
4
19 18
5
4
1
0
15 14
1
0
1
0
20-Bit Mode
19 18
16-Bit Mode
15 14
T0034-02
NOTE: All data presented in 2s-complement form with MSB first.
Figure 21. Left-Justified 64-fS Format
2-Channel Left-Justified Stereo Input (24-Bit Transfer Word Size)
24 Clks
24 Clks
Left Channel
Right Channel
LRCLK
SCLK
SCLK
MSB
24-Bit Mode
23 22
21
LSB
17 16
9
8
5
4
13 12
5
4
1
0
9
1
0
1
0
MSB
LSB
21
17 16
9
8
5
4
19 18 17
13 12
5
4
1
0
15 14 13
9
1
0
23 22
1
0
20-Bit Mode
19 18 17
16-Bit Mode
15 14 13
8
8
T0092-02
NOTE: All data presented in 2s-complement form with MSB first.
Figure 22. Left-Justified 48-fS Format
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2-Channel Left-Justified Stereo Input
16 Clks
16 Clks
Left Channel
Right Channel
LRCLK
SCLK
SCLK
MSB
16-Bit Mode
15 14 13 12
LSB
11 10
9
8
5
4
3
2
1
0
MSB
15 14 13 12
LSB
11 10
9
8
5
4
3
2
1
0
T0266-02
NOTE: All data presented in 2s-complement form with MSB first.
Figure 23. Left-Justified 32-fS Format
Right-Justified
Right-justified (RJ) timing uses LRCLK to define when the data being transmitted is for the left channel and when
it is for the right channel. LRCLK is high for the left channel and low for the right channel. A bit clock running at
32, 48, or 64 × fS is used to clock in the data. The first bit of data appears on the data 8 bit-clock periods (for 24bit data) after LRCLK toggles. In RJ mode, the LSB of data is always clocked by the last bit clock before LRCLK
transitions. The data is written MSB-first and is valid on the rising edge of bit clock. The DAP masks unused
leading data bit positions.
2-Channel Right-Justified (Sony Format) Stereo Input
32 Clks
32 Clks
Left Channel
Right Channel
LRCLK
SCLK
SCLK
MSB
24-Bit Mode
LSB
23 22
19 18
15 14
1
0
19 18
15 14
1
0
15 14
1
0
MSB
LSB
23 22
19 18
15 14
1
0
19 18
15 14
1
0
15 14
1
0
20-Bit Mode
16-Bit Mode
T0034-03
Figure 24. Right-Justified 64-fS Format
22
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2-Channel Right-Justified Stereo Input (24-Bit Transfer Word Size)
24 Clks
24 Clks
Left Channel
Right Channel
LRCLK
SCLK
SCLK
MSB
24-Bit Mode
23 22
LSB
19 18
15 14
6
5
2
1
0
19 18
15 14
6
5
2
1
0
15 14
6
5
2
1
0
LSB
MSB
23 22
19 18
15 14
6
5
2
1
0
19 18
15 14
6
5
2
1
0
15 14
6
5
2
1
0
20-Bit Mode
16-Bit Mode
T0092-03
Figure 25. Right-Justified 48-fS Format
Figure 26. Right-Justified 32-fS Format
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I2C SERIAL CONTROL INTERFACE
The TAS5731 DAP has a bidirectional I2C interface that is compatible with the Inter IC (I2C) bus protocol and
supports both 100-kHz and 400-kHz data transfer rates for single- and multiple-byte write and read operations.
This is a slave-only device that does not support a multimaster bus environment or wait-state insertion. The
control interface is used to program the registers of the device and to read device status.
The DAP supports the standard-mode I2C bus operation (100 kHz maximum) and the fast I2C bus operation
(400 kHz maximum). The DAP performs all I2C operations without I2C wait cycles.
General I2C Operation
The I2C bus employs two signals, SDA (data) and SCL (clock), to communicate between integrated circuits in a
system. Data is transferred on the bus serially, one bit at a time. The address and data can be transferred in byte
(8-bit) format, with the most-significant bit (MSB) transferred first. In addition, each byte transferred on the bus is
acknowledged by the receiving device with an acknowledge bit. Each transfer operation begins with the master
device driving a start condition on the bus and ends with the master device driving a stop condition on the bus.
The bus uses transitions on the data pin (SDA) while the clock is high to indicate start and stop conditions. A
high-to-low transition on SDA indicates a start and a low-to-high transition indicates a stop. Normal data-bit
transitions must occur within the low time of the clock period. These conditions are shown in Figure 27. The
master generates the 7-bit slave address and the read/write (R/W) bit to open communication with another
device and then waits for an acknowledge condition. The TAS5731 holds SDA low during the acknowledge clock
period to indicate an acknowledgment. When this occurs, the master transmits the next byte of the sequence.
Each device is addressed by a unique 7-bit slave address plus R/W bit (1 byte). All compatible devices share the
same signals via a bidirectional bus using a wired-AND connection. An external pullup resistor must be used for
the SDA and SCL signals to set the high level for the bus.
SDA
R/
A
W
7-Bit Slave Address
7
6
5
4
3
2
1
0
8-Bit Register Address (N)
7
6
5
4
3
2
1
0
8-Bit Register Data For
Address (N)
A
7
6
5
4
3
2
1
8-Bit Register Data For
Address (N)
A
0
7
6
5
4
3
2
1
A
0
SCL
Start
Stop
T0035-01
Figure 27. Typical I2C Sequence
There is no limit on the number of bytes that can be transmitted between start and stop conditions. When the last
word transfers, the master generates a stop condition to release the bus. A generic data transfer sequence is
shown in Figure 27.
The 7-bit address for TAS5731 is 0011 011 (0x36).
Single- and Multiple-Byte Transfers
The serial control interface supports both single-byte and multiple-byte read/write operations for subaddresses
0x00 to 0x1F. However, for the subaddresses 0x20 to 0xFF, the serial control interface supports only multiplebyte read/write operations (in multiples of 4 bytes).
During multiple-byte read operations, the DAP responds with data, a byte at a time, starting at the subaddress
assigned, as long as the master device continues to respond with acknowledges. If a particular subaddress does
not contain 32 bits, the unused bits are read as logic 0.
During multiple-byte write operations, the DAP compares the number of bytes transmitted to the number of bytes
that are required for each specific subaddress. For example, if a write command is received for a biquad
subaddress, the DAP must receive five 32-bit words. If fewer than five 32-bit data words have been received
when a stop command (or another start command) is received, the received data is discarded.
24
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Supplying a subaddress for each subaddress transaction is referred to as random I2C addressing. The TAS5731
also supports sequential I2C addressing. For write transactions, if a subaddress is issued followed by data for
that subaddress and the 15 subaddresses that follow, a sequential I2C write transaction has taken place, and the
data for all 16 subaddresses is successfully received by the TAS5731. For I2C sequential-write transactions, the
subaddress then serves as the start address, and the amount of data subsequently transmitted, before a stop or
start is transmitted, determines how many subaddresses are written. As was true for random addressing,
sequential addressing requires that a complete set of data be transmitted. If only a partial set of data is written to
the last subaddress, the data for the last subaddress is discarded. However, all other data written is accepted;
only the incomplete data is discarded.
Single-Byte Write
As shown in Figure 28, a single-byte data-write transfer begins with the master device transmitting a start
condition followed by the I2C device address and the read/write bit. The read/write bit determines the direction of
the data transfer. For a data-write transfer, the read/write bit is a 0. After receiving the correct I2C device address
and the read/write bit, the DAP responds with an acknowledge bit. Next, the master transmits the address byte or
bytes corresponding to the TAS5731 internal memory address being accessed. After receiving the address byte,
the TAS5731 again responds with an acknowledge bit. Next, the master device transmits the data byte to be
written to the memory address being accessed. After receiving the data byte, the TAS5731 again responds with
an acknowledge bit. Finally, the master device transmits a stop condition to complete the single-byte data-write
transfer.
Start
Condition
Acknowledge
A6
A5
A4
A3
A2
A1
A0
Acknowledge
R/W ACK A7
A6
A5
2
A4
A3
A2
A1
Acknowledge
A0 ACK D7
D6
Subaddress
I C Device Address and
Read/Write Bit
D5
D4
D3
D2
D1
D0 ACK
Stop
Condition
Data Byte
T0036-01
Figure 28. Single-Byte Write Transfer
Multiple-Byte Write
A multiple-byte data-write transfer is identical to a single-byte data-write transfer except that multiple data bytes
are transmitted by the master device to the DAP as shown in Figure 29. After receiving each data byte, the
TAS5731 responds with an acknowledge bit.
Start
Condition
Acknowledge
A6
A5
A1
A0 R/W ACK A7
A6
A5
2
A4
A3
Subaddress
I C Device Address and
Read/Write Bit
A1
Acknowledge
Acknowledge
Acknowledge
Acknowledge
A0 ACK D7
D0 ACK D7
D0 ACK D7
D0 ACK
First Data Byte
Other Data Bytes
Last Data Byte
Stop
Condition
T0036-02
Figure 29. Multiple-Byte Write Transfer
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Single-Byte Read
As shown in Figure 30, a single-byte data-read transfer begins with the master device transmitting a start
condition, followed by the I2C device address and the read/write bit. For the data read transfer, both a write
followed by a read are actually done. Initially, a write is done to transfer the address byte or bytes of the internal
memory address to be read. As a result, the read/write bit becomes a 0. After receiving the TAS5731 address
and the read/write bit, TAS5731 responds with an acknowledge bit. In addition, after sending the internal memory
address byte or bytes, the master device transmits another start condition followed by the TAS5731 address and
the read/write bit again. This time, the read/write bit becomes a 1, indicating a read transfer. After receiving the
address and the read/write bit, the TAS5731 again responds with an acknowledge bit. Next, the TAS5731
transmits the data byte from the memory address being read. After receiving the data byte, the master device
transmits a not-acknowledge followed by a stop condition to complete the single-byte data-read transfer.
Repeat Start
Condition
Start
Condition
Acknowledge
A6
A5
A1
A0 R/W ACK A7
Acknowledge
A6
2
A5
A4
A0 ACK
A6
A5
A1
A0 R/W ACK D7
D6
2
I C Device Address and
Read/Write Bit
Subaddress
I C Device Address and
Read/Write Bit
Not
Acknowledge
Acknowledge
D1
D0 ACK
Stop
Condition
Data Byte
T0036-03
Figure 30. Single-Byte Read Transfer
Multiple-Byte Read
A multiple-byte data-read transfer is identical to a single-byte data-read transfer except that multiple data bytes
are transmitted by the TAS5731 to the master device as shown in Figure 31. Except for the last data byte, the
master device responds with an acknowledge bit after receiving each data byte.
Repeat Start
Condition
Start
Condition
Acknowledge
A6
2
A0 R/W ACK A7
I C Device Address and
Read/Write Bit
Acknowledge
A6
A6
A0 ACK
A5
Subaddress
2
Acknowledge
Acknowledge
Acknowledge
Not
Acknowledge
A0 R/W ACK D7
D0 ACK D7
D0 ACK D7
D0 ACK
I C Device Address and
Read/Write Bit
First Data Byte
Other Data Bytes
Last Data Byte
Stop
Condition
T0036-04
Figure 31. Multiple-Byte Read Transfer
26
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Dynamic Range Control (DRC)
The DRC scheme has two DRC blocks. There is one ganged DRC for the high-band left/right channels and one
DRC for the low-band left/right channels.
Output Level (dB)
The DRC input/output diagram is shown in Figure 32.
1:1 Transfer Function
Implemented Transfer Function
T
Input Level (dB)
M0091-04
Professional-quality dynamic range compression automatically adjusts volume to flatten volume level.
• Each DRC has adjustable threshold levels.
• Programmable attack and decay time constants
• Transparent compression: compressors can attack fast enough to avoid apparent clipping before engaging,
and decay times can be set slow enough to avoid pumping.
Figure 32. Dynamic Range Control
a, w
T
aa, wa / ad, wd
DRC1
0x3C
0x3B
0x40
DRC2
0x3F
0x3E
0x43
Alpha Filter Structure
S
a
w
–1
Z
B0265-04
T = 9.23 format, all other DRC coefficients are 3.23 format
Figure 33. DRC Structure
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PWM LEVEL METER
26-Bit 3.23 Number Format
All mixer gain coefficients are 26-bit coefficients using a 3.23 number format. Numbers formatted as 3.23
numbers means that there are 3 bits to the left of the binary point and 23 bits to the right of the binary point. This
is shown in Figure 34 .
2
–23
2
2
–5
–1
Bit
Bit
Bit
0
2 Bit
1
2 Bit
Sign Bit
S_xx.xxxx_xxxx_xxxx_xxxx_xxxx_xxx
M0125-01
Figure 34. 3.23 Format
The decimal value of a 3.23 format number can be found by following the weighting shown in Figure 34. If the
most significant bit is logic 0, the number is a positive number, and the weighting shown yields the correct
number. If the most significant bit is a logic 1, then the number is a negative number. In this case every bit must
be inverted, a 1 added to the result, and then the weighting shown in Figure 35 applied to obtain the magnitude
of the negative number.
1
0
2 Bit
2 Bit
1
2
0
–1
Bit
(1 or 0) ´ 2 + (1 or 0) ´ 2 + (1 or 0) ´ 2
2
–1
–4
Bit
+ ....... (1 or 0) ´ 2
2
–4
–23
Bit
+ ....... (1 or 0) ´ 2
–23
M0126-01
Figure 35. Conversion Weighting Factors—3.23 Format to Floating Point
Gain coefficients, entered via the I2C bus, must be entered as 32-bit binary numbers. The format of the 32-bit
number (4-byte or 8-digit hexadecimal number) is shown in Figure 36.
28
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Fraction
Digit 6
Sign
Bit
Integer
Digit 1
Fraction
Digit 1
Fraction
Digit 2
Fraction
Digit 3
Fraction
Digit 4
Fraction
Digit 5
u u u u
u u S x
x. x x x
x x x x
x x x x
x x x x
x x x x
x x x x 0
Coefficient
Digit 8
Coefficient
Digit 7
Coefficient
Digit 6
Coefficient
Digit 5
Coefficient
Digit 4
Coefficient
Digit 3
Coefficient
Digit 2
Coefficient
Digit 1
u = unused or don’t care bits
Digit = hexadecimal digit
M0127-01
2
Figure 36. Alignment of 3.23 Coefficient in 32-Bit I C Word
Table 1. Sample Calculation for 3.23 Format
db
Linear
Decimal
0
1
8,388,608
Hex (3.23 Format)
80 0000
5
1.77
14,917,288
00E3 9EA8
–5
0.56
4,717,260
0047 FACC
X
L = 10(X/20)
D = 8,388,608 × L
H = dec2hex (D, 8)
Table 2. Sample Calculation for 9.17 Format
db
Linear
Decimal
Hex (9.17 Format)
0
1
131,072
2 0000
5
1.77
231,997
3 8A3D
–5
0.56
73,400
1 1EB8
X
L = 10(X/20)
D = 131,072 × L
H = dec2hex (D, 8)
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29
30
2
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PVDD
RESET
SCL
SDA
0 ns
0 ns
100 ms
100 μs
3V
10 ms
8V
6V
13.5 ms
Trim
50 ms
DAP
Config
Other
Config
(1) tPLL has to be greater than 240 ms + 1.3 tstart.
This constraint only applies to the first trim command following AVDD/DVDD power-up.
It does not apply to trim commands following subsequent resets.
(2) tstart/tstop = PWM start/stop time as defined in register 0X1A
I C
PDN
AVDD/DVDD
Initialization
Exit
SD
(1)
tPLL
1 ms + 1.3 tstart
(2)
Volume and Mute Commands
Normal Operation
Enter
SD
(2)
1 ms + 1.3 tstop
Shutdown
2 ms
2 ms
2 ms
8V
6V
0 ns
Powerdown
T0419-06
3V
TAS5731
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Recommended Use Model
Figure 37. Recommended Command Sequence
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TAS5731
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SLOS726A – DECEMBER 2011 – REVISED SEPTEMBER 2013
3V
AVDD/DVDD
0 ns
2 ms
PDN
0 ns
2
I C
2 ms
RESET
2 ms
0 ns
8V
PVDD
6V
T0420-05
Figure 38. Power-Loss Sequence
Initialization Sequence
Use the following sequence to power up and initialize the device:
1.
Hold all digital inputs low and ramp up AVDD/DVDD to at least 3 V.
2.
Initialize digital inputs and PVDD supply as follows:
•
Drive RESET = 0, PDN = 1, and other digital inputs to their desired state while ensuring that
all are never more than 2.5 V above AVDD/DVDD. Wait at least 100 µs, drive RESET = 1,
and wait at least another 13.5 ms.
•
Ramp up PVDD to at least 8 V while ensuring that it remains below 6 V for at least 100 µs
after AVDD/DVDD reaches 3 V. Then wait at least another 10 µs.
3.
Trim oscillator (write 0x00 to register 0x1B) and wait at least 50 ms.
4.
Configure the DAP via I2C (see User's Guide for typical values).
5.
Configure remaining registers.
6.
Exit shutdown (sequence defined below).
Normal Operation
The following are the only events supported during normal operation:
1.
Writes to master/channel volume registers
2.
Writes to soft-mute register
3.
Enter and exit shutdown (sequence defined below)
Note: Event 3 is not supported for 240 ms + 1.3 × tstart after trim following AVDD/DVDD power-up ramp
(where tstart is specified by register 0x1A).
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Shutdown Sequence
Enter:
1.
Write 0x40 to register 0x05.
2.
Wait at least 1 ms + 1.3 × tstop (where tstop is specified by register 0x1A).
3.
If desired, reconfigure by returning to step 4 of initialization sequence.
1.
Write 0x00 to register 0x05 (exit shutdown command may not be serviced for as much as 240 ms
after trim following AVDD/DVDD power-up ramp).
2.
Wait at least 1 ms + 1.3 × tstart (where tstart is specified by register 0x1A).
3.
Proceed with normal operation.
Exit:
Power-Down Sequence
Use the following sequence to power down the device and its supplies:
1.
If time permits, enter shutdown (sequence defined above); else, in case of sudden power loss,
assert PDN = 0 and wait at least 2 ms.
2.
Assert RESET = 0.
3.
Drive digital inputs low and ramp down PVDD supply as follows:
4.
32
•
Drive all digital inputs low after RESET has been low for at least 2 µs.
•
Ramp down PVDD while ensuring that it remains above 8 V until RESET has been low for at
least 2 µs.
Ramp down AVDD/DVDD while ensuring that it remains above 3 V until PVDD is below 6 V and
that it is never more than 2.5 V below the digital inputs.
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Table 3. Serial Control Interface Register Summary
SUBADDRESS
REGISTER NAME
NO. OF
BYTES
INITIALIZATION
VALUE
CONTENTS
A u indicates unused bits.
0x00
Clock control register
1
Description shown in subsequent section
0x6C
0x01
Device ID register
1
Description shown in subsequent section
0x00
0x02
Error status register
1
Description shown in subsequent section
0x00
0x03
System control register 1
1
Description shown in subsequent section
0xA0
0x04
Serial data interface
register
1
Description shown in subsequent section
0x05
0x05
System control register 2
1
Description shown in subsequent section
0x40
0x06
Soft mute register
1
Description shown in subsequent section
0x00
0x07
Master volume
1
Description shown in subsequent section
0xFF (mute)
0x08
Channel 1 vol
1
Description shown in subsequent section
0x30 (0 dB)
0x09
Channel 2 vol
1
Description shown in subsequent section
0x30 (0 dB)
0x0A
Channel 3 vol
1
Description shown in subsequent section
0x30 (0 dB)
1
Reserved (1)
1
Description shown in subsequent section
1
Reserved (1)
0x0B–0x0D
0x0E
Volume configuration
register
0x0F
0x10
Modulation limit register
1
Description shown in subsequent section
0x02
0x11
IC delay channel 1
1
Description shown in subsequent section
0xAC
0x12
IC delay channel 2
1
Description shown in subsequent section
0x54
0x13
IC delay channel 3
1
Description shown in subsequent section
0xAC
0x14
IC delay channel 4
1
Description shown in subsequent section
0x54
1
Reserved (1)
Description shown in subsequent section
0x15-0x18
0x19
PWM channel shutdown
group register
1
0x1A
Start/stop period register
1
0x0F
0x1B
Oscillator trim register
1
0x82
0x1C
BKND_ERR register
1
0x1D–0x1F
0x30
0x02
(1)
1
Reserved
0x20
Input MUX register
4
Description shown in subsequent section
0x0001 7772
0x21
Ch 4 source select register
4
Description shown in subsequent section
0x0000 4303
0x22 -0x24
0x25
PWM MUX register
0x26-0x28
0x29
0x2A
(1)
0x91
ch1_bq[0]
ch1_bq[1]
(1)
4
Reserved
4
Description shown in subsequent section
4
Reserved (1)
20
u[31:26], b0[25:0]
0x0080 0000
u[31:26], b1[25:0]
0x0000 0000
u[31:26], b2[25:0]
0x0000 0000
u[31:26], a1[25:0]
0x0000 0000
u[31:26], a2[25:0]
0x0000 0000
u[31:26], b0[25:0]
0x0080 0000
u[31:26], b1[25:0]
0x0000 0000
u[31:26], b2[25:0]
0x0000 0000
u[31:26], a1[25:0]
0x0000 0000
u[31:26], a2[25:0]
0x0000 0000
20
0x0102 1345
Reserved registers should not be accessed.
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Table 3. Serial Control Interface Register Summary (continued)
SUBADDRESS
0x2B
0x2C
0x2D
0x2E
0x2F
0x30
0x31
0x32
0x33
34
REGISTER NAME
ch1_bq[2]
ch1_bq[3]
ch1_bq[4]
ch1_bq[5]
ch1_bq[6]
ch2_bq[0]
ch2_bq[1]
ch2_bq[2]
ch2_bq[3]
NO. OF
BYTES
20
20
20
20
20
20
20
20
20
CONTENTS
INITIALIZATION
VALUE
u[31:26], b0[25:0]
0x0080 0000
u[31:26], b1[25:0]
0x0000 0000
u[31:26], b2[25:0]
0x0000 0000
u[31:26], a1[25:0]
0x0000 0000
u[31:26], a2[25:0]
0x0000 0000
u[31:26], b0[25:0]
0x0080 0000
u[31:26], b1[25:0]
0x0000 0000
u[31:26], b2[25:0]
0x0000 0000
u[31:26], a1[25:0]
0x0000 0000
u[31:26], a2[25:0]
0x0000 0000
u[31:26], b0[25:0]
0x0080 0000
u[31:26], b1[25:0]
0x0000 0000
u[31:26], b2[25:0]
0x0000 0000
u[31:26], a1[25:0]
0x0000 0000
u[31:26], a2[25:0]
0x0000 0000
u[31:26], b0[25:0]
0x0080 0000
u[31:26], b1[25:0]
0x0000 0000
u[31:26], b2[25:0]
0x0000 0000
u[31:26], a1[25:0]
0x0000 0000
u[31:26], a2[25:0]
0x0000 0000
u[31:26], b0[25:0]
0x0080 0000
u[31:26], b1[25:0]
0x0000 0000
u[31:26], b2[25:0]
0x0000 0000
u[31:26], a1[25:0]
0x0000 0000
u[31:26], a2[25:0]
0x0000 0000
u[31:26], b0[25:0]
0x0080 0000
u[31:26], b1[25:0]
0x0000 0000
u[31:26], b2[25:0]
0x0000 0000
u[31:26], a1[25:0]
0x0000 0000
u[31:26], a2[25:0]
0x0000 0000
u[31:26], b0[25:0]
0x0080 0000
u[31:26], b1[25:0]
0x0000 0000
u[31:26], b2[25:0]
0x0000 0000
u[31:26], a1[25:0]
0x0000 0000
u[31:26], a2[25:0]
0x0000 0000
u[31:26], b0[25:0]
0x0080 0000
u[31:26], b1[25:0]
0x0000 0000
u[31:26], b2[25:0]
0x0000 0000
u[31:26], a1[25:0]
0x0000 0000
u[31:26], a2[25:0]
0x0000 0000
u[31:26], b0[25:0]
0x0080 0000
u[31:26], b1[25:0]
0x0000 0000
u[31:26], b2[25:0]
0x0000 0000
u[31:26], a1[25:0]
0x0000 0000
u[31:26], a2[25:0]
0x0000 0000
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Table 3. Serial Control Interface Register Summary (continued)
SUBADDRESS
0x34
0x35
0x36
REGISTER NAME
ch2_bq[4]
ch2_bq[5]
ch2_bq[6]
0x37 - 0x39
0x3A
DRC1 ae (3)
NO. OF
BYTES
20
20
20
DRC1 aa
DRC1 ad
DRC2 ae
DRC2 aa
DRC2 ad
0x0000 0000
u[31:26], a2[25:0]
0x0000 0000
u[31:26], b0[25:0]
0x0080 0000
u[31:26], b1[25:0]
0x0000 0000
u[31:26], b2[25:0]
0x0000 0000
u[31:26], a1[25:0]
0x0000 0000
u[31:26], a2[25:0]
0x0000 0000
u[31:26], b0[25:0]
0x0080 0000
u[31:26], b1[25:0]
0x0000 0000
u[31:26], b2[25:0]
0x0000 0000
u[31:26], a1[25:0]
0x0000 0000
u[31:26], a2[25:0]
0x0000 0000
0x0080 0000
0x0000 0000
u[31:26], aa[25:0]
0x0080 0000
u[31:26], (1 – aa)[25:0]
0x0000 0000
u[31:26], ad[25:0]
0x0080 0000
u[31:26], (1 – ad)[25:0]
0x0000 0000
u[31:26], ae[25:0]
0x0080 0000
u[31:26], (1 – ae)[25:0]
0x0000 0000
u[31:26], aa[25:0]
0x0080 0000
u[31:26], (1 – aa)[25:0]
0x0000 0000
u[31:26], ad[25:0]
0x0080 0000
8
8
8
8
8
DRC2 (1 – ad)
u[31:26], (1 – ad)[25:0]
0x0000 0000
0x40
DRC1-T
4
T1[31:0] (9.23 format)
0xFDA2 1490
0x41
DRC1-K
4
u[31:26], K1[25:0]
0x0384 2109
0x42
DRC1-O
4
u[31:26], O1[25:0]
0x0008 4210
0x43
DRC2-T
4
T2[31:0] (9.23 format)
0xFDA2 1490
0x44
DRC2-K
4
u[31:26], K2[25:0]
0x0384 2109
0x45
DRC2-O
4
u[31:26], O2[25:0]
0x0008 4210
0x46
DRC control
4
Description shown in subsequent section
0x0000 0000
4
Reserved (2)
0x47–0x4F
0x50
Bank switch control
4
Description shown in subsequent section
0x0F70 8000
0x51
Ch 1 output mixer
12
Ch 1 output mix1[2]
0x0080 0000
Ch 1 output mix1[1]
0x0000 0000
Ch 1 output mix1[0]
0x0000 0000
Ch 2 output mix2[2]
0x0080 0000
Ch 2 output mix2[1]
0x0000 0000
Ch 2 output mix2[0]
0x0000 0000
0x52
(2)
(3)
u[31:26], a1[25:0]
u[31:26], (1 – ae)[25:0]
DRC2 (1 – aa)
0x3F
0x0000 0000
u[31:26], ae[25:0]
DRC 2 (1 – ae)
0x3E
0x0000 0000
u[31:26], b2[25:0]
8
DRC1 (1 – ad)
0x3D
0x0080 0000
u[31:26], b1[25:0]
Reserved (2)
DRC1 (1 – aa)
0x3C
u[31:26], b0[25:0]
4
DRC1 (1 – ae)
0x3B
INITIALIZATION
VALUE
CONTENTS
Ch 2 output mixer
12
Reserved registers should not be accessed.
"ae" stands for ∝ of energy filter, "aa" stands for ∝ of attack filter and "ad" stands for ∝ of decay filter and 1- ∝ = ω.
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Table 3. Serial Control Interface Register Summary (continued)
SUBADDRESS
0x53
0x54
0x55
Ch 1 input mixer
Ch 2 input mixer
Channel 3 input mixer
NO. OF
BYTES
16
16
12
CONTENTS
INITIALIZATION
VALUE
Ch 1 input mixer[3]
0x0080 0000
Ch 1 input mixer[2]
0x0000 0000
Ch 1 input mixer[1]
0x0000 0000
Ch 1 input mixer[0]
0x0080 0000
Ch 2 input mixer[3]
0x0080 0000
Ch 2 input mixer[2]
0x0000 0000
Ch 2 input mixer[1]
0x0000 0000
Ch 2 input mixer[0]
0x0080 0000
Channel 3 input mixer [2]
0x0080 0000
Channel 3 input mixer [1]
0x0000 0000
Channel 3 input mixer [0]
0x0000 0000
0x56
Output post-scale
4
u[31:26], post[25:0]
0x0080 0000
0x57
Output pre-scale
4
u[31:26], pre[25:0] (9.17 format)
0x0002 0000
0x58
ch1 BQ[7]
20
u[31:26], b0[25:0]
0x0080 0000
u[31:26], b1[25:0]
0x0000 0000
u[31:26], b2[25:0]
0x0000 0000
u[31:26], a1[25:0]
0x0000 0000
u[31:26], a2[25:0]
0x0000 0000
u[31:26], b0[25:0]
0x0080 0000
u[31:26], b1[25:0]
0x0000 0000
u[31:26], b2[25:0]
0x0000 0000
u[31:26], a1[25:0]
0x0000 0000
u[31:26], a2[25:0]
0x0000 0000
u[31:26], b0[25:0]
0x0080 0000
u[31:26], b1[25:0]
0x0000 0000
u[31:26], b2[25:0]
0x0000 0000
u[31:26], a1[25:0]
0x0000 0000
u[31:26], a2[25:0]
0x0000 0000
u[31:26], b0[25:0]
0x0080 0000
u[31:26], b1[25:0]
0x0000 0000
u[31:26], b2[25:0]
0x0000 0000
u[31:26], a1[25:0]
0x0000 0000
u[31:26], a2[25:0]
0x0000 0000
u[31:26], b0[25:0]
0x0080 0000
u[31:26], b1[25:0]
0x0000 0000
u[31:26], b2[25:0]
0x0000 0000
u[31:26], a1[25:0]
0x0000 0000
u[31:26], a2[25:0]
0x0000 0000
u[31:26], b0[25:0]
0x0080 0000
u[31:26], b1[25:0]
0x0000 0000
u[31:26], b2[25:0]
0x0000 0000
u[31:26], a1[25:0]
0x0000 0000
u[31:26], a2[25:0]
0x0000 0000
0x59
0x5A
0x5B
0x5C
0x5D
36
REGISTER NAME
ch1 BQ[8]
Subchannel BQ[0]
Subchannel BQ[1]
ch2 BQ[7]
ch2 BQ[8]
20
20
20
20
20
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SLOS726A – DECEMBER 2011 – REVISED SEPTEMBER 2013
Table 3. Serial Control Interface Register Summary (continued)
SUBADDRESS
0x5E
REGISTER NAME
pseudo_ch2 BQ[0]
0x61
0x62
20
u[31:26], b0[25:0]
0x0080 0000
u[31:26], b1[25:0]
0x0000 0000
u[31:26], b2[25:0]
0x0000 0000
u[31:26], a1[25:0]
0x0000 0000
u[31:26], a2[25:0]
0x0000 0000
Reserved (4)
Channel 4 (subchannel)
output mixer
8
Ch 4 output mixer[1]
0x0000 0000
Ch 4 output mixer[0]
0x0080 0000
Channel 4 (subchannel)
input mixer
8
Ch 4 input mixer[1]
0x0040 0000
Ch 4 input mixer[0]
0x0040 0000
IDF post scale
4
Post-IDF attenuation register
0x0000 0080
Reserved (4)
0x0000 0000
0x63–0xF7
0xF8
Device address enable
register
4
Write F9 A5 A5 A5 in this register to enable write to
device address update (0xF9)
0x0000 0000
0xF9
Device address Update
Register
4
u[31:8], New Dev Id[7:1] , ZERO[0] (New Dev Id
(7:1) defines the new device address
0X0000 0036
4
Reserved (4)
0x0000 0000
0xFA–0xFF
(4)
INITIALIZATION
VALUE
CONTENTS
4
0x5F
0x60
NO. OF
BYTES
Reserved registers should not be accessed.
All DAP coefficients are 3.23 format unless specified otherwise.
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CLOCK CONTROL REGISTER (0x00)
The clocks and data rates are automatically determined by the TAS5731. The clock control register contains the
auto-detected clock status. Bits D7–D5 reflect the sample rate. Bits D4–D2 reflect the MCLK frequency. The
device accepts a 64 fS or 32 fS SCLK rate for all MCLK ratios, but accepts a 48 fS SCLK rate for MCLK ratios of
192 fS and 384 fS only.
Table 4. Clock Control Register (0x00)
D7
D6
D5
D4
D3
D2
D1
D0
0
0
0
–
–
–
–
–
fS = 32-kHz sample rate
0
0
1
–
–
–
–
–
Reserved (1)
0
1
0
–
–
–
–
–
Reserved (1)
0
1
1
–
–
–
–
–
fS = 44.1/48-kHz sample rate
1
0
0
–
–
–
–
–
fS = 16-kHz sample rate
1
0
1
–
–
–
–
–
fS = 22.05/24 -kHz sample rate
1
1
0
–
–
–
–
–
fS = 8-kHz sample rate
1
1
1
–
–
–
–
–
fS = 11.025/12 -kHz sample rate
–
–
–
0
0
0
–
–
MCLK frequency = 64 × fS
–
–
–
0
0
1
–
–
MCLK frequency = 128 × fS
(3)
–
–
–
0
1
0
–
–
MCLK frequency = 192 × fS
(4)
–
–
–
0
1
1
–
–
MCLK frequency = 256 × fS
–
–
–
1
0
0
–
–
MCLK frequency = 384 × fS
–
–
–
1
0
1
–
–
MCLK frequency = 512 × fS
–
–
–
1
1
0
–
–
Reserved (1)
–
–
–
1
1
1
–
–
Reserved (1)
–
–
–
–
–
–
0
–
Reserved (1)
(2)
–
–
–
–
–
–
–
0
Reserved (1)
(2)
(1)
(2)
(3)
(4)
(5)
FUNCTION
(2)
(3)
(2) (5)
Reserved registers should not be accessed.
Default values are in bold.
Only available for 44.1-kHz and 48-kHz rates
Rate only available for 32/44.1/48-KHz sample rates
Not available at 8 kHz
DEVICE ID REGISTER (0x01)
The device ID register contains the ID code for the firmware revision.
Table 5. General Status Register (0x01)
D7
D6
D5
D4
D3
D2
D1
D0
0
0
0
0
0
0
0
0
38
FUNCTION
Identification code
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SLOS726A – DECEMBER 2011 – REVISED SEPTEMBER 2013
ERROR STATUS REGISTER (0x02)
The error bits are sticky and are not cleared by the hardware. This means that the software must clear the
register (write zeroes) and then read them to determine if they are persistent errors.
Error Definitions:
• MCLK Error : MCLK frequency is changing. The number of MCLKs per LRCLK is changing.
• SCLK Error: The number of SCLKs per LRCLK is changing.
• LRCLK Error: LRCLK frequency is changing.
• Frame Slip: LRCLK phase is drifting with respect to internal Frame Sync.
Table 6. Error Status Register (0x02)
D7
D6
D5
D4
D3
D2
D1
D0
1
-
–
–
–
–
–
–
MCLK error
–
1
–
–
–
–
–
–
PLL autolock error
–
–
1
–
–
–
–
–
SCLK error
–
–
–
1
–
–
–
–
LRCLK error
–
–
–
–
1
–
–
–
Frame slip
–
–
–
–
–
1
–
–
Clip indicator
–
–
–
–
–
–
1
–
Overcurrent, overtemperature, or undervoltage errors
–
–
–
–
–
–
–
0
Reserved
0
0
0
0
0
0
0
–
No errors
(1)
FUNCTION
(1)
Default values are in bold.
SYSTEM CONTROL REGISTER 1 (0x03)
The system control register 1 has several functions:
Bit D7:
If 0, the dc-blocking filter for each channel is disabled.
If 1, the dc-blocking filter (–3 dB cutoff
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