THS6022
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SLOS225D – SEPTEMBER 1998 – REVISED JULY 2007
250-mA DUAL DIFFERENTIAL LINE DRIVER
FEATURES
•
•
•
•
•
•
•
•
ADSL, HDSL and VDSL Differential Line Driver
200-mA Output Current Minimum Into 50-Ω
Load
High Speed
– 210-MHz Bandwidth (–3-dB) at 50-Ω Load
– 300-MHz Bandwidth (–3-dB) at 100-Ω Load
– 1900-V/μs Slew Rate, G = 5
Low Distortion
– –69-dB Third-Order Harmonic Distortion at
f = 1 MHz, 50-Ω Load, and VO(PP) = 20 V
Independent Power Supplies for Low
Crosstalk
Wide Supply Range ±5 V to ±15 V
Thermal-Shutdown and Short-Circuit
Protection
Evaluation Module Available
Thermally Enchanced TSSOP (PWP)
PowerPAD™ Package
(Top View)
VCC–
1OUT
VCC+
1IN+
1IN–
NC
NC
1
2
14
13
3
4
5
6
12
11
10
9
7
8
VCC–
2OUT
VCC+
2IN+
2IN–
NC
NC
NC – No internal connection
(Side View)
Cross Section View Showing Thermal Pad
DESCRIPTION
MicroStar™ Junior (GQE) Package
(Top View)
The THS6022 contains two high-speed drivers
capable of providing 200-mA output current
(minimum) into a 50-Ω load. These drivers can be
configured differentially to drive a 50-V p-p output
signal over low-impedance lines. The drivers are
current feedback amplifiers, designed for the high
slew rates necessary to support low total harmonic
distortion (THD) in xDSL applications. The THS6022
is ideally suited for asymmetrical digital subscriber
line (ADSL) at the remote terminal, high-data-rate
digital
subscriber
line
(HDSL),
and
very
high-data-rate digital subscribe line (VDSL), where it
supports the high-peak voltage and current
requirements of these applications. Separate power
supply connections for each driver are provided to
minimize crosstalk.
(Side View)
P0067-01
HIGH-SPEED xDSL LINE DRIVER/RECEIVER FAMILY
DEVICE
DRIVER
RECEIVER
THS6002
√
√
THS6012
√
500-mA dual differential line driver
THS6022
√
250-mA dual differential line driver
THS6032
√
THS6062
DESCRIPTION
Dual differential line drivers and receivers
Low-power ADSL central office line driver
√
Low-noise ADSL receiver
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PowerPAD, MicroStar Junior are trademarks of Texas Instruments.
All other trademarks are the property of their respective owners.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 1998–2007, Texas Instruments Incorporated
THS6022
www.ti.com
SLOS225D – SEPTEMBER 1998 – REVISED JULY 2007
HIGH-SPEED xDSL LINE DRIVER/RECEIVER FAMILY (continued)
DEVICE
THS7002
2
DRIVER
RECEIVER
√
DESCRIPTION
Low-noise programmable gain ADSL receiver
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THS6022
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SLOS225D – SEPTEMBER 1998 – REVISED JULY 2007
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
DESCRIPTION (CONTINUED)
The THS6022 is packaged in the patented PowerPAD™ package. This package provides outstanding thermal
characteristics in a small-footprint package that is fully compatible with automated surface-mount assembly
procedures. The exposed thermal pad on the underside of the package is in direct contact with the die. By
simply soldering the pad to the PWB copper and using other thermal outlets, the heat is conducted away from
the junction.
AVAILABLE OPTIONS
PACKAGED DEVICE
(1)
TA
PowerPAD™ PLASTIC
SMALL OUTLINE (1) (PWP)
MicroStar Junior™
(GQE)
EVALUATION MODULE
0°C to 70°C
THS6022CPWP
THS6022CGQE
THS6022EVM
–40°C to 85°C
THS6022IPWP
THS6022IGQE
–
The PWP packages are available taped and reeled. Add an R suffix to the device type (e.g.,
THS6022CPWPR)
TERMINAL FUNCTIONS
TERMINAL
NAME
PWP PACKAGE
TERMINAL NO.
GQE PACKAGE
TERMINAL NO.
1OUT
2
A3
1IN–
5
F1
1IN+
4
D1
2OUT
13
A7
2IN–
10
F9
2IN+
11
D9
VCC+
3, 12
B1, B9
VCC–
1, 14
A4, A6
NC
6, 7, 8, 9
NA
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THS6022
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SLOS225D – SEPTEMBER 1998 – REVISED JULY 2007
A
VCC+
1
2
NC
NC
NC
B
C
NC
D
3
2OUT
VCC–
VCC–
1OUT
MicroStar™Junior (GQE) Package
(Top View)
5
4
7
6
NC
NC
NC
8
9
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
VCC+
NC
2IN+
1N+
E
NC
F
NC
2IN–
1IN–
G
NC
NC
NC
NC
NC
NC
NC
NC
NC
H
NC
NC
NC
NC
NC
NC
NC
NC
NC
J
NC
NC
NC
NC
NC
NC
NC
NC
NC
P0068-01
NOTE: Shaded terminals are used for thermal connection to the ground plane.
Functional Block Diagram
Driver 1
3
1 IN+
4
+
2
1 IN–
5
Driver 2
2 IN+
2 IN–
10
1OUT
_
1
11
VCC+
+
12
13
VCC–
VCC+
2 OUT
_
14
VCC–
B0247-01
4
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THS6022
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SLOS225D – SEPTEMBER 1998 – REVISED JULY 2007
ABSOLUTE MAXIMUM RATINGS
(1)
over operating free-air temperature range (unless otherwise noted)
VCC+ to VCC–
Supply voltage
VI
Input voltage
IO
Output current
VID
Differential input voltage
Continuous total power dissipation at (or below) TA = 25°C
VALUE
UNIT
33
V
±VCC
V
400
mA
6
V
3.3
W
TA
Operating free air temperature
–40 to 85
°C
Tstg
Storage temperature
–65 to 125
°C
300
°C
Lead temperature, 1,6 mm (1/16 inch) from case for 10 seconds
(1)
Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating
conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
RECOMMENDED OPERATING CONDITIONS
over operating free-air temperature range (unless otherwise noted)
MIN
VCC+ and VCC–
Supply voltage
TA
Operating free-air temperature
Split supply
Single supply
C suffix
I suffix
NOM
MAX
±4.5
±16
9
32
0
70
–40
85
UNIT
V
°C
ELECTRICAL CHARACTERISTICS
VCC = ±15 V, RL = 50 Ω, RF = 1 kΩ, TA = 25°C (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Dynamic Performance
VO = 200 mV, G = 1
VO = 200 mV, G = 2
Small-signal bandwidth (–3
dB)
VO = 100 mV, G = 1
BW
VO = 100 mV, G = 2
RL = 50 Ω, G = 2
Bandwidth for 0.1-dB
flatness
(1)
SR
Slew rate
tS
Settling time to 0.1%
Full-power bandwidth
(1)
(2)
RL = 100 Ω, G = 2
(2)
VCC = ±15 V
RF = 787 Ω
210
VCC = ±5 V
RF = 910 Ω
150
VCC = ±15 V
RF = 787 Ω
590
VCC = ±5 V
RF = 910 Ω
715
VCC = ±15 V
RF = 750 Ω
300
VCC = ±5 V
RF = 910 Ω
210
VCC = ±15 V
RF = 620 Ω
260
VCC = ±5 V
RF = 680 Ω
180
VCC = ±15 V
RF = 590 Ω
115
VCC = ±5 V
RF = 715 Ω
70
VCC = ±15 V
RF = 620 Ω
140
VCC = ±5 V
RF = 680 Ω
VCC = ±15 V,
VO(PP) = 20 V,
G=5
1900
VCC = ±5 V,
VO(PP) = 5 V,
G=2
950
0-V to 10-V step,
G = 2,
RL = 1 kΩ
VCC = ±15 V,
VO = 20 V(PP)
30
VCC = ±5 V,
VO = 4 V(PP)
75
MHz
80
70
V/μs
ns
MHz
Slew rate is measured from an output level range of 25% to 75%.
Full power bandwidth = slew rate/2πVpeak
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SLOS225D – SEPTEMBER 1998 – REVISED JULY 2007
ELECTRICAL CHARACTERISTICS (continued)
VCC = ±15 V, RL = 50 Ω, RF = 1 kΩ, TA = 25°C (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Noise/Distortion Performance
f = 500 kHz
VCC = ±5 V, G = 2
f = 1 MHz
THD
Total harmonic distortion
VCC = ±5 V, VO(PP) = 2
V, G = 2
Input noise current,
positive (IN+)
In
Input noise current,
negative (IN–)
AD
Differential gain error
φD
Vn
RL = 50 Ω
G=2
RL = 150 Ω, G = 2,
NTSC, 40 IRE Mod.
RL = 150 Ω, G = 2,
NTSC, 40 IRE Mod.
Crosstalk
VI = 200 mV,
f = 1 MHz
Input voltage noise
VCC = ±5 V or ±15 V,
f = 10 kHz,
Input offset voltage
VCC = ±5 V or ±15 V
Input offset voltage drift
VCC = ±5 V or ±15 V,
Differential input offset
voltage
VCC = ±5 V or ±15 V
Differential input offset
voltage drift
VCC = ±5 V or ±15 V,
Input bias current, positive
Open-loop transresistance
Input Characteristics
CMRR
(3)
6
–75
f = 500 kHz
–71
f = 1 MHz
–65
f = 500 kHz
–78
f = 1 MHz
–72
dBc
f = 10 kHz
pA/√Hz
VCC = ±5 V
0.03%
VCC = ±15 V
0.04%
VCC = ±5 V
0.08°
VCC = ±15 V
0.06°
G = 2, single-ended
TA = 25°C
–64
dB
1.7
nV/√Hz
1
TA = full range
20
TA = 25°C
0.5
4
TA = full range
5
TA = full range
10
TA = 25°C
1
TA = full range
VCC = ±5 V or ±15 V
5
7
TA = full range
mV
μV/°C
mV
μV/°C
9
12
TA = 25°C
5
TA = full range
10
12
TA = 25°C
1.5
TA = full range
μA
8
11
VCC = ±5
1
VCC = ±15 V
4
MΩ
(3)
Common-mode input voltage VCC = ±5
range
VCC = ±15
VICR
Ci
–66
VO(PP) = 2 V
(3)
Input bias current,
differential
ri
–80
VO(PP) = 20 V
16
Input bias current, negative
IIB
–69
VO(PP) = 2 V
11.5
VCC = ±5 V or ±15 V
Differential phase error
DC Performance
VIO
RL = 25 Ω
VO(PP) = 20 V
Common-mode rejection
ratio
Differential common-mode
rejection ratio
±3.5
±3.6
±13.3
±13.4
62
73
VCC = ±5 V or ±15 V, TA = full range
V
dB
100
Input resistance,
+ input
1.5
Input resistance,
– input
15
Ω
1.4
pF
Input capacitance
Full range is 0°C to 70°C for the THS6022C, and –40°C to 85°C for the THS6022I.
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THS6022
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SLOS225D – SEPTEMBER 1998 – REVISED JULY 2007
ELECTRICAL CHARACTERISTICS (continued)
VCC = ±15 V, RL = 50 Ω, RF = 1 kΩ, TA = 25°C (unless otherwise noted)
PARAMETER
Output Characteristics
VO
TEST CONDITIONS
MIN
single-ended
RL = 50 Ω
differential
RL = 100 Ω
VCC = ±5 V,
RL = 5 Ω
VCC = ±15,
RL = 50 Ω
Output voltage swing
IO
Output current (5)
IOS
Short-circuit output current (6)
RO
Output resistance
Power Supply
MAX
±12.6
VCC = ±5
±6
±6.6
UNIT
±24.6
±25.2
V
250
mA
250
400
mA
13
Ω
(4)
Split supply
Single supply
±4.5
±16.5
9
33
TA = 25°C
6
TA = full range
7.2
TA = full range
VCC = ±5
Power-supply rejection ratio
VCC = ±15
V
8
10
TA = 25°C
VCC = ±15
(4)
(5)
(6)
±3.2
±12
200
Quiescent current (each driver)
PSRR
±3
VCC = ±15
VCC = ±15
VCC = ±5
ICC
VCC = ±5
Open-loop
Power supply operating
range
VCC
TYP
(4)
9
mA
11
TA = 25°C
–68
TA = full range
–65
TA = 25°C
–64
TA = full range
–62
–76
–75
dB
dB
Full range is 0°C to 70°C for the THS6022C, and –40°C to 85°C for the THS6022I.
Slew rate is measured from an output level range of 25% to 75%.
A heat sink is required to keep the junction temperature below absolute maximum when an output is heavily loaded or shorted. See the
absolute maximum ratings and Thermal Information section.
PARAMETER MEASUREMENT INFORMATION
1 kW
1 kW
1 kW
–
–
Driver 1
VI
1 kW
Driver 2
VO
VO
+
+
50 W
VI
50 W
50 W
50 W
S0284-01
Figure 1. Input-to-Output Crosstalk Test Circuit
RG
RF
VCC+
–
VO
+
VI
50 W
VCC–
RL
50 W
S0285-01
Figure 2. Test Circuit, Gain = 1 + (RF/RG)
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THS6022
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SLOS225D – SEPTEMBER 1998 – REVISED JULY 2007
TYPICAL CHARACTERISTICS
Table of Graphs
FIGURE
VO(PP)
Peak-to-peak output voltage
vs Load resistance
3
Maximum peak-to-peak output voltage swing vs Free-air temperature
4
VIO
Input offset voltage
vs Free-air temperature
5
IIB
Input bias current
vs Free-air temperature
6
Positive input bias current
vs Common-mode input voltage
7
Common-mode rejection ratio
vs Free-air temperature
8
Input-to-output crosstalk
vs Frequency
9
Power supply rejection ratio
vs Free-air temperature
10
11
CMRR
PSRR
Closed-loop output impedance
vs Frequency
ICC
Supply current
vs Free-air temperature
SF
Slew rate
vs Output step
13, 14
Vn
Input voltage noise
vs Frequency
15
In
Input current noise
vs Frequency
15
Output amplitude
vs Frequency
16, 17, 19–32
Closed-loop output phase
vs Frequency
18
12
Small and large frequency response
33–36
Single-ended output distortion
vs Peak-to-peak output voltage
37, 38
Harmonic distortion
vs Frequency
39, 40
Differential gain
Number of 150-Ω loads
41, 42
Differential phase
Number of 150-Ω loads
43, 44
400-mV output step response
45, 47
20-V step response
46
4-V step response
48
MAXIMUM PEAK-TO-PEAK
OUTPUT VOLTAGE SWING
vs
FREE-AIR TEMPERATURE
PEAK-TO-PEAK OUTPUT VOLTAGE
vs
LOAD RESISTANCE
14.0
|Maximum Peak-to-Peak Output Voltage Swing| − V
VO(PP) − Peak-to-Peak Output Voltage − V
15
VCC = ±15 V
10
VCC = ±5 V
5
0
TA = 25°C
RF = 1 kΩ
Gain = 1
VCC = ±5 V
−5
−10
VCC = ±15 V
−15
10
100
RL − Load Resistance − Ω
1k
13.0
VCC = ±15 V
50 Ω Load
12.5
12.0
4.0
VCC = ±5 V
No Load
3.5
VCC = ±5 V
50 Ω Load
3.0
2.5
2.0
−40
−20
0
20
40
60
TA − Free-Air Temperature − °C
G001
Figure 3.
8
VCC = ±15 V
No Load
13.5
Figure 4.
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80
100
G002
THS6022
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SLOS225D – SEPTEMBER 1998 – REVISED JULY 2007
INPUT OFFSET VOLTAGE
vs
FREE-AIR TEMPERATURE
INPUT BIAS CURRENT
vs
FREE-AIR TEMPERATURE
7
1.0
6
Gain = 1
RF = 1 kΩ
VCC = ±15 V
0.6
0.4
VCC = ±5 V
5
VCC = ±5 V
IIB+
4
3
VCC = ±15 V
IIB−
2
VCC = ±5 V
IIB−
0.2
1
0.0
−40
−20
0
20
40
60
80
0
−40
100
0
20
40
60
80
100
G004
G003
Figure 5.
Figure 6.
POSITIVE INPUT BIAS CURRENT
vs
COMMON-MODE INPUT VOLTAGE
COMMON-MODE REJECTION RATIO
vs
FREE-AIR TEMPERATURE
20
CMRR − Common-Mode Rejection Ratio − dB
90
15
10
±15 V
5
0
−5
−10
−15
−20
−15
−20
TA − Free-Air Temperature − °C
TA − Free-Air Temperature − °C
IIB+ − Input Bias Current − µA
VCC = ±15 V
IIB+
0.8
IIB − Input Bias Current − µA
VIO − Input Offset Voltage − mV
Gain = 1
RF = 1 kΩ
−10
−5
0
5
10
VIC − Common-Mode Input Voltage − V
15
VCC = ±15 V
85
80
75
VCC = ±5 V
70
1 kΩ
1 kΩ
−
+
VI
65
60
−40
G005
Figure 7.
1 kΩ
−20
0
VO
1 kΩ
20
40
60
TA − Free-Air Temperature − °C
80
100
G006
Figure 8.
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THS6022
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SLOS225D – SEPTEMBER 1998 – REVISED JULY 2007
INPUT-TO-OUTPUT CROSSTALK
vs
FREQUENCY
Input-to-Output Crosstalk − dB
−10
−20
84
VCC = ±15 V
Gain = 2
RL = 50 Ω
RF = 1 kΩ
VO = 0.2 V
PSRR − Power Supply Rejection Ratio − dB
0
POWER SUPPLY REJECTION RATIO
vs
FREE-AIR TEMPERATURE
Driver 1 = Output
Driver 2 = Input
−30
−40
−50
−60
−70
Driver 1 = Input
Driver 2 = Output
−80
−90
100k
1M
10M
100M
82
80
VCC+
78
76
VCC−
74
72
−40
500M
VCC = ±15 V or ±5 V
Gain = 1
RF = 1 kΩ
−20
G007
60
CLOSED-LOOP OUTPUT IMPEDANCE
vs
FREQUENCY
SUPPLY CURRENT
vs
FREE-AIR TEMPERATURE
80
100
G008
9
VCC = ±15 V
8
10
ICC − Supply Current − mA
Zo − Output Impedance − Ω
40
Figure 10.
Gain = 2
RF = 1 kΩ
VI(PP) = 2 V
VCC = ±5 V
1
VCC = ±15 V
VO
1 kΩ
1 kΩ
1 kΩ
−
0.1
+
50 Ω
1M
10M
7
VCC = ±5 V
6
5
VI
THS6022
1000
VI
Zo =
−1
VO
(
100M
4
)
500M
3
−40
f − Frequency − Hz
G009
Figure 11.
10
20
Figure 9.
100
0.01
100k
0
TA − Free-Air Temperature − °C
f − Frequency − Hz
−20
0
20
40
Figure 12.
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60
TA − Free-Air Temperature − °C
80
100
G010
THS6022
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SLOS225D – SEPTEMBER 1998 – REVISED JULY 2007
SLEW RATE
vs
OUTPUT STEP
SLEW RATE
vs
OUTPUT STEP
2200
1000
1900
900
+SR
RL = 50 Ω
800
+SR
+SR
RL = 25 Ω
Slew Rate − V/µs
1300
−SR
1000
VCC = ±15 V
Gain = 5
RF = 1 kΩ
RL = 50 Ω
Minimal Saturation
700
400
0
5
10
15
600
−SR
RL = 50 Ω
500
−SR
RL = 25 Ω
400
VCC = ±5 V
Gain = 2
RF = 1 kΩ
200
100
20
Output Step − VPP
700
300
100
0
1
2
3
Output Step − VPP
G011
Figure 13.
4
5
G012
Figure 14.
INPUT VOLTAGE AND CURRENT NOISE
vs
FREQUENCY
100
In − Current Noise − pA/√Hz
Vn − Voltage Noise − nV/√Hz
Slew Rate − V/µs
1600
VCC = ±15 V
TA = 25°C
In− Noise
10
In+ Noise
Vn Noise
1
10
100
1k
10k
100k
f − Frequency − Hz
G013
Figure 15.
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SLOS225D – SEPTEMBER 1998 – REVISED JULY 2007
OUTPUT AMPLITUDE
vs
FREQUENCY
OUTPUT AMPLITUDE
vs
FREQUENCY
70
60
70
VCC = ±15 V
RG = 10 Ω
RL = 50 Ω
VO = 2 V
Gain = 1000
40
Gain = 100
30
20
Gain = 10
Gain = 100
40
30
20
10
10
0
0
−10
100k
1M
10M
100M
VCC = ±5 V
RG = 10 Ω
RL = 50 Ω
VO = 2 V
Gain = 1000
50
Output Amplitude − dB
Output Amplitude − dB
50
60
Gain = 10
−10
100k
500M
1M
f − Frequency − Hz
10M
100M
G014
Figure 17.
CLOSED-LOOP OUTPUT PHASE
vs
FREQUENCY
OUTPUT AMPLITUDE
vs
FREQUENCY
45
2
0
1
−90
−135
VCC = ±5 V
−180
−225
−270
−315
100k
Gain = 1000
RF = 1 kΩ
RG = 10 Ω
VO(PP) = 2 V
1M
−1
500M
RF = 1 kΩ
−3
−4
−6
100M
RF = 787 Ω
−2
−5
10M
RF = 560 Ω
0
VCC = ±15 V
Output Amplitude − dB
Output Phase − °
G015
Figure 16.
−45
VCC = ±15 V
Gain = 1
RL = 50 Ω
VO = 0.2 V
−7
100k
f − Frequency − Hz
1M
10M
100M
500M
f − Frequency − Hz
G016
Figure 18.
12
500M
f − Frequency − Hz
G017
Figure 19.
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SLOS225D – SEPTEMBER 1998 – REVISED JULY 2007
OUTPUT AMPLITUDE
vs
FREQUENCY
OUTPUT AMPLITUDE
vs
FREQUENCY
2
8
RF = 620 Ω
1
6
Output Amplitude − dB
Output Amplitude − dB
0
−1
RF = 910 Ω
−2
−3
RF = 1.3 kΩ
−4
−5
−6
−7
100k
RF = 470 Ω
7
VCC = ±5 V
Gain = 1
RL = 50 Ω
VO = 0.2 V
5
4
RF = 590 Ω
3
RF = 1 kΩ
2
1
0
1M
10M
100M
VCC = ±15 V
Gain = 2
RL = 50 Ω
VO = 0.2 V
−1
100k
500M
1M
f − Frequency − Hz
10M
100M
G018
G019
Figure 20.
Figure 21.
OUTPUT AMPLITUDE
vs
FREQUENCY
OUTPUT AMPLITUDE
vs
FREQUENCY
8
2
RF = 470 Ω
7
1
6
0
Output Amplitude − dB
Output Amplitude − dB
RF = 510 Ω
5
RF = 715 Ω
4
3
RF = 1 kΩ
2
1
0
−1
100k
500M
f − Frequency − Hz
VCC = ±5 V
Gain = 2
RL = 50 Ω
VO = 0.2 V
1M
−1
−3
RF = 1 kΩ
−4
−5
−6
10M
100M
500M
RF = 560 Ω
−2
VCC = ±15 V
Gain = −1
RL = 50 Ω
VO = 0.2 V
−7
100k
f − Frequency − Hz
1M
10M
100M
500M
f − Frequency − Hz
G020
Figure 22.
G021
Figure 23.
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OUTPUT AMPLITUDE
vs
FREQUENCY
OUTPUT AMPLITUDE
vs
FREQUENCY
2
1
RF = 510 Ω
1
0
−1
Output Amplitude − dB
Output Amplitude − dB
0
−1
−2
RF = 680 Ω
−3
RF = 1 kΩ
−4
−5
−6
−7
100k
VCC = ±5 V
Gain = −1
RL = 50 Ω
VO = 0.2 V
−2
RL = 200 Ω
−3
−7
10M
100M
RL = 50 Ω
RL = 25 Ω
−5
−6
1M
RL = 100 Ω
−4
VCC = ±15 V
Gain = 1
RF = 1 kΩ
VO = 0.2 V
−8
100k
500M
1M
f − Frequency − Hz
OUTPUT AMPLITUDE
vs
FREQUENCY
OUTPUT AMPLITUDE
vs
FREQUENCY
8
0
7
−1
6
−2
RL = 200 Ω
−3
RL = 100 Ω
−4
RL = 50 Ω
−5
−8
100k
RL = 25 Ω
1M
VCC = ±15 V
Gain = 2
RF = 1 kΩ
VO = 0.2 V
5
4
3
2
RL = 200 Ω
RL = 100 Ω
1
VCC = ±5 V
Gain = 1
RF = 1 kΩ
VO = 0.2 V
RL = 50 Ω
RL = 25 Ω
0
10M
100M
500M
−1
100k
1M
10M
100M
500M
f − Frequency − Hz
f − Frequency − Hz
G025
G024
Figure 26.
14
500M
G023
Figure 25.
1
−7
100M
Figure 24.
Output Amplitude − dB
Output Amplitude − dB
G022
−6
10M
f − Frequency − Hz
Figure 27.
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OUTPUT AMPLITUDE
vs
FREQUENCY
OUTPUT AMPLITUDE
vs
FREQUENCY
8
2
VCC = ±5 V
Gain = 2
RF = 1 kΩ
VO = 0.2 V
Output Amplitude − dB
6
RF = 620 Ω
1
0
Output Amplitude − dB
7
5
4
3
RL = 200 Ω
2
RL = 100 Ω
RL = 50 Ω
1
−2
RF = 750 Ω
−3
RF = 1.3 kΩ
−4
VCC = ±15 V
Gain = 1
RL = 100 Ω
VO = 0.2 V
−5
RL = 25 Ω
0
−1
100k
−1
−6
1M
10M
100M
−7
100k
500M
1M
f − Frequency − Hz
10M
100M
G026
G027
Figure 28.
Figure 29.
OUTPUT AMPLITUDE
vs
FREQUENCY
OUTPUT AMPLITUDE
vs
FREQUENCY
8
2
RF = 680 Ω
RF = 510 Ω
7
1
0
Output Amplitude − dB
Output Amplitude − dB
6
5
4
3
RF = 620 Ω
2
1
0
−1
100k
500M
f − Frequency − Hz
VCC = ±15 V
Gain = 2
RL = 100 Ω
VO = 0.2 V
1M
RF = 1 kΩ
−1
−2
−3
RF = 1.3 kΩ
−4
−5
−6
10M
100M
500M
RF = 1 kΩ
VCC = ±5 V
Gain = 1
RL = 25 Ω
VO = 0.2 V
−7
100k
f − Frequency − Hz
1M
10M
100M
500M
f − Frequency − Hz
G028
Figure 30.
G029
Figure 31.
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OUTPUT AMPLITUDE
vs
FREQUENCY
8
RF = 560 Ω
7
Output Amplitude − dB
6
5
RF = 820 Ω
4
3
RF = 1 kΩ
2
1
0
VCC = ±5 V
Gain = 2
RL = 25 Ω
VO = 0.2 V
−1
100k
1M
10M
100M
500M
f − Frequency − Hz
G030
Figure 32.
SMALL AND LARGE SIGNAL FREQUENCY RESPONSE
SMALL AND LARGE SIGNAL FREQUENCY RESPONSE
−3
−3
VI = 500 mV
−6
−9
VI = 250 mV
−12
Output Level − dBV
Output Level − dBV
−9
−15
VI = 125 mV
−18
−21
−24
−27
−30
100k
VI = 500 mV
−6
VI = 62.5 mV
1M
−15
−21
−27
10M
100M
500M
VI = 125 mV
−18
−24
VCC = ±15 V
Gain = 1
RL = 50 Ω
RF = 787 Ω
VI = 250 mV
−12
−30
100k
VI = 62.5 mV
VCC = ±5 V
Gain = 1
RL = 50 Ω
RF = 910 Ω
f − Frequency − Hz
1M
10M
G031
Figure 33.
16
100M
500M
f − Frequency − Hz
G032
Figure 34.
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SMALL AND LARGE SIGNAL FREQUENCY RESPONSE
SMALL AND LARGE SIGNAL FREQUENCY RESPONSE
3
3
VI = 500 mV
0
−3
−3
VI = 250 mV
−6
Output Level − dBV
Output Level − dBV
VI = 500 mV
0
−9
VI = 125 mV
−12
−15
VI = 62.5 mV
−18
−21
−24
100k
−9
VI = 125 mV
−12
−15
VI = 62.5 mV
−18
VCC = ±15 V
Gain = 2
RL = 50 Ω
RF = 590 Ω
1M
VI = 250 mV
−6
−21
10M
100M
−24
100k
500M
VCC = ±5 V
Gain = 2
RL = 50 Ω
RF = 715 Ω
1M
f − Frequency − Hz
10M
100M
G033
G034
Figure 35.
Figure 36.
SINGLE-ENDED OUTPUT DISTORTION
vs
PEAK-TO-PEAK OUTPUT VOLTAGE
SINGLE-ENDED OUTPUT DISTORTION
vs
PEAK-TO-PEAK OUTPUT VOLTAGE
−40
−40
VCC = ±15 V
RF = 1 kΩ
RL = 50 Ω
f = 500 kHz
Gain = 2
−50
Single-Ended Output Distortion − dBc
Single-Ended Output Distortion − dBc
500M
f − Frequency − Hz
−60
3rd Harmonic
−70
−80
2nd Harmonic
−90
−100
VCC = ±15 V
RF = 1 kΩ
RL = 50 Ω
f = 1 MHz
Gain = 2
−50
2nd Harmonic
−60
−70
−80
3rd Harmonic
−90
−100
0
5
10
15
20
VO(PP) − Peak-to-Peak Output Voltage − V
0
G035
Figure 37.
5
10
15
VO(PP) − Peak-to-Peak Output Voltage − V
20
G036
Figure 38.
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HARMONIC DISTORTION
vs
FREQUENCY
HARMONIC DISTORTION
vs
FREQUENCY
−40
−40
−50
Harmonic Distortion − dBc
−50
Harmonic Distortion − dBc
3rd Harmonic
RL = 25 Ω
VCC = ±15 V
RF = 1 kΩ
RL = 50 Ω
VO = 2 VPP
Gain = 2
−60
2nd Harmonic
−70
−80
2nd Harmonic
RL = 25 Ω
2nd Harmonic
RL = 50 Ω
−60
3rd Harmonic
RL = 50 Ω
−70
−80
VCC = ±5 V
RF = 1 kΩ
VO = 2 VPP
Gain = 2
3rd Harmonic
−90
−90
−100
100k
1M
−100
100k
10M
1M
f − Frequency − Hz
10M
f − Frequency − Hz
G037
G038
Figure 39.
Figure 40.
DIFFERENTIAL GAIN
vs
LOADING
DIFFERENTIAL GAIN
vs
LOADING
0.14
0.16
Gain = 2
RF = 680 Ω
40 IRE − NTSC Modulation
Worst Case ±100 IRE Ramp
0.12
0.12
0.08
Differential Gain − %
0.10
Differential Gain − %
Gain = 2
RF = 680 Ω
40 IRE − PAL Modulation
Worst Case ±100 IRE Ramp
0.14
VCC = ±15 V
0.06
VCC = ±5 V
0.04
0.10
VCC = ±15 V
0.08
VCC = ±5 V
0.06
0.04
0.02
0.02
0.00
0.00
1
2
3
4
5
1
6
Number of 150−Ω Loads
2
3
4
G039
Figure 41.
18
5
6
Number of 150−Ω Loads
G040
Figure 42.
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DIFFERENTIAL PHASE
vs
LOADING
DIFFERENTIAL PHASE
vs
LOADING
0.45
0.30
Gain = 2
RF = 680 Ω
40 IRE − NTSC Modulation
Worst Case ±100 IRE Ramp
0.35
Differential Phase − °
Differential Phase − °
0.25
0.20
VCC = ±5 V
0.15
Gain = 2
RF = 680 Ω
40 IRE − PAL Modulation
Worst Case ±100 IRE Ramp
0.40
VCC = ±15 V
0.10
0.30
0.25
VCC = ±5 V
0.20
VCC = ±15 V
0.15
0.10
0.05
0.05
0.00
0.00
1
2
3
4
5
1
6
2
Number of 150−Ω Loads
3
4
5
6
Number of 150−Ω Loads
G041
G042
Figure 43.
Figure 44.
20-V STEP RESPONSE
16
300
12
200
8
VO − Output Voltage − V
VO − Output Voltage − mV
400-mV STEP RESPONSE
400
100
0
−100
VCC = ±15 V
Gain = 5
RF = 1 kΩ
RL = 50 Ω
tr/tf = 900 ns
−200
−300
10
20
30
40
50
60
0
−4
Minimal Saturation
VCC = ±15 V
Gain = 5
RF = 1 kΩ
RL = 50 Ω
tr/tf = 7 ns
−8
−12
−400
0
4
70
80
90
100
−16
0
10
t − Time − ns
G043
Figure 45.
20
30
40
50
60
70
80
90
100
t − Time − ns
G044
Figure 46.
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400-mV STEP RESPONSE
4-V STEP RESPONSE
RL = 25 Ω
RL = 25 Ω
VCC = ±5 V
Gain = 2
RF = 1 kΩ
tr/tf = 900 ns
See Figure 2
0
10
20
30
40
50
RL = 50 Ω
100 mV Per Division
100 mV Per Division
RL = 50 Ω
60
70
80
90
100
VCC = ±5 V
Gain = 2
RF = 1 kΩ
tr/tf = 900 ns
See Figure 2
0
10
t − Time − ns
20
30
40
50
60
G045
Figure 47.
20
70
80
90
100
t − Time − ns
G046
Figure 48.
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APPLICATION INFORMATION
Simplified Schematic
VCC+
Ibias
IN+
IN–
OUT
Ibias
VCC–
S0286-01
The THS6022 contains two independent operational amplifiers. These amplifiers are current feedback topology
amplifiers made for high-speed operation. They have been specifically designed to deliver the full power
requirements of ADSL and therefore can deliver output currents of at least 200 mA at full output voltage.
The THS6022 is fabricated using Texas Instruments 30-V complementary bipolar process, HVBiCOM. This
process provides excellent isolation and high slew rates that result in excellent crosstalk and extremely low
distortion.
Independent Power Supplies
Each amplifier of the THS6022 has its own power supply pins. This was specifically done to solve a problem that
often occurs when multiple devices in the same package share common power pins. This problem is crosstalk
between the individual devices caused by currents flowing in common connections. Whenever the current
required by one device flows through a common connection shared with another device, this current, in
conjunction with the impedance in the shared line, produces an unwanted voltage on the power supply. Proper
power-supply decoupling and good device power-supply rejection helps to reduce this unwanted signal. What is
left is crosstalk.
However, with independent power-supply pins for each device, the effects of crosstalk through common
impedance in the power supplies are more easily managed. This is because it is much easier to achieve low
common impedance on the PCB with copper etch than it is to achieve low impedance within the package with
either bond wires or metal traces on silicon.
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APPLICATION INFORMATION (continued)
Power Supply Restrictions
Although the THS6022 is specified for operation from power supplies of ±5 V to ±15 V (or singled-ended power
supply operation from 10 V to 30 V), and each amplifier has its own power supply pins, several precautions must
be taken to assure proper operation.
• The power supplies for each amplifier must be the same value. For example, if the driver 1 uses ±15 volts,
then the driver 2 must also use ±15 volts. Using ±15 volts for one amplifier and ±5 volts for another amplifier
is not allowed.
• To save power by powering down one of the amplifiers in the package, the following rules must be followed.
– The amplifier designated driver 1 must always receive power. This is because the internal startup circuitry
uses the power from the driver 1 device.
– The –VCC pins from both drivers must always be at the same potential.
– Individual amplifiers are powered down by simply opening the VCC+ connection.
The THS6022 incorporates a standard class A-B output stage. This means that some of the quiescent current is
directed to the load as the load current increases. So under heavy load conditions, accurate power dissipation
calculations are best achieved through actual measurements. For small loads, however, internal power
dissipation for each amplifier in the THS6022 can be approximated by the following formula:
P
D
ǒ
≅ 2V
Ǔ ǒ
I
) V
_V
CC CC
CC
O
Ǔ
ǒ Ǔ
V
O
R
L
where:
PD = Power dissipation for one amplifier
VCC = Split supply voltage
ICC = Supply current for that particular amplifier
VO = RMS output voltage of amplifier
RL = Load resistance
To find the total THS6022 power dissipation, we simply sum up both amplifier power dissipation results.
Generally, the worst-case power dissipation occurs when the output voltage is one-half the VCC voltage. One last
note, which is often overlooked: the feedback resistor (RF) is also a load to the output of the amplifier and should
be taken into account for low value feedback resistors.
Device Protection Features
The THS6022 has two built-in features that protect the device against improper operation. The first protection
mechanism is output current limiting. Should the output become shorted to ground, the output current is
automatically limited to the value given in the data sheet. While this protects the output against excessive
current, the device internal power dissipation increases due to the high current and large voltage drop across the
output transistors. Continuous output shorts are not recommended and could damage the device. Additionally,
connection of the amplifier output to one of the supply rails (±VCC) can cause failure of the device and is not
recommended.
The second built-in protection feature is thermal shutdown. Should the internal junction temperature rise above
approximately 180°C, the device automatically shuts down. Such a condition could exist with improper heat
sinking or if the output is shorted to ground. When the abnormal condition is fixed, the internal thermal shutdown
circuit automatically turns the device back on.
Thermal Information
The THS6022 is packaged in a thermally-enhanced PWP package, which is a member of the PowerPAD family
of packages. This package is constructed using a downset leadframe upon which the die is mounted [see
Figure 49(a) and Figure Figure 49(b)]. This arrangement results in the lead frame being exposed as a thermal
pad on the underside of the package [see Figure 49(c)]. Because this thermal pad has direct thermal contact
with the die, excellent thermal performance can be achieved by providing a good thermal path away from the
thermal pad.
22
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APPLICATION INFORMATION (continued)
The PowerPAD package allows for both assembly and thermal management in one manufacturing operation.
During the surface-mount solder operation (when the leads are being soldered), the thermal pad can also be
soldered to a copper area underneath the package. Through the use of thermal paths within this copper area,
heat can be conducted away from the package into either a ground plane or other heat dissipating device. This
is discussed in more detail in the PCB Design Considerations section of this document.
The PowerPAD package represents a design breakthrough, combining the small area and ease of the surface
mount assembly method to eliminate the previously difficult mechanical methods of heatsinking.
DIE
Side View (a)
Thermal
Pad
DIE
End View (b)
Bottom View (c)
M0088-01
The thermal pad is electrically isolated from all terminals in the package.
Figure 49. Views of Thermally Enhanced PWP Package
Recommended Feedback and Gain Resistor Values
As with all current feedback amplifiers, the bandwidth of the THS6022 is an inversely proportional function of the
value of the feedback resistor. This can be seen from Figure 19 through Figure 32. The recommended resistors
for the optimum frequency response are shown in Table 1. These should be used as a starting point and once
optimum values are found, 1% tolerance resistors should be used to maintain frequency response
characteristics. Because there is a finite amount of output resistance of the operational amplifier, load resistance
can play a major part in frequency response. This is especially true with these drivers, which tend to drive
low-impedance loads. This can be seen in Figure 10 and Figure 25 through Figure 28. As the load resistance
increases, the output resistance of the amplifier becomes less dominant at high frequencies. To compensate for
this, the feedback resistor should change. For most applications, a feedback resistor value of 1 kΩ is
recommended, which is a good compromise between bandwidth and phase margin that yields a very stable
amplifier.
Table 1. Recommended Feedback (RF) Values for Optimum Frequency Response
GAIN
VCC = ±15 V
VCC = ±15 V
RL = 50 Ω
RL = 100 Ω
RL = 25 Ω
RL = 50 Ω
RL = 100 Ω
1
787 Ω
750 Ω
1 kΩ
910 Ω
820 Ω
2
590 Ω
590 Ω
820 Ω
715 Ω
680 Ω
–1
560 Ω
–
–
680 Ω
–
Consistent with current-feedback amplifiers, increasing the gain is best accomplished by changing the gain
resistor, not the feedback resistor. This is because the bandwidth of the amplifier is dominated by the feedback
resistor value and internal dominant-pole capacitor. The ability to control the amplifier gain independently of the
bandwidth constitutes a major advantage of current-feedback amplifiers over conventional voltage feedback
amplifiers. Therefore, once a frequency response is found suitable to a particular application, adjust the value of
the gain resistor to increase or decrease the overall amplifier gain.
Finally, it is important to realize the effects of the feedback resistance on distortion. Increasing the resistance
decreases the loop gain and increases the distortion. It is also important to know that decreasing load
impedance increases total harmonic distortion (THD). Typically, the third-order harmonic distortion increases
more than the second-order harmonic distortion. This is illustrated in Figure 40.
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Offset Voltage
The output offset voltage, (VOO) is the sum of the input offset voltage (VIO) and both input bias currents (IIB)
times the corresponding gains. The following schematic and formula can be used to calculate the output offset
voltage:
Figure 50. Output Offset Voltage Model
Noise Calculations and Noise Figure
Noise can cause errors on very small signals. This is especially true for amplifying small signals. The noise
model for current-feedback amplifiers (CFB) is the same as for voltage-feedback amplifiers (VFB). The only
difference between the two is that the CFB amplifiers generally specify different current noise parameters for
each input, whereas VFB amplifiers usually only specify one noise-current parameter. The noise model is shown
in Figure 51. This model includes all of the noise sources as follows:
•
•
•
•
en = Amplifier internal voltage noise (nV/√Hz)
IN+ = Noninverting current noise (pA/√Hz)
IN– = Inverting current noise (pA/√Hz)
eRx = Thermal voltage noise associated with each resistor (eRx = 4 kTRx)
RS
eRs
en
eni
Noiseless
+
_
IN+
IN–
eno
eRf
RF
eRg
RG
S0277-01
Figure 51. Noise Model
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The total equivalent input noise density (eni) is calculated by using the following equation:
e
ni
+
Ǹ
ǒenǓ ) ǒIN )
2
R
Ǔ
S
2
ǒ
) IN–
ǒR F ø R G ǓǓ
2
ǒ
) 4 kTRs ) 4 kT R ø R
F
G
Ǔ
where:
k = Boltzmann’s constant = 1.380658 × 10–23
T = Temperature in degrees Kelvin (273 + °C)
RF || RG = Parallel resistance of RF and RG
To get the equivalent output noise of the amplifier, just multiply the equivalent input noise density (eni) by the
overall amplifier gain (AV).
e no + e
ni
A
V
ǒ
+ e ni 1 )
Ǔ
RF
(Noninverting Case)
RG
As the previous equations show, to keep noise at a minimum, small-value resistors should be used. As the
closed-loop gain is increased (by reducing RG), the input noise is reduced considerably because of the parallel
resistance term. This leads to the general conclusion that the most dominant noise sources are the source
resistor (RS) and the internal amplifier noise voltage (en). Because noise is summed in a root-mean-squares
method, noise sources smaller than 25% of the largest noise source can be effectively ignored. This can greatly
simplify the formula and make noise calculations much easier to calculate.
This brings up another noise measurement usually preferred in RF applications, the noise figure (NF). Noise
figure is a measure of noise degradation caused by the amplifier. The value of the source resistance must be
defined and is typically 50 Ω in RF applications.
NF +
ȱ e 2ȳ
10logȧ ni ȧ
ȧ 2ȧ
ȲǒeRsǓ ȴ
Because the dominant noise components are generally the source resistance and the internal amplifier noise
voltage, we can approximate noise figure as:
NF +
ȱ ȡǒ Ǔ2 ǒ
ȧ en ) IN )
ȧ
Ȣ
ȧ
10logȧ1 )
4 kTR
ȧ
S
ȧ
Ȳ
ȣȳ
Ǔ
S ȧȧ
Ȥȧ
ȧ
ȧ
ȧ
ȴ
2
R
Figure 52 shows the noise figure graph for the THS6022.
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NOISE FIGURE
vs
SOURCE RESISTANCE
20
18
TA = 25°C
16
Noise Figure − dB
14
12
10
8
6
4
2
0
10
100
1k
10k
RS − Source Resistance − Ω
G047
Figure 52. Noise Figure vs Source Resistance
Slew Rate
The slew rate performance of a current-feedback amplifier like the THS6022 is affected by many different
factors. Some of these factors are external to the device, such as amplifier configuration and PCB parasitics,
and others are internal to the device, such as available currents and node capacitance. Understanding some of
these factors should help the PCB designer arrive at a more optimum circuit with fewer problems.
Whether the THS6022 is used in an inverting amplifier configuration or a noninverting configuration can impact
the output slew rate. Slew rate performance in the inverting configuration is generally faster than the
noninverting configuration. This is because in the inverting configuration, the input terminals of the amplifier are
at a virtual ground and do not significantly change voltage as the input changes. Consequently, the time to
charge any capacitance on these input nodes is less than for the noninverting configuration, where the input
nodes actually do change in voltage an amount equal to the size of the input step. In addition, any PCB parasitic
capacitance on the input nodes degrades the slew rate further simply because there is more capacitance to
charge. If the supply voltage (VCC) to the amplifier is reduced, slew rate decreases because there is less current
available within the amplifier to charge the capacitance on the input nodes as well as other internal nodes. Also,
as the load resistance decreases, the slew rate typically decreases due to the increasing internal currents, which
slow down the transitions (see Figure 13 and Figure 14).
Internally, the THS6022 has other factors that impact the slew rate. The amplifier’s behavior during the slew rate
transition varies slightly depending upon the rise time of the input. This is because of the way the input stage
handles faster and faster input edges. Slew rates (as measured at the amplifier output) of less than about 1300
V/μs are processed by the input stage in a very linear fashion. Consequently, the output waveform smoothly
transitions between initial and final voltage levels. This is shown in Figure 53. For slew rates greater than 1300
V/μs, additional slew-enhancing transistors present in the input stage begin to turn on to support these faster
signals. The result is an amplifier with extremely fast slew rate capabilities. Figure 54 shows waveforms for
these faster slew rates. The additional aberrations present in the output waveform with these faster slewing input
signals are due to the brief saturation of the internal current mirrors. This phenomenon, which typically lasts less
than 20 ns, is considered normal operation and is not detrimental to the device in any way. If for any reason this
type of response is not desired, then increasing the feedback resistor or slowing down the input signal slew rate
reduces the effect.
26
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THS6022
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SLOS225D – SEPTEMBER 1998 – REVISED JULY 2007
SLEW RATE—LINEAR
16
12
12
8
8
VO − Output Voltage − V
VO − Output Voltage − V
SLEW RATE—SATURATION
16
4
0
−4
SR ≅ 1300 V/µs
VCC = ±15 V
Gain = 5
RF = 1 kΩ
RL = 50 Ω
tr/tf = 10 ns
−8
−12
4
0
−4
SR = 3500 V/µs
VCC = ±15 V
Gain = 5
RL = 1 kΩ
RF = 50 Ω
tr/tf = 900 ns
−8
−12
−16
−16
0
10
20
30
40
50
60
70
80
90
100
0
10
20
30
40
t − Time − ns
50
60
70
80
90
100
t − Time − ns
G048
G049
Figure 53.
Figure 54.
Driving a Capacitive Load
Driving capacitive loads with high-performance amplifiers is not a problem as long as certain precautions are
taken. The first is to realize that the THS6022 has been internally compensated to maximize its bandwidth and
slew-rate performance. When the amplifier is compensated in this manner, capacitive loading directly on the
output decreases the device phase margin, leading to high-frequency ringing or oscillations. Therefore, for
capacitive loads of greater than 10 pF, it is recommended that a resistor be placed in series with the output of
the amplifier, as shown in Figure 55. A minimum value of 15 Ω should work well for most applications. For
example, in 75-Ω transmission systems, setting the series resistor value to 75 Ω both isolates any capacitance
loading and provides the proper line impedance matching at the source end.
1 kW
1 kW
Input
_
15 W
Output
THS6022
+
CLOAD
S0278-02
Figure 55. Driving a Capacitive Load
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THS6022
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SLOS225D – SEPTEMBER 1998 – REVISED JULY 2007
PCB Design Considerations
Proper PCB design techniques in two areas are important to assure proper operation of the THS6022. These
areas are high-speed layout techniques and thermal-management techniques. Because the THS6022 is a
high-speed part, the following guidelines are recommended.
• Ground plane—It is essential that a ground plane be used on the board to provide all components with a
low-inductance ground connection. Although a ground connection directly to a terminal of the THS6022 is not
necessarily required, it is recommended that the thermal pad of the package be tied to ground. This serves
two functions. It provides a low-inductance ground to the device substrate to minimize internal crosstalk, and
it provides the path for heat removal.
• Input stray capacitance—To minimize potential problems with amplifier oscillation, the capacitance at the
inverting input of the amplifiers must be kept to a minimum. To do this, PCB trace runs to the inverting input
must be as short as possible, the ground plane must be removed under any etch runs connected to the
inverting input, and external components should be placed as close as possible to the inverting input. This is
especially true in the noninverting configuration. An example of this can be seen in Figure 56, which shows
what happens when a 1-pF capacitor is added to the inverting input terminal in the noninverting
configuration. The bandwidth increases dramatically at the expense of peaking. This is because some of the
error current is flowing through the stray capacitor instead of the inverting node of the amplifier. While the
device is in the inverting mode, stray capacitance at the inverting input has a minimal effect. This is because
the inverting node is at a virtual ground and the voltage does not fluctuate nearly as much as in the
noninverting configuration. This can be seen in Figure 57, where a 27-pF capacitor adds only 0.5 dB of
peaking. In general, as the gain of the system increases, the output peaking due to this capacitor decreases.
While this can initially appear to be a faster and better system, overshoot and ringing are more likely to occur
under fast transient conditions. So, proper analysis of adding a capacitor to the inverting input node should
always be performed for stable operation.
OUTPUT AMPLITUDE
vs
FREQUENCY
OUTPUT AMPLITUDE
vs
FREQUENCY
3
2
VCC = ±15 V
Gain = 1
RL = 50 Ω
VO = 0.2 V
Output Amplitude − dB
1
Ci = 1 pF
0
0
−1
Ci = 0 pF
(Stray C Only)
−2
C in
−3
Ci = 27 pF
1
Output Amplitude − dB
2
1 kΩ
−1
−2
VCC = ±15 V
Gain = −1
RL = 50 Ω
VO = 0.2 V
Ci = 0 pF
(Stray C Only)
−3
1 kΩ
−4
1 kΩ
−4
−
+
VI
50 Ω
−5
−6
100k
1M
−5
VO
VI
50 Ω
−6
10M
100M
500M
−7
100k
f − Frequency − Hz
−
+
50 Ω
C in
1M
VO
RL = 50 Ω
10M
G050
Figure 56.
•
28
100M
500M
f − Frequency − Hz
G051
Figure 57.
Proper power supply decoupling—Use a minimum of a 6.8-μF tantalum capacitor in parallel with a 0.1-μF
ceramic capacitor on each supply terminal. It may be possible to share the tantalum among several
amplifiers depending on the application, but a 0.1-μF ceramic capacitor should always be used on the supply
terminal of every amplifier. In addition, the 0.1-μF capacitor should be placed as close as possible to the
supply terminal. As this distance increases, the inductance in the connecting etch makes the capacitor less
effective. The designer should strive for distances of less than 0.1 inch (2.55 mm) between the device power
terminal and the ceramic capacitors.
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SLOS225D – SEPTEMBER 1998 – REVISED JULY 2007
Because of its power dissipation, proper thermal management of the THS6022 is required. Although there are
many ways to properly heatsink this device, the following steps illustrate one recommended approach for a
multilayer PCB with an internal ground plane. See Figure 58 for the following steps.
Thermal pad area = 150 mils x 170 mils (3.81 mm x 4.32 mm) with 6 vias.
Via diameter = 13 mils (0.33 mm).
M0089-01
Figure 58. PowerPAD PCB Etch and Via Pattern Minimum Requirements
1. Place six holes in the area of the thermal pad. These holes should be 13 mils (0.33 mm) in diameter.
They are kept small so that solder wicking through the holes is not a problem during reflow.
2. Additional vias may be placed anywhere along the thermal plane outside of the thermal pad area. This
will help dissipate the heat generated from the THS6022. These additional vias may be larger than the
13-mil (0.33-mm) diameter vias directly under the thermal pad. They can be larger because they are not
in the thermal-pad area to be soldered; therefore, wicking is generally not a problem.
3. Connect all holes to the internal ground plane.
4. When connecting these holes to the ground plane, do not use the typical web or spoke via connection
methodology. Web connections have a high thermal resistance connection that is useful for slowing the
heat transfer during soldering operations. This makes the soldering of vias that have plane connections
easier. However, in this application, low thermal resistance is desired for the most efficient heat transfer.
Therefore, the holes under the THS6022 package should make their connection to the internal ground
plane with a complete connection around the entire circumference of the plated-through hole.
5. The top-side solder mask should leave exposed the terminals of the package and the thermal pad area
with its six holes. The bottom-side solder mask should cover the six holes of the thermal pad area. This
prevents solder from being pulled away from the thermal pad area during the reflow process.
6. Apply solder paste to the exposed thermal pad area and all of the operational amplifier terminals.
7. With these preparatory steps in place, the THS6022 is simply placed in position and run through the
solder reflow operation as any standard surface-mount component. This results in a part that is properly
installed.
The actual thermal performance achieved with the THS6022 in its PowerPAD package depends on the
application. In the example above, if the size of the internal ground plane is approximately 3 inches × 3 inches
(7.62 mm × 7.62 mm), then the expected thermal coefficient, θJA, is about 37.5°C/W. For a given θJA, the
maximum power dissipation is shown in Figure 60 and is calculated by the following formula:
ǒ
T
P
D
+
–T
MAX A
q
JA
Ǔ
where:
PD = Maximum power dissipation of THS6022 (watts)
TMAX = Absolute maximum junction temperature (150°C)
TA = Ambient free-air temperature (°C)
θJA = θJC + θCA
θJC = Thermal coefficient from junction to case (2.07°C/W)
θCA = Thermal coefficient from case to ambient air
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THS6022
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SLOS225D – SEPTEMBER 1998 – REVISED JULY 2007
More-complete details of the thermal pad installation process and thermal management techniques can be found
in the PowerPAD Thermally Enhanced Package application report (SLMA002).
MAXIMUM POWER DISSIPATION
vs
FREE-AIR TEMPERATURE
6
TJ = 150°C
PCB Size = 3” x 3”
No Air Flow
Maximum Power Dissipation − W
5
θJA = 37.5°C/W
2 oz Trace and
Copper Pad
with Solder
4
3
2
1
0
−40
θJA = 97.7°C/W
2 oz Trace and Copper Pad
without Solder
−20
0
20
40
60
TA − Free-Air Temperature − °C
Figure 59.
30
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80
100
G052
THS6022
www.ti.com
SLOS225D – SEPTEMBER 1998 – REVISED JULY 2007
ADSL
The THS6022 was primarily designed as a line driver and line receiver for ADSL (asymmetrical digital subscriber
line). The driver output stage has been sized to provide full ADSL power levels of 13 dBm onto the telephone
lines. Although actual driver output peak voltages and currents vary with each particular ADSL application, the
THS6022 is specified for a minimum full output current of 200 mA at its full output voltage of approximately 12 V.
This performance meets the demanding needs of ADSL at the client side end of the telephone line. A typical
ADSL schematic is shown in Figure 60
15 V
THS6022
Driver 1
VI+
0.1 mF
+
6.8 mF
50 W
+
_
1:1
1 kW
Telephone Line
100 W
1 kW
0.1 mF
6.8 mF
+
-15 V
1 kW
15 V
THS6022
Driver 2
VI-
15 V
0.1 mF
+
6.8 mF
2 kW
0.1 mF
50 W
+
_
1 kW
–
VO+
+
1 kW
THS6062
Receiver 1
–15 V
1 kW
0.1 mF
1 kW
6.8 mF
+
15 V
–15 V
2 kW
0.1 mF
1 kW
–
+
VO–
THS6062
Receiver 2
–15 V
0.01 mF
S0287-01
Figure 60. THS6022 ADSL Application
The ADSL transmit band consists of 255 separate carrier frequencies each with its own modulation and
amplitude level. With such an implementation, it is imperative that signals put onto the telephone line have as
low a distortion as possible. This is because any distortion either interferes directly with other ADSL carrier
frequencies or it creates intermodulation products that interfere with ADSL carrier frequencies.
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THS6022
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SLOS225D – SEPTEMBER 1998 – REVISED JULY 2007
The THS6022 has been specifically designed for ultralow distortion by careful circuit implementation and by
taking advantage of the superb characteristics of the complementary bipolar process. Driver single-ended
distortion measurements are shown in Figure 37 through Figure 40. It is commonly known that in the differential
driver configuration, the second-order harmonics tend to cancel out. Thus, the dominant total harmonic distortion
(THD) is primarily due to the third-order harmonics. Additionally, distortion should be reduced as the feedback
resistance drops. This is because the bandwidth of the amplifier increases, which allows the amplifier to react
faster to any nonlinearities in the closed-loop system.
Another significant point is the fact that distortion decreases as the impedance load increases. This is because
the output resistance of the amplifier becomes less significant as compared to the output load resistance. This is
illustrated in Figure 40.
One problem that has been receiving a lot of attention in the ADSL area is power dissipation. One way to
substantially reduce power dissipation is to lower the power supply voltages. This is because the RMS voltage of
an ADSL remote terminal signal is 1.35-V RMS. But to meet ADSL requirements, the drivers must have a
voltage RMS-to-peak crest factor of 5.6 in order to keep the bit-error probability rate below 10–7. Hence, the
power supply voltages must be high enough to accomplish the peak output voltage of 1.35 V × 5.6 = 7.6
V(PEAK). If ±15-V power supplies are used for the THS6022 drivers in the circuit shown in Figure 61, the power
dissipation of the THS6022 is approximately 600 mW. This is assuming that part of the quiescent current is
diverted back to the load, which typically happens in a class-AB amplifier. But if the power supplies are dropped
down to ±12 V, then the power dissipation drops to approximately 460 mW. This is a 23% reduction of power,
which ultimately lowers the temperature of the drivers and increases efficiency.
Another way to reduce power dissipation in the drivers is to increase the transformer ratio. The drawback in
doing this is that it increases the loading on the drivers and reduces the signals being received from the central
office. If this can be overcome, then a power reduction in the drivers results. By going to a 1:2 transformer ratio,
the power supply voltages can drop to ±6 V. The driver output voltage has now been reduced to 675 mV RMS.
But the loading on the output of the drivers drops to 25 Ω. The power dissipated is now approximately 360 mW,
a reduction of 22% over the previous example. But, the received signal is now 1/2 of the previous example. This
must be dealt with by requiring low-noise receivers. There are always trade offs when it comes to dealing with
power, so proper analysis of the system should always be considered.
General Configurations
A common error for the first-time CFB user is to create a unity-gain buffer amplifier by shorting the output
directly to the inverting input. A CFB amplifier in this configuration oscillates and is not recommended. The
THS6022, like all CFB amplifiers, must have a feedback resistor for stable operation. Additionally, placing
capacitors directly from the output to the inverting input is not recommended. This is because, at high
frequencies, a capacitor has a very low impedance. This results in an unstable amplifier and should not be
considered when using a current-feedback amplifier. Because of this, integrators and simple low-pass filters,
which are easily implemented on a VFB amplifier, must be designed slightly differently. If filtering is required,
simply place an RC-filter at the noninverting terminal of the operational-amplifier (see Figure 62).
RG
RF
–
VO
VI
+
R1
C1
f-3dB =
1
2pR1C1
VO æ
R öæ
1
ö
= ç 1 + F ÷÷ ç
÷
VI çè
RG ø è 1 + sR1C1 ø
S0281-01
Figure 61. Single-Pole Low-Pass Filter
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SLOS225D – SEPTEMBER 1998 – REVISED JULY 2007
If a multiple-pole filter is required, the use of a Sallen-Key filter can work very well with CFB amplifiers. This is
because the filtering elements are not in the negative feedback loop and stability is not compromised. Because
of their high slew-rates and high bandwidths, CFB amplifiers can create very accurate signals and help minimize
distortion. An example is shown in Figure 63
C1
R1 = R2 = R
C1 = C2 = C
Q = Peaking Factor
(Butterworth Q = 0.707)
VI
R1
+
_
R2
f-3dB =
C2
RG =
RF
RG
1
2pRC
RF
1ö
æ
ç2 - ÷
Qø
è
S0288-01
Figure 62. Two-Pole Low-Pass Sallen-Key Filter
There are two simple ways to create an integrator with a CFB amplifier. The first one, shown in Figure 64, adds
a resistor in series with the capacitor. This is acceptable because at high frequencies, the resistor is dominant
and the feedback impedance never drops below the resistor value. The second one, shown in Figure 65, uses
positive feedback to create the integration. Caution is advised because oscillations can occur because of the
positive feedback.
C1
RF
RG
–
VI
VO
+
VO æ RF
=ç
VI çè RG
THS6022
1 ö
æ
S+
÷
öç
R
C1 ÷
F
÷÷ ç
ç
÷
S
ø
ç
÷
è
ø
S0289-01
Figure 63. Inverting CFB Integrator
RG
RF
For Stable Operation:
–
THS6022
R1
+
VO
R2
VI
RA
C1
R
R2
³ F
R1|| R A RG
RF ö
æ
ç 1+
÷
RG ÷
ç
VO @ VI
ç sR1C1 ÷
ç
÷
è
ø
S0290-01
Figure 64. Noninverting CFB Integrator
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THS6022
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SLOS225D – SEPTEMBER 1998 – REVISED JULY 2007
Another good use for the THS6022 amplifiers is as very good video distribution amplifiers. One characteristic of
distribution amplifiers is the fact that the differential phase (DP) and the differential gain (DG) are compromised
as the number of lines increases and the closed-loop gain increases. Be sure to use termination resistors
throughout the distribution system to minimize reflections and capacitive loading.
715 W
715 W
+5V
THS6022
75 W Transmission Line
–
75 W
VO1
+
VI
75 W
75 W
–5V
N Lines
75 W
VON
75 W
S0291-01
Figure 65. Video Distribution Amplifier Application
Evaluation Board
An evaluation board is available for the THS6022 (literature number SLOP133). This board has been configured
for proper thermal management of the THS6022. The circuitry has been designed for a typical ADSL application
as shown previously in this document. For more detailed information, see the THS6022 250-mA Dual Differential
Drivers Evaluation Module user's guide (SLOV035). To order the evaluation board, contact your local TI sales
office or distributor.
34
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PACKAGE OPTION ADDENDUM
www.ti.com
6-Feb-2020
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
Lead/Ball Finish
MSL Peak Temp
(2)
(6)
(3)
Op Temp (°C)
Device Marking
(4/5)
THS6022CPWP
ACTIVE
HTSSOP
PWP
14
90
Green (RoHS
& no Sb/Br)
NIPDAU
Level-2-260C-1 YEAR
0 to 70
HS6022C
THS6022CPWPR
ACTIVE
HTSSOP
PWP
14
2000
Green (RoHS
& no Sb/Br)
NIPDAU
Level-2-260C-1 YEAR
0 to 70
HS6022C
THS6022IPWP
ACTIVE
HTSSOP
PWP
14
90
Green (RoHS
& no Sb/Br)
NIPDAU
Level-2-260C-1 YEAR
-40 to 85
HS6022I
THS6022IPWPR
ACTIVE
HTSSOP
PWP
14
2000
Green (RoHS
& no Sb/Br)
NIPDAU
Level-2-260C-1 YEAR
THS6022IPWPRG4
ACTIVE
HTSSOP
PWP
14
2000
Green (RoHS
& no Sb/Br)
NIPDAU
Level-2-260C-1 YEAR
HS6022I
-40 to 85
HS6022I
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of
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