THS6214IPWP

Order Now Product Folder Support & Community Tools & Software Technical Documents THS6214 SBOS431A – MAY 2009 – REVISED MARCH 2017 THS6214 Dual-Port, Differential, VDSL2 Line Driver Amplifiers 1 Features 3 Description • The THS6214 is a dual-port, current-feedback architecture, differential line driver amplifier system ideal for xDSL systems. The device is targeted for use in very-high-bit-rate digital subscriber line 2 (VDSL2) line driver systems that enable greater than 14.5-dBm line power, supporting the G.993.2 VDSL2 17a profile. The device is also fast enough to support central-office transmissions of 14.5-dBm line power up to 30 MHz. The device is also targeted for use as a broadband or wideband power line communications (PLC) amplifier for line driver applications. 1 • • • • • • • • Low Power Consumption: – Full Bias Mode: 21 mA per Port – Mid Bias Mode: 16.2 mA per Port – Low Bias Mode: 11.2 mA per Port – Low-Power Shutdown Mode – IADJ Pin for Variable Bias Low Noise: – Voltage Noise: 2.7 nV/√Hz – Inverting Current Noise: 17 pA/√Hz – Noninverting Current Noise: 1.2 pA/√Hz Low MTPR Distortion: – 70 dB with 20.5 dBm G.993.2—Profile 8b –93 dBc HD3 (1 MHz, 100-Ω Differential) High Output Current: > 416 mA (25-Ω Load) Wide Output Swing: 43.2 VPP (±12 V, 100-Ω Differential Load) Wide Bandwidth: 150 MHz (GDIFF = 10 V/V) PSRR: 50 dB at 1 MHz for Good Isolation Wide Power-Supply Range: 10 V to 28 V The unique architecture of the THS6214 uses minimal quiescent current and still achieves very high linearity. Differential distortion, under full bias conditions, is –93 dBc at 1 MHz and reduces to only –73 dBc at 10 MHz. Fixed multiple bias settings of the amplifiers allow for enhanced power savings for line lengths where the full performance of the amplifier is not required. To allow for even more flexibility and power savings, an adjustable current pin (IADJ) is available to further lower the bias currents. 2 Applications The wide output swing of 43.2 VPP (100-Ω differential load) with ±12-V power supplies, coupled with over 416-mA current drive (25-Ω load), allows for wide dynamic headroom, keeping distortion minimal. • • The THS6214 is available in a VQFN-24 or a HTSSOP-24 PowerPAD™ package. • Ideal For VDSL2 Systems Backwards-Compatible with ADSL, ADSL2+, ADSL2++ Systems Broadband Power Line Communications Device Information(1) PART NUMBER THS6214 PACKAGE BODY SIZE (NOM) VQFN (24) 5.00 mm × 4.00 mm HTSSOP (24) 7.80 mm × 4.40 mm (1) For all available packages, see the orderable addendum at the end of the data sheet. Typical VDSL2 Line Driver Circuit Using One Port of the THS6214 12 V RS RT RF RP RG 100 W RP RF RS IADJ RT 12 V 1 An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. PRODUCTION DATA. THS6214 SBOS431A – MAY 2009 – REVISED MARCH 2017 www.ti.com Table of Contents 1 2 3 4 5 6 Features .................................................................. Applications ........................................................... Description ............................................................. Revision History..................................................... Pin Configuration and Functions ......................... Specifications......................................................... 6.1 6.2 6.3 6.4 6.5 6.6 6.7 6.8 6.9 6.10 6.11 6.12 6.13 1 1 1 2 3 4 Absolute Maximum Ratings ...................................... 4 ESD Ratings.............................................................. 5 Recommended Operating Conditions....................... 5 Thermal Information .................................................. 5 Electrical Characteristics: VS = ±12 V....................... 6 Electrical Characteristics: VS = ±6 V......................... 8 Timing Requirements .............................................. 10 Typical Characteristics: VS = ±12 V, Full Bias ........ 11 Typical Characteristics: VS = ±12 V, Mid Bias ........ 14 Typical Characteristics: VS = ±12 V, Low Bias ..... 16 Typical Characteristics: VS = ±6 V, Full Bias ........ 18 Typical Characteristics: VS = ±6 V, Mid Bias ........ 21 Typical Characteristics: VS = ±6 V, Low Bias ....... 23 7 Detailed Description ............................................ 25 7.1 7.2 7.3 7.4 8 Overview ................................................................. Functional Block Diagram ....................................... Feature Description................................................. Device Functional Modes........................................ 25 25 25 28 Application and Implementation ........................ 29 8.1 Application Information............................................ 29 8.2 Typical Applications ................................................ 29 9 Power Supply Recommendations...................... 35 10 Layout................................................................... 36 10.1 Board Layout Guidelines....................................... 36 10.2 Layout Example .................................................... 37 11 Device and Documentation Support ................. 38 11.1 11.2 11.3 11.4 11.5 Receiving Notification of Documentation Updates Community Resources.......................................... Trademarks ........................................................... Electrostatic Discharge Caution ............................ Glossary ................................................................ 38 38 38 38 38 12 Mechanical, Packaging, and Orderable Information ........................................................... 38 4 Revision History Changes from Original (May 2009) to Revision A Page • Added Device Information table, Pin Functions table, ESD Ratings table, Recommended Operating Conditions table, Thermal Information table, Timing Requirements table, Overview section, Functional Block Diagram section, Feature Description section, Device Functional Modes section, Application and Implementation section, Power Supply Recommendations section, Layout section, Device and Documentation Support section, and Mechanical, Packaging, and Orderable Information section ...................................................................................................................... 1 • Added last Applications bullet ................................................................................................................................................ 1 • Added last sentence to first paragraph of Description section .............................................................................................. 1 • Changed QFN to VQFN and TSSOP to HTSSOP throughout document ............................................................................. 1 • Deleted Ordering Information table ....................................................................................................................................... 3 • Deleted Dissipation Ratings table .......................................................................................................................................... 5 • Changed second paragraph of Distortion Performance section for clarity........................................................................... 26 2 Submit Documentation Feedback Copyright © 2009–2017, Texas Instruments Incorporated Product Folder Links: THS6214 THS6214 www.ti.com SBOS431A – MAY 2009 – REVISED MARCH 2017 5 Pin Configuration and Functions VS+ D1 OUT PWP Package 24-Pin HTSSOP Top View 20 22 21 VS- BIAS-1/D1D2 23 24 BIAS-2/D1D2 RHF Package 24-Pin VQFN Top View VS- 1 24 VS+ BIAS-1/D1D2 2 23 D1 OUT BIAS-2/D1D2 3 22 D1 FB D1 IN+ 4 21 D2 FB D2 IN+ 5 20 D2 OUT GND 6 19 NC D1 IN+ 1 19 D1 FB D2 IN+ 2 18 D2 FB GND 3 17 D2 OUT IADJ 7 18 NC IADJ 4 16 NC D3 IN+ 8 17 D3 OUT NC 5 15 D3 OUT D4 IN+ 9 16 D3 FB D3 IN+ 6 14 D3 FB BIAS-2/D3D4 10 15 D4 FB D4 IN+ 7 13 D4 FB BIAS-1/D3D4 11 14 D4 OUT VS- 12 13 VS+ 8 9 10 11 12 BIAS-2/D3D4 BIAS-1/D3D4 VS- VS+ D4 OUT PowerPAD PowerPAD (1) The PowerPAD is electrically isolated from all other pins and can be connected to any potential voltage range from VS– to VS+. Typically, the PowerPAD is connected to the GND plane because this plane tends to physically be the largest and is able to dissipate the most amount of heat. (2) The THS6214 defaults to the shutdown (disable) state if no signal is present on the bias pins. (3) The GND pin range is from VS– to (VS+ – 5 V). NOTE: NC = no connection. Pin Functions (1) PIN NAME NO. RHF I/O DESCRIPTION PWP BIAS-1/D1D2 23 2 I Bias mode parallel control for port A, LSB BIAS-1/D3D4 9 11 I Bias mode parallel control for port B, LSB BIAS-2/D1D2 24 3 I Bias mode parallel control for port A, MSB BIAS-2/D3D4 8 10 I Bias mode parallel control for port B, MSB D1 FB 19 22 I Amplifier D1 inverting input D2 FB 18 21 I Amplifier D2 inverting input D3 FB 14 16 I Amplifier D3 inverting input D4 FB 13 15 I Amplifier D4 inverting input D1 IN+ 1 4 I Amplifier D1 noninverting input D2 IN+ 2 5 I Amplifier D2 noninverting input D3 IN+ 6 8 I Amplifier D3 noninverting input D4 IN+ 7 9 I Amplifier D4 noninverting input D1 OUT 20 23 O Amplifier D1 output D2 OUT 17 20 O Amplifier D2 output (1) The THS6214 defaults to the shutdown (disable) state if no signal is present on the bias pins. Submit Documentation Feedback Copyright © 2009–2017, Texas Instruments Incorporated Product Folder Links: THS6214 3 THS6214 SBOS431A – MAY 2009 – REVISED MARCH 2017 www.ti.com Pin Functions(1) (continued) PIN NO. NAME I/O DESCRIPTION RHF PWP D3 OUT 15 17 O Amplifier D3 output D4 OUT 12 14 O Amplifier D4 output GND (2) 3 6 I/O Control pin ground reference IADJ 4 7 I/O Bias current adjustment pin NC 5, 16 18, 19 — No internal connection VS– 10, 22 1, 12 I/O Negative power-supply connection VS+ 11, 21 11, 24 I/O Positive power-supply connection (2) The GND pin range is from VS– to (VS+ – 5 V). Table 1. BIAS-1, BIAS-2 Logic Table BIAS-1 BIAS-0 FUNCTION DESCRITPION 0 0 Full bias mode (100%) Amplifiers on with lowest distortion possible (default state) 1 0 Mid bias mode (75%) Amplifiers on with power savings and a reduction in distortion performance 0 1 Low bias mode (50%) Amplifiers on with enhanced power savings and a reduction of overall performance 1 1 Shutdown mode Amplifiers off and output has high impedance 6 Specifications 6.1 Absolute Maximum Ratings over operating free-air temperature range (unless otherwise noted) (1) MIN Supply voltage, VS– to VS+ Input voltage, VI Differential input voltage, VID Output current, IO Static dc (2) Continuous power dissipation Storage temperature, Tstg (2) (3) (4) 4 28 V ±VS V ±2 V ±500 mA 150 Continuous operation, long-term reliability (4), RHF package only Continuous operation, long-term reliability PWP package only (1) UNIT See Thermal Information Under any condition (3) Maximum junction temperature, TJ MAX 130 °C (4) , 140 –65 150 °C Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. The THS6214 incorporates a PowerPAD on the underside of the chip. This pad functions as a heatsink and must be connected to a thermally dissipating plane for proper power dissipation. Failure to do so may result in exceeding the maximum junction temperature, which can permanently damage the device. See PowerPAD™ Thermally Enhanced Package (SLMA002) for more information about using the PowerPAD thermally-enhanced package. Under high-frequency ac operation (greater than 10 kHz), the short-term output current capability is much greater than the continuous dc output current rating. This short-term output current rating is approximately 8.5 times the dc capability, or approximately ±850 mA. The absolute maximum junction temperature under any condition is limited by the constraints of the silicon process. The absolute maximum junction temperature for continuous operation is limited by the package constraints. Operation above this temperature may result in reduced reliability and/or lifetime of the device. Submit Documentation Feedback Copyright © 2009–2017, Texas Instruments Incorporated Product Folder Links: THS6214 THS6214 www.ti.com SBOS431A – MAY 2009 – REVISED MARCH 2017 6.2 ESD Ratings VALUE V(ESD) (1) (2) Electrostatic discharge Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001 (1) ±2000 Charged-device model (CDM), per JEDEC specification JESD22-C101 (2) ±500 Machine model (MM) ±100 UNIT V JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process. 6.3 Recommended Operating Conditions over operating free-air temperature range (unless otherwise noted) MIN VS Supply voltage, VS– to VS+ TJ Operating junction temperature TA Ambient operating air temperature NOM MAX 10 25 UNIT 28 V 130 °C 85 °C 6.4 Thermal Information THS6214 THERMAL METRIC (1) RHF (VQFN) PWP (HTSSOP) 24 PINS 24 PINS UNIT RθJA Junction-to-ambient thermal resistance 33.2 35.7 °C/W RθJC(top) Junction-to-case (top) thermal resistance 31.7 22.9 °C/W RθJB Junction-to-board thermal resistance 11.3 10.1 °C/W ψJT Junction-to-top characterization parameter 0.4 0.4 °C/W ψJB Junction-to-board characterization parameter 11.3 10.3 °C/W RθJC(bot) Junction-to-case (bottom) thermal resistance 3.9 1.7 °C/W (1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report. Submit Documentation Feedback Copyright © 2009–2017, Texas Instruments Incorporated Product Folder Links: THS6214 5 THS6214 SBOS431A – MAY 2009 – REVISED MARCH 2017 www.ti.com 6.5 Electrical Characteristics: VS = ±12 V at TA = 25°C, GDIFF = 10 V/V with RL = 100-Ω differential load, RADJ = 0 Ω, active impedance circuit configuration, and full bias (unless otherwise noted); each port is independently tested PARAMETER TEST CONDITIONS MIN TYP MAX UNIT TEST LEVEL (1) AC PERFORMANCE GDIFF = 5 V/V , RF = 1.5 kΩ, VO = 2 VPP Small-signal bandwidth, –3 dB 160 GDIFF = 10 V/V , RF = 1.5 kΩ, VO = 2 VPP 120 Over –40°C to +85°C temperature range 100 C 150 MHz B 0.1-dB bandwidth flatness GDIFF = 10 V/V , RF = 1.24 kΩ 114 MHz C Large-signal bandwidth GDIFF = 10 V/V , RF = 1.24 kΩ, VO = 20 VPP 120 MHz C Slew rate (10% to 90% level) Rise and fall time GDIFF = 10 V/V, VO = 20-V step, differential 3200 TA = –40°C to +85°C 3000 GDIFF = 10 V/V, VO = 2 VPP 3800 5 Full bias, f = 1 MHz –100 TA = –40°C to +85°C 2nd-order harmonic distortion GDIFF = 10 V/V, VO = 2 VPP, RL = 100-Ω differential Low bias, f = 1 MHz –96 Full bias, f = 10 MHz –75 Low bias, f = 10 MHz –72 Full bias, f = 1 MHz –89 Low bias, f = 1 MHz –85 Full bias, f = 10 MHz –73 Differential inverting current noise dBc 2.7 TA = –40°C to +85°C 1.2 TA = –40°C to +85°C –65 B B dBc 17 TA = –40°C to +85°C C B B C 3.2 1.4 1.6 f = 1 MHz B B –85 3.5 f = 1 MHz C C –58 f = 1 MHz, input-referred B C B –53 Low bias, f = 10 MHz Differential noninverting current noise –70 B B –80 TA = –40°C to +85°C Differential input voltage noise –95 –65 TA = –40°C to +85°C 3rd-order harmonic distortion ns –90 TA = –40°C to +85°C GDIFF = 10 V/V, VO = 2 VPP, RL = 100-Ω differential V/µs 20 24 nV/√Hz pA/√Hz pA/√Hz B B B B B B DC PERFORMANCE Open-loop transimpedance gain Input offset voltage Input offset voltage drift Input offset voltage matching Noninverting input bias current Noninverting input bias current drift Inverting input bias current Inverting input bias current drift Inverting input bias current matching (1) (2) 6 330 (2) RL = 100 Ω 700 kΩ 300 ±15 ±50 (2) TA = –40°C to +85°C ±60 TA = –40°C to +85°C ±155 ±0.5 TA = –40°C to +85°C ±5 (2) ±7 ±1 ±3.5 ±5.5 TA = –40°C to +85°C ±30 (2) ±45 (2) TA = –40°C to +85°C ±55 TA = –40°C to +85°C ±154 ±8 TA = –40°C to +85°C µV/°C mV (2) TA = –40°C to +85°C ±8 mV ±30 (2) ±40 µA nA/°C µA nA/°C µA A B A B B A B A B B A B B A B Test levels: (A) 100% tested at 25°C. Overtemperature limits set by characterization and simulation. (B) Limits set by characterization and simulation. (C) Typical value only for information. This specification is 100% tested at 25°C. Submit Documentation Feedback Copyright © 2009–2017, Texas Instruments Incorporated Product Folder Links: THS6214 THS6214 www.ti.com SBOS431A – MAY 2009 – REVISED MARCH 2017 Electrical Characteristics: VS = ±12 V (continued) at TA = 25°C, GDIFF = 10 V/V with RL = 100-Ω differential load, RADJ = 0 Ω, active impedance circuit configuration, and full bias (unless otherwise noted); each port is independently tested PARAMETER TEST CONDITIONS MIN TYP Each input ±9 (2) ±9.5 TA = –40°C to +85°C ±8.6 Each input 53 (2) MAX UNIT TEST LEVEL (1) INPUT CHARACTERISTICS Common-mode input range Common-mode rejection ratio TA = –40°C to +85°C V 65 dB 49 Noninverting input resistance 500 || 2 Inverting input resistance 50 A B A B kΩ || pF C Ω C OUTPUT CHARACTERISTICS (3) RL = 100 Ω, each output RL = 50 Ω, each output Output voltage swing TA = –40°C to +85°C RL = 25 Ω, each output TA = –40°C to +85°C Output current (sourcing and sinking) RL = 25 Ω, based on VO tests TA = –40°C to +85°C ±10.9 ±10.6 (2) C ±10.8 A ±10.4 ±10.2 (2) V ±10.4 A ±10 ±408 (2) B ±416 mA ±400 Short-circuit output current B 1 A B A C Output impedance f = 1 MHz, differential 0.2 Ω C Crosstalk f = 1 MHz, VO = 2 VPP, port 1 to port 2 –90 dB C POWER SUPPLY Operating voltage ±5 (2) TA = –40°C to +85°C Per port, full bias (BIAS-1 = 0, BIAS-2 = 0) TA = –40°C to +85°C IS+ quiescent current ±5 19.5 (2) 15 (2) TA = –40°C to +85°C 12.8 Per port, low bias (BIAS-1 = 0, BIAS-2 = 1) 10 (2) 21 16.2 11.2 0.4 TA = –40°C to +85°C IS– quiescent current 18.5 (2) 20 16 A B 17.4 (2) A 12.4 (2) A 1 B 21.5 (2) A 23 B 16.4 (2) A 11.8 17.6 (2) (2) 9 7.1 Per port, bias off (BIAS-1 = 1, BIAS-2 = 1) 10.2 0.1 TA = –40°C to +85°C Current through GND pin +PSRR Positive power-supply rejection ratio Negative power-supply rejection –PSRR ratio (3) 1 54 (2) Differential TA = –40°C to +85°C TA = –40°C to +85°C 66 52 52 (2) Differential 11.6 mA 50 65 B A 11.4 B 0.3 (2) A 0.8 Per port, full bias (BIAS-1 = 0, BIAS-2 = 0) A B TA = –40°C to +85°C TA = –40°C to +85°C B 0.8 (2) 14 (2) Per port, low bias (BIAS-1 = 0, BIAS-2 = 1) mA 13.2 Per port, mid bias (BIAS-1 = 1, BIAS-2 = 0) 15.2 A C 24 TA = –40°C to +85°C Per port, full bias (BIAS-1 = 0, BIAS-2 = 0) V 22.5 (2) 18.6 8.1 Per port, bias off (BIAS-1 = 1, BIAS-2 = 1) ±14 (2) ±14 17 Per port, mid bias (BIAS-1 = 1, BIAS-2 = 0) TA = –40°C to +85°C ±12 B mA dB dB C A B A B Test circuit is shown in Figure 1. Submit Documentation Feedback Copyright © 2009–2017, Texas Instruments Incorporated Product Folder Links: THS6214 7 THS6214 SBOS431A – MAY 2009 – REVISED MARCH 2017 www.ti.com Electrical Characteristics: VS = ±12 V (continued) at TA = 25°C, GDIFF = 10 V/V with RL = 100-Ω differential load, RADJ = 0 Ω, active impedance circuit configuration, and full bias (unless otherwise noted); each port is independently tested PARAMETER TEST CONDITIONS MIN TYP MAX UNIT TEST LEVEL (1) LOGIC Bias control pin logic threshold Logic 1, with respect to GND (4), TA = –40°C to +85°C 1.9 Logic 0, with respect to GND , TA = –40°C to +85°C BIAS-1, BIAS-2 = 0.5 V (logic 0) Bias pin quiescent current B V (4) 20 TA = –40°C to +85°C BIAS-1, BIAS-2 = 3.3 V (logic 1) 0.3 A 30 1 (2) µA 1.2 Bias pin input impedance (4) B (2) 35 TA = –40°C to +85°C Amplifier output impedance 0.8 50 Off bias (BIAS-1 = 1, BIAS-2 = 1) 10 || 5 B A B kΩ C kΩ || pF C The GND pin usable range is from VS– to (VS+ – 5 V). 6.6 Electrical Characteristics: VS = ±6 V at TA = 25°C, GDIFF = 5 V/V with RL = 100-Ω differential load, RADJ = 0 Ω, active impedance circuit configuration, and full bias (unless otherwise noted); each port is independently tested PARAMETER TEST CONDITIONS MIN TYP MAX UNIT TEST LEVEL (1) AC PERFORMANCE GDIFF = 5 V/V , RF = 1.5 kΩ, VO = 2 VPP Small-signal bandwidth, –3 dB 140 GDIFF = 10 V/V , RF = 1.5 kΩ, VO = 2 VPP 110 Over –40°C to +85°C temperature range 95 MHz GDIFF = 10 V/V , RF = 1.24 kΩ 100 MHz C Large-signal bandwidth GDIFF = 10 V/V , RF = 1.24 kΩ, VO = 20 VPP 120 MHz C Rise and fall time GDIFF = 10 V/V, VO = 20-V step, differential 1200 TA = –40°C to +85°C 1000 GDIFF = 10 V/V, VO = 2 VPP Full bias 1600 2nd-order harmonic distortion GDIFF = 10 V/V, VO = 2 VPP, RL = 100-Ω differential –98 Low bias –93 Full bias –80 Low bias –74 Full bias –93 –89 Full bias –66 TA = –40°C to +85°C Differential input voltage noise Differential noninverting current noise Differential inverting current noise f = 1 MHz, input-referred TA = –40°C to +85°C TA = –40°C to +85°C B B –84 –60 B B dBc C B B C 3.0 1.4 1.6 17 C C 3.3 1.2 f = 1 MHz dBc –55 2.5 B C B –54 TA = –40°C to +85°C f = 1 MHz –75 B B –79 Low bias Low bias –92 –68 TA = –40°C to +85°C 3rd-order harmonic distortion ns –87 TA = –40°C to +85°C GDIFF = 10 V/V, VO = 2 VPP, RL = 100-Ω differential V/µs 5 TA = –40°C to +85°C 8 B 0.1-dB bandwidth flatness Slew rate (10% to 90% level) (1) C 140 20 24 nV/√Hz pA/√Hz pA/√Hz B B B B B B Test levels: (A) 100% tested at 25°C. Overtemperature limits set by characterization and simulation. (B) Limits set by characterization and simulation. (C) Typical value only for information. Submit Documentation Feedback Copyright © 2009–2017, Texas Instruments Incorporated Product Folder Links: THS6214 THS6214 www.ti.com SBOS431A – MAY 2009 – REVISED MARCH 2017 Electrical Characteristics: VS = ±6 V (continued) at TA = 25°C, GDIFF = 5 V/V with RL = 100-Ω differential load, RADJ = 0 Ω, active impedance circuit configuration, and full bias (unless otherwise noted); each port is independently tested PARAMETER TEST CONDITIONS MIN TYP 330 (2) 650 MAX UNIT TEST LEVEL (1) DC PERFORMANCE Open-loop transimpedance gain Input offset voltage Input offset voltage drift Input offset voltage matching Noninverting input bias current Noninverting input bias current drift Inverting input bias current Inverting input bias current drift Inverting input bias current matching RL = 100 Ω TA = –40°C to +85°C kΩ 300 ±10 ±45 (2) TA = –40°C to +85°C ±55 TA = –40°C to +85°C ±155 Channels 1 to 2 and 3 to 4 only ±0.5 TA = –40°C to +85°C ±5 (2) ±7 ±1 ±3.5 (2) TA = –40°C to +85°C ±5.5 TA = –40°C to +85°C ±30 (2) ±8 TA = –40°C to +85°C ±45 (2) ±55 TA = –40°C to +85°C ±135 ±8 TA = –40°C to +85°C ±30 (2) ±40 mV µV/°C mV µA nA/°C µA nA/°C µA A B A B B A B A B B A B B A B INPUT CHARACTERISTICS Common-mode input range Common-mode rejection ratio ±2.9 (2) Each input TA = –40°C to +85°C ±2.7 Each input 51 (2) TA = –40°C to +85°C ±3.0 62 47 Noninverting input resistance 500 || 2 Inverting input resistance 55 V dB A B A B kΩ || pF C Ω C OUTPUT CHARACTERISTICS (3) RL = 100 Ω, each output RL = 50 Ω, each output Output voltage swing TA = –40°C to +85°C RL = 25 Ω, each output TA = –40°C to +85°C Output current (sourcing and sinking) RL = 25 Ω, based on VO tests TA = –40°C to +85°C Short-circuit output current (2) (3) ±4.9 ±4.75 (2) ±4.6 ±4.55 (2) C ±4.9 A V ±4.7 A ±4.4 ±182 (2) B B ±188 ±176 mA A B ±1 A C Output impedance f = 1 MHz, differential 0.2 Ω C Crosstalk f = 1 MHz, VO = 2 VPP, port 1 to port 2 –90 dB C This specification is 100% tested at 25°C. Test circuit is shown in Figure 1. Submit Documentation Feedback Copyright © 2009–2017, Texas Instruments Incorporated Product Folder Links: THS6214 9 THS6214 SBOS431A – MAY 2009 – REVISED MARCH 2017 www.ti.com Electrical Characteristics: VS = ±6 V (continued) at TA = 25°C, GDIFF = 5 V/V with RL = 100-Ω differential load, RADJ = 0 Ω, active impedance circuit configuration, and full bias (unless otherwise noted); each port is independently tested PARAMETER TEST CONDITIONS MIN TYP MAX ±5 (2) ±6 ±14 (2) UNIT TEST LEVEL (1) POWER SUPPLY Operating voltage TA = –40°C to +85°C ±5 Per port, full bias (BIAS-1 = 0, BIAS-2 = 0) TA = –40°C to +85°C 13 (2) 17 TA = –40°C to +85°C 10.2 (2) 13.2 9.3 Per port, low bias (BIAS-1 = 0, BIAS-2 = 1) TA = –40°C to +85°C 9.4 6.7 A B 16.2 (2) A 11.4 (2) IS– quiescent current TA = –40°C to +85°C A 0.9 B 20 (2) A 9 21 B (2) (2) A 12 (2) 9.2 16 12.2 8.3 Per port, low bias (BIAS-1 = 0, BIAS-2 = 1) TA = –40°C to +85°C 15.2 15.4 6.4 (2) 8.4 5.7 Per port, bias off (BIAS-1 = 1, BIAS-2 = 1) 0.1 10.4 (2) +PSRR Positive power-supply rejection ratio Negative power-supply rejection –PSRR ratio mA B A 1 54 (2) Differential TA = –40°C to +85°C 64 52 (2) TA = –40°C to +85°C B mA dB 52 Differential A 0.3 (2) 0.5 Per port, full bias (BIAS-1 = 0, BIAS-2 = 0) B 10.6 TA = –40°C to +85°C Current through GND pin A B TA = –40°C to +85°C Per port, mid bias (BIAS-1 = 1, BIAS-2 = 0) B 0.8 (2) 0.5 TA = –40°C to +85°C mA 11.6 Per port, bias off (BIAS-1 = 1, BIAS-2 = 1) Per port, full bias (BIAS-1 = 0, BIAS-2 = 0) A C 22 16.4 7.4 (2) V 21 (2) 10 Per port, mid bias (BIAS-1 = 1, BIAS-2 = 0) IS+ quiescent current ±14 63 dB 50 C A B A B LOGIC Bias control pin logic threshold Logic 1, with respect to GND (4), TA = –40°C to +85°C 1.9 B V (4) Logic 0, with respect to GND , TA = –40°C to +85°C BIAS-1, BIAS-2 = 0.5 V (logic 0) Bias pin quiescent current 20 0.8 B 30 (2) A TA = –40°C to +85°C 35 BIAS-1, BIAS-2 = 3.3 V (logic 1) 1 (2) 0.3 TA = –40°C to +85°C 1.2 Bias pin input impedance Amplifier output impedance (4) 50 Off bias (BIAS-1 = 1, BIAS-2 = 1) µA 10 || 5 B A B kΩ C kΩ || pF C The GND pin usable range is from VS– to (VS+ – 5 V). 6.7 Timing Requirements MIN NOM MAX UNIT tON Turn-on time delay: time for IS to reach 50% of final value 1 µs tOFF Turn-off time delay: time for IS to reach 50% of final value 1 µs 10 Submit Documentation Feedback Copyright © 2009–2017, Texas Instruments Incorporated Product Folder Links: THS6214 THS6214 www.ti.com SBOS431A – MAY 2009 – REVISED MARCH 2017 6.8 Typical Characteristics: VS = ±12 V, Full Bias at TA = 25°C, GDIFF = 10 V/V, GCM = 1 V/V, RADJ = 0 Ω, RF = 1.24 kΩ, and RL = 100 Ω (unless otherwise noted) 3 0 -3 -6 GDIFF = 10 V/V RF = 1.24 kW -9 Full Bias Normalized Gain (dB) 0 Normalized Gain (dB) 3 GDIFF = 5 V/V RF = 1.5 kW -12 -3 -6 75% Bias -9 -12 50% Bias -15 -15 -18 10M 100M -18 10M 400M 100M VO = 2 VPP VO = 2 VPP Figure 1. Small-Signal Frequency Response Figure 2. Small-Signal Frequency Response vs Bias Mode 12 1.2 0 8 0.8 -3 VO = 4 VPP -6 VO = 2 VPP VO = 20 VPP -9 -12 VO = 8 VPP Output Voltage (V) 3 4 0 0 -4 -0.4 Large-Signal Pulse Response (±10 VP) Left Scale -8 -15 -18 0.4 Small-Signal ±500 mVP Right Scale -0.8 -12 0 120 60 180 240 Output Voltage (V) Normalized Gain (dB) 400M Frequency (Hz) Frequency (Hz) -1.2 300 Time (10 ns/div) Frequency (MHz) Figure 4. Pulse Response Figure 3. Large-Signal Frequency Response 23 100 22 pF 20 470 pF Gain (dB) RS (W) 17 10 100 pF 14 THS6214 10 100 1000 CL VIN 1 kW VOUT Optional RS 5 1 47 pF 11 8 1 39 pF RS THS6214 2 10M 100M 300M Frequency (Hz) Capacitive Load (pF) RS optimized for 100% bias Figure 5. Recommended RS vs Capacitive Load Figure 6. Frequency Response vs Capacitive Load Submit Documentation Feedback Copyright © 2009–2017, Texas Instruments Incorporated Product Folder Links: THS6214 11 THS6214 SBOS431A – MAY 2009 – REVISED MARCH 2017 www.ti.com Typical Characteristics: VS = ±12 V, Full Bias (continued) at TA = 25°C, GDIFF = 10 V/V, GCM = 1 V/V, RADJ = 0 Ω, RF = 1.24 kΩ, and RL = 100 Ω (unless otherwise noted) -60 -60 Third Harmonic -70 -80 Second Harmonic -90 -100 -110 400k -70 Harmonic Distortion (dBc) Harmonic Distortion (dBc) -50 Third Harmonic -80 -90 -100 Second Harmonic -110 -120 10M 1M 40M 0.5 1 10 Frequency (Hz) VO = 2 VPP f = 1 MHz Figure 7. Harmonic Distortion vs Frequency Figure 8. Harmonic Distortion vs Output Voltage -70 -80 -82 Third Harmonic -84 -86 -88 -90 Third Harmonic -92 -94 -96 -80 Harmonic Distortion (dBc) Harmonic Distortion (dBc) 20 Output Voltage (VPP) Second Harmonic -90 -100 Second Harmonic -110 -98 -120 -100 4 5 6 7 8 9 10 11 50 12 100 1k Resistance (W) Supply Voltage (±VS) VO = 2 VPP, f = 1 MHz VO = 2 VPP, f = 1 MHz Figure 10. Harmonic Distortion vs Load Resistance Figure 9. Harmonic Distortion vs Supply Voltage -85 55 Third Harmonic Intercept Point (dBm) Harmonic Distortion (dBc) 50 -90 -95 -100 Second Harmonic -105 45 40 35 30 25 20 -110 15 1 10 30 0 Gain (V/V) 5 10 15 20 25 30 Frequency (MHz) VO = 2 VPP, f = 1 MHz Figure 11. Harmonic Distortion vs Noninverting Gain 12 Figure 12. Two-Tone, Third-Order Intermodulation Intercept Submit Documentation Feedback Copyright © 2009–2017, Texas Instruments Incorporated Product Folder Links: THS6214 THS6214 www.ti.com SBOS431A – MAY 2009 – REVISED MARCH 2017 Typical Characteristics: VS = ±12 V, Full Bias (continued) Output Voltage (V) 12 10 8 6 4 2 0 -2 1-W Internal -4 Power Dissipation -6 -8 -10 -12 -14 -600 -400 -200 Output Voltage Noise Density (nV/ÖHz) Input Current Noise Density (pA/ÖHz) at TA = 25°C, GDIFF = 10 V/V, GCM = 1 V/V, RADJ = 0 Ω, RF = 1.24 kΩ, and RL = 100 Ω (unless otherwise noted) 1-W Internal Power Dissipation 50-W Load Line 100-W Load Line 1000 100 Inverting Current Noise (17.4 pA/ÖHz) Voltage Noise (2.7 nV/ÖHz) 10 Noninverting Current Noise (1.2 pV/ÖHz) 1 0 200 1k 100 600 400 10k 100k 1M 10M Frequency (Hz) Output Current (mA) Voltage and current noise contributing to differential noise Figure 14. Input Voltage and Current Noise Density Figure 13. Output Voltage and Current Limitations 60 Power-Supply Rejection Ratio (dB) Quiescent Current (±IQ, mA) 25 20 15 +IQ 10 -IQ 5 -PSRR 50 +PSRR 40 30 20 10 0 0 0 1 2 3 4 5 1k 6 10k 100k 1M 10M 100M Frequency (Hz) RADJ (kW) Figure 16. PSRR vs Frequency Figure 15. Quiescent Current for Full Bias Setting vs RADJ 140 0 10 -45 100 -90 Phase 80 -135 60 -180 40 -225 20 -270 0 -315 10k 100k 1M 10M 100M 1G Output Impedance (W) 120 Transimpedance Phase (°) Transimpedance Gain (dBW) Gain 1 0.1 0.01 0.001 100k Frequency (Hz) 1M 10M 100M Frequency (Hz) Figure 17. Open-Loop Gain and Phase Figure 18. Closed-Loop Output Impedance Submit Documentation Feedback Copyright © 2009–2017, Texas Instruments Incorporated Product Folder Links: THS6214 13 THS6214 SBOS431A – MAY 2009 – REVISED MARCH 2017 www.ti.com 6.9 Typical Characteristics: VS = ±12 V, Mid Bias at TA = 25°C, GDIFF = 10 V/V, GCM = 1 V/V, RADJ = 0 Ω, RF = 1.24 kΩ, and RL = 100 Ω (unless otherwise noted) 3 0 Normalized Gain (dB) 0 Normalized Gain (dB) 3 GDIFF = 5 V/V RF = 1.5 kW -3 -6 GDIFF = 10 V/V RF = 1.24 kW -9 -12 -3 VO = 20 VPP VO = 4 VPP -6 -9 VO = 8 VPP -12 VO = 2 VPP -15 -15 -18 -18 10M 100M 0 400M 20 40 60 80 100 120 140 160 180 200 220 240 260 Frequency (MHz) Frequency (Hz) VO = 2 VPP Figure 19. Small-Signal Frequency Response Figure 20. Large-Signal Frequency Response 12 1.2 8 0.8 18 0.4 Small-Signal ±500 mVP Right Scale 0 0 -4 -0.4 Large-Signal Pulse Response (±10 VP) Left Scale -8 -12 -0.8 Quiescent Current (±IQ, mA) 4 Output Voltage (V) Output Voltage (V) 16 14 12 10 8 +IQ 6 -IQ 4 2 -1.2 0 Time (10 ns/div) 0 1 2 3 4 5 6 RADJ (kW) Figure 21. Pulse Response Figure 22. Quiescent Current for Mid Bias Setting vs RADJ 23 100 22 pF 20 470 pF Gain (dB) RS (W) 17 10 100 pF 14 THS6214 10 100 1000 CL VIN 5 1 47 pF 11 8 1 39 pF RS 2 10M 1 kW VOUT Optional RS THS6214 100M 300M Frequency (Hz) Capacitive Load (pF) RS optimized for 100% bias Figure 23. Recommended RS vs Capacitive Load 14 Figure 24. Frequency Response vs Capacitive Load Submit Documentation Feedback Copyright © 2009–2017, Texas Instruments Incorporated Product Folder Links: THS6214 THS6214 www.ti.com SBOS431A – MAY 2009 – REVISED MARCH 2017 Typical Characteristics: VS = ±12 V, Mid Bias (continued) at TA = 25°C, GDIFF = 10 V/V, GCM = 1 V/V, RADJ = 0 Ω, RF = 1.24 kΩ, and RL = 100 Ω (unless otherwise noted) -70 -50 -70 Second Harmonic -80 Third Harmonic -75 -60 Harmonic Distortion (dBc) Harmonic Distortion (dBc) Third Harmonic -90 -100 -80 -85 -90 -95 Second Harmonic -100 -105 -110 400k -110 10M 1M 40M 0 4 2 Frequency (Hz) VO = 2 VPP Figure 25. Harmonic Distortion vs Frequency 10 12 14 16 Figure 26. Harmonic Distortion vs Output Voltage -60 -85 Third Harmonic -90 -95 -70 Harmonic Distortion (dBc) Harmonic Distortion (dBc) 8 f = 1 MHz -80 Second Harmonic -100 Third Harmonic -80 -90 -100 Second Harmonic -110 -120 -105 4 5 6 7 8 9 10 11 10 12 100 1k Resistance (W) Supply Voltage (±VS) VO = 2 VPP, f = 1 MHz VO = 2 VPP, f = 1 MHz Figure 28. Harmonic Distortion vs Load Resistance Figure 27. Harmonic Distortion vs Supply Voltage -85 60 50 -90 Third Harmonic Intercept Point (dBm) Harmonic Distortion (dBc) 6 Output Voltage (VPP) -95 Second Harmonic -100 -105 40 30 20 10 0 -110 1 10 20 0 5 10 15 20 25 30 Frequency (MHz) Gain (V/V) VO = 2 VPP, f = 1 MHz Figure 29. Harmonic Distortion vs Noninverting Gain Figure 30. Two-Tone, Third-Order Intermodulation Intercept Submit Documentation Feedback Copyright © 2009–2017, Texas Instruments Incorporated Product Folder Links: THS6214 15 THS6214 SBOS431A – MAY 2009 – REVISED MARCH 2017 www.ti.com 6.10 Typical Characteristics: VS = ±12 V, Low Bias at TA = 25°C, GDIFF = 10 V/V, GCM = 1 V/V, RADJ = 0 Ω, RF = 1.24 kΩ, and RL = 100 Ω (unless otherwise noted) 6 3 GDIFF = 5 V/V RF = 1.5 kW 0 0 Normalized Gain (dB) Normalized Gain (dB) 3 -3 -6 GDIFF = 10 V/V RF = 1.24 kW -9 -12 -3 VO = 20 VPP -6 VO = 4 VPP VO = 8 VPP -9 -12 -15 -15 -18 10M -18 VO = 2 VPP 100M 300M 0 20 40 60 80 Frequency (Hz) 100 120 140 160 180 200 220 Frequency (MHz) VO = 2 VPP Figure 32. Large-Signal Frequency Response 1.2 14 8 0.8 12 4 0.4 Small-Signal ±500 mVP Right Scale 0 0 -4 -0.4 Large-Signal Pulse Response (±10 VP) Left Scale -8 -12 -0.8 Quiescent Current (±IQ, mA) 12 Output Voltage (V) Output Voltage (V) Figure 31. Small-Signal Frequency Response -1.2 10 8 6 +IQ 4 -IQ 2 0 Time (10 ns/div) 0 1 2 3 4 5 6 RADJ (kW) Figure 33. Pulse Response Figure 34. Supply Current for Low Bias Setting vs RADJ 100 26 22 pF 23 Gain (dB) RS (W) 20 10 100 pF 17 470 pF THS6214 14 11 39 pF RS 47 pF CL VIN 1 kW VOUT Optional 8 RS 5 1 1 10 100 1000 THS6214 2 10M Capacitive Load (pF) 100M 200M Frequency (Hz) RS optimized for 100% bias Figure 35. Recommended RS vs Capacitive Load 16 Figure 36. Frequency Response vs Capacitive Load Submit Documentation Feedback Copyright © 2009–2017, Texas Instruments Incorporated Product Folder Links: THS6214 THS6214 www.ti.com SBOS431A – MAY 2009 – REVISED MARCH 2017 Typical Characteristics: VS = ±12 V, Low Bias (continued) at TA = 25°C, GDIFF = 10 V/V, GCM = 1 V/V, RADJ = 0 Ω, RF = 1.24 kΩ, and RL = 100 Ω (unless otherwise noted) -60 -50 -70 Harmonic Distortion (dBc) Harmonic Distortion (dBc) -40 Third Harmonic -60 -70 -80 Second Harmonic -90 -80 -90 Second Harmonic -100 -110 -100 -110 100k Third Harmonic -120 10M 1M 30M 0 4 2 Frequency (Hz) VO = 2 VPP Figure 37. Harmonic Distortion vs Frequency 10 12 14 16 Figure 38. Harmonic Distortion vs Output Voltage -80 Third Harmonic -90 Second Harmonic -95 -85 Harmonic Distortion (dBc) -85 -100 Third Harmonic -90 -95 Second Harmonic -100 -105 -110 -105 4 5 6 7 8 9 10 11 50 12 100 1k Resistance (W) Supply Voltage (±VS) VO = 2 VPP, f = 1 MHz VO = 2 VPP, f = 1 MHz Figure 40. Harmonic Distortion vs Load Resistance Figure 39. Harmonic Distortion vs Supply Voltage -85 55 Third Harmonic 50 -90 Intercept Point (dBm) Harmonic Distortion (dBc) 8 f = 1 MHz -80 Harmonic Distortion (dBc) 6 Output Voltage (VPP) -95 Second Harmonic -100 -105 45 40 35 30 25 20 15 -110 1 10 20 0 Gain (V/V) 5 10 15 20 25 30 Frequency (MHz) VO = 2 VPP, f = 1 MHz Figure 41. Harmonic Distortion vs Noninverting Gain Figure 42. Two-Tone, Third-Order Intermodulation Intercept Submit Documentation Feedback Copyright © 2009–2017, Texas Instruments Incorporated Product Folder Links: THS6214 17 THS6214 SBOS431A – MAY 2009 – REVISED MARCH 2017 www.ti.com 6.11 Typical Characteristics: VS = ±6 V, Full Bias at TA = 25°C, GDIFF = 5 V/V, GCM = 1 V/V, RADJ = 0 Ω, RF = 1.82 kΩ, and RL = 100 Ω (unless otherwise noted) 3 6 GDIFF = 5 V/V RF = 1.82 kW 0 3 Normalized Gain (dB) Normalized Gain (dB) Full Bias -3 GDIFF = 10 V/V RF = 1.5 kW -6 -9 -12 -15 0 75% Bias -3 -6 50% Bias -9 -12 -15 -18 10M 100M -18 10M 400M 100M VO = 2 VPP VO = 2 VPP Figure 43. Small-Signal Frequency Response Figure 44. Small-Signal Frequency Response vs Bias 7.5 Large-Signal Pulse Response (±5 VP) Left Scale 6 -3 VO = 4 VPP -6 VO = 16 VPP -9 VO = 2 VPP -12 VO = 20 VPP -15 Output Voltage (V) 0 50 100 150 200 250 300 1.6 4.5 1.2 3 0.8 1.5 0.4 Small-Signal Pulse Response (±500 mVP) Right Scale 0 -1.5 0 -0.4 -3 -0.8 -4.5 -1.2 -6 -1.6 -2 -7.5 -18 2 Output Voltage (V) Normalized Gain (3 dB/div) 3 0 400M Frequency (Hz) Frequency (Hz) 350 Time (10 ns/div) Frequency (MHz) Figure 46. Pulse Response Figure 45. Large-Signal Frequency Response 100 17 14 Gain (dB) RS (W) 470 pF 10 22 pF 11 RS THS6214 100 pF 39 pF 8 CL VIN 5 1 kW VOUT Optional 47 pF RS THS6214 1 1 10 100 1000 2 10M Capacitive Load (pF) 100M 300M Frequency (Hz) RS optimized for 100% bias Figure 47. Recommended RS vs Capacitive Load 18 Figure 48. Frequency Response vs Capacitive Load Submit Documentation Feedback Copyright © 2009–2017, Texas Instruments Incorporated Product Folder Links: THS6214 THS6214 www.ti.com SBOS431A – MAY 2009 – REVISED MARCH 2017 Typical Characteristics: VS = ±6 V, Full Bias (continued) at TA = 25°C, GDIFF = 5 V/V, GCM = 1 V/V, RADJ = 0 Ω, RF = 1.82 kΩ, and RL = 100 Ω (unless otherwise noted) -50 -55 -65 Harmonic Distortion (dBc) Harmonic Distortion (dBc) -60 -60 Third Harmonic -70 -80 -90 Second Harmonic -100 Third Harmonic -70 -75 -80 -85 Second Harmonic -90 -95 -100 -110 400k -105 10M 1M 40M 0 4 2 VO = 2 VPP 8 10 12 14 16 VO = 2 VPP, f = 1 MHz Figure 49. Harmonic Distortion vs Frequency Figure 50. Harmonic Distortion vs Output Voltage -75 -80 -85 Third Harmonic -90 -95 -80 Harmonic Distortion (dBc) Harmonic Distortion (dBc) 6 Output Voltage (VPP) Frequency (Hz) Second Harmonic -100 -85 -90 Third Harmonic -95 Second Harmonic -100 -105 -110 -105 4 5 6 7 8 9 10 11 50 12 100 1k Supply Voltage (±VS) Resistance (W) VO = 2 VPP, f = 1 MHz VO = 2 VPP, f = 1 MHz Figure 51. Harmonic Distortion vs Supply Voltage Figure 52. Harmonic Distortion vs Load Resistance -80 60 Intercept Point (dBm) Harmonic Distortion (dBc) 55 -85 Third Harmonic -90 -95 Second Harmonic -100 50 45 40 35 30 25 -105 20 1 10 20 0 5 10 15 20 25 30 Frequency (MHz) Gain (V/V) VO = 2 VPP, f = 1 MHz Figure 53. Harmonic Distortion vs Noninverting Gain Figure 54. Two-Tone, Third-Order Intermodulation Intercept Submit Documentation Feedback Copyright © 2009–2017, Texas Instruments Incorporated Product Folder Links: THS6214 19 THS6214 SBOS431A – MAY 2009 – REVISED MARCH 2017 www.ti.com Typical Characteristics: VS = ±6 V, Full Bias (continued) at TA = 25°C, GDIFF = 5 V/V, GCM = 1 V/V, RADJ = 0 Ω, RF = 1.82 kΩ, and RL = 100 Ω (unless otherwise noted) 20 Quiescent Current (±IQ, mA) 18 16 14 12 10 8 +IQ 6 -IQ 4 2 0 0 1 2 3 4 5 6 RADJ (kW) Figure 55. Quiescent Current for Full Bias Setting vs RADJ 20 Submit Documentation Feedback Copyright © 2009–2017, Texas Instruments Incorporated Product Folder Links: THS6214 THS6214 www.ti.com SBOS431A – MAY 2009 – REVISED MARCH 2017 6.12 Typical Characteristics: VS = ±6 V, Mid Bias at TA = 25°C, GDIFF = 5 V/V, GCM = 1 V/V, RADJ = 0 Ω, RF = 1.82 kΩ, and RL = 100 Ω (unless otherwise noted) 3 0 Normalized Gain (dB) 0 Normalized Gain (dB) 3 GDIFF = 5 V/V RF = 1.82 kW -3 GDIFF = 10 V/V RF = 1.5 kW -6 -9 -12 -3 VO = 4 VPP -6 VO = 16 VPP VO = 2 VPP -9 -12 VO = 20 VPP -15 -15 -18 10M -18 100M 300M 0 50 100 150 200 250 300 Frequency (MHz) Frequency (Hz) VO = 2 VPP Figure 56. Small-Signal Frequency Response Large-Signal Pulse Response (±5 VP) Left Scale 2 16 1.6 14 4.5 1.2 3 0.8 1.5 0.4 Small-Signal Pulse Response (±500 mVP) Right Scale 0 -1.5 0 -0.4 Output Voltage (V) Output Voltage (V) 6 Quiescent Current (±IQ, mA) 7.5 Figure 57. Large-Signal Frequency Response 12 10 8 -3 -0.8 -4.5 -1.2 -6 -1.6 2 -2 0 -7.5 +IQ 6 -IQ 4 0 Time (10 ns/div) 1 2 3 4 5 6 RADJ (kW) Figure 58. Pulse Response Figure 59. Quiescent Current for Mid Bias Setting vs RADJ 100 17 22 pF 14 470 pF 39 pF Gain (dB) RS (W) RS 10 11 8 THS6214 CL VIN 1 kW VOUT Optional 100 pF RS 5 THS6214 47 pF 1 1 10 100 1000 2 10M Capacitive Load (pF) 100M 200M Frequency (Hz) RS optimized for 100% bias Figure 60. Recommended RS vs Capacitive Load Figure 61. Frequency Response vs Capacitive Load Submit Documentation Feedback Copyright © 2009–2017, Texas Instruments Incorporated Product Folder Links: THS6214 21 THS6214 SBOS431A – MAY 2009 – REVISED MARCH 2017 www.ti.com Typical Characteristics: VS = ±6 V, Mid Bias (continued) at TA = 25°C, GDIFF = 5 V/V, GCM = 1 V/V, RADJ = 0 Ω, RF = 1.82 kΩ, and RL = 100 Ω (unless otherwise noted) -60 -65 -50 Harmonic Distortion (dBc) Harmonic Distortion (dBc) -40 Third Harmonic -60 -70 -80 -90 Second Harmonic -70 Third Harmonic -75 -80 -85 Second Harmonic -90 -100 -95 -110 400k -100 10M 1M 40M 0 4 2 VO = 2 VPP Figure 62. Harmonic Distortion vs Frequency 10 12 14 16 Figure 63. Harmonic Distortion vs Output Voltage -80 -85 Harmonic Distortion (dBc) -85 Third Harmonic -90 Second Harmonic -95 -90 Third Harmonic -95 Second Harmonic -100 -105 -110 -100 4 5 6 7 8 9 10 11 50 12 100 1k Supply Voltage (±VS) Resistance (W) VO = 2 VPP, f = 1 MHz VO = 2 VPP, f = 1 MHz Figure 64. Harmonic Distortion vs Supply Voltage Figure 65. Harmonic Distortion vs Load Resistance -86 60 55 -88 Third Harmonic Intercept Point (dBm) Harmonic Distortion (dBc) 8 f = 1 MHz -80 Harmonic Distortion (dBc) 6 Output Voltage (VPP) Frequency (Hz) -90 -92 -94 Second Harmonic -96 50 45 40 35 30 25 -98 20 1 10 20 0 5 10 15 20 25 30 Frequency (MHz) Gain (V/V) VO = 2 VPP, f = 1 MHz Figure 66. Harmonic Distortion vs Noninverting Gain 22 Figure 67. Two-Tone, Third-Order Intermodulation Intercept Submit Documentation Feedback Copyright © 2009–2017, Texas Instruments Incorporated Product Folder Links: THS6214 THS6214 www.ti.com SBOS431A – MAY 2009 – REVISED MARCH 2017 6.13 Typical Characteristics: VS = ±6 V, Low Bias at TA = 25°C, GDIFF = 5 V/V, GCM = 1 V/V, RADJ = 0 Ω, RF = 1.82 kΩ, and RL = 100 Ω (unless otherwise noted) 6 6 GDIFF = 5 V/V RF = 1.82 kW 3 3 -3 GDIFF = 10 V/V RF = 1.5 kW -6 0 Normalized Gain (dB) Normalized Gain (dB) 0 -9 -12 -3 VO = 16 VPP VO = 4 VPP -6 -9 VO = 2 VPP VO = 20 VPP -12 -15 -15 -18 10M -18 100M 300M 0 20 40 60 80 100 120 140 160 180 200 220 240 260 Frequency (MHz) Frequency (Hz) VO = 2 VPP Figure 69. Large-Signal Frequency Response Figure 68. Small-Signal Frequency Response Large-Signal Pulse Response (±5 VP) Left Scale 2 1.6 4.5 1.2 3 0.8 1.5 0.4 Small-Signal Pulse Response (±500 mVP) Right Scale 0 -1.5 0 -0.4 -3 -0.8 -4.5 -1.2 -6 -1.6 Output Voltage (V) Output Voltage (V) 6 Quiescent Current (±IQ, mA) 7.5 12 8 6 +IQ 4 -IQ 2 0 -2 -7.5 10 0 Time (10 ns/div) 1 2 3 4 5 6 RADJ (kW) Figure 70. Pulse Response Figure 71. Quiescent Current for Low Bias Setting vs RADJ 100 20 17 100 pF Gain (dB) RS (W) 14 10 22 pF 470 pF RS THS6214 11 39 pF 8 CL VIN 1 kW VOUT Optional 47 pF RS 5 THS6214 1 1 10 100 1000 2 10M Capacitive Load (pF) 100M 200M Frequency (Hz) RS optimized for 100% bias Figure 72. Recommended RS vs Capacitive Load Figure 73. Frequency Response vs Capacitive Load Submit Documentation Feedback Copyright © 2009–2017, Texas Instruments Incorporated Product Folder Links: THS6214 23 THS6214 SBOS431A – MAY 2009 – REVISED MARCH 2017 www.ti.com Typical Characteristics: VS = ±6 V, Low Bias (continued) at TA = 25°C, GDIFF = 5 V/V, GCM = 1 V/V, RADJ = 0 Ω, RF = 1.82 kΩ, and RL = 100 Ω (unless otherwise noted) -60 -50 Harmonic Distortion (dBc) Harmonic Distortion (dBc) -40 -60 -70 Third Harmonic -80 Second Harmonic -70 Third Harmonic -80 Second Harmonic -90 -90 -100 -100 100k 1M 10M 0 100M 4 2 Frequency (Hz) VO = 2 VPP 8 10 12 14 16 f = 1 MHz Figure 74. Harmonic Distortion vs Frequency Figure 75. Harmonic Distortion vs Output Voltage -80 -80 -85 -85 Harmonic Distortion (dBc) Harmonic Distortion (dBc) 6 Output Voltage (VPP) Third Harmonic -90 Second Harmonic -95 Second Harmonic -90 -95 -100 Third Harmonic -105 -100 -110 4 5 6 7 8 9 10 11 12 50 100 1k Resistance (W) Supply Voltage (±VS) VO = 2 VPP, f = 1 MHz VO = 2 VPP, f = 1 MHz Figure 77. Harmonic Distortion vs Load Resistance Figure 76. Harmonic Distortion vs Supply Voltage 60 -80 Intercept Point (dBm) Harmonic Distortion (dBc) 55 -85 Third Harmonic -90 -95 Second Harmonic 50 45 40 35 30 25 -100 20 1 10 20 0 5 10 15 20 25 30 Frequency (MHz) Gain (V/V) VO = 2 VPP, f = 1 MHz Figure 78. Harmonic Distortion vs Noninverting Gain 24 Figure 79. Two-Tone, Third-Order Intermodulation Intercept Submit Documentation Feedback Copyright © 2009–2017, Texas Instruments Incorporated Product Folder Links: THS6214 THS6214 www.ti.com SBOS431A – MAY 2009 – REVISED MARCH 2017 7 Detailed Description 7.1 Overview The THS6214 is a differential line-driver amplifier with a current-feedback architecture. The device is targeted for use in line-driver applications (such as xDSL and wide-band, power-line communications) and is fast enough to support transmissions of 14.5-dBm line power up to 30 MHz. The architecture of the THS6214 is designed to provide maximum flexibility with multiple bias settings that are selectable based on application performance requirements, and also provides an external current pin (IADJ) to further adjust the bias current to the device. The wide output swing (43.2 VPP) and high current drive (416 mA) of the THS6214 make the device ideally suited for high-power, line-driving applications. 7.2 Functional Block Diagram VS+ D1 IN+ D1 THS6214 D1 OUT D1 FB D2 FB D2 THS6214 D2 OUT D2 IN+ BIAS-1/D1D2 BIAS-2/D1D2 IADJ BIAS-2/D3D4 BIAS-1/D3D4 D3 IN+ BIAS D3 THS6214 GND D3 OUT D3 FB D4 FB D4 THS6214 D4 OUT D4 IN+ VS- Copyright © 2017, Texas Instruments Incorporated 7.3 Feature Description 7.3.1 Output Current and Voltage The THS6214 provides output voltage and current capabilities that are unsurpassed in a low-cost, dual monolithic op amp. Under no-load conditions at 25°C, the output voltage typically swings closer than 1.1 V to either supply rail; tested at 25°C, the swing limit is within 1.4 V of either rail into a 100-Ω differential load. Into a 25-Ω load (the minimum tested load), the amplifier delivers more than ±408-mA continuous and greater than ±1A peak output current. The specifications described in the previous paragraph, though familiar in the industry, consider voltage and current limits separately. In many applications, the voltage times current (or V-I product) is more relevant to circuit operation. See the Output Voltage and Current Limitations plot (Figure 13) in the Typical Characteristics section. The X- and Y-axes of this graph show the zero-voltage output current limit and the zero-current output voltage limit, respectively. The four quadrants give a more detailed view of the THS6214 output drive capabilities, noting that the graph is bounded by a safe operating area of 1-W maximum internal power dissipation (in this case, for one channel only). Superimposing resistor load lines onto the plot illustrates that the THS6214 can drive ±10.9 V into 100 Ω or ±10.5 V into 50 Ω without exceeding the output capabilities or the 1-W dissipation limit. A 100-Ω load line (the standard test circuit load) illustrates the full ±12-V output swing capability, as provided in the Submit Documentation Feedback Copyright © 2009–2017, Texas Instruments Incorporated Product Folder Links: THS6214 25 THS6214 SBOS431A – MAY 2009 – REVISED MARCH 2017 www.ti.com Feature Description (continued) Electrical Characteristics tables. The minimum specified output voltage and current over temperature are set by worst-case simulations at the cold temperature extreme. Only at cold startup do the output current and voltage decrease to the numbers provided in the Electrical Characteristics tables. When the output transistors deliver power, the junction temperature increases, decreasing the VBEs (increasing the available output voltage swing), and increasing the current gains (increasing the available output current). In steady-state operation, the available output voltage and current are always greater than that shown in the overtemperature specifications, because the output stage junction temperatures are higher than the minimum specified operating ambient temperature. To maintain maximum output stage linearity, no output short-circuit protection is provided. This absence of shortcircuit protection is normally not a problem because most applications include a series-matching resistor at the output that limits the internal power dissipation if the output side of this resistor is shorted to ground. However, shorting the output pin directly to the adjacent positive power-supply pin (24-pin package), in most cases destroys the amplifier. If additional short-circuit protection is required, a small series resistor can be included in the supply lines. Under heavy output loads, this additional resistor reduces the available output voltage swing. A 5-Ω series resistor in each power-supply lead limits the internal power dissipation to less than 1 W for an output short-circuit, and decreases the available output voltage swing only 0.5 V for up to 100-mA desired load currents. Always place the 0.1-µF power-supply decoupling capacitors after these supply current limiting resistors, directly on the supply pins. 7.3.2 Driving Capacitive Loads One of the most demanding and yet very common load conditions for an op amp is capacitive loading. Often, the capacitive load is the input of an ADC—including additional external capacitance that may be recommended to improve the ADC linearity. A high-speed, high open-loop gain amplifier such as the THS6214 can be very susceptible to decreased stability and closed-loop response peaking when a capacitive load is placed directly on the output pin. When the amplifier open-loop output resistance is considered, this capacitive load introduces an additional pole in the signal path that can decrease the phase margin. Several external solutions to this problem have been suggested below. When the primary considerations are frequency response flatness, pulse response fidelity, and distortion, the simplest and most effective solution is to isolate the capacitive load from the feedback loop by inserting a series isolation resistor between the amplifier output and the capacitive load. This series resistor does not eliminate the pole from the loop response, but shifts the pole and adds a zero at a higher frequency. The additional zero functions to cancel the phase lag from the capacitive load pole, thus increasing the phase margin and improving stability. The Typical Characteristics illustrate the recommended RS versus capacitive load (see Figure 5, Figure 23, Figure 35, Figure 47, Figure 60, and Figure 72) and the resulting frequency response at the load. Parasitic capacitive loads greater than 2 pF can begin to degrade device performance. Long printed-circuit board (PCB) traces, unmatched cables, and connections to multiple devices can easily cause this value to be exceeded. Always consider this effect carefully, and add the recommended series resistor as close as possible to the THS6214 output pin (see the Board Layout Guidelines section). 7.3.3 Distortion Performance The THS6214 provides good distortion performance into a 100-Ω load on ±12-V supplies. Relative to alternative solutions, the amplifier provides exceptional performance into lighter loads and operation on a dual ±6-V supply. Generally, until the fundamental signal reaches very high frequency or power levels, the second harmonic dominates the distortion with a negligible third-harmonic component. Focusing then on the second harmonic, increasing the load impedance improves distortion directly. Remember that the total load includes the feedback network—in the noninverting configuration (see Figure 81), this value is the sum of RF + RG, whereas in the inverting configuration this value is just RF. Also, providing an additional supply decoupling capacitor (0.01 µF) between the supply pins (for bipolar operation) improves the second-order distortion slightly (from 3 dB to 6 dB). In most op amps, increasing the output voltage swing directly increases harmonic distortion. The Typical Characteristics illustrate the second harmonic increasing at a little less than the expected 2x rate, whereas the third harmonic increases at a little less than the expected 3x rate. Where the test power doubles, the second harmonic decreases less than the expected 6 dB, and the third harmonic decreases by less than the expected 12 dB. This difference also appears in the two-tone, third-order intermodulation spurious (IM3) response curves. The third-order spurious levels are extremely low at low-output power levels, and the output stage continues to hold them low even when the fundamental power reaches very high levels. 26 Submit Documentation Feedback Copyright © 2009–2017, Texas Instruments Incorporated Product Folder Links: THS6214 THS6214 www.ti.com SBOS431A – MAY 2009 – REVISED MARCH 2017 Feature Description (continued) 7.3.4 Differential Noise Performance The THS6214 is designed to be used as a differential driver in xDSL applications. Therefore, analyzing the noise in such a configuration is important. Figure 80 shows the op amp noise model for the differential configuration. IN EN RS IN ERS RF 4 kTRF 4 kTRS RG 2 EO 4 kTRG RF 4 kTRF IN EN RS IN ERS 4 kTRS Figure 80. Differential Op Amp Noise Analysis Model As a reminder, the differential gain is expressed as given in Equation 1: 2 ´ RF GD = 1 + RG (1) The output noise can be expressed as shown in Equation 2: EO = 2 2 2 2 ´ GD2 ´ eN + (iN ´ RS) + 4 kTRS + 2(iIRF) + 2(4 kTRFGD) (2) Dividing this expression by the differential noise gain [GD = (1 + 2RF / RG)] gives the equivalent input-referred spot noise voltage at the noninverting input, as shown in Equation 3. EO = 2 2 2 ´ eN + (iN ´ RS) + 4 kTRS + 2 iIRF GD 2 +2 4 kTRF GD (3) Evaluating these equations for the THS6214 ADSL circuit and component values of Figure 84 gives a total output spot noise voltage of 38.9 nV/√Hz and a total equivalent input spot noise voltage of 7 nV/√Hz. In order to minimize the output noise as a result of the noninverting input bias current noise, keeping the noninverting source impedance as low as possible is recommended. Submit Documentation Feedback Copyright © 2009–2017, Texas Instruments Incorporated Product Folder Links: THS6214 27 THS6214 SBOS431A – MAY 2009 – REVISED MARCH 2017 www.ti.com Feature Description (continued) 7.3.5 DC Accuracy and Offset Control A current-feedback op amp such as the THS6214 provides exceptional bandwidth in high gains, giving fast pulse settling but only moderate dc accuracy. The Electrical Characteristics describe an input offset voltage comparable to high-speed, voltage-feedback amplifiers; however, the two input bias currents are somewhat higher and are unmatched. Although bias current cancellation techniques are very effective with most voltagefeedback op amps, these techniques do not generally reduce the output dc offset for wideband current-feedback op amps. Because the two input bias currents are unrelated in both magnitude and polarity, matching the input source impedance to reduce error contribution to the output is ineffective. Evaluating the configuration of Figure 81, using a worst-case condition at 25°C input offset voltage and the two input bias currents, gives a worst-case output offset range equal to Equation 4: RS § · VOFF r NG u VOS MAX ¨ IBN u 2 u NG ¸ r IBI u RF © ¹ r 10 u 5 mV 3.5 PA u 25 : u 10 r 1.24 k: u 45 PA r50 mV 0.875 mV r 55.5 mV VOFF 104.92 mV to 106.67 mV where • NG = noninverting signal gain (4) 7.4 Device Functional Modes The THS6214 has four different functional modes for each port set by the BIAS-1/xxxx and BIAS-2/xxxx pins. Table 2 shows the truth table for the device mode pin configuration and the associated description of each mode. Table 2. Bias Logic Table 28 BIAS-1/XXXX BIAS-2/XXXX FUNCTION DESCRIPTION 0 0 Full-bias mode (100%) Amplifiers on with lowest distortion possible (default state) 1 0 Mid-bias mode (75%) Amplifiers on with power savings and a reduction in distortion performance 0 1 Low-bias mode (50%) Amplifiers on with enhanced power savings and a reduction of overall performance 1 1 Shutdown mode Amplifiers off and output has high impedance Submit Documentation Feedback Copyright © 2009–2017, Texas Instruments Incorporated Product Folder Links: THS6214 THS6214 www.ti.com SBOS431A – MAY 2009 – REVISED MARCH 2017 8 Application and Implementation NOTE Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes. Customers should validate and test their design implementation to confirm system functionality. 8.1 Application Information The THS6214 is typically used to drive high output power applications with various load conditions. In the Typical Applications section, the amplifier is presented in a general-purpose, wideband, current-feedback configuration, and a more specific 100-Ω twisted pair cable line driver. However, the amplifier is also applicable for many different general-purpose and specific cable line-driving scenarios beyond what is described in the Typical Applications section. 8.2 Typical Applications 8.2.1 Wideband Current-Feedback Operation The THS6214 provides the exceptional ac performance of a wideband current-feedback op amp with a highly linear, high-power output stage. Requiring only 21-mA/port quiescent current, the THS6214 swings to within 1.9 V of either supply rail on a 100-Ω load and delivers in excess of 416 mA at room temperature. This lowoutput headroom requirement, along with supply voltage independent biasing, provides remarkable ±6-V supply operation. The THS6214 delivers greater than 140-MHz bandwidth driving a 2-VPP output into 100 Ω on a ±6-V supply. Previous boosted output stage amplifiers typically suffer from very poor crossover distortion when the output current goes through zero. The THS6214 achieves a comparable power gain with much better linearity. The primary advantage of a current-feedback op amp over a voltage-feedback op amp is that ac performance (bandwidth and distortion) is relatively independent of signal gain. Figure 81 shows the dc-coupled, gain of 10 V/V, dual power-supply circuit configuration used as the basis of the ±12-V Electrical Characteristics and Typical Characteristics. For test purposes, the input impedance is set to 50 Ω with a resistor to ground and the output impedance is set to 50 Ω with a series output resistor. Voltage swings reported in the Electrical Characteristics are taken directly at the input and output pins, whereas load powers (dBm) are defined at a matched 50-Ω load. For the circuit of Figure 81, the total effective load is 100 Ω || 1.24 kΩ || 1.24 kΩ = 86.1 Ω. 12 V D1 THS6214 RF 1.24 kW VIN RG 274 W RF 1.24 kW VOUT RL D2 THS6214 GDIFF = 1 + -12 V 2 ´ RF RG = VOUT VIN Figure 81. Noninverting Differential I/O Amplifier Submit Documentation Feedback Copyright © 2009–2017, Texas Instruments Incorporated Product Folder Links: THS6214 29 THS6214 SBOS431A – MAY 2009 – REVISED MARCH 2017 www.ti.com Typical Applications (continued) 8.2.1.1 Design Requirements The main design requirements for wideband current-feedback operation are to choose power supplies that satisfy common-mode requirements at the input and output of the device, and also to use a feedback resistor value that allows for the proper bandwidth when maintaining stability. These requirements and the proper solutions are described in the Detailed Design Procedure section. Using transformers and split power supplies can be required for certain applications. 8.2.1.2 Detailed Design Procedure For ease of test purposes in this design, the THS6214 input impedance is set to 50 Ω with a resistor to ground and the output impedance is set to 50 Ω with a series output resistor. Voltage swings reported in the Electrical Characteristics tables are taken directly at the input and output pins, whereas load powers (dBm) are defined at a matched 50-Ω load. For the circuit of Figure 81, the total effective load is 100 Ω || 1.24 kΩ || 1.24 kΩ = 86.1 Ω. This approach allows a source termination impedance to be set at the input that is independent of the signal gain. For instance, simple differential filters can be included in the signal path right up to the noninverting inputs with no interaction with the gain setting. The differential signal gain for the circuit of Figure 81 is given by Equation 5: RF AD = 1 + 2 ´ RG where • AD = differential gain (5) A value of 274 Ω for the AD = 10-V/V design is given by Figure 81. The device bandwidth is primarily controlled with the feedback resistor value because the THS6214 is a current-feedback (CFB) amplifier; the differential gain, however, can be adjusted with considerable freedom using just the RG resistor. In fact, RG can be reduced by a reactive network that provides a very isolated shaping to the differential frequency response. Various combinations of single-supply or ac-coupled gain can also be delivered using the basic circuit of Figure 81. Common-mode bias voltages on the two noninverting inputs pass on to the output with a gain of 1 V/V because an equal dc voltage at each inverting node does not create current through RG. This circuit does show a common-mode gain of 1 V/V from the input to output. The source connection must either remove this commonmode signal if undesired (using an input transformer can provide this function), or the common-mode voltage at the inputs can be used to set the output common-mode bias. If the low common-mode rejection of this circuit is a problem, the output interface can also be used to reject that common-mode signal. For instance, most modern differential input analog-to-digital converters (ADCs) reject common-mode signals very well, and a line-driver application through a transformer also attenuates the common-mode signal through to the line. 30 Submit Documentation Feedback Copyright © 2009–2017, Texas Instruments Incorporated Product Folder Links: THS6214 THS6214 www.ti.com SBOS431A – MAY 2009 – REVISED MARCH 2017 Typical Applications (continued) 8.2.1.3 Application Curves 3 -50 0 -60 Harmonic Distortion (dBc) Normalized Gain (dB) Figure 82 and Figure 83 show the frequency response and distortion performance of the circuit in Figure 81. The measurements are made with a load resistor (RL) of 100 Ω, and at room temperature. Figure 82 is measured using the three different device power modes, and the distortion measurements in Figure 83 are made at an output voltage level of 2 VPP. -3 -6 -9 -12 Full-Bias (100%) Mode Mid-Bias (75%) Mode Low-Bias (50%) Mode -15 -70 -80 -90 -100 -18 1 HD2 HD3 10 Frequency (MHz) 100 -110 0.4 400 1 10 Frequency (MHz) D002 Figure 82. Frequency Response 40 D007 Figure 83. Harmonic Distortion 8.2.2 Dual-Supply VDSL Downstream Driver Figure 84 shows an example of a dual-supply downstream driver with a synthesized output impedance circuit. The THS6214 is configured as a differential gain stage to provide a signal drive to the primary winding of the transformer (a step-up transformer with a turns ratio of 1:n is shown in Figure 84). The main advantage of this configuration is the cancellation of all even harmonic-distortion products. Another important advantage is that each amplifier must only swing half of the total output required driving the load. 12 V 20 W D1 THS6214 RF 2.2 kW 0.1 mF RP 2.9 kW 2 kW AFE 2 VPP Max Assumed RG 1.4 kW 2 kW 0.1 mF 20 W IP = 159 mA RM 10 W 1:1.1 ZLINE RP 2.9 kW RF 2.2 kW D2 THS6214 RL 100 W RM 10 W IP = 159 mA -12 V Figure 84. Dual-Supply VDSL Downstream Driver Submit Documentation Feedback Copyright © 2009–2017, Texas Instruments Incorporated Product Folder Links: THS6214 31 THS6214 SBOS431A – MAY 2009 – REVISED MARCH 2017 www.ti.com Typical Applications (continued) The analog front-end (AFE) signal is ac-coupled to the driver, and the noninverting input of each amplifier is biased to the mid-supply voltage (ground in this case). In addition to providing the proper biasing to the amplifier, this approach also provides a high-pass filtering with a corner frequency that is set at 5 kHz in this example. Because the signal bandwidth starts at 26 kHz, this high-pass filter does not generate any problems and has the advantage of filtering out unwanted lower frequencies. 8.2.2.1 Design Requirements The main design requirements for Figure 84 are to match the output impedance correctly, satisfy headroom requirements, and ensure that the circuit meets power driving requirements. These requirements are described in the Detailed Design Procedure section and include the required equations to properly implement the design. The design must be fully worked through before physical implementation because small changes in a single parameter can often have large effects on performance. 8.2.2.2 Detailed Design Procedure For Figure 84, the input signal is amplified with a gain set by Equation 6: 2 ´ RF GD = 1 + RG (6) The two back-termination resistors (RM = 10 Ω, each) added at each terminal of the transformer make the impedance of the amplifier match the impedance of the line, and also provide a means of detecting the received signal for the receiver. The value of these resistors (RM) is a function of the line impedance and the transformer turns ratio (n), given by Equation 7: ZLINE RM = 2n2 (7) 8.2.2.2.1 Line Driver Headroom Model Requirements The first step in a transformer-coupled, twisted-pair driver design is to compute the peak-to-peak output voltage from the target specifications. This calculation is done using Equation 8 to Equation 11: VRMS2 PL = 10 ´ log (1 mW) ´ RL where • • • PL = power at the load VRMS = voltage at the load RL = load impedance (8) These values produce the following: VRMS = (1 mW) ´ RL ´ 10 PL 10 (9) VP = Crest Factor ´ VRMS = CF ´ VRMS where • • VP = peak voltage at the load CF = crest factor (10) VLPP = 2 ´ CF ´ VRMS where • 32 VLPP = peak-to-peak voltage at the load Submit Documentation Feedback (11) Copyright © 2009–2017, Texas Instruments Incorporated Product Folder Links: THS6214 THS6214 www.ti.com SBOS431A – MAY 2009 – REVISED MARCH 2017 Typical Applications (continued) Consolidating Equation 8 to Equation 11 allows the required peak-to-peak voltage at the load to be expressed as a function of the crest factor, the load impedance, and the power at the load, as given by Equation 12: VLPP = 2 ´ CF ´ (1 mW) ´ RL ´ 10 PL 10 (12) VLPP is usually computed for a nominal line impedance and can be taken as a fixed design target. The next step in the design is to compute the individual amplifier output voltage and currents as a function of peak-to-peak voltage on the line and transformer-turns ratio. When this turns ratio changes, the minimum allowed supply voltage also changes. The peak current in the amplifier output is given by Equation 13: 2 ´ VLPP 1 1 ±IP = ´ ´ n 2 4 RM where • • VPP is as defined in Equation 12, and RM is as defined in Equation 7 and Figure 85 (13) RM VPP = 2 VLPP n VLPP n RL VLPP RM Copyright © 2016, Texas Instruments Incorporated Figure 85. Driver Peak Output Voltage With the previous information available, a supply voltage and the turns ratio desired for the transformer can now be selected, and the headroom for the THS6214 can be calculated. The model illustrated in Figure 86 can be described with Equation 14 and Equation 15 as: 1. The available output swing: VPP = VCC - (V1 + V2) - IP ´ (R1 + R2) 2. Or as the required supply voltage: VCC = VPP + (V1 + V2) + IP ´ (R1 + R2) (14) (15) The minimum supply voltage for power and load requirements is given by Equation 15. V1, V2, R1, and R2 are given in Table 3 for the ±12-V operation. Submit Documentation Feedback Copyright © 2009–2017, Texas Instruments Incorporated Product Folder Links: THS6214 33 THS6214 SBOS431A – MAY 2009 – REVISED MARCH 2017 www.ti.com Typical Applications (continued) VCC R1 V1 VOUT IP V2 R2 Figure 86. Line Driver Headroom Model Table 3. Line Driver Headroom Model Values VS V1 R1 V2 R2 ±12 V 1V 0.6 Ω 1V 1.2 Ω When using a synthetic output impedance circuit (see Figure 84), a significant drop in bandwidth occurs from the specification provided in the Electrical Characteristics tables. This apparent drop in bandwidth for the differential signal is a result of the apparent increase in the feedback transimpedance for each amplifier. This feedback transimpedance equation is given by Equation 16: 1+2´ ZFB = RF ´ 1+2´ RS RL RS RP RL + RS + RS RF - RP RP (16) To increase the 0.1-dB flatness to the frequency of interest, adding a serial RC in parallel with the gain resistor may be needed, as shown in Figure 87. RS D1 THS6214 RF RP RM ZLINE VIN RG RP 100 W CM RF D2 THS6214 RS Figure 87. 0.1-dB Flatness Compensation Circuit 34 Submit Documentation Feedback Copyright © 2009–2017, Texas Instruments Incorporated Product Folder Links: THS6214 THS6214 www.ti.com SBOS431A – MAY 2009 – REVISED MARCH 2017 8.2.2.2.2 Total Driver Power for xDSL Applications The total internal power dissipation for the THS6214 in an xDSL line driver application is the sum of the quiescent power and the output stage power. The THS6214 holds a relatively constant quiescent current versus supply voltage—giving a power contribution that is simply the quiescent current times the supply voltage used (the supply voltage is greater than the solution given in Equation 15). The total output stage power can be computed with reference to Figure 88. VCC IAVG = IP CF RT Figure 88. Output Stage Power Model The two output stages used to drive the load of Figure 85 are shown as an H-Bridge in Figure 88. The average current drawn from the supply into this H-Bridge and load is the peak current in the load given by Equation 13 divided by the crest factor (CF) for the xDSL modulation. This total power from the supply is then reduced by the power in RT, leaving the power dissipated internal to the drivers in the four output stage transistors. That power is simply the target line power used in Equation 8 plus the power lost in the matching elements (RM). In the following examples, a perfect match is targeted giving the same power in the matching elements as in the load. The output stage power is then set by Equation 17. IP POUT = ´ VCC - 2PL CF (17) The total amplifier power is then given by Equation 18: IP PTOT = IQ ´ VCC + ´ VCC - 2PL CF (18) For the ADSL CO driver design of Figure 84, the peak current is 159 mA for a signal that requires a crest factor of 5.6 with a target line power of 20.5 dBm into a 100-Ω load (115 mW). With a typical quiescent current of 21 mA and a nominal supply voltage of ±12 V, the total internal power dissipation for the solution of Figure 84 is given by Equation 19: 159 mA PTOT = 21 mA (24 V) + (24 V) - 2(115 mW) = 955 mW 5.6 (19) 9 Power Supply Recommendations The THS6214 is designed to operate optimally using split power supplies. The device has a very wide supply range of ±5 V to ±14 V to accommodate many different application scenarios. Choose power-supply voltages that allow for adequate swing on both the inputs and outputs of the amplifier to prevent affecting device performance. The ground pin provides the ground reference for the control pins and must be within VS– to (VS+ – 5 V) for proper operation. Submit Documentation Feedback Copyright © 2009–2017, Texas Instruments Incorporated Product Folder Links: THS6214 35 THS6214 SBOS431A – MAY 2009 – REVISED MARCH 2017 www.ti.com 10 Layout 10.1 Board Layout Guidelines Achieving optimum performance with a high-frequency amplifier such as the THS6214 requires careful attention to board layout parasitic and external component types. Recommendations that optimize performance include: a. Minimize parasitic capacitance to any ac ground for all signal I/O pins. Parasitic capacitance on the output and inverting input pins can cause instability; on the noninverting input, this capacitance can react with the source impedance to cause unintentional band limiting. To reduce unwanted capacitance, a window around the signal I/O pins must be opened in all ground and power planes around these pins. Otherwise, ground and power planes must be unbroken elsewhere on the board. b. Minimize the distance (less than 0.25 in, or 6.35 mm) from the power-supply pins to high-frequency 0.1-µF decoupling capacitors. At the device pins, the ground and power plane layout must not be in close proximity to the signal I/O pins. Avoid narrow power and ground traces to minimize inductance between the pins and the decoupling capacitors. The power-supply connections must always be decoupled with these capacitors. An optional supply decoupling capacitor across the two power supplies (for bipolar operation) improves second-harmonic distortion performance. Larger (2.2 µF to 6.8 µF) decoupling capacitors, effective at lower frequencies, must also be used on the main supply pins. These capacitors can be placed somewhat farther from the device and can be shared among several devices in the same area of the PCB. c. Careful selection and placement of external components preserve the high-frequency performance of the THS6214. Resistors must be of a very low reactance type. Surface-mount resistors work best and allow a tighter overall layout. Metal film and carbon composition, axially-leaded resistors can also provide good highfrequency performance. Again, keep leads and PCB trace length as short as possible. Never use wire-wound type resistors in a highfrequency application. Although the output pin and inverting input pin are the most sensitive to parasitic capacitance, always position the feedback and series output resistor, if any, as close as possible to the output pin. Other network components, such as noninverting input termination resistors, must also be placed close to the package. Where double-side component mounting is allowed, place the feedback resistor directly under the package on the other side of the board between the output and inverting input pins. The frequency response is primarily determined by the feedback resistor value as described previously. Increasing the value reduces the bandwidth, whereas decreasing the value leads to a more peaked frequency response. The 1.24-kΩ feedback resistor used in the Typical Characteristics at a gain of 10 V/V on ±12-V supplies is a good starting point for design. Note that a 1.5-kΩ feedback resistor, rather than a direct short, is recommended for a unity-gain follower application. A current-feedback op amp requires a feedback resistor to control stability even in the unity-gain follower configuration. d. Connections to other wideband devices on the board can be made with short direct traces or through onboard transmission lines. For short connections, consider the trace and the input to the next device as a lumped capacitive load. Relatively wide traces (50 mils to 100 mils [0.050 in to 0.100 in, or 1.27 mm to 2.54 mm]) must be used, preferably with ground and power planes opened up around them. Estimate the total capacitive load and set RS from the recommended RS versus capacitive load plots (see Figure 5, Figure 23, Figure 35, Figure 47, Figure 60, and Figure 72). Low parasitic capacitive loads (less than 5 pF) may not need an isolation resistor because the THS6214 is nominally compensated to operate with a 2-pF parasitic load. If a long trace is required, and the 6-dB signal loss intrinsic to a doubly-terminated transmission line is acceptable, implement a matched-impedance transmission line using microstrip or stripline techniques (consult an ECL design handbook for microstrip and stripline layout techniques). A 50-Ω environment is not necessary on board; in fact, a higher impedance environment improves distortion (see the distortion versus load plots). With a characteristic board trace impedance defined based on board material and trace dimensions, a matching series resistor into the trace from the output of the THS6214 is used, as well as a terminating shunt resistor at the input of the destination device. Remember also that the terminating impedance is the parallel combination of the shunt resistor and the input impedance of the destination device. This total effective impedance must be set to match the trace impedance. The high output voltage and current capability of the THS6214 allows multiple destination devices to be handled as separate transmission lines, each with their own series and shunt terminations. If the 6-dB attenuation of a doubly-terminated transmission line is unacceptable, a long trace can be series-terminated at the source end only. 36 Submit Documentation Feedback Copyright © 2009–2017, Texas Instruments Incorporated Product Folder Links: THS6214 THS6214 www.ti.com SBOS431A – MAY 2009 – REVISED MARCH 2017 Board Layout Guidelines (continued) Treat the trace as a capacitive load in this case and set the series resistor value as shown in the recommended RS versus capacitive load plots. However, this configuration does not preserve signal integrity as well as a doubly-terminated line. If the input impedance of the destination device is low, there is some signal attenuation as a result of the voltage divider formed by the series output into the terminating impedance. e. Socketing a high-speed part such as the THS6214 is not recommended. The additional lead length and pinto-pin capacitance introduced by the socket can create an extremely troublesome parasitic network, and can make achieving a smooth, stable frequency response almost impossible. Best results are obtained by soldering the THS6214 directly onto the board. f. Use the –VS plane to conduct heat out of the VQFN-24 and HTSSOP-24 PowerPAD packages. These packages attach the die directly to an exposed thermal pad on the bottom, and must be soldered to the board. This pad must be connected electrically to the same voltage plane as the most negative supply applied to the THS6214 (in Figure 84, this supply is –12 V). 10.2 Layout Example Figure 89. Example Layout Submit Documentation Feedback Copyright © 2009–2017, Texas Instruments Incorporated Product Folder Links: THS6214 37 THS6214 SBOS431A – MAY 2009 – REVISED MARCH 2017 www.ti.com 11 Device and Documentation Support 11.1 Receiving Notification of Documentation Updates To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper right corner, click on Alert me to register and receive a weekly digest of any product information that has changed. For change details, review the revision history included in any revised document. 11.2 Community Resources The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of Use. TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help solve problems with fellow engineers. Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and contact information for technical support. 11.3 Trademarks PowerPAD, E2E are trademarks of Texas Instruments. All other trademarks are the property of their respective owners. 11.4 Electrostatic Discharge Caution This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. 11.5 Glossary SLYZ022 — TI Glossary. This glossary lists and explains terms, acronyms, and definitions. 12 Mechanical, Packaging, and Orderable Information The following pages include mechanical, packaging, and orderable information. This information is the most current data available for the designated devices. This data is subject to change without notice and revision of this document. For browser-based versions of this data sheet, refer to the left-hand navigation. 38 Submit Documentation Feedback Copyright © 2009–2017, Texas Instruments Incorporated Product Folder Links: THS6214 PACKAGE OPTION ADDENDUM www.ti.com 10-Dec-2020 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan (2) Lead finish/ Ball material MSL Peak Temp Op Temp (°C) Device Marking (3) (4/5) (6) THS6214IPWP ACTIVE HTSSOP PWP 24 60 RoHS & Green NIPDAU Level-2-260C-1 YEAR -40 to 85 THS6214 THS6214IPWPR ACTIVE HTSSOP PWP 24 2000 RoHS & Green NIPDAU Level-2-260C-1 YEAR -40 to 85 THS6214 THS6214IRHFR ACTIVE VQFN RHF 24 3000 RoHS & Green NIPDAU | NIPDAUAG Level-2-260C-1 YEAR -40 to 85 6214 THS6214IRHFT ACTIVE VQFN RHF 24 250 RoHS & Green NIPDAU | NIPDAUAG Level-2-260C-1 YEAR -40 to 85 6214 (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of