THS8136PHPR

THS8136 www.ti.com SLES236B – NOVEMBER 2008 – REVISED APRIL 2013 TRIPLE 10-BIT 180-MSPS GRAPHICS AND VIDEO DAC Check for Samples: THS8136 FEATURES APPLICATIONS • • • • 1 2 • • • • • • • Triple 10-Bit Digital-to-Analog Converters (DACs) 180-MSPS Operation Direct Drive of Double-Terminated 75-Ω Load Into Standard Video Levels Bi-Level Sync and Blank Level Generation Internal Voltage Reference Low-Power Operation From 3.3-V Analog and 1.8-V Digital Supply Levels 1.8-V Compatible Inputs Qualified for Automotive Applications (AEC-Q100 Rev G – THS8136IPHPQ1, THS8136IPHPRQ1) Graphics and Video Generation High-Resolution Image Processing Generic Triple D/A Converter DESCRIPTION The THS8136 is a general-purpose triple high-speed digital-to-analog (D/A) converter optimized for use in video/graphics applications. The device operates from 3.3-V analog and 1.8-V digital supplies with D/A converter performance assured at sampling rates up to 180 MHz. The THS8136 consists of three 10-bit D/A converters and additional circuitry for bi-level sync and blanking level generation. The current-steering DACs have been specifically designed to produce standard video output levels when directly connected to a single-ended doubleterminated 75-Ω coaxial cable. By providing a dc offset in sync insertion mode, the THS8136 can generate a bi-level sync on the AG DAC output without sacrificing DAC resolution. Support is also provided for insertion of RGB or YPbPr reference or blanking levels, irrespective of the DAC input codes. A generic DAC mode is provided for applications not requiring sync generation. All digital inputs are 1.8-V compatible. ORDERING INFORMATION (1) TA 0°C to 70°C –40°C to 85°C (1) (2) (3) PACKAGED DEVICES (2) PowerPAD™ TQFP-48 – PHP PACKAGE OPTION THS8136PHP Tray THS8136PHPR Tape and reel THS8136IPHP Tray THS8136IPHPR Tape and reel THS8136IPHPQ1 (3) Tray THS8136IPHPRQ1 (3) Tape and reel For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI web site at www.ti.com. Package drawings, thermal data, and symbolization are available at www.ti.com/packaging. AEC-Q100 Rev G certified 1 2 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. PowerPAD is a trademark of Texas Instruments. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright © 2008–2013, Texas Instruments Incorporated THS8136 SLES236B – NOVEMBER 2008 – REVISED APRIL 2013 www.ti.com M2 M1 AVSS AB AVDD AR AVSS AG AVDD COMP FSADJ VREF PHP (TQFP-48) PowerPAD PACKAGE (TOP VIEW) 48 47 46 45 44 43 42 41 40 39 38 37 B9 B8 B7 B6 B5 B4 B3 B2 B1 B0 DV SS DV DD 1 36 2 35 3 34 4 33 5 32 6 31 7 30 8 29 9 28 10 27 11 26 25 12 G0 G1 G2 G3 G4 G5 G6 G7 G8 G9 CLK SYNC-T R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 BLANK SYNC 13 14 15 16 17 18 19 20 21 22 23 24 2 Submit Documentation Feedback Copyright © 2008–2013, Texas Instruments Incorporated Product Folder Links: THS8136 THS8136 www.ti.com SLES236B – NOVEMBER 2008 – REVISED APRIL 2013 TERMINAL FUNCTIONS TERMINAL NAME NO. I/O DESCRIPTION AB 45 O Analog blue current output, capable of directly driving a double terminated 75-Ω coaxial cable AG 41 O Analog green current output, capable of directly driving a double terminated 75-Ω coaxial cable AR 43 O Analog red current output, capable of directly driving a double terminated 75-Ω coaxial cable AVDD 40, 44 I Analog power supply (3.3 V). All AVDD pins must be connected. AVSS 42, 46 I Analog ground SYNC 24 I Sync insertion input. Active low. When asserted, the G output is forced to the bottom sync tip level. SYNC-T 25 I Connect to DVSS (GND) or logic low to enable bi-level sync insertion. Connect to DVDD (1.8 V) or logic high for generic DAC applications not requiring sync insertion. M2 48 I Connect to DVSS (GND) or logic 0 for RGB blanking level operation. Connect to the SYNC control input for YPbPr video operation. M1 47 I Must be tied to DVSS (GND) or logic 0 for normal operation. B0 B1 B2 B3 B4 B5 B6 B7 B8 B9 10 9 8 7 6 5 4 3 2 1 I Blue or (Pb) pixel data input. Signals with index 0 denote the least significant bit. Unused inputs should be connected to DVSS(GND). BLANK 23 I Blanking control input, active low. A rising edge on CLK latches BLANK. When asserted, the AR, AG, and AB outputs are driven to the reference blanking level, regardless of the value on the data inputs. CLK 26 I Clock input. A rising edge on CLK latches R0–R9, G0–G9, B0–B9, and BLANK. COMP 39 O Compensation terminal. A 0.1-µF capacitor must be connected between COMP and AVDD. DVDD 12 I Digital power supply (1.8 V) DVSS 11 I Digital ground FSADJ 38 I Full-scale adjust control. The full-scale current drive on each of the output channels is determined by the value of a resistor RFS connected between this terminal and AVSS. Figure 3 shows the relationship between full-scale output voltage compliance and RFS for the nominal DAC termination of 37.5 Ω. G0 G1 G2 G3 G4 G5 G6 G7 G8 G9 36 35 34 33 32 31 30 29 28 27 I Green (or Y) pixel data input. Signals with index 0 denote the least significant bit. Unused inputs should be connected to DVSS(GND). R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 13 14 15 16 17 18 19 20 21 22 I Red (or Pr) pixel data input. Signals with index 0 denote the least significant bit. Unused inputs should be connected to DVSS(GND). VREF 37 O Voltage reference for DACs. An internal voltage reference of nominally 1.2 V is provided, which requires an external 0.1-µF ceramic capacitor between VREF and AVSS. Submit Documentation Feedback Copyright © 2008–2013, Texas Instruments Incorporated Product Folder Links: THS8136 3 THS8136 SLES236B – NOVEMBER 2008 – REVISED APRIL 2013 www.ti.com DETAILED DESCRIPTION The THS8136 is a fast well-matched triple DAC with current outputs optimized for graphics and video applications without sacrificing is usefulness as a generic DAC. The DAC output stages are designed to provide direct drive of doubly-terminated 75-Ω loads (37.5 Ω). The full-scale output current of all three DACs is determined by a single resistor connecting the FSADJ pin to AVSS (GND). A 3.8-kΩ resistor is suitable for most applications requiring 700-mV output levels. Additional circuitry and digital input controls for analog sync and blank level generation are provided for both RGB and YPbPr color spaces. A generic mode of operation is provided for applications not requiring sync insertion. Figure 1 shows a block diagram of the device. DVDD COMP FSADJ VREF DVSS Bandgap Reference R[9:0] Input Formatter G[9:0] B[9:0] CLK M1 M2 R Register DAC AR G Register DAC AG B Register DAC AB Configuration Control AVDD SYNC/BLANK Control SYNC BLANK SYNC_T AVSS Figure 1. Functional Block Diagram Generic DAC Mode Versus Sync Insertion Mode When configured for sync insertion, the THS8136 provides additional dc bias on the DAC outputs to provide headroom for negative bi-level sync insertion. Such bias might be undesirable in applications where no analog sync insertion is required, since it results in additional power consumption and might prevent dc coupling of the DAC outputs. In such cases, only triple DAC operation without dc bias (i.e., DAC input code 0 corresponding to 0-V output) might be preferred. Generic DAC mode is easily selected by connecting the SYNC and SYNC_T pins to DVDD (or logic 1) and the M1 and M2 pins to DVSS (or logic 0). BLANK is functional in both generic mode and sync insertion mode. 4 Submit Documentation Feedback Copyright © 2008–2013, Texas Instruments Incorporated Product Folder Links: THS8136 THS8136 www.ti.com SLES236B – NOVEMBER 2008 – REVISED APRIL 2013 Blanking Generation The BLANK control input forces the output amplitude on all channels to the blanking or reference level, irrespective of the value on the data input ports. The output blanking level on each channel and its relation to active video varies depending on the mode of operation. In generic DAC mode, the output blank level for each DAC is at 0 V and corresponds to a DAC input code of 0. When sync insertion is enabled a 350-mV dc bias (RFS selected for 700-mV output) is applied to provide room for bi-level sync insertion. When RGB sync insertion is enabled, the output blank level of each DAC will be at 350 mV and will correspond to a DAC input code of 0. In YPbPr video mode, the blank level of each DAC is 350 mV, but the AR and AB blank levels correspond to a DAC input code of 512 to accommodate mid-level UV blank levels. A video to blank level amplitude ratio of 2:1 is maintained for various RFS values, provided the maximum DAC output compliance is not exceeded. Sync Generation The SYNC and SYNC_T control inputs can be used to enable the superposition of a bi-level sync on the AG DAC output. Correctly timed assertion of the SYNC input (active low) allows insertion of an analog composite sync on the AG DAC output consisting of horizontal sync and vertical sync. The video to sync amplitude ratio is 7:3 providing a 300 mV sync tip, when FSADJ is selected to provide 700 mV full-scale graphics or video. This 7:3 video to sync amplitude ratio is maintained for various RFS values, provided the maximum DAC output compliance is not exceeded. The SYNC-T input pin must be connected to DVSS (or logic low) to enable sync insertion. Device Configuration The THS8136 operating mode is determined from the state of the SYNC, SYNC-T, M1, and M2 control terminals. Generic DAC mode is easily selected by connecting SYNC and SYNC_T to DVDD (or logic high) and M1 and M2 to DVSS (logic low). To enable sync insertion, the SYNC_T terminal must be connected to DVSS (or logic low). YPbPr video mode can be selected for support of mid-level PbPr blanking by connecting the sync control input to both the SYNC and M2 input terminals. The M1 terminal must be connected to DVSS (logic 0) for all operating modes. See Table 1 and Figure 4, Figure 5, and Figure 6 for additional information on configuring the THS8136. Table 1. Table 1. Device Configuration OPERATING MODE M1 M2 SYNC_T SYNC DESCRIPTION Generic DAC 0 0 1 1 Sync insertion disabled. The blank level on all DAC outputs corresponds to 0-V and DAC input code 0. RGB Sync Insertion 0 0 0 SYNC DC bias and sync insertion enabled. The blank level on all DAC outputs corresponds to DAC input code 0. YPbPr Sync Insertion 0 SYNC 0 SYNC DC bias and sync insertion enabled. AB and AR mid-level blanking corresponds to DAC input code 512. DAC Operation The DAC output drivers generate a current with a drive level that can be user-modified by choosing an appropriate resistor value RFS connected between the FSADJ terminal and AVSS (GND). All current source amplitudes (graphics/video, blanking, and sync on AG) are derived from RFS and an internal voltage reference such that the relative amplitudes of sync, blank, and graphics/video are always equal to their nominal relationships. The relative amplitudes of these current drivers are maintained without regard to the value of RFS, as long as the maximum current drive capability is not exceeded. Figure 3 shows the relationship between RFS and the current drive level on each channel for full-range DAC input. The voltage compliance outputs in Figure 3 assume termination with a 37.5-Ω resistor. When sync insertion is enabled, an additional current source is enabled providing a DC bias and head-room for negative sync insertion. A fixed RFS value of 3.8 kΩ (RFS(nom)) is suitable for most applications requiring 700-mV output levels. Submit Documentation Feedback Copyright © 2008–2013, Texas Instruments Incorporated Product Folder Links: THS8136 5 THS8136 SLES236B – NOVEMBER 2008 – REVISED APRIL 2013 www.ti.com IOUT 75-W Cable DACs ZL =75 W (Monitor) ZS = 75 W Figure 2. DAC Output Termination OUTPUT VOLTAGE vs FULL-SCALE RESISTANCE 1450 1350 VO – Output Voltage – mV 1250 Full-scale DAC output current adjustment at 37.5-W DAC termination 1150 1050 950 850 750 650 550 450 350 1.8 2.3 2.8 3.3 3.8 4.3 4.8 5.3 5.8 6.3 6.8 7.3 R(FS) – Full-Scale Resistance – kW Figure 3. Output Voltage vs Full-Scale Resistance The user is free to connect another resistor value, but care should be taken not to exceed the maximum current level on each of the DAC outputs as shown in the specifications section. Additionally, DAC output linearity will degrade if the 1.2-V maximum output compliance is exceeded. 6 Submit Documentation Feedback Copyright © 2008–2013, Texas Instruments Incorporated Product Folder Links: THS8136 THS8136 www.ti.com SLES236B – NOVEMBER 2008 – REVISED APRIL 2013 Input Codes AR, AG, AB VO mV 1023 700 0 0 700 mV BLANK NOTE: BLANK = High in applications not requiring a forced blank level. RFS chosen for 700-mV output. RLOAD = 37.5 Ω Figure 4. Generic DAC Mode (M1 = Low, M2 = Low, SYNC = High, SYNC_T = High) Input Codes VO mV 1023 1050 0 350 700 mV AG 300 mV 50 SYNC BLANK AR, AB Input Codes VO mV 1023 1050 0 350 700 mV NOTE: RFS chosen for 700-mV output. RLOAD = 37.5 Ω Figure 5. RGB Sync-on-G (M1 = Low, M2 = Low, SYNC_T = Low) Submit Documentation Feedback Copyright © 2008–2013, Texas Instruments Incorporated Product Folder Links: THS8136 7 THS8136 SLES236B – NOVEMBER 2008 – REVISED APRIL 2013 www.ti.com Input Codes VO mV 1023 1050 0 350 700 mV AG 300 mV 50 SYNC M2 BLANK Input Codes 700 mV VO mV 1023 700 512 350 0 0 AR, AB NOTE: RFS chosen for 700-mV output. RLOAD = 37.5 Ω Figure 6. YPbPr Sync-on-Y (M1 = Low, M2 = SYNC, SYNC_T = Low) 8 Submit Documentation Feedback Copyright © 2008–2013, Texas Instruments Incorporated Product Folder Links: THS8136 THS8136 www.ti.com SLES236B – NOVEMBER 2008 – REVISED APRIL 2013 ABSOLUTE MAXIMUM RATINGS (1) over operating free-air temperature range (unless otherwise noted) Supply voltage AVDD to AVSS –0.5 V to 3.6 V DVDD to DVSS –0.5 V to 1.95 V AVSS to DVSS –0.5 to 0.5 V Digital input voltage range to DVSS TA Operating free-air temperature range Tstg Storage temperature range VESD (1) (2) (3) (4) ESD stress voltage (2) –0.5 V to (DVDD + 0.5) V –40°C to 85°C –55°C to 150°C Human-body model (HBM) (3), All pins >2000 V Charged-device model (CDM) (4), All pins >500 V Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. Electrostatic discharge (ESD) to measure device sensitivity/immunity to damage caused by electrostatic discharges into the device. Level listed is the passing level per ANSI/ESDA/JEDEC JS-001-2010 and AEC Q100-002 rev D. JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process, and manufacturing with less than 500-V HBM is possible if necessary precautions are taken. Pins listed as 2000 V may actually have higher performance. Level listed is the passing level per EIA-JEDEC JESD22-C101E and AEC Q100-011 rev B. JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process. Pins listed as 500 V may actually have higher performance. Corner pins meet the AEC Q100-011 rev B 750-V requirement. THERMAL SPECIFICATIONS TEST CONDITIONS (1) PARAMETER θJA Junction-to-ambient thermal resistance, still air θJC Junction-to-case thermal resistance, still air TJ(MAX) Maximum junction temperature for reliable operation (1) MIN TYP MAX UNIT Thermal PAD soldered to 4-layer High-K PCB 29.11 °C/W Low-K PCB, Thermal PAD not soldered 64.42 °C/W 0.12 105 °C UNIT When split ground planes are used, attach the thermal pad to the analog ground plane. RECOMMENDED OPERATING CONDITIONS MIN NOM MAX AVDD 3 3.3 3.6 V DVDD 1.65 1.8 1.95 V Power Supply Digital and Reference Inputs VIH High-level input voltage 1.2 DVDD V VIL Low-level input voltage DVSS 0.7 V fCLK Clock frequency 0 180 MHz tw(CLKH) Pulse duration, clock high 40% 60% CLK period tw(CLKL) Pulse duration, clock low 40% 60% CLK period RFS(nom) FSADJ resistor (1) (1) 3.8 kΩ RFS should be chosen such that the maximum full-scale DAC output current (IFS) does not exceed the maximum stated level. This yields the nominal output voltage compliance at the nominal load termination of 37.5 Ω. Submit Documentation Feedback Copyright © 2008–2013, Texas Instruments Incorporated Product Folder Links: THS8136 9 THS8136 SLES236B – NOVEMBER 2008 – REVISED APRIL 2013 www.ti.com POWER SUPPLY ELECTRICAL CHARACTERISTICS over recommended operating conditions, fCLK = 180 MHz, use of internal reference voltage VREF, RFS = RFS(nom), 37.5-Ω load termination (unless otherwise noted) TEST CONDITIONS (1) PARAMETER CLK = 80 MSPS CLK = 180 MSPS IAVDD Operating supply current, analog CLK = 80 MSPS CLK = 180 MSPS CLK = 80 MSPS CLK = 180 MSPS CLK = 80 MSPS CLK = 180 MSPS IDVDD Operating supply current, digital CLK = 80 MSPS CLK = 180 MSPS CLK = 80 MSPS CLK = 180 MSPS CLK = 80 MSPS CLK = 180 MSPS PD Power dissipation CLK = 80 MSPS CLK = 180 MSPS CLK = 80 MSPS CLK = 180 MSPS (1) (2) (3) MIN Generic (700 mV) Generic (1.2 mV) Sync Insertion (700 mV + Sync) Generic (700 mV) Generic (1.2 mV) Sync Insertion (700 mV + Sync) Generic (700 mV) Generic (1.2 mV) Sync Insertion (700 mV + Sync) TYP (2) MAX (3) 65 72 65 72 110 112 110 112 94 102 94 103 13 16 31 36 14 16 31 37 13 16 31 36 238 290 270 329 388 434 419 475 334 398 366 441 UNIT mA mA mW A multiburst RGB input test pattern was used in all cases. TYP current and PD measured at AVDD = 3.3 V and DVDD = 1.8 V. MAX current and PD measured at AVDD = 3.6 V and DVDD = 1.95 V. DIGITAL INPUTS – DC ELECTRICAL CHARACTERISTICS over recommended operating conditions, fCLK = 180 MHz, use of internal reference voltage VREF, RFS = RFS(nom), 37.5-Ω load termination (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT IIH High-level input current AVDD = 3.3 V, DVDD = 1.8 V, Digital inputs at 1.95 V IIL Low-level input current AVDD = 3.3 V, DVDD = 1.8 V, Digital inputs at 0 V IIH(CLK) High-level input current, CLK AVDD = 3.3 V, DVDD = 1.8 V, CLK at 1.95 V –1 IIL(CLK) Low-level input current, CLK AVDD = 3.3 V, DVDD = 1.8 V, CLK at 0 V –1 CI Input capacitance TA = 25°C ts Setup time, data and control inputs (1) 1.5 ns th Hold time, data and control inputs (1) 500 ps td(D) Digital process delay time from first registered color component of pixel (2) (1) (2) 10 5 7.5 1 µA –1 µA 1 µA 1 µA pF CLK periods Specified by characterization only. This parameter is specified by design. The digital process delay is defined as the number of CLK cycles required for the first registered color component of a pixel, starting from the time of registering it on the input bus, to propagate through all processing and appear at the DAC output drivers. The remaining delay through the IC is the analog delay td(A) of the analog output drivers. Submit Documentation Feedback Copyright © 2008–2013, Texas Instruments Incorporated Product Folder Links: THS8136 THS8136 www.ti.com SLES236B – NOVEMBER 2008 – REVISED APRIL 2013 ANALOG (DAC) OUTPUTS ELECTRICAL CHARACTERISTICS over recommended operating conditions, fCLK = 180 MHz, use of internal reference voltage VREF, RFS = RFS(nom), 37.5-Ω load termination (unless otherwise noted) PARAMETER TEST CONDITIONS MIN DAC resolution INL Integral nonlinearity -1/1 –2.5/1.5 Static, best fit, generic mode, 1.2 V output range –1/1 Static, RGB with sync insertion (700 + sync) –0.4/0.4 Static, generic mode, 1.2 V output range -0.4/0.4 PSRR Power supply ripple rejection ratio of f = DC (1) DAC output (full scale) Vrefo Voltage reference output RR VREF output resistance KIMBAL Imbalance between DACs (2) VOC DAC output compliance voltage tFDAC ±1 38.5 1.12 1.16 –2 LSB LSB dB 1.20 V Ω 284 CLK = 80 MSPS, video mode UNIT Bits Static, best fit, RGB with sync insertion (700 + sync) Differential nonlinearity tRDAC MAX 10 DNL IFS TYP 1.8 2 % 0.7 1.2 V Generic DAC mode CLK = 80 MSPS (3) 18 18.67 19.5 RGB with sync insertion enabled CLK = 80 MSPS (3) 27 28 29.3 DAC output current rise time CLK = 80 MSPS, 10 to 90% of full scale (4) 2.8 3.3 3.6 ns (4) 2.8 3.3 3.6 ns mA DAC output current fall time CLK = 80 MSPS, 10 to 90% of full scale td(A) Analog output delay Measured from CLK = VIH(min) to 50% of fullscale transition (5) 4.5 ns tS Analog output settling time Measured from 50% of full scale transition on output to output settling, within 2% (4) 15 ns (1) (2) (3) (4) (5) PSRR is measured with a 0.1-µF capacitor between the COMP and AVDD pins and with a 0.1-µF capacitor connected between the VREF and AVSS pins. The ripple amplitude is within the range 100 mVp-p to 500 mVp-p with the DAC output set to full scale and a doubleterminated 75 Ω (= 37.5 Ω) load. PSRR is defined as 20 × log(ripple voltage at DAC output/ripple voltage at AVDD input). Limits are from characterization only. The imbalance between DACs applies to all possible pairs of the three DACs. Values at RFS = RFS(nom) From characterization only. Measured on the AG channel with RFS = RFS(nom). This value excludes the digital process delay, tD(D). Limit are from characterization only. Submit Documentation Feedback Copyright © 2008–2013, Texas Instruments Incorporated Product Folder Links: THS8136 11 THS8136 SLES236B – NOVEMBER 2008 – REVISED APRIL 2013 www.ti.com TYPICAL CHARACTERISTICS CLK T0 T1 T2 T3 T4 T5 T6 T7 T8 R(0) R(1) R(2) R(3) R(4) R(5) R(6) R(7) R(8) G(0) G(1) G(2) G(3) G(4) G(5) G(6) G(7) G(8) B(0) B(1) B(2) B(3) B(4) B(5) B(6) B(7) B(8) Data Path Latency = 7.5 CLK Cycles R(0), G(0), B(0) Registered AR, AG, AB Output Corresponding to R(0), G(0), B(0) Figure 7. Input Data Internally Latched on Rising Edge of CLK (Data Path Latency is 7.5 CLK Cycles) CLK ts th RGB Data, SYNC, BLANK, M2 Figure 8. Input Data Registered on Rising Edge of CLK 400 390 380 P – Power – mW 370 360 350 340 330 320 310 300 0 50 100 150 200 250 300 f – Frequency – MHz Figure 9. Power vs Clock Frequency, RGB Sync Insertion, 1-MHz Input Tone on All Channels 12 Submit Documentation Feedback Copyright © 2008–2013, Texas Instruments Incorporated Product Folder Links: THS8136 THS8136 www.ti.com SLES236B – NOVEMBER 2008 – REVISED APRIL 2013 APPLICATION INFORMATION DVDD AVDD FB FB D 1.8 V A 3.3 V 10 µF 10 µF 0.1 µF 0.1 µF 10 µF 0.1 µF 12 40 DVDD AVDD 44 AVDD 27–36 G[9:0] 1–10 FB 41 G[9:0] B[9:0] 10 µF AG 75 W 75 W B[9:0] FB 43 AR 13–22 R[9:0] R[9:0] 75 W 75 W FB 45 Monitor AB DVDD 23 24 2.2 kW AVDD SYNC 25 39 SYNC_T 0.1 µF 48 VSYNC 37 VREF CLK 47 HSYNC COMP 26 CLK 75 W 75 W THS8136 BLANK 0.1 µF M1 38 FSADJ M2 2.2 kW DVSS 11 AVSS 42 AVSS Thermal Pad 3.8 kW 46 NOTE: System level ESD protection is not included in this application circuit, but it is highly recommended on the analog RGB outputs. Figure 10. Typical Generic DAC Application Circuit Submit Documentation Feedback Copyright © 2008–2013, Texas Instruments Incorporated Product Folder Links: THS8136 13 THS8136 SLES236B – NOVEMBER 2008 – REVISED APRIL 2013 www.ti.com REVISION HISTORY REVISION SLES236 14 COMMENTS Initial release SLES236A AEC-Q100 qualification added. Added ESD data to Absolute Maximum Ratings table. Power dissipation ratings changed to Thermal specifications. Modified Digital inputs - DC electrical characteristics table. SLES236B Figure 10, Added note concerning ESD protection. Submit Documentation Feedback Copyright © 2008–2013, Texas Instruments Incorporated Product Folder Links: THS8136 PACKAGE MATERIALS INFORMATION www.ti.com 5-Jan-2022 TRAY Chamfer on Tray corner indicates Pin 1 orientation of packed units. *All dimensions are nominal Device Package Name Package Type Pins SPQ Unit array Max L (mm) W matrix temperature (mm) (°C) THS8136IPHP PHP HTQFP 48 250 10 x 25 150 315 THS8136PHP PHP HTQFP 48 250 10 x 25 150 315 Pack Materials-Page 1 K0 (µm) P1 (mm) CL (mm) CW (mm) 135.9 7620 12.2 11.1 11.25 135.9 7620 12.2 11.1 11.25 GENERIC PACKAGE VIEW PHP 48 TQFP - 1.2 mm max height 7 x 7, 0.5 mm pitch QUAD FLATPACK This image is a representation of the package family, actual package may vary. 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