TMP112-Q1
SLOS887F – SEPTEMBER 2014 – REVISED JUNE 2022
TMP112-Q1 Automotive Grade High-Accuracy, Low-Power,
Digital Temperature Sensor in SOT563
1 Features
3 Description
•
The TMP112-Q1 device is a digital temperature
sensor designed for NTC/PTC thermistor replacement
where high accuracy is required. The device offers
an accuracy of ±0.5°C without requiring calibration
or external component signal conditioning. Device
temperature sensors are highly linear and do not
require complex calculations or lookup tables to
derive the temperature. The calibrating for improved
accuracy feature allows users to calibrate for an
accuracy as good as ±0.17°C (see the Calibrating for
Improved Accuracy section). The on-chip 12-bit ADC
offers resolutions down to 0.0625°C.
•
•
•
•
•
•
•
•
AEC-Q100 qualified with:
– Temperature grade 1: –40°C to 125°C Ambient
Operating Temperature Range
– Device HBM ESD classification level 2
– Device CDM ESD classification level C6
Functional Safety-Capable
– Documentation available to aid functional safety
system design
SOT563 package (1.6 mm × 1.6 mm) is a 68%
smaller footprint than SOT23
Accuracy without calibration:
– 0.5°C (maximum) from 0°C to 65°C
– 1°C (maximum) from –40°C to 125°C
Low quiescent current:
– 10-μA active (maximum)
– 1-μA shutdown (maximum)
Supply range: 1.4 to 3.6 V
Resolution: 12 bits
Digital output: SMBus, two-wire and I2C interface
compatibility
NIST traceable
The 1.6-mm × 1.6-mm SOT563 package is 68%
smaller footprint than an SOT23 package. The
TMP112-Q1 device features SMBus™, two-wire and
I2C interface compatibility, and allows up to four
devices on one bus. The device also features an
SMBus alert function. The device is specified to
operate over supply voltages from 1.4 to 3.6 V with
the maximum quiescent current of 10 µA over the full
operating range.
2 Applications
•
•
•
•
•
•
•
•
•
Device Information(1)
PART NUMBER
Climate control
Infotainment processor management
Airflow sensor
Battery control unit
Engine control unit
UREA sensors
Water pumps
HID lamps
Airbag control unit
TMP112-Q1
(1)
SCL
2
3
1
2
3
Diode
temp.
sensor
Control
logic
6
ΔΣ
ADC
Serial
interface
5
Oscillator
Config.
and temp.
register
4
SDA
V+
ADD0
TMP112-Q1
SCL
SDA
GND
V+
ALERT
GND
ALERT
TMP112-Q1
1
1.60 mm × 1.20 mm
For all available packages, see the orderable addendum at
the end of the data sheet.
Supply Bypass
Capacitor
0.01 µF
5k
Two-Wire
Host Controller
SOT563 (6)
BODY SIZE (NOM)
Temperature
Supply Voltage
1.4 V to 3.6 V
Pullup Resistors
PACKAGE
6
Block Diagram
5
4
ADD0
Simplified Schematic
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
TMP112-Q1
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SLOS887F – SEPTEMBER 2014 – REVISED JUNE 2022
Table of Contents
1 Features............................................................................1
2 Applications..................................................................... 1
3 Description.......................................................................1
4 Revision History.............................................................. 2
5 Description (continued).................................................. 3
6 Pin Configuration and Functions...................................4
7 Specifications.................................................................. 5
7.1 Absolute Maximum Ratings........................................ 5
7.2 ESD Ratings............................................................... 5
7.3 Recommended Operating Conditions.........................5
7.4 Thermal Information....................................................5
7.5 Electrical Characteristics.............................................5
7.6 Specifications for User-Calibrated Systems................6
7.7 Timing Requirements.................................................. 7
7.8 Typical Characteristics................................................ 8
8 Detailed Description......................................................10
8.1 Overview................................................................... 10
8.2 Functional Block Diagram......................................... 10
8.3 Feature Description...................................................11
8.4 Device Functional Modes..........................................17
8.5 Programming............................................................ 19
9 Application and Implementation.................................. 24
9.1 Application Information............................................. 24
9.2 Typical Application.................................................... 27
10 Power Supply Recommendations..............................28
11 Layout........................................................................... 29
11.1 Layout Guidelines................................................... 29
11.2 Layout Example...................................................... 29
12 Device and Documentation Support..........................30
12.1 Documentation Support.......................................... 30
12.2 Receiving Notification of Documentation Updates..30
12.3 Community Resources............................................30
12.4 Trademarks............................................................. 30
13 Mechanical, Packaging, and Orderable
Information.................................................................... 30
4 Revision History
Changes from Revision E (December 2018) to Revision F (June 2022)
Page
• Updated the numbering format for tables, figures, and cross-references throughout the document..................1
• Changed all instances of legacy terminology to controller and target where I2C is mentioned.......................... 1
• Added the Functional Safety information to the Features section...................................................................... 1
Changes from Revision D (December 2015) to Revision E (December 2018)
Page
• Updated description for ADD0 pin for connection to SDA and SCL................................................................... 4
• Changed supply voltage maximum value from: 5 V to: 4 V................................................................................ 5
• Changed input voltage maximum value for the SCL, ADD0, and SDA pins from: 5 V to: 4 V............................5
• Changed input voltage maximum value for the ALERT pin from: (V+) + 0.5 V to: (V+) + 0.3 and ≤ 4................5
• Updated junction-to-ambient thermal resistance from 200 °C/W to 210.3 °C/W................................................ 5
• Updated junction-to-case (top) thermal resistance from 73.7 °C/W to 105.0 °C/W ........................................... 5
• Updated junction-to-board thermal resistance from 34.4 °C/W to 87.5 °C/W.....................................................5
• Updated junction-to-top characterization parameter from 3.1 °C/W to 6.1 °C/W ...............................................5
• Updated junction-to-board characterization parameter from 34.2 °C/W to 87.0 °C/W....................................... 5
• Added Receiving Notification of Documentation Updates section ...................................................................30
Changes from Revision C (March 2015) to Revision D (December 2015)
Page
• Added NIST Features bullet .............................................................................................................................. 1
• Added last paragraph to Description section ..................................................................................................... 1
Changes from Revision B (November 2014) to Revision C (March 2015)
Page
• Updated pin numbers on the schematic images ................................................................................................1
• Changed the Handling Ratings table to ESD Ratings and moved the storage temperature parameter to the
Absolute Maximum Ratings table ...................................................................................................................... 5
• Changed min, typ, max values for the Temperature Accuracy (temperature error) parameter ......................... 5
• Changed the frequency from 2.85 to 3.4 MHz in the POWER SUPPLY section of the Electrical Characteristics
table.................................................................................................................................................................... 5
• Changed the Temperature Error at 25°C graph in the Typical Characteristics section.......................................8
• Changed the Temperature Error vs. Temperature graph in the Typical Characteristics section ........................8
2
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Changes from Revision A (October 2014) to Revision B (November 2014)
Page
• Changed device status from Product Preview to Production Data .................................................................... 1
5 Description (continued)
The TMP112-Q1 device is designed for extended temperature measurement in control units, climate control,
infotainment, and sensor modules. The device is specified for operation over a temperature range of –40°C to
125°C.
The TMP112-Q1 production units are 100% tested against sensors that are NIST-traceable and are verified with
equipment that are NIST-traceable through ISO/IEC 17025 accredited calibrations.
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6 Pin Configuration and Functions
1
GND
2
ALERT
3
SLP
SCL
6
SDA
5
V+
4
ADD0
Figure 6-1. DRL Package 6-Pin SOT563 Top View
Table 6-1. Pin Functions
PIN
NO.
4
NAME
I/O
DESCRIPTION
1
SCL
I
2
GND
—
Ground
3
ALERT
O
Overtemperature alert. Open-drain output; requires a pullup resistor.
4
ADD0
I
Address select. Connect to V+, GND, SDA or SCL
Supply voltage, 1.4 V to 3.6 V
5
V+
I
6
SDA
I/O
Serial clock. Open-drain output; requires a pullup resistor.
Serial data. Open-drain output; requires a pullup resistor.
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7 Specifications
7.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)(1)
MIN
MAX
UNIT
4
V
–0.5
4
V
Voltage at ALERT
–0.5
(V+) + 0.3
and ≤ 4
V
Output voltage
–0.5
5
V
Operating temperature
–55
150
°C
150
°C
150
°C
Supply voltage
V+
Voltage at SCL, ADD0, and SDA
Junction temperature, TJ
Storage temperature, Tstg
(1)
–60
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress
ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under
Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device
reliability.
7.2 ESD Ratings
VALUE
V(ESD)
(1)
Human body model (HBM), per AEC
Electrostatic discharge
Q100-002(1)
UNIT
±2000
Charged device model (CDM), per AEC Q100-011
V
±1000
AEC Q100-002 indicates HBM stressing is done in accordance with the ANSI/ESDA/JEDEC JS-001 specification.
7.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MIN
NOM
3.3
V+
Supply Voltage
1.4
TA
Operating free-air temperature
–40
MAX
UNIT
3.6
V
125
°C
7.4 Thermal Information
TMP112-Q1
THERMAL
METRIC(1)
DRL (SOT563)
UNIT
6 PINS
RθJA
Junction-to-ambient thermal resistance
210.3
°C/W
RθJC(top)
Junction-to-case (top) thermal resistance
105.0
°C/W
RθJB
Junction-to-board thermal resistance
87.5
°C/W
ψJT
Junction-to-top characterization parameter
6.1
°C/W
ψJB
Junction-to-board characterization parameter
87.0
°C/W
(1)
For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.
7.5 Electrical Characteristics
At TA = 25°C and V+ = 1.4 to 3.6 V, unless otherwise noted.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
125
°C
TEMPERATURE INPUT
Temperature range
–40
25°C, V+ = 3.3 V
Temperature accuracy
(temperature error)
0°C to 65°C, V+ = 3.3 V
–40°C to 125°C
±0.1
±0.5
±0.25
±0.5
±0.5
±1.0
°C
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At TA = 25°C and V+ = 1.4 to 3.6 V, unless otherwise noted.
PARAMETER
TEST CONDITIONS
Accuracy vs. supply
–40°C to 125°C
Long-term stability
3000 Hours
MIN
TYP
MAX
UNIT
0.0625
±0.25
°C/V
2 V, IOL = 3 mA
0
0.4
V+ < 2 V, IOL = 3 mA
0
0.2 × (V+)
V+ > 2 V, IOL = 3 mA
0
0.4
V+< 2 V, IOL = 3 mA
0
0.2 × (V+)
Resolution
Conversion time
Conversion modes
pF
0.7 × (V+)
V
V
V
12
One-shot mode
Bits
26
CR1 = 0, CR0 = 0
0.25
CR1 = 0, CR0 = 1
1
CR1 = 1, CR0 = 0 (default)
4
CR1 = 1, CR0 = 1
8
Timeout time
35
ms
Conv/s
30
40
ms
3.6
V
POWER SUPPLY
Operating supply range
1.4
Serial bus inactive, CR1 = 1, CR0 = 0
(default)
IQ
Average quiescent current
ISD
Shutdown current
7
Serial bus active, SCL frequency
(ƒ(SCL)) = 400 kHz
15
Serial bus active, ƒ(SCL) = 3.4 MHz
85
Serial bus inactive
0.5
Serial bus active, ƒ(SCL) = 400 kHz
10
Serial bus active, ƒ(SCL) = 3.4 MHz
80
10
μA
1
μA
7.6 Specifications for User-Calibrated Systems
For additional information on the slopes listed in this table, see the Calibrating for Improved Accuracy section.
PARAMETER
Average Slope
(Temperature Error vs. Temperature)(1)
(1)
6
CONDITION
MIN
MAX
V+ = 3.3, –40°C to 25°C
–7
0
m°C/°C
UNIT
V+ = 3.3, 25°C to 85°C
0
5
m°C/°C
V+ = 3.3, 85°C to 125°C
0
8
m°C/°C
User-calibrated temperature accuracy can be within ±1LSB because of quantization noise.
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7.7 Timing Requirements
See the Timing Diagrams section for timing diagrams.
FAST MODE
V+
HIGH-SPEED
MODE
MIN
MAX
MIN
MAX
0.001
0.4
0.001
2.85
UNIT
ƒ(SCL)
SCL operating frequency
t(BUF)
Bus-free time between STOP and START
condition
600
160
ns
t(HDSTA)
Hold time after repeated START condition.
After this period, the first clock is generated.
600
160
ns
t(SUSTA)
repeated start condition setup time
600
160
ns
t(SUSTO)
STOP condition setup time
600
160
ns
t(HDDAT)
Data hold time
100
t(SUDAT)
Data setup time
100
25
ns
t(LOW)
SCL-clock low period
V+ , see Two-Wire Timing
Diagrams
1300
210
ns
t(HIGH)
SCL-clock high period
See Two-Wire Timing Diagrams
tFD
Data fall time
See Two-Wire Timing Diagrams
300
See Two-Wire Timing Diagrams
300
ns
tRD
Data rise time
SCLK ≤ 100 kHz, see Two-Wire
Timing Diagrams
1000
ns
tFC
Clock fall time
See Two-Wire Timing Diagrams
300
40
ns
tRC
Clock rise time
See Two-Wire Timing Diagrams
300
40
ns
See Two-Wire Timing Diagrams
900
600
25
105
60
MHz
ns
ns
80
ns
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7.8 Typical Characteristics
At TA = 25°C and V+ = 3.3 V, unless otherwise noted.
30
25
Population
Population
20
15
10
-0.250
-0.225
-0.200
-0.175
-0.150
-0.125
-0.100
-0.075
-0.050
-0.025
0
0.025
0.050
0.075
0.100
0.125
0.150
0.175
0.200
0.225
0.250
0.3
0.35
0.2
0.25
0.15
0.1
0.05
0
-0.05
-0.1
-0.15
-0.2
-0.25
-0.3
0
-0.35
5
D001
Temperature Error (qC)
Accuracy vs Supply (°C/V)
Figure 7-2. Accuracy vs. Supply
1
20
0.8
18
0.6
16
Quiescent Current (µA)
Temperature Error (qC)
Figure 7-1. Temperature Error at 25°C
0.4
0.2
0
-0.2
-0.4
-0.6
-0.8
-1
-60
Mean
Mean + 3 V
Mean 3 V
-40
-20
0
1.4-V Supply
3.6-V Supply
14
12
10
8
6
4
2
0
20
40
60
80
Temperature (qC)
100
120
-60
140
-40 -20
40
60
80
100 120 140 160
Four conversions per second
Figure 7-3. Temperature Error vs. Temperature
Figure 7-4. Average Quiescent Current vs.
Temperature
100
10
1.4-V Supply
9
8
7
6
5
4
3
2
–55°C
90
3.6-V Supply
25°C
125°C
80
Quiescent Current (µA)
Shutdown Current (µA)
20
Temperature (°C)
.
70
60
50
40
30
20
10
1
0
0
-60
-40 -20
0
20
40
60
80
100 120 140 160
1k
10k
100k
1M
10M
Bus Frequency (Hz)
Temperature (°C)
.
Temperature at 3.3-V supply
Figure 7-5. Shutdown Current vs. Temperature
8
0
D002
Figure 7-6. Quiescent Current vs. Bus Frequency
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40
1.4-V Supply
Conversion Time (ms)
38
3.6-V Supply
36
34
32
30
28
26
24
22
20
-60
-40 -20
0
20
40
60
80
100 120 140 160
Temperature (°C)
Figure 7-7. Conversion Time vs. Temperature
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8 Detailed Description
8.1 Overview
The TMP112-Q1 device is a digital temperature sensor that is optimal for thermal-management and thermalprotection applications. The TMP112-Q1 device is two-wire, SMBus and I2C interface-compatible. The device
is specified over an operating temperature range of –40°C to 125°C. Figure 8-1 shows a block diagram of the
TMP112-Q1 device. Figure 8-2 illustrates the ESD protection circuitry contained in the TMP112-Q1 device.
The temperature sensor in the TMP112-Q1 device is the chip itself. Thermal paths run through the package
leads as well as the plastic package. The package leads provide the primary thermal path because of the lower
thermal resistance of the metal.
An alternative version of the TMP112-Q1 device is available. The TMP102-Q1 device has reduced accuracy, the
same micro-package, and is pin-to-pin compatible.
Table 8-1. Advantages of TMP112-Q1 vs. TMP102-Q1
Device
Compatible
Interfaces
Package
Supply
Current
Supply
Voltage
(Min)
Supply
Voltage
(Max)
Resolution
Local Sensor Accuracy
(Max)
Specified
Calibration
Drift Slope
TMP112-Q1
I2C
SMBus
SOT563
1.2 × 1.6 × 0.6
10 µA
1.4 V
3.6 V
12-bit
0.0625°C
0.5°C: (0°C to 65°C)
1°C: (-40°C to 125°C)
Yes
I2C
SOT563
1.2 × 1.6 × 0.6
10 µA
1.4 V
3.6 V
12-bit
0.0625°C
2°C: (25°C to 85°C)
3°C: (-40°C to 125°C)
No
TMP102-Q1
SMBus
8.2 Functional Block Diagram
Temperature
SCL
GND
ALERT
1
2
3
Diode
temp.
sensor
Control
logic
6
ΔΣ
ADC
Serial
interface
5
Oscillator
Config.
and temp.
register
4
SDA
V+
ADD0
TMP112-Q1
Figure 8-1. Internal Block Diagram
10
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Device
SCL
SDA
V+
GND
Core
V+
ALERT
A0
Figure 8-2. Equivalent Internal ESD Circuitry
8.3 Feature Description
8.3.1 Digital Temperature Output
The digital output from each temperature measurement conversion is stored in the read-only temperature
register. The temperature register of the TMP112-Q1 device is configured as a 12-bit read-only register (setting
the EM bit to 0 in the configuration register; see the Extended Mode (EM) section), or as a 13-bit read-only
register (setting the EM bit to 1 in the configuration register) that stores the output of the most recent conversion.
Two bytes must be read to obtain data and are listed in Table 8-8. Byte 1 is the most significant byte (MSB),
followed by byte 2, the least significant byte (LSB). The first 12 bits (13 bits in extended mode) are used to
indicate temperature. The least significant byte does not have to be read if that information is not needed. The
data format for temperature is listed in Table 8-2 and Table 8-3. One LSB equals 0.0625°C. Negative numbers
are represented in binary twos complement format. Following power up or reset, the temperature register reads
0°C until the first conversion is complete. Bit D0 of byte 2 indicates normal mode (EM bit equals 0) or extended
mode (EM bit equals 1), and can be used to distinguish between the two temperature register data formats. The
unused bits in the temperature register always read 0.
Table 8-2. 12-Bit Temperature Data Format(1)
(1)
TEMPERATURE (°C)
DIGITAL OUTPUT (BINARY)
HEX
128
0111 1111 1111
7FF
127.9375
0111 1111 1111
7FF
100
0110 0100 0000
640
80
0101 0000 0000
500
75
0100 1011 0000
4B0
50
0011 0010 0000
320
25
0001 1001 0000
190
0.25
0000 0000 0100
004
0
0000 0000 0000
000
–0.25
1111 1111 1100
FFC
–25
1110 0111 0000
E70
–55
1100 1001 0000
C90
The resolution for the temperature ADC in internal temperature mode is 0.0625°C/count.
Table 8-2 does not list all temperatures. Use the following rules to obtain the digital data format for a given
temperature or the temperature for a given digital data format.
To convert positive temperatures to a digital data format:
1. Divide the temperature by the resolution
2. Convert the result to binary code with a 12-bit, left-justified format, and MSB = 0 to denote a positive sign.
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Example: (50°C) / (0.0625°C / LSB) = 800 = 320h = 0011 0010 0000
To convert a positive digital data format to temperature:
1. Convert the 12-bit, left-justified binary temperature result, with the MSB = 0 to denote a positive sign, to a
decimal number.
2. Multiply the decimal number by the resolution to obtain the positive temperature.
Example: 0011 0010 0000 = 320h = 800 × (0.0625°C / LSB) = 50°C
To convert negative temperatures to a digital data format:
1. Divide the absolute value of the temperature by the resolution, and convert the result to binary code with a
12-bit, left-justified format.
2. Generate the twos complement of the result by complementing the binary number and adding one. Denote a
negative number with MSB = 1.
Example: (|–25°C|) / (0.0625°C / LSB) = 400 = 190h = 0001 1001 0000
Two's complement format: 1110 0110 1111 + 1 = 1110 0111 0000
To convert a negative digital data format to temperature:
1. Generate the twos compliment of the 12-bit, left-justified binary number of the temperature result (with
MSB = 1, denoting negative temperature result) by complementing the binary number and adding one. This
represents the binary number of the absolute value of the temperature.
2. Convert to decimal number and multiply by the resolution to get the absolute temperature, then multiply by
–1 for the negative sign.
Example: 1110 0111 0000 has twos compliment of 0001 1001 0000 = 0001 1000 1111 + 1
Convert to temperature: 0001 1001 0000 = 190h = 400; 400 × (0.0625°C / LSB) = 25°C = (|–25°C|); (|–
25°C|) × (–1) = –25°C
Table 8-3. 13-Bit Temperature Data Format
TEMPERATURE (°C)
12
DIGITAL OUTPUT (BINARY)
HEX
150
0 1001 0110 0000
0960
128
0 1000 0000 0000
0800
127.9375
0 0111 1111 1111
07FF
100
0 0110 0100 0000
0640
80
0 0101 0000 0000
0500
75
0 0100 1011 0000
04B0
50
0 0011 0010 0000
0320
25
0 0001 1001 0000
0190
0.25
0 0000 0000 0100
0004
0
0 0000 0000 0000
0000
–0.25
1 1111 1111 1100
1FFC
–25
1 1110 0111 0000
1E70
–55
1 1100 1001 0000
1C90
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8.3.2 Serial Interface
The TMP112-Q1 device operates as a target device only on the I2C, SMBus and two-wire interface-compatible
bus. Connections to the bus are made through the open-drain I/O lines, SDA and SCL. The SDA and SCL
pins feature integrated spike suppression filters and Schmitt triggers to minimize the effects of input spikes and
bus noise. The TMP112-Q1 device supports the transmission protocol for both fast (1 kHz to 400 kHz) and
high-speed (1 kHz to 2.85 MHz) modes. All data bytes are transmitted MSB first.
8.3.2.1 Bus Overview
The device that initiates the transfer is called a controller, and the devices controlled by the controller are targets.
The bus must be controlled by a controller device that generates the serial clock (SCL), controls the bus access,
and generates the START and STOP conditions.
To address a specific device, a START condition is initiated, indicated by pulling the data-line (SDA) from a highto low-logic level when the SCL pin is high. All targets on the bus shift in the target address byte on the rising
edge of the clock, with the last bit indicating whether a read or write operation is intended. During the ninth clock
pulse, the target being addressed responds to the controller by generating an acknowledge and pulling the SDA
pin low.
A data transfer is then initiated and sent over eight clock pulses followed by an acknowledge bit. During the data
transfer the SDA pin must remain stable when the SCL pin is high, because any change in the SDA pin when the
SCL pin is high is interpreted as a START or STOP signal.
When all data have been transferred, the controller generates a STOP condition indicated by pulling the SDA pin
from low to high when the SCL pin is high.
8.3.2.2 Serial Bus Address
To communicate with the TMP112-Q1 device, the controller must first address target devices through a targetaddress byte. The target-address byte consists of seven address bits and a direction bit indicating the intent of
executing a read or write operation.
The TMP112-Q1 device features an address pin to allow up to four devices to be addressed on a single bus.
Table 8-4 lists the pin logic levels used to properly connect up to four devices.
Table 8-4. Address Pin and Target Addresses
DEVICE TWO-WIRE ADDRESS
A0 PIN CONNECTION
1001 000
Ground
1001 001
V+
1001 010
SDA
1001 011
SCL
8.3.2.3 Writing and Reading Operation
Accessing a particular register on the TMP112-Q1 device is accomplished by writing the appropriate value to the
pointer register. The value for the pointer register is the first byte transferred after the target address byte with
the R/ W bit low. Every write operation to the TMP112-Q1 device requires a value for the pointer register (see
Figure 8-4).
When reading from the TMP112-Q1 device, the last value stored in the pointer register by a write operation is
used to determine which register is read by a read operation. To change the register pointer for a read operation,
a new value must be written to the pointer register. This action is accomplished by issuing a target-address byte
with the R/ W bit low, followed by the pointer register byte. No additional data are required. The controller can
then generate a START condition and send the target address byte with the R/ W bit high to initiate the read
command. See Figure 8-5 for details of this sequence. If repeated reads from the same register are desired,
continuously sending the pointer register bytes is not necessary because the TMP112-Q1 device retains the
pointer register value until the value is changed by the next write operation.
Register bytes are sent with the most significant byte first, followed by the least significant byte.
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8.3.2.4 Target Mode Operation
The TMP112-Q1 device can operate as a target receiver or target transmitter. As a target device, the TMP112Q1 device never drives the SCL line.
8.3.2.4.1 Target Receiver Mode
The first byte transmitted by the controller is the target address with the R/ W bit low. The TMP112-Q1 device
then acknowledges reception of a valid address. The next byte transmitted by the controller is the pointer
register. The TMP112-Q1 device then acknowledges reception of the pointer register byte. The next byte or
bytes are written to the register addressed by the pointer register. The TMP112-Q1 device acknowledges
reception of each data byte. The controller can terminate data transfer by generating a START or STOP
condition.
8.3.2.4.2 Target Transmitter Mode
The first byte transmitted by the controller is the target address with the R/ W bit high. The target acknowledges
reception of a valid target address. The next byte is transmitted by the target and is the most significant byte of
the register indicated by the pointer register. The controller acknowledges reception of the data byte. The next
byte transmitted by the target is the least significant byte. The controller acknowledges reception of the data
byte. The controller can terminate data transfer by generating a not-acknowledge on reception of any data byte
or by generating a START or STOP condition.
8.3.2.5 SMBus Alert Function
The TMP112-Q1 device supports the SMBus alert function. When the TMP112-Q1 device operates in interrupt
mode (TM = 1), the ALERT pin can be connected as an SMBus alert signal. When a controller senses that
an alert condition is present on the alert line, the controller sends an SMBus ALERT command (0001 1001) to
the bus. If the ALERT pin is active, the device acknowledges the SMBus ALERT command and responds by
returning the target address on the SDA line. The eighth bit (LSB) of the target address byte indicates if the
alert condition is caused by the temperature exceeding T(HIGH) or falling below T(LOW). The LSB is high if the
temperature is greater than T(HIGH), or low if the temperature is less than T(LOW). See Figure 8-6 for details of this
sequence.
If multiple devices on the bus respond to the SMBus ALERT command, arbitration during the target address
portion of the SMBus ALERT command determines which device clears the alert status of that device. The
device with the lowest two-wire address wins the arbitration. If the TMP112-Q1 device wins the arbitration, the
TMP112-Q1 ALERT pin becomes inactive at the completion of the SMBus ALERT command. If the TMP112-Q1
device loses the arbitration, the TMP112-Q1 ALERT pin remains active.
8.3.2.6 General Call
The TMP112-Q1 device responds to a two-wire general-call address (0000 000) if the eighth bit is 0. The device
acknowledges the general-call address and responds to commands in the second byte. If the second byte is
0000 0110, the TMP112-Q1 internal registers are reset to power-up values. The TMP112-Q1 device does not
support the general-address acquire command.
8.3.2.7 High-Speed (Hs) Mode
In order for the two-wire bus to operate at frequencies above 400 kHz, the controller device must issue an
Hs-mode controller code (0000 1xxx) as the first byte after a START condition to switch the bus to high-speed
operation. The TMP112-Q1 device does not acknowledge this byte, but switches the input filters on the SDA
and SCL pins and the output filters on the SDA pin to operate in Hs-mode thus allowing transfers at up to 2.85
MHz. After the Hs-mode controller code has been issued, the controller transmits a two-wire target address to
initiate a data-transfer operation. The bus continues to operate in Hs-mode until a STOP condition occurs on the
bus. Upon receiving the STOP condition, the TMP112-Q1 device switches the input and output filters back to
fast-mode operation.
8.3.2.8 Timeout Function
The TMP112-Q1 device resets the serial interface if the SCL pin is held low for 30 ms (typical) between a start
and stop condition. The TMP112-Q1 releases the SDA line if the SCL pin is pulled low and waits for a start
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condition from the host controller. To avoid activating the timeout function, maintain a communication speed of at
least 1 kHz for SCL operating frequency.
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8.3.2.9 Timing Diagrams
The TMP112-Q1 device is two-wire, SMBus and I2C interface-compatible. Figure 8-3 to Figure 8-6 illustrate the
various operations on the TMP112-Q1 device. Parameters for Figure 8-3 are listed in the Timing Requirements
table. The bus definitions are defined as follows:
Bus Idle:
Both SDA and SCL lines remain high.
Start Data
Transfer:
A change in the state of the SDA line, from high to low, when the SCL line is high, defines
a START condition. Each data transfer is initiated with a START condition.
Stop Data
Transfer:
A change in the state of the SDA line from low to high when the SCL line is high defines
a STOP condition. Each data transfer is terminated with a repeated START or STOP
condition.
Data Transfer:
The number of data bytes transferred between a START and a STOP condition is not
limited and is determined by the controller device. Using the TMP112-Q1 device for single
byte updates is also possible. To update only the most-significant (MS) byte, terminate the
communication by issuing a START or STOP communication on the bus.
Acknowledge:
Each receiving device, when addressed, is obliged to generate an acknowledge bit. A
device that acknowledges must pull down the SDA line during the acknowledge clock pulse
in such a way that the SDA line is stable low during the high period of the acknowledge
clock pulse. Setup and hold times must be taken into account. On a controller receive,
the termination of the data transfer can be signaled by the controller generating a notacknowledge (1) on the last byte that has been transmitted by the target.
8.3.2.9.1 Two-Wire Timing Diagrams
See the Timing Requirements table for timing specifications.
t(LOW)
tFC
t(HDSTA)
tRC
SCL
t(HDSTA)
t(HIGH)
t(SUSTO)
t(SUSTA)
t(HDDAT)
t(SUDAT)
SDA
t(BUF)
P
tRD
tFD
S
S
P
Figure 8-3. Two-Wire Timing Diagram
1
9
1
9
SCL
SDA
¼
1
0
0
1
0
A1(1)
A0(1)
R/W
Start By
Controller
0
0
0
0
0
0
P1
P0
ACK By
Device
¼
ACK By
Device
Frame 2 Pointer Register Byte
Frame 1 Two-Wire Target Address Byte
9
1
1
9
SCL
(Continued)
SDA
(Continued)
D7
D6
D5
D4
D3
D2
D1
D0
D7
D6
D5
D4
D3
D2
D1
D0
ACK By
Device
ACK By
Device
Frame 3 Data Byte 1
A.
Stop By
Controller
Frame 4 Data Byte 2
The values of A0 and A1 are determined by the ADD0 pin.
Figure 8-4. Two-Wire Timing Diagram for Write Word Format
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1
9
1
9
SCL
¼
SDA
1
0
0
1
0
A1
(1)
A0
(1)
R/W
Start By
Controller
0
0
0
0
0
0
P1
P0
ACK By
Device
ACK By
Device
Frame 1 Two-Wire Target Address Byte
Stop By
Controller
Frame 2 Pointer Register Byte
1
9
1
9
SCL
(Continued)
¼
SDA
(Continued)
1
0
0
1
0
A1
(1)
A0
(1)
R/W
Start By
Controller
D7
D6
D5
D4
D3
D1
D0
From
Device
ACK By
Device
Frame 3 Two-Wire Target Address Byte
1
D2
¼
ACK by
Controller
(2)
Frame 4 Data Byte 1 Read Register
9
SCL
(Continued)
SDA
(Continued)
D7
D6
D5
D4
D3
D2
D1
D0
From
Device
ACK by
Controller
(3)
Stop by
Controller
Frame 5 Data Byte 2 Read Register
A.
B.
C.
The values of A0 and A1 are determined by the ADD0 pin.
The controller must leave the SDA pin high to terminate a single-byte read operation.
The controller must leave the SDA pin high to terminate a two-byte read operation.
Figure 8-5. Two-Wire Timing Diagram for Read Word Format
ALERT
1
9
1
9
SCL
SDA
0
0
0
1
1
0
0
R/W
Start By
Controller
1
0
1
ACK By
Device
Frame 1 SMBus ALERT Response Address Byte
A.
0
A1
A0
From
Device
Status
NACK By Stop By
Controller Controller
Frame 2 Target Address from Device
The values of A0 and A1 are determined by the ADD0 pin.
Figure 8-6. Timing Diagram for SMBus ALERT
8.4 Device Functional Modes
8.4.1 Continuous-Conversion Mode
The default mode of the TMP112-Q1 device is continuous conversion mode. During continuous-conversion
mode, the ADC performs continuous temperature conversions and stores each results to the temperature
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register, overwriting the result from the previous conversion. The conversion rate bits, CR1 and CR0, configure
the TMP112-Q1 device for conversion rates of 0.25 Hz, 1 Hz, 4 Hz, or 8 Hz. The default rate is 4 Hz. The
TMP112-Q1 device has a typical conversion time of 26 ms. To achieve different conversion rates, the TMP112Q1 device makes a conversion and then powers down and waits for the appropriate delay set by CR1 and CR0.
Table 8-5 lists the settings for CR1 and CR0.
Table 8-5. Conversion Rate Settings
CR1
CR0
CONVERSION RATE
0
0
0.25 Hz
0
1
1 Hz
1
0
4 Hz (default)
1
1
8 Hz
After a power up or general-call reset, the TMP112-Q1 device immediately begins a conversion as shown in
Figure 8-7. The first result is available after 26 ms (typical). The active quiescent current during conversion is
40 μA (typical at 27°C). The quiescent current during delay is 2.2 μA (typical at 27°C).
Delay
(1)
26 ms
26 ms
Startup
A.
Start of
Conversion
The delay is set by CR1 and CR0 bits in the configuration register.
Figure 8-7. Conversion Start
8.4.2 Extended Mode (EM)
The extended mode bit configures the device for normal mode operation (EM = 0) or extended mode operation
(EM = 1). In normal mode, the temperature register and the high and low limit registers use a 12-bit data format.
Normal mode is used to make the TMP112-Q1 device compatible with the TMP75 device.
Extended mode (EM = 1) allows measurement of temperatures above 128°C by configuring the temperature
register and the high and low limit registers for 13-bit data format.
8.4.3 Shutdown Mode (SD)
The shutdown mode bit saves maximum power by shutting down all device circuitry other than the serial
interface which reduces current consumption to typically less than 0.5 μA. Shutdown mode is enabled when the
SD bit is set to 1. When this bit is set to 1 the device shuts down when current conversion is completed. When
the SD bit is set to 0 the device maintains a continuous conversion state.
8.4.4 One-Shot and Conversion Ready Mode (OS)
The TMP112-Q1 device features a one-shot temperature-measurement mode. When the device is in shutdown
mode, writing a 1 to the OS bit begins a single temperature conversion. During the conversion, the OS bit reads
0. The device returns to the SHUTDOWN state at the completion of the single conversion. After the conversion,
the OS bit reads 1. This feature is useful for reducing power consumption in the TMP112-Q1 device when
continuous temperature monitoring is not required.
As a result of the short conversion time, the TMP112-Q1 device can achieve a higher conversion rate. A single
conversion typically occurs for 26 ms and a read can occur in less than 20 μs. When using one-shot mode, 30 or
more conversions per second are possible.
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8.4.5 Thermostat Mode (TM)
The thermostat mode bit indicates to the device whether to operate in comparator mode (TM = 0 ) or interrupt
mode (TM = 1).
8.4.5.1 Comparator Mode (TM = 0)
In Comparator mode (TM = 0), the Alert pin is activated when the temperature equals or exceeds the value in
the T(HIGH) register and remains active until the temperature falls below the value in the T(LOW)register. For more
information on the comparator mode, see the High- and Low-Limit Registers section.
8.4.5.2 Interrupt Mode (TM = 1)
In Interrupt mode (TM = 1), the Alert pin is activated when the temperature exceeds T(HIGH) or goes below T(LOW)
registers. The Alert pin is cleared when the host controller reads the temperature register. For more information
on the interrupt mode, see the High- and Low-Limit Registers section.
8.5 Programming
8.5.1 Pointer Register
Figure 8-8 shows the internal register structure of the TMP112-Q1 device. The 8-bit pointer register of the device
is used to address a given data register. The pointer register uses the two LSBs (see Table 8-12) to identify
which of the data registers must respond to a read or write command. The power-up reset value of the P[1:0]
byte is 00. By default, the TMP112-Q1 device reads the temperature on power up.
Pointer
Register
Temperature
Register
Configuration
Register
T(LOW)
Register
SCL
I/O
Control
Interface
SDA
T(HIGH)
Register
Figure 8-8. Internal Register Structure
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Table 8-6 lists the pointer address of the registers available in the TMP112-Q1 device.Table 8-7 lists the bits of
the pointer register byte. During a write command, bytes P2 through P7 must always be 0.
Table 8-6. Pointer Addresses
P1
P0
REGISTER
0
0
Temperature register (read only [R])
0
1
Configuration register (read-write [R/W])
1
0
T(LOW) register (R/W)
1
1
T(HIGH) register (R/W)
Table 8-7. Pointer Register Byte
P7
P6
P5
P4
P3
P2
0
0
0
0
0
0
P1
P0
Register Bits
8.5.2 Temperature Register
The temperature register of the TMP112-Q1 device is configured as a 12-bit read-only register (setting the EM
bit to 0 in the configuration register; see the Extended Mode (EM) section), or as a 13-bit read-only register
(setting the EM bit to 1 in the configuration register) that stores the output of the most recent conversion. Two
bytes must be read to obtain data and are listed in Table 8-8. Byte 1 is the most significant byte (MSB), followed
by byte 2, the least significant byte (LSB). The first 12 bits (13 bits in extended mode) are used to indicate
temperature. The least significant byte does not have to be read if that information is not needed.
Table 8-8. Bytes 1 and 2 of Temperature Register(1)
BYTE
1
2
(1)
D7
D6
D5
D4
D3
D2
D1
D0
T11
T10
T9
T8
T7
T6
T5
T4
(T12)
(T11)
(T10)
(T9)
(T8)
(T7)
(T6)
(T5)
T3
T2
T1
T0
0
0
0
0
(T4)
(T3)
(T2)
(T1)
(T0)
(0)
(0)
(1)
Extended mode 13-bit configuration shown in parentheses.
8.5.3 Configuration Register
The configuration register is a 16-bit R/W register used to store bits that control the operational modes of the
temperature sensor. Read-write operations are performed MSB first. Table 8-9 lists the format and power-up and
reset values of the configuration register. For compatibility, the first byte corresponds to the configuration register
in the TMP75 and TMP275 devices. All registers are updated byte by byte.
Table 8-9. Configuration and Power-Up and Reset Formats
BYTE
1
2
D7
D6
D5
D4
D3
D2
D1
D0
OS
R1
R0
F1
F0
POL
TM
SD
0
1
1
0
0
0
0
0
CR1
CR0
AL
EM
0
0
0
0
1
0
1
0
0
0
0
0
8.5.3.1 Shutdown Mode (SD)
The shutdown mode bit saves maximum power by shutting down all device circuitry other than the serial
interface which reduces current consumption to typically less than 0.5 μA. Shutdown mode is enabled when the
SD bit is set to 1. When this bit is set to 1 the device shuts down when current conversion is completed. When
the SD bit is set to 0 the device maintains a continuous conversion state.
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8.5.3.2 Thermostat Mode (TM)
The thermostat mode bit indicates to the device whether to operate in comparator mode (TM = 0) or interrupt
mode (TM = 1). For more information on comparator and interrupt modes, see the High- and Low-Limit Registers
section.
8.5.3.3 Polarity (POL)
The polarity bit allows the user to adjust the polarity of the ALERT pin output. If the POL bit is set to 0 (default),
the ALERT pin becomes active low . When the POL bit is set to 1, the ALERT pin becomes active high and the
state of the ALERT pin is inverted. The operation of the ALERT pin in various modes is shown in Figure 8-9.
T(HIGH)
Measured
Temperature
T(LOW)
ALERT PIN
(Comparator Mode)
POL = 0
ALERT PIN
(Interrupt Mode)
POL = 0
ALERT PIN
(Comparator Mode)
POL = 1
ALERT PIN
(Interrupt Mode)
POL = 1
Read
Read
Read
Time
Figure 8-9. Output Transfer Function Diagrams
8.5.3.4 Fault Queue (F1/F0)
A fault condition exists when the measured temperature exceeds the user-defined limits set in the T(HIGH) and
T(LOW) registers. Additionally, the number of fault conditions required to generate an alert can be programmed
using the fault queue. The fault queue is provided to prevent a false alert as a result of environmental noise. The
fault queue requires consecutive fault measurements in order to trigger the alert function. Table 8-10 lists the
number of measured faults that can be programmed to trigger an alert condition in the device. For T(HIGH) and
T(LOW) register format and byte order, see the High- and Low-Limit Registers section.
Table 8-10. TMP112-Q1 Fault Settings
F1
F0
CONSECUTIVE FAULTS
0
0
1
0
1
2
1
0
4
1
1
6
8.5.3.5 Converter Resolution (R1 and R0)
The converter resolution bits, R1 and R0, are read-only bits. The TMP112-Q1 converter resolution is set on start
up to 11 which sets the temperature register to a 12 bit-resolution.
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8.5.3.6 One-Shot (OS)
When the device is in shutdown mode, writing a 1 to the OS bit begins a single temperature conversion. During
the conversion, the OS bit reads 0. The device returns to the SHUTDOWN state at the completion of the single
conversion. For more information on the one-shot conversion mode, see the One-Shot and Conversion Ready
Mode (OS) section.
8.5.3.7 Extended Mode (EM)
The extended mode bit configures the device for normal mode operation (EM = 0) or extended mode operation
(EM = 1). In normal mode, the temperature register and the high and low limit registers use a 12-bit data format.
For more information on the extended mode, see the Extended Mode (EM) section.
8.5.3.8 Alert (AL)
The AL bit is a read-only function. Reading the AL bit provides information about the comparator mode status.
The state of the POL bit inverts the polarity of data returned from the AL bit. When the POL bit equals 0, the AL
bit reads as 1 until the temperature equals or exceeds T(HIGH) for the programmed number of consecutive faults,
causing the AL bit to read as 0. The AL bit continues to read as 0 until the temperature falls below T(LOW) for the
programmed number of consecutive faults, when it again reads as 1. The status of the TM bit does not affect the
status of the AL bit.
8.5.3.9 Conversion Rate (CR)
The conversion rate bits, CR1 and CR0, configure the TMP112-Q1 device for conversion rates of 0.25 Hz, 1
Hz, 4 Hz, or 8 Hz. The default rate is 4 Hz. For more information on conversion rate bits, see the ContinuousConversion Mode section.
8.5.4 High- and Low-Limit Registers
The temperature limits are stored in the T(LOW) and T(HIGH) registers in the same format as the temperature
result, and their values are compared to the temperature result on every conversion. The outcome of the
comparison drives the behavior of the ALERT pin, which operates as a comparator output or an interrupt, and is
set by the TM bit in the configuration register.
In Comparator mode (TM = 0), the ALERT pin becomes active when the temperature equals or exceeds the
value in the T(HIGH) register and generates a consecutive number of faults according to fault bits F1 and F0. The
ALERT pin remains active until the temperature falls below the indicated T(LOW) value for the same number of
faults.
In interrupt mode (TM = 1), the ALERT pin becomes active when the temperature equals or exceeds the value
in T(HIGH) for a consecutive number of fault conditions (as shown in Table 8-10). The ALERT pin remains active
until a read operation of any register occurs, or the device successfully responds to the SMBus alert response
address. The ALERT pin is also cleared if the device is placed in shutdown mode. When the ALERT pin is
cleared, it becomes active again only when temperature falls below T(LOW), and remains active until cleared
by a read operation of any register or a successful response to the SMBus alert response address. When the
ALERT pin is cleared, the above cycle repeats, with the ALERT pin becoming active when the temperature
equals or exceeds T(HIGH). The ALERT pin can also be cleared by resetting the device with the general-call
Reset command. This action also clears the state of the internal registers in the device, returning the device to
comparator mode (TM = 0).
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Both operating modes are represented in Figure 8-9. Table 8-11 and Table 8-12 list the format for the T(HIGH) and
T(LOW) registers. The most significant byte is sent first, followed by the least significant byte. The power-up reset
values for T(HIGH) and T(LOW) are:
• T(HIGH) = 80°C
• T(LOW) = 75°C
The format of the data for T(HIGH) and T(LOW) is the same as for the temperature register.
Table 8-11. Bytes 1 and 2 of T(HIGH) Register(1)
BYTE
1
2
(1)
D7
D6
D5
D4
D3
D2
D1
H11
H10
H9
H8
H7
H6
H5
D0
H4
(H12)
(H11)
(H10)
(H9)
(H8)
(H7)
(H6)
(H5)
H3
H2
H1
H0
0
0
0
0
(H4)
(H3)
(H2)
(H1)
(H0)
(0)
(0)
(0)
Extended mode 13-bit configuration shown in parenthesis.
Table 8-12. Bytes 1 and 2 of T(LOW) Register(1)
BYTE
1
2
(1)
D7
D6
D5
D4
D3
D2
D1
D0
L11
L10
L9
L8
L7
L6
L5
L4
(L12)
(L11)
(L10)
(L9)
(L8)
(L7)
(L6)
(L5)
L3
L2
L1
L0
0
0
0
0
(L4)
(L3)
(L2)
(L1)
(L0)
(0)
(0)
(0)
Extended mode 13-bit configuration shown in parenthesis.
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9 Application and Implementation
Note
Information in the following applications sections is not part of the TI component specification,
and TI does not warrant its accuracy or completeness. TI’s customers are responsible for
determining suitability of components for their purposes, as well as validating and testing their design
implementation to confirm system functionality.
9.1 Application Information
9.1.1 Calibrating for Improved Accuracy
Many temperature monitoring applications require better than 0.5°C accuracy over a limited temperature range.
Knowing the offset of a temperature sensor at a given temperature in conjunction with the average temperature
span (slope) error over a fixed range makes achieving this improved accuracy possible.
The TMP112-Q1 device has three distinct slope regions that conservatively approximate the inherent curvature.
The following lists the three distinct slope regions:
1. Slope1 applies over –40°C to 25°C
2. Slope2 applies over 25°C to 85°C
3. Slope3 applies over 85°C to 125°C
The Specifications for User-Calibrated Systems table defines these slopes which are also shown in Figure 9-1.
Note
Each slope listed in the Specifications for User-Calibrated Systems table is increasing with respect to
25°C.
0.8
Slope3MAX
Slope1MAX
Temperature Error (°C)
0.6
Slope2MAX
0.4
0.2
0
-0.2
-0.4
Slope1MIN
Slope2MIN
Slope3MIN
-0.6
-40 -30 -20 -10 0 10 20 30 40 50 60 70 80 90 100 110 120 130
Temperature (°C)
Figure 9-1. Accuracy and Slope Curves versus Temperature
Use Equation 1 to calculate the worst-case accuracy at a specific temperature.
Accuracy(worst-case) = Accuracy(25°C) + DT ´ Slope
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9.1.1.1 Example 1: Finding Worst-Case Accuracy From –15°C to 50°C
As an example, if the user is concerned only about the temperature accuracy between –15°C to 50°C, the
worst-case accuracy could be determined by using the two slope calculations shown in Equation 2 and Equation
4:
Accuracy(worst -case ) = Accuracy(25°C ) + DT ´ Slope
(2)
æ m°C ö
Accuracy(MAX[ -15°C to 25°C] ) = 0.3°C + (-15°C - 25°C ) ´ ç -7
÷ = 0.58°C
°C ø
è
(3)
Accuracy(MAX[25°C to 50°C] ) = Accuracy(25°C ) + DT ´ Slope2(MAX )
(4)
æ m°C ö
Accuracy(MAX[25°C to 50°C] ) = 0.3°C + (50°C - 25°C ) ´ ç 5
÷ = 0.425°C
è °C ø
(5)
The same calculations must be applied to the minimum case:
Accuracy(MIN[ -15°C to 25°C] ) = Accuracy(25°C ) + DT ´ Slope1(MIN)
(6)
é
Accuracy(MIN[ -15°C to 25°C] ) = -0.5°C + ê(-15°C - 25°C ) ´
ë
(7)
æ m°C ö ù
ç 0 °C ÷ ú = -0.5°C
è
øû
Accuracy(MIN[25°C to 50°C] ) = Accuracy(25°C ) + DT ´ Slope2(MIN)
(8)
é
Accuracy(MIN[25°C to 50°C] ) = -0.5°C + ê(50°C - 25°C ) ´
ë
(9)
æ m°C ö ù
ç 0 °C ÷ ú = -0.5°C
è
øû
Based on these calculations, a user can expect a worst-case accuracy of 0.58°C to –0.5°C in the temperature
range of –15°C to 50°C.
9.1.1.2 Example 2: Finding Worst-Case Accuracy From 25°C to 100°C
If the desired temperature range falls in the region of slope 3, first calculate the worst-case value from 25°C to
85°C and add it to the change in temperature multiplied by the span error of slope 3. As an example, consider
the temperature range of 25°C to 125°C as shown in Equation 10:
Accuracy(MAX[25°C to 100°C] ) = Accuracy(25°C ) + DT ´ Slope2(MAX ) + DT ´ Slope3(MAX )
(10)
m°C ö
æ
æ m°C ö
Accuracy(MAX[25°C to 100°C] ) = 0.3°C + (85°C - 25°C ) ´ ç 4.5
÷ + (100°C - 85°C ) ´ ç 8
÷ = 0.69°C
°C ø
è
è °C ø
(11)
Then perform the same calculation for the minimum case as shown in Equation 12:
Accuracy(MIN[25°C to 100°C] ) = Accuracy(25°C ) + DT ´ Slope2(MIN) + DT ´ Slope3(MIN)
(12)
é
æ m°C ö ù é
æ m°C ö ù
Accuracy(MIN[25°C to 100°C] ) = -0.5°C + ê(85°C - 25°C ) ´ ç 0
÷ ú + ê(100°C - 85°C ) ´ ç 0 °C ÷ ú = -0.5°C
è °C ø û ë
è
øû
ë
(13)
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9.1.2 Using The Slope Specifications With a 1-Point Calibration
The initial accuracy assurance at 25°C with the slope regions provides an accuracy that is high enough for most
applications. However, if higher accuracy is desired, this increase can be achieved with a 1-point calibration
at 25°C. This calibration removes the offset at room temperature, thereby reducing the source of error in a
TMP112-Q1 temperature reading down to the curvature. Figure 9-2 shows the error of a calibrated TMP112-Q1
device.
0.8
Slope3MAX
Temperature Error (°C)
0.6
0.4
Slope1MAX
Slope2MAX
0.2
0
-0.2
Calibration at 25°C Removes Offset
-0.4
-0.6
-40 -30 -20 -10 0 10 20 30 40 50 60 70 80 90 100 110 120 130
Temperature (°C)
Figure 9-2. Calibrated Accuracy and Slope Curves versus Temperature
Using the previous example temperature range of 0°C to 50°C, the worst-case temperature error is now reduced
to the worst-case slopes because the offset at 25°C (that is, the maximum and minimum temperature errors of
0.3°C and –0.5°C) is removed. Therefore, a user can expect the worst-case accuracy to improve to 0.175°C.
9.1.2.1 Power Supply-Level Contribution to Accuracy
The superior accuracy that can be achieved with the TMP112-Q1 device is complemented by the immunity-toDC variations from a 3.3-V supply voltage. This immunity is important because it spares the user from having
to use another LDO regulator to produce 3.3 V to achieve accuracy. Nevertheless, the noise quantization
that results from changing supply can add some slight change in temperature measurement accuracy. As an
example, if the user chooses to operate the device at 1.8 V, the worst-case expected change in accuracy can be
calculated with Equation 14:
é 0.25°C ù
Accuracy(PSR ) = ± (V+ - 3.3 V ) ´ ê
ú
ë V û
(14)
é 0.25°C ù
Accuracy(PSR )= ± (1.8 V - 3.3 V ) ´ ê
ú = ±0.375°C
ë V û
(15)
This example is a worst-case accuracy contribution as a result of variation in power supply that must be added to
the accuracy plus the slope maximum.
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9.2 Typical Application
The TMP112-Q1 device is used to measure the PCB temperature of the board location where the device is
mounted. The programmable address options allow up to four locations on the board to be monitored on a single
serial bus.
Supply Voltage
1.4 V to 3.6 V
Supply Bypass
Capacitor
0.01 µF
Pullup Resistors
5k
TMP112-Q1
Two-Wire
Host Controller
1
2
3
SCL
SDA
GND
V+
ALERT
6
5
4
ADD0
The SCL, SDA, and ALERT pins require pullup resistors.
Figure 9-3. Typical Connections
9.2.1 Design Requirements
The TMP112-Q1 device requires pullup resistors on the SCL, SDA, and ALERT pins. The recommended value
for the pullup resistors is 5-kΩ. In some applications the pullup resistor can be lower or higher than 5 kΩ
but must not exceed 3 mA of current on any of those pins. A 0.01-μF bypass capacitor on the supply is
recommended as shown in Figure 9-3. The SCL and SDA lines can be pulled up to a supply that is equal to or
higher than V+ through the pullup resistors. To configure one of four different addresses on the bus, connect the
ADD0 pin to either the GND, V+, SDA, or SCL pin.
9.2.2 Detailed Design Procedure
Place the TMP7112-Q1 device in close proximity to the heat source that must be monitored, with a proper layout
for good thermal coupling. This placement ensures that temperature changes are captured within the shortest
possible time interval. To maintain accuracy in applications that require air or surface temperature measurement,
care must be taken to isolate the package and leads from ambient air temperature. A thermally-conductive
adhesive is helpful in achieving accurate surface temperature measurement.
The TMP112-Q1 device is a very low-power device and generates very low noise on the supply bus. Applying an
RC filter to the V+ pin of the TMP112-Q1 device can further reduce any noise that the TMP112-Q1 device might
propagate to other components. R(F) in Figure 9-4 must be less than 5 kΩ and C(F) must be greater than 10 nF.
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Supply Voltage
R(F) ≤ 5 kΩ
Device
SCL
SDA
GND
V+
ALERT
C(F) ≥ 10 nF
ADD0
Figure 9-4. Noise Reduction Techniques
9.2.3 Application Curve
Temperature (qC)
Figure 9-5 shows the step response of the TMP112-Q1 device to a submersion in an oil bath of 100°C from room
temperature (27°C). The time-constant, or the time for the output to reach 63% of the input step, is 0.8 s. The
time-constant result depends on the printed circuit board (PCB) that the TMP112-Q1 device is mounted. For this
test, the TMP112-Q1 device was soldered to a two-layer PCB that measured 0.375 in × 0.437 in.
100
95
90
85
80
75
70
65
60
55
50
45
40
35
30
25
-1
1
3
5
7
9
11
Time (s)
13
15
17
19
Figure 9-5. Temperature Step Response
10 Power Supply Recommendations
The TMP112-Q1 device operates with power supply in the range of 1.4 to 3.6 V. The device is optimized
for operation at 3.3-V supply but can measure temperature accurately in the full supply range. Refer to the
Power Supply-Level Contribution to Accuracy section for more information about the power supply impact on the
accuracy of the device.
A power-supply bypass capacitor is required for proper operation. Place this capacitor as close as possible
to the supply and ground pins of the device. A typical value for this supply bypass capacitor is 0.01 μF.
Applications with noisy or high-impedance power supplies may require additional decoupling capacitors to reject
power-supply noise.
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11 Layout
11.1 Layout Guidelines
Place the power-supply bypass capacitor as close as possible to the supply and ground pins. The recommended
value of this bypass capacitor is 0.01 μF. Additional decoupling capacitance can be added to compensate for
noisy or high-impedance power supplies. Pull up the open-drain output pins (SDA , SCL and ALERT) through
5-kΩ pullup resistors.
11.2 Layout Example
Via to Power or Ground Plane
Via to Internal Layer
Pull-Up Resistors
SCL
SDA
GND
V+
ALERT
Supply Voltage
ADD0
Supply Bypass
Capacitor
Ground Plane for
Thermal Coupling
to Heat Source
Serial Bus Traces
Heat Source
Figure 11-1. Layout Example
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12 Device and Documentation Support
12.1 Documentation Support
12.1.1 Related Documentation
For related documentation see the following:
TMP112 Data Sheet, SBOS473
Or view the TMP112 product folder at http://www.ti.com/product/TMP112
12.2 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper
right corner, click on Alert me to register and receive a weekly digest of any product information that has
changed. For change details, review the revision history included in any revised document.
12.3 Community Resources
12.4 Trademarks
SMBus™ is a trademark of Intel, Inc.
All trademarks are the property of their respective owners.
13 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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PACKAGE OPTION ADDENDUM
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16-May-2022
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
Samples
(4/5)
(6)
TMP112AQDRLRQ1
ACTIVE
SOT-5X3
DRL
6
4000
RoHS & Green
NIPDAUAG
Level-2-260C-1 YEAR
-40 to 125
SLP
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of
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