Order
Now
Product
Folder
Technical
Documents
Support &
Community
Tools &
Software
TMUX1108
SCDS388A – NOVEMBER 2018 – REVISED NOVEMBER 2018
TMUX1108 5V / ±2.5V, Low-Leakage-Current, 8:1 Precision Multiplexer
1 Features
3 Description
•
•
•
•
•
•
•
•
•
•
•
The TMUX1108 is a precision complementary metaloxide semiconductor (CMOS) multiplexer (MUX). The
TMUX1108 offers a single channel, 8:1 configuration.
Wide operating supply of 1.08 V to 5.5 V allows for
use in a wide array of applications from medical
equipment to industrial systems. The device supports
bidirectional analog and digital signals on the source
(Sx) and drain (D) pins ranging from GND to VDD. All
logic inputs have 1.8 V logic compatible thresholds,
ensuring both TTL and CMOS logic compatibility
when operating in the valid supply voltage range.
Fail-Safe Logic circuitry allows voltages on the control
pins to be applied before the supply pin, protecting
the device from potential damage.
1
Wide Supply Range: ±2.5 V, 1.08 V to 5.5 V
Low Leakage Current: 3 pA
Low Charge Injection: 1 pC
Low On-Resistance: 2.5 Ω
-40°C to +125°C Operating Temperature
1.8 V Logic Compatible
Fail-Safe Logic
Rail to Rail Operation
Bidirectional Signal Path
Break-Before-Make Switching Action
ESD Protection HBM: 2000 V
The TMUX1108 is part of the precision switches and
multiplexers family of devices. These devices have
very low on and off leakage currents and low charge
injection, allowing them to be used in high precision
measurement applications. A low supply current of
8nA and small package options enable use in
portable applications.
2 Applications
•
•
•
•
•
•
•
•
•
•
•
Ultrasound Scanners
Patient Monitoring & Diagnostics
Optical Networking
Optical Test Equipment
Remote Radio Unit
ATE Test Equipment
Factory Automation and Industrial Process
Controls
Programmable Logic Controllers (PLC)
Analog Input Modules
Digital Multimeters
Battery Monitoring Systems
Device Information(1)
PART NUMBER
TMUX1108
5.00 mm × 4.40 mm
QFN (16)
2.60 mm x 1.80 mm
SPACER
SPACER
Block Diagram
TMUX1108
VREF
EN
REF
Bridge Sensor
+
S1
Op Amp
S2
-
S3
D
S4
S5
+
Op Amp
S6
Current Sensing
TSSOP (16)
VDD
VDD
-
Precision
ADC
S1
S2
S3
S4
S5
S6
S7
S8
D
S7
1-OF-8
DECODER
S8
Photo
LED Detector
Optical Sensor
Analog Inputs
GND
A0
BODY SIZE (NOM)
(1) For all available packages, see the package option addendum
at the end of the data sheet.
Application Example
Thermocouple
PACKAGE
A1
A2
1.8V Logic
Signals
A0
A1
A2
EN
TMUX1108
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
TMUX1108
SCDS388A – NOVEMBER 2018 – REVISED NOVEMBER 2018
www.ti.com
Table of Contents
1
2
3
4
5
6
7
Features ..................................................................
Applications ...........................................................
Description .............................................................
Revision History.....................................................
Device Comparison Table.....................................
Pin Configuration and Functions .........................
Specifications.........................................................
1
1
1
2
3
3
4
7.1
7.2
7.3
7.4
7.5
7.6
7.7
Absolute Maximum Ratings ...................................... 4
ESD Ratings.............................................................. 4
Recommended Operating Conditions....................... 4
Thermal Information .................................................. 4
Electrical Characteristics (VDD = 5 V ±10 %) ............ 5
Electrical Characteristics (VDD = 3.3 V ±10 %) ......... 7
Electrical Characteristics (VDD = 2.5 V ±10 %), (VSS =
–2.5 V ±10 %) ............................................................ 9
7.8 Electrical Characteristics (VDD = 1.8 V ±10 %) ....... 11
7.9 Electrical Characteristics (VDD = 1.2 V ±10 %) ....... 13
7.10 Typical Characteristics .......................................... 15
8
Detailed Description ............................................ 18
8.1 Overview ................................................................. 18
8.2 Functional Block Diagram ....................................... 23
8.3 Feature Description................................................. 23
8.4 Device Functional Modes........................................ 25
9
Application and Implementation ........................ 26
9.1
9.2
9.3
9.4
9.5
Application Information............................................
Typical Application .................................................
Design Requirements..............................................
Detailed Design Procedure .....................................
Application Curve ....................................................
26
26
26
27
27
10 Power Supply Recommendations ..................... 27
11 Layout................................................................... 28
11.1 Layout Guidelines ................................................. 28
11.2 Layout Example .................................................... 28
12 Device and Documentation Support ................. 29
12.1
12.2
12.3
12.4
12.5
12.6
12.7
Documentation Support ........................................
Related Links ........................................................
Receiving Notification of Documentation Updates
Community Resources..........................................
Trademarks ...........................................................
Electrostatic Discharge Caution ............................
Glossary ................................................................
29
29
29
29
29
29
29
13 Mechanical, Packaging, and Orderable
Information ........................................................... 29
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Original (November 2018) to Revision A
Page
•
Added footnotes to Absolute Maximum Ratings: table........................................................................................................... 4
•
Added RSV (QFN) thermal information to Thermal Information: table................................................................................... 4
•
Added footnote to clarify test conditions ................................................................................................................................ 7
•
Changed leakage current test conditions for dual supply ...................................................................................................... 9
2
Submit Documentation Feedback
Copyright © 2018, Texas Instruments Incorporated
Product Folder Links: TMUX1108
TMUX1108
www.ti.com
SCDS388A – NOVEMBER 2018 – REVISED NOVEMBER 2018
5 Device Comparison Table
PRODUCT
DESCRIPTION
TMUX1108
8:1, 1-Channel. single-ended multiplexer
6 Pin Configuration and Functions
TMUX1108: PW Package
16-Pin TSSOP
Top View
2
15
A2
VSS
3
14
GND
S1
4
13
VDD
S2
5
12
S5
S3
6
11
S4
7
D
8
VSS
1
A2
13
EN
A1
A1
14
16
A0
1
16
A0
15
EN
TMUX1108: RSV Package
16-Pin QFN
Top View
12
GND
S6
S2
3
10
S5
10
S7
S3
4
9
S6
9
S8
S7
S8
D
S4
Not to scale
8
VDD
7
11
6
2
5
S1
Not to scale
Pin Functions
PIN
NAME
TYPE (1)
DESCRIPTION
TSSOP
UQFN
A0
1
15
I
Address line 0
EN
2
16
I
Active high logic input. When this pin is low, all switches are turned off. When this pin is high,
the A[2:0] logic inputs determine which switch is turned on.
VSS
3
1
P
Negative power supply. This pin is the most negative power-supply potential. For reliable
operation, connect a decoupling capacitor ranging from 0.1 µF to 10 µF between VSS and GND.
VSS can be connected to ground for single supply applications.
S1
4
2
I/O
Source pin 1. Can be an input or output.
S2
5
3
I/O
Source pin 2. Can be an input or output.
S3
6
4
I/O
Source pin 3. Can be an input or output.
S4
7
5
I/O
Source pin 4. Can be an input or output.
D
8
6
I/O
Drain pin. Can be an input or output.
S8
9
7
I/O
Source pin 8. Can be an input or output.
S7
10
8
I/O
Source pin 7. Can be an input or output.
S6
11
9
I/O
Source pin 6. Can be an input or output.
S5
12
10
I/O
Source pin 5. Can be an input or output.
VDD
13
11
P
Positive power supply. This pin is the most positive power-supply potential. For reliable
operation, connect a decoupling capacitor ranging from 0.1 µF to 10 µF between VDD and GND.
GND
14
12
P
Ground (0 V) reference
A2
15
13
I
Address line 2
A1
16
14
I
Address line 1
(1)
I = input, O = output, I/O = input and output, P = power
Submit Documentation Feedback
Copyright © 2018, Texas Instruments Incorporated
Product Folder Links: TMUX1108
3
TMUX1108
SCDS388A – NOVEMBER 2018 – REVISED NOVEMBER 2018
www.ti.com
7 Specifications
7.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted) (1)
(2) (3)
VDD–VSS
VDD
Supply voltage
VSS
MIN
MAX
–0.5
6
UNIT
V
–0.5
6
V
V
–3.0
0.3
VSEL or VEN
Logic control input pin voltage (EN, A0, A1, A2)
–0.5
6
V
ISEL or IEN
Logic control input pin current (EN, A0, A1, A2)
–30
30
mA
VS or VD
Source or drain voltage (Sx, D)
–0.5
VDD+0.5
IS or ID (CONT)
Source or drain continuous current (Sx, D)
–30
30
mA
Tstg
Storage temperature
–65
150
°C
TJ
Junction temperature
150
°C
(1)
(2)
(3)
V
Stresses beyond those listed under Absolute Maximum Rating may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Condition. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
The algebraic convention, whereby the most negative value is a minimum and the most positive value is a maximum.
All voltages are with respect to ground, unless otherwise specified.
7.2 ESD Ratings
VALUE
V(ESD)
(1)
(2)
Electrostatic discharge
Human body model (HBM), per
ANSI/ESDA/JEDEC JS-001, all pins (1)
±2000
Charged device model (CDM), per JEDEC
specification JESD22-C101, all pins (2)
±750
UNIT
V
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
7.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MIN
NOM
MAX
UNIT
VDD
Positive power supply voltage (single)
1.08
5.5
V
VSS
Negative power supply voltage (dual)
-2.75
0
V
VDD - VSS
Supply rail voltage difference
1.08
5.5
V
VS or VD
Signal path input/output voltage (source or drain pin) (Sx, D)
VSS
VDD
V
VSEL or
VEN
Address or enable pin voltage
0
5.5
V
TA
Ambient temperature
–40
125
°C
7.4 Thermal Information
THERMAL METRIC (1)
DEVICE
DEVICE
PW (TSSOP)
RSV (QFN)
16 PINS
16 PINS
UNIT
RθJA
Junction-to-ambient thermal resistance
118.9
134.6
°C/W
RθJC(top)
Junction-to-case (top) thermal resistance
49.3
74.3
°C/W
RθJB
Junction-to-board thermal resistance
65.2
62.8
°C/W
ΨJT
Junction-to-top characterization parameter
7.6
4.3
°C/W
YJB
Junction-to-board characterization parameter
64.6
61.1
°C/W
RθJC(bot)
Junction-to-case (bottom) thermal resistance
N/A
N/A
°C/W
(1)
4
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
Submit Documentation Feedback
Copyright © 2018, Texas Instruments Incorporated
Product Folder Links: TMUX1108
TMUX1108
www.ti.com
SCDS388A – NOVEMBER 2018 – REVISED NOVEMBER 2018
7.5 Electrical Characteristics (VDD = 5 V ±10 %)
at TA = 25°C, VDD = 5 V (unless otherwise noted)
PARAMETER
TEST CONDITIONS
TA
MIN
TYP
MAX
UNIT
ANALOG SWITCH
25°C
RON
VS = 0 V to VDD
ISD = 10 mA
On-resistance
4
Ω
–40°C to +85°C
2.5
4.5
Ω
–40°C to +125°C
4.9
Ω
25°C
ΔRON
On-resistance matching between
channels
VS = 0 V to VDD
ISD = 10 mA
0.13
0.4
Ω
–40°C to +125°C
0.5
Ω
25°C
RON
VS = 0 V to VDD
ISD = 10 mA
On-resistance flatness
FLAT
IS(OFF)
ID(OFF)
ID(ON)
IS(ON)
ID(ON)
IS(ON)
Source off leakage current (1)
Drain off leakage current
(1)
Channel on leakage current
Channel on leakage current
Ω
–40°C to +85°C
0.85
Ω
–40°C to +85°C
1.6
Ω
–40°C to +125°C
1.6
Ω
0.08
nA
0.3
nA
0.9
nA
0.1
nA
–1
1
nA
–5.5
5.5
nA
0.025
nA
VDD = 5 V
Switch Off
VD = 4.5 V / 1.5 V
VS = 1.5 V / 4.5 V
25°C
VDD = 5 V
Switch Off
VD = 4.5 V / 1.5 V
VS = 1.5 V / 4.5 V
VDD = 5 V
Switch On
VD = VS = 2.5 V
25°C
VDD = 5 V
Switch On
VD = VS = 4.5 V / 1.5 V
25°C
–0.08
–40°C to +85°C
–0.3
–40°C to +125°C
–0.9
25°C
–0.1
–40°C to +85°C
–40°C to +125°C
–0.025
±0.005
±0.01
±0.003
–40°C to +85°C
–0.5
0.5
nA
–40°C to +125°C
–0.95
0.95
nA
0.1
nA
–0.75
0.75
nA
–40°C to +125°C
–4
4
nA
–40°C to +85°C
–0.1
±0.01
LOGIC INPUTS (EN, A0, A1, A2)
VIH
Input logic high
–40°C to +125°C
1.49
5.5
V
VIL
Input logic low
–40°C to +125°C
0
0.87
V
IIH
IIL
Input leakage current
25°C
IIH
IIL
Input leakage current
–40°C to +125°C
CIN
Logic input capacitance
25°C
CIN
Logic input capacitance
–40°C to +125°C
±0.005
µA
±0.05
1
µA
pF
2
pF
POWER SUPPLY
IDD
(1)
VDD supply current
Logic inputs = 0 V or 5.5 V
25°C
–40°C to +125°C
0.008
µA
1
µA
When VS is 4.5 V, VD is 1.5 V, and vice versa.
Submit Documentation Feedback
Copyright © 2018, Texas Instruments Incorporated
Product Folder Links: TMUX1108
5
TMUX1108
SCDS388A – NOVEMBER 2018 – REVISED NOVEMBER 2018
www.ti.com
Electrical Characteristics (VDD = 5 V ±10 %) (continued)
at TA = 25°C, VDD = 5 V (unless otherwise noted)
PARAMETER
TEST CONDITIONS
TA
MIN
TYP
MAX
UNIT
DYNAMIC CHARACTERISTICS
25°C
tTRAN
Transition time between channels
VS = 3 V
RL = 200 Ω, CL = 15 pF
14
–40°C to +85°C
–40°C to +125°C
25°C
tOPEN
Break before make time
(BBM)
VS = 3 V
RL = 200 Ω, CL = 15 pF
Enable turn-on time
VS = 3 V
RL = 200 Ω, CL = 15 pF
QC
OISO
XTALK
Charge Injection
Off Isolation
Crosstalk
19
ns
ns
–40°C to +85°C
1
ns
–40°C to +125°C
1
ns
12
ns
–40°C to +85°C
19
ns
–40°C to +125°C
20
ns
25°C
tOFF(EN) Enable turn-off time
ns
8
25°C
tON(EN)
ns
18
6
ns
VS = 3 V
RL = 200 Ω, CL = 15 pF
–40°C to +85°C
8
ns
–40°C to +125°C
9
ns
VS = 1 V
RS = 0 Ω, CL = 1 nF
25°C
–1
pC
RL = 50 Ω, CL = 5 pF
f = 1 MHz
25°C
–65
dB
RL = 50 Ω, CL = 5 pF
f = 10 MHz
25°C
–45
dB
RL = 50 Ω, CL = 5 pF
f = 1 MHz
25°C
–65
dB
RL = 50 Ω, CL = 5 pF
f = 10 MHz
25°C
–45
dB
BW
Bandwidth
RL = 50 Ω, CL = 5 pF
25°C
90
MHz
CSOFF
Source off capacitance
f = 1 MHz
25°C
7
pF
CDOFF
Drain off capacitance
f = 1 MHz
25°C
60
pF
CSON
CDON
On capacitance
f = 1 MHz
25°C
65
pF
6
Submit Documentation Feedback
Copyright © 2018, Texas Instruments Incorporated
Product Folder Links: TMUX1108
TMUX1108
www.ti.com
SCDS388A – NOVEMBER 2018 – REVISED NOVEMBER 2018
7.6 Electrical Characteristics (VDD = 3.3 V ±10 %)
at TA = 25°C, VDD = 3.3 V (unless otherwise noted)
PARAMETER
TEST CONDITIONS
TA
MIN
TYP
MAX
UNIT
4
ANALOG SWITCH
25°C
RON
VS = 0 V to VDD
ISD = 10 mA
On-resistance
8.75
Ω
–40°C to +85°C
9.5
Ω
–40°C to +125°C
9.75
Ω
25°C
ΔRON
On-resistance matching between
channels
VS = 0 V to VDD
ISD = 10 mA
0.13
0.4
Ω
–40°C to +125°C
0.5
Ω
25°C
RON
VS = 0 V to VDD
ISD = 10 mA
On-resistance flatness
FLAT
IS(OFF)
ID(OFF)
ID(ON)
IS(ON)
Source off leakage current (1)
Drain off leakage current
(1)
Channel on leakage current
Ω
–40°C to +85°C
–40°C to +85°C
–40°C to +125°C
VDD = 3.3 V
Switch Off
VD = 3 V / 1 V
VS = 1 V / 3 V
25°C
VDD = 3.3 V
Switch Off
VD = 3 V / 1 V
VS = 1 V / 3 V
VDD = 3.3 V
Switch On
VD = VS = 3 V / 1 V
–0.05
1.9
Ω
2
Ω
2.2
Ω
0.05
nA
0.1
nA
0.5
nA
0.1
nA
–0.5
0.5
nA
–1.5
1.5
nA
0.1
nA
–0.5
0.5
nA
–1.5
1.5
nA
–40°C to +85°C
–0.1
–40°C to +125°C
–0.5
25°C
–0.1
–40°C to +85°C
–40°C to +125°C
25°C
–0.1
–40°C to +85°C
–40°C to +125°C
±0.001
±0.005
±0.005
LOGIC INPUTS (EN, A0, A1, A2)
VIH
Input logic high
–40°C to +125°C
1.35
5.5
V
VIL
Input logic low
–40°C to +125°C
0
0.8
V
IIH
IIL
Input leakage current
25°C
IIH
IIL
Input leakage current
–40°C to +125°C
CIN
Logic input capacitance
25°C
CIN
Logic input capacitance
–40°C to +125°C
±0.005
µA
±0.05
1
µA
pF
2
pF
POWER SUPPLY
IDD
(1)
VDD supply current
Logic inputs = 0 V or 5.5 V
25°C
–40°C to +125°C
0.006
µA
1
µA
When VS is 3 V, VD is 1 V, and vice versa.
Submit Documentation Feedback
Copyright © 2018, Texas Instruments Incorporated
Product Folder Links: TMUX1108
7
TMUX1108
SCDS388A – NOVEMBER 2018 – REVISED NOVEMBER 2018
www.ti.com
Electrical Characteristics (VDD = 3.3 V ±10 %) (continued)
at TA = 25°C, VDD = 3.3 V (unless otherwise noted)
PARAMETER
TEST CONDITIONS
TA
MIN
TYP
MAX
UNIT
DYNAMIC CHARACTERISTICS
25°C
tTRAN
Transition time between channels
VS = 2 V
RL = 200 Ω, CL = 15 pF
15
–40°C to +85°C
–40°C to +125°C
25°C
tOPEN
Break before make time
(BBM)
VS = 2 V
RL = 200 Ω, CL = 15 pF
Enable turn-on time
VS = 2 V
RL = 200 Ω, CL = 15 pF
QC
OISO
XTALK
Charge Injection
Off Isolation
Crosstalk
23
ns
ns
–40°C to +85°C
1
ns
–40°C to +125°C
1
ns
14
ns
–40°C to +85°C
25
ns
–40°C to +125°C
25
ns
25°C
tOFF(EN) Enable turn-off time
ns
8
25°C
tON(EN)
ns
23
7
ns
VS = 2 V
RL = 200 Ω, CL = 15 pF
–40°C to +85°C
12
ns
–40°C to +125°C
12
ns
VS = 1 V
RS = 0 Ω, CL = 1 nF
25°C
–2
pC
RL = 50 Ω, CL = 5 pF
f = 1 MHz
25°C
–65
dB
RL = 50 Ω, CL = 5 pF
f = 10 MHz
25°C
–45
dB
RL = 50 Ω, CL = 5 pF
f = 1 MHz
25°C
–65
dB
RL = 50 Ω, CL = 5 pF
f = 10 MHz
25°C
–45
dB
BW
Bandwidth
RL = 50 Ω, CL = 5 pF
25°C
90
MHz
CSOFF
Source off capacitance
f = 1 MHz
25°C
7
pF
CDOFF
Drain off capacitance
f = 1 MHz
25°C
60
pF
CSON
CDON
On capacitance
f = 1 MHz
25°C
65
pF
8
Submit Documentation Feedback
Copyright © 2018, Texas Instruments Incorporated
Product Folder Links: TMUX1108
TMUX1108
www.ti.com
SCDS388A – NOVEMBER 2018 – REVISED NOVEMBER 2018
7.7 Electrical Characteristics (VDD = 2.5 V ±10 %), (VSS = –2.5 V ±10 %)
at TA = 25°C, VDD = +2.5 V, VSS = –2.5 V (unless otherwise noted)
PARAMETER
TEST CONDITIONS
TA
MIN
TYP
MAX
UNIT
ANALOG SWITCH
25°C
RON
VS = VSS to VDD
ISD = 10 mA
On-resistance
4
Ω
–40°C to +85°C
2.5
4.5
Ω
–40°C to +125°C
4.9
Ω
25°C
ΔRON
On-resistance matching between
channels
VS = VSS to VDD
ISD = 10 mA
0.13
0.4
Ω
–40°C to +125°C
0.5
Ω
25°C
RON
VS = VSS to VDD
ISD = 10 mA
On-resistance flatness
FLAT
IS(OFF)
ID(OFF)
ID(ON)
IS(ON)
Source off leakage current (1)
Drain off leakage current
(1)
Channel on leakage current
Ω
–40°C to +85°C
0.85
Ω
–40°C to +85°C
1.6
Ω
–40°C to +125°C
1.6
Ω
0.08
nA
0.3
nA
0.9
nA
0.1
nA
VDD = +2.5 V, VSS = –2.5 V
Switch Off
VD = +2 V / –1 V
VS = –1 V / +2 V
25°C
–0.08
VDD = +2.5 V, VSS = –2.5 V
Switch Off
VD = +2 V / –1 V
VS = –1 V / +2 V
–1
1
nA
–40°C to +125°C
–5.5
5.5
nA
VDD = +2.5 V, VSS = –2.5 V
Switch On
VD = VS = +2 V / –1 V
25°C
–0.1
0.1
nA
–40°C to +85°C
–0.3
–40°C to +125°C
–0.9
25°C
–0.1
–40°C to +85°C
–40°C to +85°C
±0.005
±0.01
±0.01
–0.75
0.75
nA
–40°C to +125°C
–4
4
nA
LOGIC INPUTS (EN, A0, A1, A2)
VIH
Input logic high
–40°C to +125°C
1.2
2.75
V
VIL
Input logic low
–40°C to +125°C
0
0.73
V
IIH
IIL
Input leakage current
25°C
IIH
IIL
Input leakage current
–40°C to +125°C
CIN
Logic input capacitance
25°C
CIN
Logic input capacitance
–40°C to +125°C
±0.005
µA
±0.05
1
µA
pF
2
pF
POWER SUPPLY
IDD
ISS
(1)
VDD supply current
VSS supply current
Logic inputs = 0 V or 2.75 V
Logic inputs = 0 V or 2.75 V
25°C
0.008
–40°C to +125°C
25°C
–40°C to +125°C
µA
1
0.008
µA
µA
1
µA
When VS is positive, VD is negative, and vice versa.
Submit Documentation Feedback
Copyright © 2018, Texas Instruments Incorporated
Product Folder Links: TMUX1108
9
TMUX1108
SCDS388A – NOVEMBER 2018 – REVISED NOVEMBER 2018
www.ti.com
Electrical Characteristics (VDD = 2.5 V ±10 %), (VSS = –2.5 V ±10 %) (continued)
at TA = 25°C, VDD = +2.5 V, VSS = –2.5 V (unless otherwise noted)
PARAMETER
TEST CONDITIONS
TA
MIN
TYP
MAX
UNIT
DYNAMIC CHARACTERISTICS
25°C
tTRAN
Transition time between channels
VS = 1.5 V
RL = 200 Ω, CL = 15 pF
14
–40°C to +85°C
–40°C to +125°C
25°C
tOPEN
Break before make time
(BBM)
VS = 1.5 V
RL = 200 Ω, CL = 15 pF
Enable turn-on time
VS = 1.5 V
RL = 200 Ω, CL = 15 pF
QC
OISO
XTALK
Charge Injection
Off Isolation
Crosstalk
21
ns
ns
–40°C to +85°C
1
ns
–40°C to +125°C
1
ns
13
ns
–40°C to +85°C
21
ns
–40°C to +125°C
21
ns
25°C
tOFF(EN) Enable turn-off time
ns
8
25°C
tON(EN)
ns
21
8
ns
VS = 1.5 V
RL = 200 Ω, CL = 15 pF
–40°C to +85°C
11
ns
–40°C to +125°C
12
ns
VS = –1 V
RS = 0 Ω, CL = 1 nF
25°C
–2.5
pC
RL = 50 Ω, CL = 5 pF
f = 1 MHz
25°C
–65
dB
RL = 50 Ω, CL = 5 pF
f = 10 MHz
25°C
–45
dB
RL = 50 Ω, CL = 5 pF
f = 1 MHz
25°C
–65
dB
RL = 50 Ω, CL = 5 pF
f = 10 MHz
25°C
–45
dB
BW
Bandwidth
RL = 50 Ω, CL = 5 pF
25°C
85
MHz
CSOFF
Source off capacitance
f = 1 MHz
25°C
7
pF
CDOFF
Drain off capacitance
f = 1 MHz
25°C
60
pF
CSON
CDON
On capacitance
f = 1 MHz
25°C
65
pF
10
Submit Documentation Feedback
Copyright © 2018, Texas Instruments Incorporated
Product Folder Links: TMUX1108
TMUX1108
www.ti.com
SCDS388A – NOVEMBER 2018 – REVISED NOVEMBER 2018
7.8 Electrical Characteristics (VDD = 1.8 V ±10 %)
at TA = 25°C, VDD = 1.8 V (unless otherwise noted)
PARAMETER
TEST CONDITIONS
TA
MIN
TYP
MAX
UNIT
ANALOG SWITCH
25°C
RON
VS = 0 V to VDD
ISD = 10 mA
On-resistance
40
80
Ω
–40°C to +125°C
80
Ω
25°C
ΔRON
IS(OFF)
ID(OFF)
ID(ON)
IS(ON)
On-resistance matching between
channels
Source off leakage current (1)
Drain off leakage current
(1)
Channel on leakage current
VS = 0 V to VDD
ISD = 10 mA
Ω
–40°C to +85°C
0.3
Ω
–40°C to +85°C
1.5
Ω
–40°C to +125°C
1.5
Ω
0.05
nA
0.1
nA
0.5
nA
0.1
nA
0.3
nA
1.5
nA
0.1
nA
VDD = 1.98 V
Switch Off
VD = 1.62 V / 1 V
VS = 1 V / 1.62 V
25°C
VDD = 1.98 V
Switch Off
VD = 1.62 V / 1 V
VS = 1 V / 1.62 V
VDD = 1.98 V
Switch On
VD = VS = 1.62 V / 1 V
–0.05
–40°C to +85°C
–0.1
–40°C to +125°C
–0.5
25°C
–0.1
–40°C to +85°C
–0.3
–40°C to +125°C
–1.5
25°C
–0.1
–40°C to +85°C
±0.003
±0.005
±0.003
–0.5
0.5
nA
–40°C to +125°C
–2
2
nA
LOGIC INPUTS (EN, A0, A1, A2)
VIH
Input logic high
–40°C to +125°C
1.07
5.5
V
VIL
Input logic low
–40°C to +125°C
0
0.68
V
IIH
IIL
Input leakage current
25°C
IIH
IIL
Input leakage current
–40°C to +125°C
CIN
Logic input capacitance
25°C
CIN
Logic input capacitance
–40°C to +125°C
±0.005
µA
±0.05
1
µA
pF
2
pF
POWER SUPPLY
IDD
(1)
VDD supply current
Logic inputs = 0 V or 5.5 V
25°C
–40°C to +125°C
0.001
µA
0.85
µA
When VS is 1.62 V, VD is 1 V, and vice versa.
Submit Documentation Feedback
Copyright © 2018, Texas Instruments Incorporated
Product Folder Links: TMUX1108
11
TMUX1108
SCDS388A – NOVEMBER 2018 – REVISED NOVEMBER 2018
www.ti.com
Electrical Characteristics (VDD = 1.8 V ±10 %) (continued)
at TA = 25°C, VDD = 1.8 V (unless otherwise noted)
PARAMETER
TEST CONDITIONS
TA
MIN
TYP
MAX
UNIT
DYNAMIC CHARACTERISTICS
25°C
tTRAN
Transition time between channels
VS = 1 V
RL = 200 Ω, CL = 15 pF
28
–40°C to +85°C
–40°C to +125°C
25°C
tOPEN
Break before make time
(BBM)
VS = 1 V
RL = 200 Ω, CL = 15 pF
Enable turn-on time
VS = 1 V
RL = 200 Ω, CL = 15 pF
QC
OISO
XTALK
Charge Injection
Off Isolation
Crosstalk
48
ns
ns
–40°C to +85°C
1
ns
–40°C to +125°C
1
ns
28
ns
–40°C to +85°C
48
ns
–40°C to +125°C
48
ns
25°C
tOFF(EN) Enable turn-off time
ns
16
25°C
tON(EN)
ns
48
16
ns
VS = 1 V
RL = 200 Ω, CL = 15 pF
–40°C to +85°C
27
ns
–40°C to +125°C
27
ns
VS = 1 V
RS = 0 Ω, CL = 1 nF
25°C
–0.5
pC
RL = 50 Ω, CL = 5 pF
f = 1 MHz
25°C
–65
dB
RL = 50 Ω, CL = 5 pF
f = 10 MHz
25°C
–45
dB
RL = 50 Ω, CL = 5 pF
f = 1 MHz
25°C
–65
dB
RL = 50 Ω, CL = 5 pF
f = 10 MHz
25°C
–45
dB
BW
Bandwidth
RL = 50 Ω, CL = 5 pF
25°C
80
MHz
CSOFF
Source off capacitance
f = 1 MHz
25°C
7
pF
CDOFF
Drain off capacitance
f = 1 MHz
25°C
65
pF
CSON
CDON
On capacitance
f = 1 MHz
25°C
70
pF
12
Submit Documentation Feedback
Copyright © 2018, Texas Instruments Incorporated
Product Folder Links: TMUX1108
TMUX1108
www.ti.com
SCDS388A – NOVEMBER 2018 – REVISED NOVEMBER 2018
7.9 Electrical Characteristics (VDD = 1.2 V ±10 %)
PARAMETER
TEST CONDITIONS
TA
MIN
TYP
MAX
UNIT
ANALOG SWITCH
25°C
RON
VS = 0 V to VDD
ISD = 10 mA
On-resistance
70
–40°C to +85°C
–40°C to +125°C
25°C
ΔRON
IS(OFF)
ID(OFF)
ID(ON)
IS(ON)
On-resistance matching between
channels
VS = 0 V to VDD
ISD = 10 mA
25°C
Source off leakage current (1)
VDD = 1.32 V
Switch Off
VD = 1 V / 0.8 V
VS = 0.8 V / 1 V
Drain off leakage current
(1)
Channel on leakage current
Ω
105
Ω
105
Ω
0.15
–40°C to +85°C
Ω
1.5
–40°C to +125°C
–0.05
±0.003
Ω
1.5
Ω
0.05
nA
–40°C to +85°C
–0.1
0.1
nA
–40°C to +125°C
–0.5
0.5
nA
VDD = 1.32 V
Switch Off
VD = 1 V / 0.8 V
VS = 0.8 V / 1 V
25°C
–0.1
0.1
nA
–40°C to +85°C
–0.3
0.3
nA
–40°C to +125°C
–1.5
1.5
nA
VDD = 1.32 V
Switch On
VD = VS = 1 V / 0.8 V
25°C
–0.1
0.1
nA
–40°C to +85°C
–0.3
0.3
nA
–40°C to +125°C
–1.5
1.5
nA
±0.003
±0.003
LOGIC INPUTS (EN, A0, A1, A2)
VIH
Input logic high
–40°C to +125°C
0.96
5.5
V
VIL
Input logic low
–40°C to +125°C
0
0.36
V
IIH
IIL
Input leakage current
25°C
IIH
IIL
Input leakage current
–40°C to +125°C
CIN
Logic input capacitance
25°C
CIN
Logic input capacitance
–40°C to +125°C
±0.005
µA
±0.05
1
µA
pF
2
pF
POWER SUPPLY
IDD
(1)
VDD supply current
Logic inputs = 0 V or 5.5 V
25°C
–40°C to +125°C
0.001
µA
0.7
µA
When VS is 1 V, VD is 0.8 V, and vice versa.
Submit Documentation Feedback
Copyright © 2018, Texas Instruments Incorporated
Product Folder Links: TMUX1108
13
TMUX1108
SCDS388A – NOVEMBER 2018 – REVISED NOVEMBER 2018
www.ti.com
Electrical Characteristics (VDD = 1.2 V ±10 %) (continued)
PARAMETER
TEST CONDITIONS
TA
MIN
TYP
MAX
UNIT
DYNAMIC CHARACTERISTICS
25°C
tTRAN
Transition time between channels
VS = 1 V
RL = 200 Ω, CL = 15 pF
60
–40°C to +85°C
210
ns
–40°C to +125°C
210
ns
25°C
tOPEN
Break before make time
(BBM)
VS = 1 V
RL = 200 Ω, CL = 15 pF
28
–40°C to +85°C
1
–40°C to +125°C
1
25°C
tON(EN)
Enable turn-on time
VS = 1 V
RL = 200 Ω, CL = 15 pF
ns
ns
ns
ns
60
–40°C to +85°C
–40°C to +125°C
25°C
ns
190
ns
190
ns
45
ns
tOFF(EN) Enable turn-off time
VS = 1 V
RL = 200 Ω, CL = 15 pF
–40°C to +85°C
150
ns
–40°C to +125°C
150
ns
QC
VS = 1 V
RS = 0 Ω, CL = 1 nF
25°C
–0.5
pC
RL = 50 Ω, CL = 5 pF
f = 1 MHz
25°C
–65
dB
RL = 50 Ω, CL = 5 pF
f = 10 MHz
25°C
–45
dB
RL = 50 Ω, CL = 5 pF
f = 1 MHz
25°C
–65
dB
RL = 50 Ω, CL = 5 pF
f = 10 MHz
25°C
–45
dB
OISO
XTALK
Charge Injection
Off Isolation
Crosstalk
BW
Bandwidth
RL = 50 Ω, CL = 5 pF
25°C
80
MHz
CSOFF
Source off capacitance
f = 1 MHz
25°C
7
pF
CDOFF
Drain off capacitance
f = 1 MHz
25°C
65
pF
CSON
CDON
On capacitance
f = 1 MHz
25°C
70
pF
14
Submit Documentation Feedback
Copyright © 2018, Texas Instruments Incorporated
Product Folder Links: TMUX1108
TMUX1108
www.ti.com
SCDS388A – NOVEMBER 2018 – REVISED NOVEMBER 2018
7.10 Typical Characteristics
at TA = 25°C, VDD = 5 V (unless otherwise noted)
6
6
VDD = 3V
5.5
5
5
4.5
On Resistance (:)
On Resistance (:)
VDD = 3.3V
4
VDD = 4.5V
3
VDD = 5.5V
2
TA = 85qC
TA = 125qC
TA = -40qC
TA = 25qC
4
3.5
3
2.5
2
1.5
1
1
0.5
0
0
0
1
2
3
4
Source or Drain Voltage (V)
5
0
5.5
1
2
3
Source or Drain Voltage (V)
D001
TA = 25°C
Figure 1. On-Resistance vs Source or Drain Voltage
D002
Figure 2. On-Resistance vs Temperature
8
7
5
VDD = 2.25V
VSS = -2.25V
4
3
2
0
-3
TA = 125qC
5
4
3
2
VDD = 2.75V
VSS = -2.75V
1
TA = 85qC
6
On Resistance (:)
On Resistance (:)
5
VDD= 5 V
6
TA = -40qC
1
TA = 25qC
0
-2
-1
0
1
Source or Drain Voltage (V)
2
3
0
0.5
D003
1
1.5
2
2.5
Source or Drain Voltage (V)
TA = 25°C
80
75
70
65
60
55
50
45
40
35
30
25
20
15
10
5
0
3
3.5
D004
VDD= 3.3 V
Figure 3. On-Resistance vs Source or Drain Voltage
Figure 4. On-Resistance vs Temperature
40
VDD = 1.08V
30
20
VDD = 1.32V
On-Leakage (pA)
On Resistance (:)
4
VDD = 1.62V
VDD = 1.32V
10
VDD = 1.98V
VDD = 3.63V
0
-10
-20
VDD = 1.98V
-30
-40
0
0.2
0.4
0.6 0.8
1
1.2 1.4
Source or Drain Voltage (V)
1.6
1.8
2
0
0.5
D005
TA = 25°C
1
1.5
2
2.5
3
Source or Drain Voltage (V)
3.5
4
D006
TA = 25°C
Figure 5. On-Resistance vs Source or Drain Voltage
Figure 6. On-Leakage vs Source or Drain Voltage
Submit Documentation Feedback
Copyright © 2018, Texas Instruments Incorporated
Product Folder Links: TMUX1108
15
TMUX1108
SCDS388A – NOVEMBER 2018 – REVISED NOVEMBER 2018
www.ti.com
Typical Characteristics (continued)
400
2
300
1.5
On-Leakage (pA)
VDD = 5V
VSS = 0V
Leakage Current (nA)
VDD = 2.5V
VSS = -2.5V
200
100
0
-100
-200
1
IS(OFF)
0.5
0
-0.5
ID(OFF)
-1
ID(ON)
-1.5
-300
-400
-3
-2
-1
0
1
2
3
Source or Drain Voltage (V)
4
-2
-40
5
-20
0
20
40
60
Temperature (qC)
D007
TA = 25°C
80
100
120
D008
VDD= 3.3 V
Figure 7. On-Leakage vs Source or Drain Voltage
Figure 8. Leakage Current vs Temperature
1
3.5
VDD = 5V
2.5
1.5
Supply Current (PA)
Leakage Current (nA)
0.8
IS(OFF)
0.5
-0.5
ID(OFF)
-1.5
ID(ON)
VDD = 3.3V
0.6
0.4
VDD = 1.8V
0.2
-2.5
VDD = 1.2V
-3.5
-40
-20
0
20
40
60
Temperature (qC)
80
100
0
-40
120
-20
0
20
40
60
Temperature (qC)
D009
VDD= 5 V
100
120
D010
VSEL= 5.5 V
Figure 9. Leakage Current vs Temperature
Figure 10. Supply Current vs Temperature
1400
20
1200
15
Charge Injection (pC)
Supply Current (PA)
80
1000
800
600
VDD = 5V
400
200
VDD = 5V
VSS = 0V
VDD = 3.3V
VSS = 0V
10
5
0
-5
VDD = 2.5V
VSS = -2.5V
-10
-15
VDD = 3.3V
0
0
0.5
1
1.5
2
2.5
3
3.5
Logic Voltage (V)
4
4.5
5
-20
-3
D011
TA = 25°C
-1
0
1
2
3
Source or Drain Voltage (V)
4
5
D012
TA = 25°C
Figure 11. Supply Current vs Logic Voltage
16
-2
Figure 12. Charge Injection vs Source or Drain Voltage
Submit Documentation Feedback
Copyright © 2018, Texas Instruments Incorporated
Product Folder Links: TMUX1108
TMUX1108
www.ti.com
SCDS388A – NOVEMBER 2018 – REVISED NOVEMBER 2018
Typical Characteristics (continued)
30
5
27
24
VDD = 1.2V
21
1
Time (ns)
Charge Injection (pC)
3
-1
18
TON
15
12
VDD = 1.8V
9
-3
TOFF
6
3
1.5
-5
0
0.5
1
1.5
Source or Drain Voltage (V)
2
2
2.5
D013
3
3.5
4
4.5
VDD - Supply Voltage (V)
5
5.5
D014
TA = 25°C
TA = 25°C
Figure 14. TON (EN) and TOFF (EN) vs Supply Voltage
Figure 13. Charge Injection vs Source or Drain Voltage
30
20
25
16
TON
Time (ns)
Time (ns)
20
12
TOFF
8
TTRANSITION_FALLING
15
10
TTRANSITION_RISING
4
0
-60
5
-30
0
30
60
90
TA - Temperature (qC)
120
0
0.5
150
1.5
D015
2.5
3.5
VDD - Supply Voltage (V)
4.5
5.5
D016
TA = 25°C
VDD= 5 V
Figure 16. TTRANSITION vs Supply Voltage
Figure 15. TON (EN) and TOFF (EN) vs Temperature
0
-10
Bandwidth
-20
Gain (dB)
-30
Off-Isolation
-40
-50
-60
-70
-80
-90
100k
1M
10M
Frequency (Hz)
100M
D006
TA = 25°C
Figure 17. Frequency Response
Submit Documentation Feedback
Copyright © 2018, Texas Instruments Incorporated
Product Folder Links: TMUX1108
17
TMUX1108
SCDS388A – NOVEMBER 2018 – REVISED NOVEMBER 2018
www.ti.com
8 Detailed Description
8.1 Overview
8.1.1 On-Resistance
The on-resistance of a device is the ohmic resistance between the source (Sx) and drain (D) pins of the device.
The on-resistance varies with input voltage and supply voltage. The symbol RON is used to denote on-resistance.
The measurement setup used to measure RON is shown in Figure 18. Voltage (V) and current (ISD) are measured
using this setup, and RON is computed with RON = V / ISD:
V
ISD
Sx
D
VS
Figure 18. On-Resistance Measurement Setup
8.1.2 Off-Leakage Current
There are two types of leakage currents associated with a switch during the off state:
1. Source off-leakage current
2. Drain off-leakage current
Source leakage current is defined as the leakage current flowing into or out of the source pin when the switch is
off. This current is denoted by the symbol IS(OFF).
Drain leakage current is defined as the leakage current flowing into or out of the drain pin when the switch is off.
This current is denoted by the symbol ID(OFF).
The setup used to measure both off-leakage currents is shown in Figure 19.
Is (OFF)
VDD
VSS
VDD
VSS
VDD
VSS
VDD
VSS
S1
S1
A
ID (OFF)
S2
S2
D
D
A
VS
S8
S8
VS
VD
VD
GND
GND
Figure 19. Off-Leakage Measurement Setup
18
Submit Documentation Feedback
Copyright © 2018, Texas Instruments Incorporated
Product Folder Links: TMUX1108
TMUX1108
www.ti.com
SCDS388A – NOVEMBER 2018 – REVISED NOVEMBER 2018
Overview (continued)
8.1.3 On-Leakage Current
Source on-leakage current is defined as the leakage current flowing into or out of the source pin when the switch
is on. This current is denoted by the symbol IS(ON).
Drain on-leakage current is defined as the leakage current flowing into or out of the drain pin when the switch is
on. This current is denoted by the symbol ID(ON).
Either the source pin or drain pin is left floating during the measurement. Figure 20 shows the circuit used for
measuring the on-leakage current, denoted by IS(ON) or ID(ON).
VDD
VSS
VDD
VSS
IS (ON)
S1
N.C.
VSS
VDD
VSS
S1
A
ID (ON)
S2
VDD
S2
D
D
A
N.C.
S8
S8
Vs
VS
VS
VD
GND
GND
Figure 20. On-Leakage Measurement Setup
8.1.4 Transition Time
Transition time is defined as the time taken by the output of the device to rise or fall 10% after the address signal
has risen or fallen past the logic threshold. The 10% transition measurement is utilized to provide the timing of
the device, system level timing can then account for the time constant added from the load resistance and load
capacitance. Figure 21 shows the setup used to measure transition time, denoted by the symbol tTRANSITION.
VDD
VSS
0.1…F
0.1…F
VDD
VSS
VDD
ADDRE SS
DRIVE
(VSEL)
tf < 5ns
tr < 5ns
VIH
VS
VIL
S1
OUTPUT
D
0V
S2
S8
RL
CL
tTRAN SITION
tTRAN SITION
A0
90%
A1
OUTPUT
VSEL
A2
10%
GND
0V
Figure 21. Transition-Time Measurement Setup
Submit Documentation Feedback
Copyright © 2018, Texas Instruments Incorporated
Product Folder Links: TMUX1108
19
TMUX1108
SCDS388A – NOVEMBER 2018 – REVISED NOVEMBER 2018
www.ti.com
Overview (continued)
8.1.5 Break-Before-Make Delay
Break-before-make delay is a safety feature that prevents two inputs from connecting when the device is
switching. The output first breaks from the on-state switch before making the connection with the next on-state
switch. The time delay between the break and the make is known as break-before-make delay. Figure 22 shows
the setup used to measure break-before-make delay, denoted by the symbol tOPEN(BBM).
VDD
VSS
0.1…F
0.1…F
VSS
VDD
VDD
S1
VS
ADDRE SS
DRIVE
(VSEL)
tr < 5ns
OUTPUT
D
tf < 5ns
S2-S7
0V
RL
CL
S8
90%
Output
tBBM 1
A0
tBBM 2
0V
A1
VSEL
tOPEN (BBM) = min ( tBBM 1, tBBM 2)
A2
GND
Figure 22. Break-Before-Make Delay Measurement Setup
8.1.6 Turn-On and Turn-Off Time
Turn-on time is defined as the time taken by the output of the device to rise to 10% after the enable has risen
past the logic threshold. The 10% measurement is utilized to provide the timing of the device, system level timing
can then account for the time constant added from the load resistance and load capacitance. Figure 23 shows
the setup used to measure turn-on time, denoted by the symbol tON(EN).
Turn-off time is defined as the time taken by the output of the device to fall to 90% after the enable has fallen
past the logic threshold. The 90% measurement is utilized to provide the timing of the device, system level timing
can then account for the time constant added from the load resistance and load capacitance. Figure 23 shows
the setup used to measure turn-off time, denoted by the symbol tOFF(EN).
VDD
VSS
0.1…F
0.1…F
VDD
VSS
VDD
ENABL E
DRIVE
(VEN)
tf < 5ns
tr < 5ns
VS
VIH
S1
OUTPUT
D
VIL
S2
0V
RL
S8
tOFF
tON (EN)
CL
(EN)
A0
EN
90%
A1
OUTPUT
VEN
10%
A2
GND
0V
Figure 23. Turn-On and Turn-Off Time Measurement Setup
20
Submit Documentation Feedback
Copyright © 2018, Texas Instruments Incorporated
Product Folder Links: TMUX1108
TMUX1108
www.ti.com
SCDS388A – NOVEMBER 2018 – REVISED NOVEMBER 2018
Overview (continued)
8.1.7 Charge Injection
The TMUX1108 has a transmission-gate topology. Any mismatch in capacitance between the NMOS and PMOS
transistors results in a charge injected into the drain or source during the falling or rising edge of the gate signal.
The amount of charge injected into the source or drain of the device is known as charge injection, and is denoted
by the symbol QC. Figure 24 shows the setup used to measure charge injection from source (Sx) to drain (D).
VDD
VSS
0.1…F
0.1…F
VSS
VDD
VDD
S1
VS
OUTPUT
D
0V
VOUT
S2
CL
S8
Output
VOUT
VS
QC = CL ×
VOUT
A0
EN
A1
VEN
A2
GND
Figure 24. Charge-Injection Measurement Setup
8.1.8 Off Isolation
Off isolation is defined as the ratio of the signal at the drain pin (D) of the device when a signal is applied to the
source pin (Sx) of an off-channel. Figure 25 shows the setup used to measure off isolation. Use the off isolation
equation to compute off isolation.
VDD
VSS
0.1µF
0.1µF
NETWORK
VSS
VDD
ANALYZER
VS
50Q
S
VSIG
D
VOUT
RL
50Q
SX/DX
GND
RL
50Q
Figure 25. Off Isolation Measurement Setup
Off Isolation
§V
·
20 ˜ Log ¨ OUT ¸
© VS ¹
(1)
Submit Documentation Feedback
Copyright © 2018, Texas Instruments Incorporated
Product Folder Links: TMUX1108
21
TMUX1108
SCDS388A – NOVEMBER 2018 – REVISED NOVEMBER 2018
www.ti.com
Overview (continued)
8.1.9 Crosstalk
Crosstalk is defined as the ratio of the signal at the drain pin (D) of a different channel, when a signal is applied
at the source pin (Sx) of an on-channel. Figure 26 shows the setup used to measure, and the equation used to
compute crosstalk.
VDD
VSS
0.1µF
0.1µF
NETWORK
VSS
VDD
ANALYZER
S1
VOUT
RL
D
50Q
VS
RL
S2
50Q
50Q
VSIG
SX
RL
GND
50Q
Figure 26. Crosstalk Measurement Setup
Channel-to-Channel Crosstalk
§V
·
20 ˜ Log ¨ OUT ¸
© VS ¹
(2)
8.1.10 Bandwidth
Bandwidth is defined as the range of frequencies that are attenuated by less than 3 dB when the input is applied
to the source pin (Sx) of an on-channel, and the output is measured at the drain pin (D) of the device. Figure 27
shows the setup used to measure bandwidth.
VSS
VDD
0.1µF
0.1µF
NETWORK
VSS
VDD
VS
ANALYZER
50Q
S
VSIG
D
VOUT
RL
50Q
GND
Figure 27. Bandwidth Measurement Setup
22
Submit Documentation Feedback
Copyright © 2018, Texas Instruments Incorporated
Product Folder Links: TMUX1108
TMUX1108
www.ti.com
SCDS388A – NOVEMBER 2018 – REVISED NOVEMBER 2018
8.2 Functional Block Diagram
The TMUX1108 is an 8:1, single-ended (1-ch.), analog mux. Each channel is turned on or turned off based on
the state of the address lines and enable pin.
TMUX1108
S1
S2
S3
S4
S5
S6
S7
S8
D
1-OF-8
DECODER
A0
A1
A2
EN
Figure 28. TMUX1108 Functional Block Diagram
8.3 Feature Description
8.3.1 Bidirectional Operation
The TMUX1108 conducts equally well from source (Sx) to drain (D) or from drain (D) to source (Sx). Each
channel has very similar characteristics in both directions and supports both analog and digital signals.
8.3.2 Rail to Rail Operation
The valid signal path input/output voltage for TMUX1108 ranges from VSS to VDD.
8.3.3 1.8 V Logic Compatible Inputs
The TMUX1108 has 1.8-V logic compatible control for all logic control inputs. The logic input thresholds scale
with supply but still provide 1.8-V logic control when operating at 5.5 V supply voltage. 1.8-V logic level inputs
allows the TMUX1108 to interface with processors that have lower logic I/O rails and eliminates the need for an
external translator, which saves both space and BOM cost. For more information on 1.8 V logic implementations
refer to Simplifying Design with 1.8 V logic Muxes and Switches
8.3.4 Fail-Safe Logic
The TMUX1108 support Fail-Safe Logic on the control input pins (EN, A0, A1, A2) allowing for operation up to
5.5 V above VSS, regardless of the state of the supply pin. This feature allows voltages on the control pins to be
applied before the supply pin, protecting the device from potential damage. Fail-Safe Logic minimizes system
complexity by removing the need for power supply sequencing on the logic control pins. For example, the FailSafe Logic feature allows the select pins of the TMUX1108 to be ramped to 5.5 V while VDD = 0 V. Additionally,
the feature enables operation of the TMUX1108 with VDD = 1.2 V while allowing the select pins to interface with a
logic level of another device up to 5.5 V.
Submit Documentation Feedback
Copyright © 2018, Texas Instruments Incorporated
Product Folder Links: TMUX1108
23
TMUX1108
SCDS388A – NOVEMBER 2018 – REVISED NOVEMBER 2018
www.ti.com
Feature Description (continued)
8.3.5 Ultra-low Leakage Current
The TMUX1108 provides extremely low on-leakage and off-leakage currents. The TMUX1108 is capable of
switching signals from high source-impedance inputs into a high input-impedance op amp with minimal offset
error because of the ultralow leakage currents. Figure 29 shows typical leakage currents of the TMUX1108
versus temperature.
3.5
Leakage Current (nA)
2.5
1.5
IS(OFF)
0.5
-0.5
ID(OFF)
-1.5
ID(ON)
-2.5
-3.5
-40
-20
0
20
40
60
Temperature (qC)
80
100
120
D009
Figure 29. Leakage Current vs Temperature
8.3.6 Ultra-low Charge Injection
The TMUX1108 has a transmission gate topology, as shown in Figure 30. Any mismatch in the stray capacitance
associated with the NMOS and PMOS causes an output level change whenever the switch is opened or closed.
OFF ON
CGSN
CGDN
S
D
CGSP
CGDP
OFF ON
Figure 30. Transmission Gate Topology
The TMUX1108 has special charge-injection cancellation circuitry that reduces the source-to-drain charge
injection to as low as 1 pC at VS = 1 V as shown in Figure 31.
24
Submit Documentation Feedback
Copyright © 2018, Texas Instruments Incorporated
Product Folder Links: TMUX1108
TMUX1108
www.ti.com
SCDS388A – NOVEMBER 2018 – REVISED NOVEMBER 2018
Feature Description (continued)
20
Charge Injection (pC)
15
VDD = 3.3V
VSS = 0V
10
VDD = 5V
VSS = 0V
5
0
-5
VDD = 2.5V
VSS = -2.5V
-10
-15
-20
-3
-2
-1
0
1
2
3
Source or Drain Voltage (V)
4
5
D012
Figure 31. Charge Injection vs Source or Drain Voltage
8.4 Device Functional Modes
When the EN pin of the TMUX1108 is pulled high, one of the switches is closed based on the state of the
address lines. When the EN pin is pulled low, all the switches are in an open state regardless of the state of the
address lines.
8.4.1 Truth Tables
Table 1 shows the truth table for the TMUX1108.
Table 1. TMUX1108 Truth Table
EN
0
A2
A1
A0
Selected Channel Connected To Drain (D) Pin
X (1) X (1) X (1)
All channels are off
1
0
0
0
S1
1
0
0
1
S2
1
0
1
0
S3
1
0
1
1
S4
1
1
0
0
S5
1
1
0
1
S6
1
1
1
0
S7
1
1
1
1
S8
(1)
X denotes don't care.
Submit Documentation Feedback
Copyright © 2018, Texas Instruments Incorporated
Product Folder Links: TMUX1108
25
TMUX1108
SCDS388A – NOVEMBER 2018 – REVISED NOVEMBER 2018
www.ti.com
9 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
9.1 Application Information
The TMUX11xx family offers ulta-low input/output leakage currents and low charge injection. These devices
operate up to 5.5 V, and offer true rail-to-rail input and output. The TMUX1108 has a low on-capacitance which
allows faster settling time when multiplexing inputs in the time domain. These features make the TMUX11xx a
family of precision, robust, high-performance analog multiplexer for low-voltage applications.
9.2 Typical Application
Figure 32 shows a 16-bit, 8 input, multiplexed, data-acquisition system. This example is typical in industrial
applications that require low distortion for precision measurements. The circuit uses the ADS8864, a 16-bit, 400kSPS successive-approximation-resistor (SAR) analog-to-digital converter (ADC), along with a precision
amplifier, and an 8 input mux.
VDD
VDD
Bridge Sensor
EN
3.3V
+
REF
S1
OPA333
S2
-
S3
Thermocouple
D
S4
...
S5
+
OPA333
S6
Gain / Filter
Network
ADS8864
-
S7
Current
Sensing
S8
GND
Photo
LED Detector
Optical Sensor
A0
A1
A2
1.8V Logic
Signals
TMUX1108
Analog Inputs
Figure 32. Multiplexing Signals to External ADC
9.3 Design Requirements
For this design example, use the parameters listed in Table 2.
Table 2. Design Parameters
PARAMETERS
26
VALUES
Supply (VDD)
3.3V
I/O signal range
0 V to VDD (Rail to Rail)
Control logic thresholds
1.8 V compatible
Submit Documentation Feedback
Copyright © 2018, Texas Instruments Incorporated
Product Folder Links: TMUX1108
TMUX1108
www.ti.com
SCDS388A – NOVEMBER 2018 – REVISED NOVEMBER 2018
9.4 Detailed Design Procedure
The TMUX1108 can be operated without any external components except for the supply decoupling capacitors. If
the device desired power-up state is disabled, the enable pin should have a weak pull-down resistor and be
controlled by the MCU via GPIO. All inputs being muxed to the ADC must fall within the recommend operating
conditions of the TMUX1108 including signal range and continuous current. For this design with a supply of 3.3 V
the signal range can be 0 V to 3.3 V and the max continuous current can be 30 mA.
The design example highlights a multiplexed, data-acquisition system for highest system linearity and fast
settling. The overall system block diagram is illustrated in Figure 32. The circuit is a multichannel, dataacquisition signal chain consisting of an input low-pass filter, mux, mux output buffer, SAR ADC driver, and the
reference buffer. The architecture allows fast sampling of multiple channels using a single ADC, providing a lowcost solution.
9.5 Application Curve
40
30
On-Leakage (pA)
20
VDD = 1.32V
10
VDD = 1.98V
VDD = 3.63V
0
-10
-20
-30
-40
0
0.5
1
1.5
2
2.5
3
Source or Drain Voltage (V)
3.5
4
D006
TA = 25°C
Figure 33. On-Leakage vs Source or Drain Voltage
10 Power Supply Recommendations
The TMUX1108 operates across a wide supply range of 1.08 V to 5.5 V.. Do not exceed the absolute maximum
ratings because stresses beyond the listed ratings can cause permanent damage to the devices.
Power-supply bypassing improves noise margin and prevents switching noise propagation from the VDD supply to
other components. Good power-supply decoupling is important to achieve optimum performance. For improved
supply noise immunity, use a supply decoupling capacitor ranging from 0.1 μF to 10 μF from VDD to ground.
Place the bypass capacitors as close to the power supply pins of the device as possible using low-impedance
connections. TI recommends using multi-layer ceramic chip capacitors (MLCCs) that offer low equivalent series
resistance (ESR) and inductance (ESL) characteristics for power-supply decoupling purposes. For very sensitive
systems, or for systems in harsh noise environments, avoiding the use of vias for connecting the capacitors to
the device pins may offer superior noise immunity. The use of multiple vias in parallel lowers the overall
inductance and is beneficial for connections to ground planes.
Submit Documentation Feedback
Copyright © 2018, Texas Instruments Incorporated
Product Folder Links: TMUX1108
27
TMUX1108
SCDS388A – NOVEMBER 2018 – REVISED NOVEMBER 2018
www.ti.com
11 Layout
11.1 Layout Guidelines
11.1.1 Layout Information
When a PCB trace turns a corner at a 90° angle, a reflection can occur. A reflection occurs primarily because of
the change of width of the trace. At the apex of the turn, the trace width increases to 1.414 times the width. This
increase upsets the transmission-line characteristics, especially the distributed capacitance and self–inductance
of the trace which results in the reflection. Not all PCB traces can be straight and therefore some traces must
turn corners.Figure 34 shows progressively better techniques of rounding corners. Only the last example (BEST)
maintains constant trace width and minimizes reflections.
BETTER
BEST
2W
WORST
1W min.
W
Figure 34. Trace Example
Route high-speed signals using a minimum of vias and corners which reduces signal reflections and
impedance changes. When a via must be used, increase the clearance size around it to minimize its
capacitance. Each via introduces discontinuities in the signal’s transmission line and increases the chance of
picking up interference from the other layers of the board. Be careful when designing test points, throughhole pins are not recommended at high frequencies.
Figure 35 illustrates an example of a PCB layout with the TMUX1108. Some key considerations are:
•
•
•
•
Decouple the VDD pin with a 0.1-µF capacitor, placed as close to the pin as possible. Make sure that the
capacitor voltage rating is sufficient for the VDD supply.
Keep the input lines as short as possible.
Use a solid ground plane to help reduce electromagnetic interference (EMI) noise pickup.
Do not run sensitive analog traces in parallel with digital traces. Avoid crossing digital and analog traces if
possible, and only make perpendicular crossings when necessary.
11.2 Layout Example
Via to
ground plane
Wide (low inductance)
trace for power
Via to
ground plane
C
A0
A1
EN
A2
VSS
S1
Via to
ground plane
Wide (low inductance)
trace for power
VDD
S5
S2
S3
C
GND
TMUX1108
S6
S4
S7
D
S8
Figure 35. TMUX1108 Layout Example
28
Submit Documentation Feedback
Copyright © 2018, Texas Instruments Incorporated
Product Folder Links: TMUX1108
TMUX1108
www.ti.com
SCDS388A – NOVEMBER 2018 – REVISED NOVEMBER 2018
12 Device and Documentation Support
12.1 Documentation Support
12.1.1 Related Documentation
Texas Instruments, Improve Stability Issues with Low CON Multiplexers.
Texas Instruments, Simplifying Design with 1.8 V logic Muxes and Switches.
Texas Instruments, Eliminate Power Sequencing with Powered-off Protection Signal Switches.
Texas Instruments, System-Level Protection for High-Voltage Analog Multiplexers.
Texas Instruments, QFN/SON PCB Attachment.
Texas Instruments, Quad Flatpack No-Lead Logic Packages.
12.2 Related Links
The table below lists quick access links. Categories include technical documents, support and community
resources, tools and software, and quick access to order now.
12.3 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper
right corner, click on Alert me to register and receive a weekly digest of any product information that has
changed. For change details, review the revision history included in any revised document.
12.4 Community Resources
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
12.5 Trademarks
E2E is a trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
12.6 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
12.7 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
13 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
Submit Documentation Feedback
Copyright © 2018, Texas Instruments Incorporated
Product Folder Links: TMUX1108
29
PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
(4/5)
(6)
TMUX1108PWR
ACTIVE
TSSOP
PW
16
2000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
TM1108
TMUX1108RSVR
ACTIVE
UQFN
RSV
16
3000
RoHS & Green
NIPDAUAG
Level-1-260C-UNLIM
-40 to 125
1B2
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of
工商网监
湘ICP备2023018690号
