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TMUX1208, TMUX1209
SCDS389C – AUGUST 2018 – REVISED DECEMBER 2018
TMUX1208 5-V Bidirectional 8:1, 1-Channel Multiplexer
TMUX1209 5-V Bidirectional 4:1, 2-Channel Multiplexer
1 Features
3 Description
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The TMUX1208 and TMUX1209 are general purpose
complementary metal-oxide semiconductor (CMOS)
multiplexers (MUX). The TMUX1208 offers 8:1 singleended channels, while the TMUX1209 offers
differential 4:1 or dual 4:1 single-ended channels.
Wide operating supply of 1.08 V to 5.5 V allows for
use in a broad array of applications from personal
electronics to building automation applications. The
device supports bidirectional analog and digital
signals on the source (Sx) and drain (D) pins ranging
from GND to VDD.
1
Rail to Rail Operation
Bidirectional Signal Path
Low On-Resistance: 5 Ω
Wide Supply Range: 1.08 V to 5.5 V
-40°C to +125°C Operating Temperature
1.8 V Logic Compatible
Fail-Safe Logic
Low Supply Current: 10 nA
Transition Time: 14 ns
Break-Before-Make Switching
ESD Protection HBM: 2000 V
Industry-Standard TSSOP and QFN Packages
2 Applications
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Analog and Digital Multiplexing / Demultiplexing
HVAC: Heating, Ventilation, and Air Conditioning
Smoke Detectors
Video Surveillance
Electronic Point of Sale
Battery-Powered Equipment
Appliances
Consumer Audio
All logic inputs have 1.8 V logic compatible
thresholds, ensuring both TTL and CMOS logic
compatibility when operating in the valid supply
voltage range. Fail-Safe Logic circuitry allows
voltages on the control pins to be applied before the
supply pin, protecting the device from potential
damage.
Device Information(1)
PART NUMBER
TMUX1208
TMUX1209
VDD
LDO #1
VDD
LDO #3
S1
RAM
LM20
Analog Temp.
Sensor
LM20
Analog Temp.
Sensor
LM20
Analog Temp.
Sensor
FLASH
S3
S4
D
S5
2.60 mm x 1.80 mm
SPACER
TMUX120 8
VI/O
EN
S2
QFN (16)
TMUX1208, TMUX1209 Block Diagram
MCU
LDO #2
BODY SIZE (NOM)
5.00 mm × 4.40 mm
(1) For all available packages, see the package option addendum
at the end of the data sheet.
Application Example
VDD
PACKAGE
TSSOP (16)
TMUX120 9
S1
S2
S3
S4
S5
S6
S7
S8
D
Integrated
12-bit ADC
S1A
S2A
S3A
S4A
DA
S1B
S2B
S3B
S4B
DB
1-OF-8
DECODER
S6
1-OF-4
DECODER
S7
Port I/O
S8
A0
GND
A1
TIMERS
A0
A1
A2
EN
A0
A1
EN
A2
1.8V Logic
I/O
System Inputs &
Sensors
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
TMUX1208, TMUX1209
SCDS389C – AUGUST 2018 – REVISED DECEMBER 2018
www.ti.com
Table of Contents
1
2
3
4
5
6
7
Features ..................................................................
Applications ...........................................................
Description .............................................................
Revision History.....................................................
Device Comparison Table.....................................
Pin Configuration and Functions .........................
Specifications.........................................................
7.1
7.2
7.3
7.4
7.5
7.6
7.7
7.8
7.9
8
1
1
1
2
3
3
5
Absolute Maximum Ratings ...................................... 5
ESD Ratings.............................................................. 5
Recommended Operating Conditions....................... 5
Thermal Information .................................................. 5
Electrical Characteristics (VDD = 5 V ±10 %) ............ 6
Electrical Characteristics (VDD = 3.3 V ±10 %) ......... 8
Electrical Characteristics (VDD = 1.8 V ±10 %) ....... 10
Electrical Characteristics (VDD = 1.2 V ±10 %) ....... 12
Typical Characteristics ............................................ 14
Detailed Description ............................................ 15
8.1 Overview ................................................................. 15
8.2 Functional Block Diagram ....................................... 20
8.3 Feature Description................................................. 20
9
Application and Implementation ........................ 22
9.1
9.2
9.3
9.4
9.5
Application Information............................................
Typical Application .................................................
Design Requirements..............................................
Detailed Design Procedure .....................................
Application Curve ....................................................
22
22
22
23
23
10 Power Supply Recommendations ..................... 23
11 Layout................................................................... 24
11.1 Layout Guidelines ................................................. 24
11.2 Layout Example .................................................... 24
12 Device and Documentation Support ................. 25
12.1
12.2
12.3
12.4
12.5
12.6
12.7
Documentation Support ........................................
Related Links ........................................................
Receiving Notification of Documentation Updates
Community Resources..........................................
Trademarks ...........................................................
Electrostatic Discharge Caution ............................
Glossary ................................................................
25
25
25
25
25
25
25
13 Mechanical, Packaging, and Orderable
Information ........................................................... 25
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision B (November 2018) to Revision C
•
Page
Added device TMUX1209 to the data sheet ......................................................................................................................... 1
Changes from Revision A (September 2018) to Revision B
Page
•
Added RSV (QFN) thermal information to Thermal Information: table................................................................................... 5
•
Added footnote to clarify test conditions ................................................................................................................................ 8
Changes from Original (August 2018) to Revision A
•
2
Page
Changed the document status From: Advanced Information To: Production data ................................................................ 1
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Product Folder Links: TMUX1208 TMUX1209
TMUX1208, TMUX1209
www.ti.com
SCDS389C – AUGUST 2018 – REVISED DECEMBER 2018
5 Device Comparison Table
PRODUCT
DESCRIPTION
TMUX1208
8:1, 1-Channel, single-ended multiplexer
TMUX1209
4:1, 2-Channel, differential multiplexer
6 Pin Configuration and Functions
TMUX1208: PW Package
16-Pin TSSOP
Top View
GND
S1
4
13
VDD
S2
5
12
S5
S3
6
11
S6
S4
7
10
S7
D
8
9
S8
N.C.
1
A2
14
13
3
12
GND
S1
2
11
VDD
S2
3
10
S5
S3
4
9
S6
8
N.C.
A1
A2
14
15
7
2
A0
EN
15
A1
6
16
16
1
5
A0
EN
TMUX1208: RSV Package
16-Pin QFN
Top View
S7
S8
D
S4
No t to scale
No t to scale
Pin Functions TMUX1208
PIN
NAME
TYPE
(1)
DESCRIPTION
TSSOP
UQFN
A0
1
15
I
Address line 0. Controls the switch configuration as shown in Table 1.
EN
2
16
I
Active high logic input. When this pin is low, all switches are turned off. When this pin is high,
the A[2:0] address inputs determine which switch is turned on.
N.C.
3
1
Not Connected
S1
4
2
I/O
Source pin 1. Can be an input or output.
S2
5
3
I/O
Source pin 2. Can be an input or output.
S3
6
4
I/O
Source pin 3. Can be an input or output.
S4
7
5
I/O
Source pin 4. Can be an input or output.
D
8
6
I/O
Drain pin. Can be an input or output.
S8
9
7
I/O
Source pin 8. Can be an input or output.
S7
10
8
I/O
Source pin 7. Can be an input or output.
S6
11
9
I/O
Source pin 6. Can be an input or output.
S5
12
10
I/O
Source pin 5. Can be an input or output.
VDD
13
11
P
Positive power supply. This pin is the most positive power-supply potential. For reliable
operation, connect a decoupling capacitor ranging from 0.1 µF to 10 µF between VDD and GND.
GND
14
12
P
Ground (0 V) reference
A2
15
13
I
Address line 2. Controls the switch configuration as shown in Table 1.
A1
16
14
I
Address line 1. Controls the switch configuration as shown in Table 1.
(1)
Not Connected
I = input, O = output, I/O = input and output, P = power
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TMUX1208, TMUX1209
SCDS389C – AUGUST 2018 – REVISED DECEMBER 2018
www.ti.com
TMUX1209: PW Package
16-Pin TSSOP
Top View
VDD
S1A
4
13
S1B
S2A
5
12
S2B
S3A
6
11
S3B
S4A
7
10
S4B
DA
8
9
DB
N.C.
1
GND
14
13
3
12
VDD
S1A
2
11
S1B
S2A
3
10
S2B
S3A
4
9
S3B
8
N.C.
A1
GND
14
15
7
2
A0
EN
15
A1
6
16
16
1
5
A0
EN
TMUX1209: RSV Package
16-Pin QFN
Top View
S4B
DB
DA
S4A
Not to scale
Not to scale
Pin Functions TMUX1209
PIN
NAME
TYPE (1)
DESCRIPTION
TSSOP
UQFN
A0
1
15
I
Address line 0. Controls the switch configuration as shown in Table 2.
EN
2
16
I
Active high logic input. When this pin is low, all switches are turned off. When this pin is high,
the A[1:0] address inputs determine which switch is turned on.
N.C.
3
1
Not Connected
S1A
4
2
I/O
Source pin 1A. Can be an input or output.
S2A
5
3
I/O
Source pin 2A. Can be an input or output.
S3A
6
4
I/O
Source pin 3A. Can be an input or output.
S4A
7
5
I/O
Source pin 4A. Can be an input or output.
DA
8
6
I/O
Drain pin A. Can be an input or output.
DB
9
7
I/O
Drain pin B. Can be an input or output.
S4B
10
8
I/O
Source pin 4B. Can be an input or output.
S3B
11
9
I/O
Source pin 3B. Can be an input or output.
S2B
12
10
I/O
Source pin 2B. Can be an input or output.
S1B
13
11
I/O
Source pin 1B. Can be an input or output.
VDD
14
12
P
Positive power supply. This pin is the most positive power-supply potential. For reliable
operation, connect a decoupling capacitor ranging from 0.1 µF to 10 µF between VDD and GND.
GND
15
13
P
Ground (0 V) reference
A1
16
14
I
Address line 1. Controls the switch configuration as shown in Table 2.
(1)
4
Not Connected
I = input, O = output, I/O = input and output, P = power
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Product Folder Links: TMUX1208 TMUX1209
TMUX1208, TMUX1209
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SCDS389C – AUGUST 2018 – REVISED DECEMBER 2018
7 Specifications
7.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted) (1)
(2) (3)
MIN
MAX
VDD
Supply voltage
–0.3
6
VSEL or VEN
Logic control input pin voltage (EN, A0, A1, A2)
–0.3
6
V
ISEL or IEN
Logic control input pin current (EN, A0, A1, A2)
–30
30
mA
VS or VD
Source or drain voltage (Sx, D)
–0.5
VDD+0.5
IS or ID (CONT)
Source or drain continuous current (Sx, D)
–30
30
mA
Tstg
Storage temperature
–65
150
°C
TJ
Junction temperature
150
°C
(1)
(2)
(3)
UNIT
V
V
Stresses beyond those listed under Absolute Maximum Rating may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Condition. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
The algebraic convention, whereby the most negative value is a minimum and the most positive value is a maximum.
All voltages are with respect to ground, unless otherwise specified.
7.2 ESD Ratings
VALUE
V(ESD)
(1)
(2)
Electrostatic discharge
Human body model (HBM), per
ANSI/ESDA/JEDEC JS-001, all pins (1)
±2000
Charged device model (CDM), per JEDEC
specification JESD22-C101, all pins (2)
±750
UNIT
V
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
7.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MIN
VDD
Supply voltage
VS or VD
NOM
MAX
UNIT
1.08
5.5
V
Signal path input/output voltage (source or drain pin) (Sx, D)
0
VDD
V
VSEL or
VEN
Logic control input pin voltage (EN, A0, A1, A2)
0
5.5
V
TA
Ambient temperature
–40
125
°C
7.4 Thermal Information
TMUX1208 / TMUX1209
THERMAL METRIC
PW (TSSOP)
RSV (QFN)
UNIT
16 PINS
16 PINS
RθJA
Junction-to-ambient thermal resistance
118.9
134.6
°C/W
RθJC(top)
Junction-to-case (top) thermal resistance
49.3
74.3
°C/W
RθJB
Junction-to-board thermal resistance
65.2
62.8
°C/W
ΨJT
Junction-to-top characterization parameter
7.6
4.3
°C/W
ΨJB
Junction-to-board characterization parameter
64.6
61.1
°C/W
RθJC(bot)
Junction-to-case (bottom) thermal resistance
N/A
N/A
°C/W
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TMUX1208, TMUX1209
SCDS389C – AUGUST 2018 – REVISED DECEMBER 2018
www.ti.com
7.5 Electrical Characteristics (VDD = 5 V ±10 %)
at TA = 25°C, VDD = 5 V (unless otherwise noted)
PARAMETER
TEST CONDITIONS
TA
MIN
TYP
MAX
UNIT
ANALOG SWITCH
RON
On-resistance
ΔRON
RON
On-resistance matching between
channels
On-resistance flatness
FLAT
IS(OFF)
ID(OFF)
ID(ON)
IS(ON)
Source off leakage current (1)
Drain off leakage current (1)
Channel on leakage current
VS = 0 V to VDD
ISD = 10 mA
Refer to On-Resistance
25°C
VS = 0 V to VDD
ISD = 10 mA
Refer to On-Resistance
25°C
VS = 0 V to VDD
ISD = 10 mA
Refer to On-Resistance
25°C
VDD = 5 V
Switch Off
VD = 4.5 V / 1 V
VS = 1 V / 4.5 V
Refer to Off-Leakage Current
25°C
VDD = 5 V
Switch Off
VD = 4.5 V / 1 V
VS = 1 V / 4.5 V
Refer to Off-Leakage Current
25°C
VDD = 5 V
Switch On
VD = VS = 4.5 V / 1 V
Refer to On-Leakage Current
25°C
5
Ω
–40°C to +85°C
7
Ω
–40°C to +125°C
9
Ω
0.15
Ω
–40°C to +85°C
1
Ω
–40°C to +125°C
1
Ω
1.5
Ω
–40°C to +85°C
2
Ω
–40°C to +125°C
3
Ω
±75
nA
–40°C to +85°C
-150
150
nA
–40°C to +125°C
-175
175
nA
±200
nA
–40°C to +85°C
-500
500
nA
–40°C to +125°C
-750
750
nA
±200
nA
–40°C to +85°C
-500
500
nA
–40°C to +125°C
-750
750
nA
LOGIC INPUTS (EN, A0, A1, A2)
VIH
Input logic high
-40°C to 125°C
1.49
5.5
V
VIL
Input logic low
-40°C to 125°C
0
0.87
V
IIH
IIL
Input leakage current
25°C
IIH
IIL
Input leakage current
–40°C to +125°C
CIN
Logic input capacitance
25°C
CIN
Logic input capacitance
–40°C to +125°C
±0.005
µA
±0.10
1
µA
pF
2
pF
POWER SUPPLY
IDD
(1)
6
VDD supply current
Logic inputs = 0 V or 5.5 V
25°C
0.02
–40°C to +125°C
µA
2.7
µA
When VS is 4.5 V, VD is 1 V, and vice versa.
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SCDS389C – AUGUST 2018 – REVISED DECEMBER 2018
Electrical Characteristics (VDD = 5 V ±10 %) (continued)
at TA = 25°C, VDD = 5 V (unless otherwise noted)
PARAMETER
TEST CONDITIONS
TA
MIN
TYP
MAX
UNIT
DYNAMIC CHARACTERISTICS
tTRAN
tOPEN
Transition time between channels
Break before make time
(BBM)
tON(EN)
Enable turn-on time
tOFF(EN) Enable turn-off time
QC
OISO
XTALK
CDOFF
CSON
CDON
25°C
VS = 3 V
RL = 200 Ω, CL = 15 pF
Refer to Break-Before-Make
25°C
VS = 3 V
RL = 200 Ω, CL = 15 pF
Refer to tON(EN) and tOFF(EN)
25°C
VS = 3 V
RL = 200 Ω, CL = 15 pF
Refer to tON(EN) and tOFF(EN)
25°C
14
–40°C to +85°C
–40°C to +125°C
ns
33
ns
33
ns
8
ns
–40°C to +85°C
1
ns
–40°C to +125°C
1
ns
14
ns
–40°C to +85°C
20
ns
–40°C to +125°C
20
ns
5
ns
–40°C to +85°C
20
ns
–40°C to +125°C
20
ns
VS = VDD/2
RS = 0 Ω, CL = 1 nF
Refer to Charge Injection
25°C
±9
pC
RL = 50 Ω, CL = 5 pF
f = 1 MHz
Refer to Off Isolation
25°C
-62
dB
RL = 50 Ω, CL = 5 pF
f = 10 MHz
Refer to Off Isolation
25°C
-42
dB
RL = 50 Ω, CL = 5 pF
f = 1 MHz
Refer to Crosstalk
25°C
-62
dB
RL = 50 Ω, CL = 5 pF
f = 10 MHz
Refer to Crosstalk
25°C
-42
dB
Bandwidth - TMUX1208
RL = 50 Ω, CL = 5 pF
Refer to Bandwidth
25°C
65
MHz
Bandwidth - TMUX1209
RL = 50 Ω, CL = 5 pF
Refer to Bandwidth
25°C
125
MHz
Source off capacitance
Charge Injection
Off Isolation
Crosstalk
BW
CSOFF
VS = 3 V
RL = 200 Ω, CL = 15 pF
Refer to Transition Time
f = 1 MHz
25°C
13
pF
Drain off capacitance - TMUX1208 f = 1 MHz
25°C
76
pF
Drain off capacitance - TMUX1209
f = 1 MHz
25°C
38
pF
On capacitance - TMUX1208
f = 1 MHz
25°C
85
pF
On capacitance - TMUX1209
f = 1 MHz
25°C
42
pF
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TMUX1208, TMUX1209
SCDS389C – AUGUST 2018 – REVISED DECEMBER 2018
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7.6 Electrical Characteristics (VDD = 3.3 V ±10 %)
at TA = 25°C, VDD = 3.3 V (unless otherwise noted)
PARAMETER
TEST CONDITIONS
TA
MIN
TYP
MAX
UNIT
ANALOG SWITCH
RON
On-resistance
ΔRON
RON
On-resistance matching between
channels
On-resistance flatness
FLAT
IS(OFF)
ID(OFF)
ID(ON)
IS(ON)
Source off leakage current (1)
Drain off leakage current (1)
Channel on leakage current
VS = 0 V to VDD
ISD = 10 mA
Refer to On-Resistance
25°C
9
VS = 0 V to VDD
ISD = 10 mA
Refer to On-Resistance
25°C
VS = 0 V to VDD
ISD = 10 mA
Refer to On-Resistance
25°C
3
Ω
–40°C to +85°C
5
Ω
–40°C to +125°C
6
Ω
VDD = 3.3 V
Switch Off
VD = 3 V / 1 V
VS = 1 V / 3 V
Refer to Off-Leakage Current
25°C
VDD = 3.3 V
Switch Off
VD = 3 V / 1 V
VS = 1 V / 3 V
Refer to Off-Leakage Current
25°C
VDD = 3.3 V
Switch On
VD = VS = 3 V / 1 V
Refer to On-Leakage Current
25°C
Ω
–40°C to +85°C
15
Ω
–40°C to +125°C
17
Ω
0.15
Ω
–40°C to +85°C
1
Ω
–40°C to +125°C
1
Ω
±75
nA
–40°C to +85°C
-150
150
nA
–40°C to +125°C
-175
175
nA
±200
nA
–40°C to +85°C
-500
500
nA
–40°C to +125°C
-750
750
nA
±200
nA
–40°C to +85°C
-500
500
nA
–40°C to +125°C
-750
750
nA
LOGIC INPUTS (EN, A0, A1, A2)
VIH
Input logic high
-40°C to 125°C
1.35
5.5
V
VIL
Input logic low
-40°C to 125°C
0
0.8
V
IIH
IIL
Input leakage current
25°C
IIH
IIL
Input leakage current
–40°C to +125°C
CIN
Logic input capacitance
25°C
CIN
Logic input capacitance
–40°C to +125°C
±0.005
µA
±0.10
1
µA
pF
2
pF
POWER SUPPLY
IDD
(1)
8
VDD supply current
Logic inputs = 0 V or 5.5 V
25°C
0.01
–40°C to +125°C
µA
1.5
µA
When VS is 3 V, VD is 1 V, and vice versa.
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SCDS389C – AUGUST 2018 – REVISED DECEMBER 2018
Electrical Characteristics (VDD = 3.3 V ±10 %) (continued)
at TA = 25°C, VDD = 3.3 V (unless otherwise noted)
PARAMETER
TEST CONDITIONS
TA
MIN
TYP
MAX
UNIT
DYNAMIC CHARACTERISTICS
tTRAN
tOPEN
Transition time between channels
Break before make time
(BBM)
tON(EN)
Enable turn-on time
tOFF(EN) Enable turn-off time
QC
OISO
XTALK
CDOFF
CSON
CDON
25°C
VS = 2 V
RL = 200 Ω, CL = 15 pF
Refer to Break-Before-Make
25°C
VS = 2 V
RL = 200 Ω, CL = 15 pF
Refer to tON(EN) and tOFF(EN)
25°C
VS = 2 V
RL = 200 Ω, CL = 15 pF
Refer to tON(EN) and tOFF(EN)
25°C
14
–40°C to +85°C
–40°C to +125°C
ns
25
ns
25
ns
8
ns
–40°C to +85°C
1
ns
–40°C to +125°C
1
ns
14
ns
–40°C to +85°C
25
ns
–40°C to +125°C
25
ns
7
ns
–40°C to +85°C
13
ns
–40°C to +125°C
13
ns
VS = VDD/2
RS = 0 Ω, CL = 1 nF
Refer to Charge Injection
25°C
±7
pC
RL = 50 Ω, CL = 5 pF
f = 1 MHz
Refer to Off Isolation
25°C
-62
dB
RL = 50 Ω, CL = 5 pF
f = 10 MHz
Refer to Off Isolation
25°C
-42
dB
RL = 50 Ω, CL = 5 pF
f = 1 MHz
Refer to Crosstalk
25°C
-62
dB
RL = 50 Ω, CL = 5 pF
f = 10 MHz
Refer to Crosstalk
25°C
-42
dB
Bandwidth - TMUX1208
RL = 50 Ω, CL = 5 pF
Refer to Bandwidth
25°C
65
MHz
Bandwidth - TMUX1209
RL = 50 Ω, CL = 5 pF
Refer to Bandwidth
25°C
125
MHz
Source off capacitance
f = 1 MHz
25°C
13
pF
Drain off capacitance - TMUX1208
f = 1 MHz
25°C
76
pF
Drain off capacitance - TMUX1209
f = 1 MHz
25°C
38
pF
On capacitance - TMUX1208
f = 1 MHz
25°C
85
pF
On capacitance - TMUX1209
f = 1 MHz
25°C
42
pF
Charge Injection
Off Isolation
Crosstalk
BW
CSOFF
VS = 2 V
RL = 200 Ω, CL = 15 pF
Refer to Transition Time
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7.7 Electrical Characteristics (VDD = 1.8 V ±10 %)
at TA = 25°C, VDD = 1.8 V (unless otherwise noted)
PARAMETER
TEST CONDITIONS
TA
MIN
TYP
MAX
UNIT
ANALOG SWITCH
RON
On-resistance
ΔRON
IS(OFF)
ID(OFF)
ID(ON)
IS(ON)
On-resistance matching between
channels
Source off leakage current (1)
Drain off leakage current (1)
Channel on leakage current
VS = 0 V to VDD
ISD = 10 mA
Refer to On-Resistance
25°C
VS = 0 V to VDD
ISD = 10 mA
Refer to On-Resistance
25°C
VDD = 1.98 V
Switch Off
VD = 1.8 V / 1 V
VS = 1 V / 1.8 V
Refer to Off-Leakage Current
25°C
VDD = 1.98 V
Switch Off
VD = 1.8 V / 1 V
VS = 1 V / 1.8 V
Refer to Off-Leakage Current
25°C
VDD = 1.98 V
Switch On
VD = VS = 1.8 V / 1 V
Refer to On-Leakage Current
25°C
40
Ω
–40°C to +85°C
80
Ω
–40°C to +125°C
80
Ω
0.15
Ω
–40°C to +85°C
1.5
Ω
–40°C to +125°C
1.5
Ω
±75
nA
–40°C to +85°C
-150
150
nA
–40°C to +125°C
-175
175
nA
±200
nA
–40°C to +85°C
-500
500
nA
–40°C to +125°C
-750
750
nA
±200
nA
–40°C to +85°C
-500
500
nA
–40°C to +125°C
-750
750
nA
LOGIC INPUTS (EN, A0, A1, A2)
VIH
Input logic high
–40°C to +125°C
1.07
5.5
V
VIL
Input logic low
–40°C to +125°C
0
0.68
V
IIH
IIL
Input leakage current
25°C
IIH
IIL
Input leakage current
–40°C to +125°C
CIN
Logic input capacitance
±0.005
25°C
µA
±0.10
1
–40°C to +125°C
µA
pF
2
pF
POWER SUPPLY
IDD
(1)
10
VDD supply current
Logic inputs = 0 V or 5.5 V
25°C
0.006
–40°C to +125°C
µA
0.95
µA
When VS is 1.8 V, VD is 1 V, and vice versa.
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Electrical Characteristics (VDD = 1.8 V ±10 %) (continued)
at TA = 25°C, VDD = 1.8 V (unless otherwise noted)
PARAMETER
TEST CONDITIONS
TA
MIN
TYP
MAX
UNIT
DYNAMIC CHARACTERISTICS
tTRAN
tOPEN
Transition time between channels
Break before make time
(BBM)
tON(EN)
Enable turn-on time
tOFF(EN) Enable turn-off time
QC
OISO
XTALK
CDOFF
CSON
CDON
25°C
VS = 1 V
RL = 200 Ω, CL = 15 pF
Refer to Break-Before-Make
25°C
VS = 1 V
RL = 200 Ω, CL = 15 pF
Refer to tON(EN) and tOFF(EN)
25°C
VS = 1 V
RL = 200 Ω, CL = 15 pF
Refer to tON(EN) and tOFF(EN)
25°C
28
–40°C to +85°C
–40°C to +125°C
ns
48
ns
48
ns
16
ns
–40°C to +85°C
1
ns
–40°C to +125°C
1
ns
28
ns
–40°C to +85°C
48
ns
–40°C to +125°C
48
ns
16
ns
–40°C to +85°C
27
ns
–40°C to +125°C
27
ns
VS = VDD/2
RS = 0 Ω, CL = 1 nF
Refer to Charge Injection
25°C
-2
pC
RL = 50 Ω, CL = 5 pF
f = 1 MHz
Refer to Off Isolation
25°C
-62
dB
RL = 50 Ω, CL = 5 pF
f = 10 MHz
Refer to Off Isolation
25°C
-42
dB
RL = 50 Ω, CL = 5 pF
f = 1 MHz
Refer to Crosstalk
25°C
-62
dB
RL = 50 Ω, CL = 5 pF
f = 10 MHz
Refer to Crosstalk
25°C
-42
dB
Bandwidth - TMUX1208
RL = 50 Ω, CL = 5 pF
Refer to Bandwidth
25°C
65
MHz
Bandwidth - TMUX1209
RL = 50 Ω, CL = 5 pF
Refer to Bandwidth
25°C
125
MHz
Source off capacitance
f = 1 MHz
25°C
13
pF
Drain off capacitance - TMUX1208
f = 1 MHz
25°C
76
pF
Drain off capacitance - TMUX1209
f = 1 MHz
25°C
38
pF
On capacitance - TMUX1208
f = 1 MHz
25°C
85
pF
On capacitance - TMUX1209
f = 1 MHz
25°C
42
pF
Charge Injection
Off Isolation
Crosstalk
BW
CSOFF
VS = 1 V
RL = 200 Ω, CL = 15 pF
Refer to Transition Time
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7.8 Electrical Characteristics (VDD = 1.2 V ±10 %)
at TA = 25°C, VDD = 1.2 V (unless otherwise noted)
PARAMETER
TEST CONDITIONS
TA
MIN
TYP
MAX
UNIT
ANALOG SWITCH
RON
On-resistance
ΔRON
IS(OFF)
ID(OFF)
ID(ON)
IS(ON)
On-resistance matching between
channels
Source off leakage current (1)
Drain off leakage current (1)
Channel on leakage current
VS = 0 V to VDD
ISD = 10 mA
Refer to On-Resistance
25°C
VS = 0 V to VDD
ISD = 10 mA
Refer to On-Resistance
25°C
VDD = 1.32 V
Switch Off
VD = 1.2 V / 1 V
VS = 1 V / 1.2 V
Refer to Off-Leakage Current
25°C
VDD = 1.32 V
Switch Off
VD = 1.2 V / 1 V
VS = 1 V / 1.2 V
Refer to Off-Leakage Current
25°C
VDD = 1.32 V
Switch On
VD = VS = 1.2 V / 1 V
Refer to On-Leakage Current
25°C
70
Ω
–40°C to +85°C
105
Ω
–40°C to +125°C
105
Ω
0.15
Ω
–40°C to +85°C
1.5
Ω
–40°C to +125°C
1.5
Ω
±75
nA
–40°C to +85°C
-150
150
nA
–40°C to +125°C
-175
175
nA
±200
nA
–40°C to +85°C
-500
500
nA
–40°C to +125°C
-750
750
nA
±200
nA
–40°C to +85°C
-500
500
nA
–40°C to +125°C
-750
750
nA
LOGIC INPUTS (EN, A0, A1, A2)
VIH
Input logic high
–40°C to +125°C
0.96
5.5
V
VIL
Input logic low
–40°C to +125°C
0
0.36
V
IIH
IIL
Input leakage current
25°C
IIH
IIL
Input leakage current
–40°C to +125°C
CIN
Logic input capacitance
±0.005
25°C
µA
±0.10
1
–40°C to +125°C
µA
pF
2
pF
POWER SUPPLY
IDD
(1)
12
VDD supply current
Logic inputs = 0 V or 5.5 V
25°C
0.005
–40°C to +125°C
µA
0.8
µA
When VS is 1.2 V, VD is 1 V, and vice versa.
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Electrical Characteristics (VDD = 1.2 V ±10 %) (continued)
at TA = 25°C, VDD = 1.2 V (unless otherwise noted)
PARAMETER
TEST CONDITIONS
TA
MIN
TYP
MAX
UNIT
DYNAMIC CHARACTERISTICS
tTRAN
tOPEN
Transition time between channels
Break before make time
(BBM)
tON(EN)
Enable turn-on time
tOFF(EN) Enable turn-off time
QC
OISO
XTALK
CDOFF
CSON
CDON
25°C
VS = 1 V
RL = 200 Ω, CL = 15 pF
Refer to Break-Before-Make
25°C
VS = 1 V
RL = 200 Ω, CL = 15 pF
Refer to tON(EN) and tOFF(EN)
25°C
VS = 1 V
RL = 200 Ω, CL = 15 pF
Refer to tON(EN) and tOFF(EN)
25°C
60
–40°C to +85°C
–40°C to +125°C
ns
210
ns
210
ns
28
ns
–40°C to +85°C
1
ns
–40°C to +125°C
1
ns
60
ns
–40°C to +85°C
190
ns
–40°C to +125°C
190
ns
45
ns
–40°C to +85°C
150
ns
–40°C to +125°C
150
ns
VS = VDD/2
RS = 0 Ω, CL = 1 nF
Refer to Charge Injection
25°C
±2
pC
RL = 50 Ω, CL = 5 pF
f = 1 MHz
Refer to Off Isolation
25°C
-62
dB
RL = 50 Ω, CL = 5 pF
f = 10 MHz
Refer to Off Isolation
25°C
-42
dB
RL = 50 Ω, CL = 5 pF
f = 1 MHz
Refer to Crosstalk
25°C
-62
dB
RL = 50 Ω, CL = 5 pF
f = 10 MHz
Refer to Crosstalk
25°C
-42
dB
Bandwidth - TMUX1208
RL = 50 Ω, CL = 5 pF
Refer to Bandwidth
25°C
65
MHz
Bandwidth - TMUX1209
RL = 50 Ω, CL = 5 pF
Refer to Bandwidth
25°C
125
MHz
Source off capacitance
f = 1 MHz
25°C
13
pF
Drain off capacitance - TMUX1208
f = 1 MHz
25°C
76
pF
Drain off capacitance - TMUX1209
f = 1 MHz
25°C
38
pF
On capacitance - TMUX1208
f = 1 MHz
25°C
85
pF
On capacitance - TMUX1209
f = 1 MHz
25°C
42
pF
Charge Injection
Off Isolation
Crosstalk
BW
CSOFF
VS = 1 V
RL = 200 Ω, CL = 15 pF
Refer to Transition Time
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7.9 Typical Characteristics
at TA = 25°C, VDD = 5 V (unless otherwise noted)
10
80
VDD= 1.08V
8
On Resistance (:)
On Resistance (:)
60
40
VDD= 1.62V
TA = +125qC
TA = +85qC
6
4
20
VDD= 3V
2
VDD= 4.5V
TA = -40qC
0
TA = +25qC
0
0
0.5
1
1.5
2
2.5
3
3.5
Source or Drain Voltage (V)
4
4.5
5
0
0.5
1
1.5
2
2.5
Source or Drain Voltage (V)
D001
TA = 25°C
3
3.5
D002
VDD= 3 V
Figure 1. On-Resistance vs Source or Drain Voltage
Figure 2. On-Resistance vs Source or Drain Voltage
30
20
27
TON
16
24
18
Time (ns)
Time (ns)
21
TON
15
12
TOFF
8
12
9
4
TOFF
6
3
1.5
2
2.5
3
3.5
4
4.5
VDD - Supply Voltage (V)
5
0
-60
5.5
-30
0
30
60
90
TA - Temperature (qC)
D003
TA = 25°C
120
150
D004
VDD= 3.3 V
Figure 3. TON (EN) and TOFF (EN) vs Supply Voltage
Figure 4. TON (EN) and TOFF (EN) vs Temperature
0
30
-10
25
-20
-30
Gain (dB)
Time (ns)
20
TTRANSITION_FALLING
15
TTRANSITION_RISING
10
-40
-50
-60
-70
-80
5
TMUX1208 Bandwidth
TMUX1209 Bandwidth
Off-Isolation
-90
0
0.5
1.5
2.5
3.5
VDD - Supply Voltage (V)
4.5
5.5
-100
100k
1M
D005
100M
D006
TA = 25°C
TA = 25°C
Figure 5. TTRANSITION vs Supply Voltage
14
10M
Frequency (Hz)
Figure 6. Frequency Response
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8 Detailed Description
8.1 Overview
8.1.1 On-Resistance
The on-resistance of a device is the ohmic resistance between the source (Sx) and drain (D) pins of the device.
The on-resistance varies with input voltage and supply voltage. The symbol RON is used to denote on-resistance.
The measurement setup used to measure RON is shown below. Voltage (V) and current (ISD) are measured using
this setup, and RON is computed as shown in Figure 7 with RON = V / ISD:
V
ISD
Sx
D
VS
Figure 7. On-Resistance Measurement Setup
8.1.2 Off-Leakage Current
There are two types of leakage currents associated with a switch during the off state:
1. Source off-leakage current
2. Drain off-leakage current
Source leakage current is defined as the leakage current flowing into or out of the source pin when the switch is
off. This current is denoted by the symbol IS(OFF).
Drain leakage current is defined as the leakage current flowing into or out of the drain pin when the switch is off.
This current is denoted by the symbol ID(OFF).
The setup used to measure both off-leakage currents is shown in Figure 8.
Is (OFF)
VDD
VDD
VDD
VDD
S1
S1
A
ID (OFF)
S2
S2
D
D
A
VS
S8
S8
VS
VD
VD
GND
GND
Figure 8. Off-Leakage Measurement Setup
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Overview (continued)
8.1.3 On-Leakage Current
Source on-leakage current is defined as the leakage current flowing into or out of the source pin when the switch
is on. This current is denoted by the symbol IS(ON).
Drain on-leakage current is defined as the leakage current flowing into or out of the drain pin when the switch is
on. This current is denoted by the symbol ID(ON).
Either the source pin or drain pin is left floating during the measurement. Figure 9 shows the circuit used for
measuring the on-leakage current, denoted by IS(ON) or ID(ON).
VDD
VDD
VDD
S1
N.C.
VDD
IS (ON)
S1
A
ID (ON)
S2
S2
D
D
A
N.C.
S8
S8
Vs
VS
VS
VD
GND
GND
Figure 9. On-Leakage Measurement Setup
8.1.4 Transition Time
Transition time is defined as the time taken by the output of the device to rise or fall 10% after the address signal
has risen or fallen past the logic threshold. The 10% transition measurement is utilized to provide the timing of
the device, system level timing can then account for the time constant added from the load resistance and load
capacitance. Figure 10 shows the setup used to measure transition time, denoted by the symbol tTRANSITION.
VDD
0.1…F
VDD
VDD
ADDRE SS
DRIVE
(VSEL)
tf < 5ns
tr < 5ns
VIH
VS
VIL
S1
OUTPUT
D
0V
S2
S8
RL
CL
tTRAN SITION
tTRAN SITION
A0
90%
A1
OUTPUT
VSEL
A2
10%
GND
0V
Figure 10. Transition-Time Measurement Setup
16
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Overview (continued)
8.1.5 Break-Before-Make
Break-before-make delay is a safety feature that prevents two inputs from connecting when the device is
switching. The output first breaks from the on-state switch before making the connection with the next on-state
switch. The time delay between the break and the make is known as break-before-make delay. Figure 11 shows
the setup used to measure break-before-make delay, denoted by the symbol tOPEN(BBM).
VDD
0.1…F
VDD
VDD
S1
VS
ADDRE SS
DRIVE
(VSEL)
tr < 5ns
OUTPUT
D
tf < 5ns
S2-S7
0V
RL
CL
S8
90%
Output
tBBM 1
A0
tBBM 2
0V
A1
VSEL
tOPEN (BBM) = min ( tBBM 1, tBBM 2)
A2
GND
Figure 11. Break-Before-Make Delay Measurement Setup
8.1.6 tON(EN) and tOFF(EN)
Turn-on time is defined as the time taken by the output of the device to rise to 10% after the enable has risen
past the logic threshold. The 10% measurement is utilized to provide the timing of the device, system level timing
can then account for the time constant added from the load resistance and load capacitance. Figure 12 shows
the setup used to measure transition time, denoted by the symbol tON(EN).
Turn-off time is defined as the time taken by the output of the device to fall to 90% after the enable has fallen
past the logic threshold. The 90% measurement is utilized to provide the timing of the device, system level timing
can then account for the time constant added from the load resistance and load capacitance. Figure 12 shows
the setup used to measure transition time, denoted by the symbol tOFF(EN).
VDD
0.1…F
VDD
VDD
ENABL E
DRIVE
(VEN)
tf < 5ns
tr < 5ns
VS
VIH
S1
OUTPUT
D
VIL
S2
0V
RL
S8
tOFF
tON (EN)
CL
(EN)
A0
EN
90%
A1
OUTPUT
VEN
10%
A2
GND
0V
Figure 12. Turn-On and Turn-Off Time Measurement Setup
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Overview (continued)
8.1.7 Charge Injection
The TMUX1208 and TMUX1209 have a transmission-gate topology. Any mismatch in capacitance between the
NMOS and PMOS transistors results in a charge injected into the drain or source during the falling or rising edge
of the gate signal. The amount of charge injected into the source or drain of the device is known as charge
injection, and is denoted by the symbol QC. Figure 13 shows the setup used to measure charge injection from
source (Sx) to drain (D).
VDD
0.1…F
VDD
VDD
VS
S1
OUTPUT
D
0V
VOUT
S2
CL
S8
Output
VOUT
VS
QC = CL ×
VOUT
A0
EN
A1
VEN
A2
GND
Figure 13. Charge-Injection Measurement Setup
8.1.8 Off Isolation
Off isolation is defined as the ratio of the signal at the drain pin (D) of the device when a signal is applied to the
source pin (Sx) of an off-channel. Figure 14 shows the setup used to measure, and the equation to compute off
isolation.
0.1µF
NETWORK
VDD
VS
ANALYZER
50Q
S
VSIG
D
VOUT
RL
50Q
SX/DX
GND
RL
50Q
Figure 14. Off Isolation Measurement Setup
Off Isolation
18
§V
·
20 ˜ Log ¨ OUT ¸
© VS ¹
(1)
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Overview (continued)
8.1.9 Crosstalk
Crosstalk is defined as the ratio of the signal at the drain pin (D) of a different channel, when a signal is applied
at the source pin (Sx) of an on-channel. Figure 15 shows the setup used to measure, and the equation used to
compute crosstalk.
0.1µF
NETWORK
VDD
ANALYZER
S1
VOUT
RL
D
50Q
VS
RL
S2
50Q
50Q
VSIG
SX
RL
GND
50Q
Figure 15. Channel-to-Channel Crosstalk Measurement Setup
§V
·
20 ˜ Log ¨ OUT ¸
© VS ¹
Channel-to-Channel Crosstalk
(2)
8.1.10 Bandwidth
Bandwidth is defined as the range of frequencies that are attenuated by less than 3 dB when the input is applied
to the source pin (Sx) of an on-channel, and the output is measured at the drain pin (D) of the device. Figure 16
shows the setup used to measure bandwidth.
0.1µF
NETWORK
VDD
VS
ANALYZER
50Q
S
VSIG
D
VOUT
RL
50Q
GND
Figure 16. Bandwidth Measurement Setup
Attenuation
§V ·
20 ˜ Log ¨ 2 ¸
© V1 ¹
(3)
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8.2 Functional Block Diagram
The TMUX1208 is an 8:1, single-ended (1-ch.), mux. The TMUX1209 is an 4:1, differential (2-ch.), mux. Each
channel is turned on or turned off based on the state of the address lines and enable pin.
TMUX120 8
TMUX120 9
S1
S2
S3
S4
S5
S6
S7
S8
D
S1A
S2A
S3A
S4A
DA
S1B
S2B
S3B
S4B
DB
1-OF-8
DECODER
A0
A1
A2
1-OF-4
DECODER
EN
A0
A1
EN
Figure 17. TMUX1208, TMUX1209 Functional Block Diagrams
8.3 Feature Description
8.3.1 Bidirectional Operation
The TMUX1208 and TMUX1209 conduct equally well from source (Sx) to drain (D) or from drain (D) to source
(Sx). Each channel has very similar characteristics in both directions and supports both analog and digital
signals.
8.3.2 Rail to Rail Operation
The valid signal path input/output voltage for TMUX1208 and TMUX1209 ranges from GND to VDD.
8.3.3 1.8 V Logic Compatible Inputs
The TMUX1208 and TMUX1209 has 1.8-V logic compatible control for all logic control inputs. The logic input
thresholds scale with supply but still provide 1.8-V logic control when operating at 5.5 V supply voltage. 1.8-V
logic level inputs allows the multiplexers to interface with processors that have lower logic I/O rails and eliminates
the need for an external translator, which saves both space and BOM cost. For more information on 1.8 V logic
implementations refer to Simplifying Design with 1.8 V logic Muxes and Switches
8.3.4 Fail-Safe Logic
The TMUX1208 and TMUX1209 have Fail-Safe Logic on the control input pins (EN, A0. A1, A2) allowing for
operation up to 5.5 V, regardless of the state of the supply pin. This feature allows voltages on the control pins to
be applied before the supply pin, protecting the device from potential damage. Fail-Safe Logic minimizes system
complexity by removing the need for power supply sequencing on the logic control pins. For example, the FailSafe Logic feature allows the select pins of the TMUX1208 or TMUX1209 to be ramped to 5.5 V while VDD = 0 V.
Additionally, the feature enables operation of the multiplexers with VDD = 1.2 V while allowing the select pins to
interface with a logic level of another device up to 5.5 V.
20
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Feature Description (continued)
8.3.5 Device Functional Modes
When the EN pin of the TMUX1208 is pulled high, one of the switches is closed based on the state of the
address lines. Similarly, when the EN pin of the TMUX1209 is pulled high, two of the switches are closed based
on the state of the address lines. When the EN pin is pulled low, all the switches are in an open state regardless
of the state of the address lines.
8.3.6 Truth Tables
Table 1 and Table 2 show the truth tables for the TMUX1208 and TMUX1209, respectively.
Table 1. TMUX1208 Truth Table
EN
0
A2
A1
A0
(1)
(1)
(1)
X
X
X
Selected Inputs Connected To Drain (D) Pin
All channels are off
1
0
0
0
S1
1
0
0
1
S2
1
0
1
0
S3
1
0
1
1
S4
1
1
0
0
S5
1
1
0
1
S6
1
1
1
0
S7
1
1
1
1
S8
(1)
X denotes don't care.
Table 2. TMUX1209 Truth Table
EN
0
A1
A0
Selected Input Connected To Drain (DA, DB) Pins
X (1) X (1)
All channels are off
1
0
0
S1A and S1B
1
0
1
S2A and S2B
1
1
0
S3A and S3B
1
1
1
S4A and S4B
(1)
X denotes don't care.
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9 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
9.1 Application Information
The TMUX12xx family offers good system performance across a wide operating supply (1.08V to 5.5V). These
devices include 1.8V logic compatible control input pins that enable operation in systems with 1.8V I/O rails.
Additionally, the control input pins support Fail-Safe Logic which allows for operation up to 5.5V, regardless of
the state of the supply pin. This protection stops the logic pins from back-powering the supply rail. These
features make the TMUX12xx a family of general purpose multiplexers and switches that can reduce system
complexity, board size, and overall system cost.
9.2 Typical Application
One useful application to take advantage of the TMUX1208 features is multiplexing various signals into an ADC
that is integrated into a MCU. Utilizing an integrated ADC in a MCU allows a system to minimize cost with a
potential tradeoff of system performance when compared to an external ADC. The multiplexer allows for multiple
inputs/sensors to be monitored with a single ADC pin of the device, which is critical in systems with limited I/O.
The TMUX1209 is suitable for similar design example using differential signals, or as two 4:1 multiplexers.
VDD
VDD
VDD
LDO #1
VI/O
EN
MCU
S1
LDO #2
S2
LDO #3
RAM
FLASH
S3
S4
LM20
Analog Temp.
Sensor
LM20
Analog Temp.
Sensor
LM20
Analog Temp.
Sensor
D
S5
Integrated
12-bit ADC
S6
S7
Port I/O
S8
A0
A1
TIMERS
A2
GND
1.8V Logic
I/O
System Inputs &
Sensors
Figure 18. Multiplexing Signals to Integrated ADC
9.3 Design Requirements
For this design example, use the parameters listed in Table 3.
Table 3. Design Parameters
22
PARAMETERS
VALUES
Supply (VDD)
5.0 V
I/O signal range
0 V to VDD (Rail to Rail)
Control logic thresholds
1.8 V compatible
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9.4 Detailed Design Procedure
The TMUX1208 and TMUX1209 can be operated without any external components except for the supply
decoupling capacitors. If the parts desired power-up state is disabled, the enable pin should have a weak pulldown resistor and be controlled by the MCU via GPIO. All inputs being muxed to the ADC of the MCU must fall
within the recommend operating conditions of the TMUX1208 and TMUX1209 including signal range and
continuous current. For this design with a supply of 5 V the signal range can be 0 V to 5 V and the max
continuous current can be 30 mA.
9.5 Application Curve
80
VDD= 1.08V
On Resistance (:)
60
40
VDD= 1.62V
20
VDD= 3V
VDD= 4.5V
0
0
0.5
1
1.5
2
2.5
3
3.5
Source or Drain Voltage (V)
4
4.5
5
D001
TA = 25°C
Figure 19. On-Resistance vs Source or Drain Voltage
10 Power Supply Recommendations
The TMUX1208 and TMUX1209 operate across a wide supply range of 1.08 V to 5.5 V. Do not exceed the
absolute maximum ratings because stresses beyond the listed ratings can cause permanent damage to the
devices.
Power-supply bypassing improves noise margin and prevents switching noise propagation from the VDD supply to
other components. Good power-supply decoupling is important to achieve optimum performance. For improved
supply noise immunity, use a supply decoupling capacitor ranging from 0.1 μF to 10 μF from VDD to ground.
Place the bypass capacitors as close to the power supply pins of the device as possible using low-impedance
connections. TI recommends using multi-layer ceramic chip capacitors (MLCCs) that offer low equivalent series
resistance (ESR) and inductance (ESL) characteristics for power-supply decoupling purposes. For very sensitive
systems, or for systems in harsh noise environments, avoiding the use of vias for connecting the capacitors to
the device pins may offer superior noise immunity. The use of multiple vias in parallel lowers the overall
inductance and is beneficial for connections to ground planes.
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11 Layout
11.1 Layout Guidelines
11.1.1 Layout Information
When a PCB trace turns a corner at a 90° angle, a reflection can occur. A reflection occurs primarily because of
the change of width of the trace. At the apex of the turn, the trace width increases to 1.414 times the width. This
increase upsets the transmission-line characteristics, especially the distributed capacitance and self–inductance
of the trace which results in the reflection. Not all PCB traces can be straight and therefore some traces must
turn corners. Figure 20 shows progressively better techniques of rounding corners. Only the last example (BEST)
maintains constant trace width and minimizes reflections.
BETTER
BEST
2W
WORST
1W min.
W
Figure 20. Trace Example
Route high-speed signals using a minimum of vias and corners which reduces signal reflections and
impedance changes. When a via must be used, increase the clearance size around it to minimize its
capacitance. Each via introduces discontinuities in the signal’s transmission line and increases the chance of
picking up interference from the other layers of the board. Be careful when designing test points, throughhole pins are not recommended at high frequencies.
Figure 21 illustrates an example of a PCB layout with the TMUX1208. Some key considerations are:
•
•
•
•
Decouple the VDD pin with a 0.1-µF capacitor, placed as close to the pin as possible. Make sure that the
capacitor voltage rating is sufficient for the VDD supply.
Keep the input lines as short as possible.
Use a solid ground plane to help reduce electromagnetic interference (EMI) noise pickup.
Do not run sensitive analog traces in parallel with digital traces. Avoid crossing digital and analog traces if
possible, and only make perpendicular crossings when necessary.
11.2 Layout Example
Via to
grou nd plane
A0
A1
EN
A2
N.C.
S1
Via to
grou nd plane
S2
S3
GND
C
Wide (low inductance)
trace for power
VDD
S5
TMUX120 8
S6
S4
S7
D
S8
Figure 21. TMUX1208 Layout Example
24
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12 Device and Documentation Support
12.1 Documentation Support
12.1.1 Related Documentation
Texas Instruments, Simplifying Design with 1.8 V logic Muxes and Switches.
Texas Instruments, QFN/SON PCB Attachment.
Texas Instruments, Quad Flatpack No-Lead Logic Packages.
12.2 Related Links
The table below lists quick access links. Categories include technical documents, support and community
resources, tools and software, and quick access to order now.
Table 4. Related Links
PARTS
PRODUCT FOLDER
ORDER NOW
TECHNICAL
DOCUMENTS
TOOLS &
SOFTWARE
SUPPORT &
COMMUNITY
TMUX1208
Click here
Click here
Click here
Click here
Click here
TMUX1209
Click here
Click here
Click here
Click here
Click here
12.3 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper
right corner, click on Alert me to register and receive a weekly digest of any product information that has
changed. For change details, review the revision history included in any revised document.
12.4 Community Resources
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
12.5 Trademarks
E2E is a trademark of Texas Instruments.
12.6 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
12.7 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
13 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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PACKAGE OPTION ADDENDUM
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10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
(4/5)
(6)
TMUX1208PWR
ACTIVE
TSSOP
PW
16
2000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
TM1208
TMUX1208RSVR
ACTIVE
UQFN
RSV
16
3000
RoHS & Green
NIPDAUAG
Level-1-260C-UNLIM
-40 to 125
1B4
TMUX1209PWR
ACTIVE
TSSOP
PW
16
2000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
TM1209
TMUX1209RSVR
ACTIVE
UQFN
RSV
16
3000
RoHS & Green
NIPDAUAG
Level-1-260C-UNLIM
-40 to 125
1D2
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of
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