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TMUX1511
SCDS390A – SEPTEMBER 2018 – REVISED DECEMBER 2018
TMUX1511 Low-Capacitance, 1:1 (SPST) 4-Channel,
Powered-Off Protected Switch with 1.8 V Logic
1 Features
3 Description
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The TMUX1511 is a complementary metal-oxide
semiconductor (CMOS) switch. The TMUX1511
offers 1:1 SPST switch configuration with 4
independently controlled channels. Wide operating
supply of 1.5 V to 5.5 V allows for use in a broad
array of applications from servers and communication
equipment to industrial applications. The device
supports bidirectional analog and digital signals on
the source (Sx) and drain (Dx) pins and can pass
signals above supply up to VDD x 2, with a maximum
input/output voltage of 5.5 V.
1
Wide Supply Range: 1.5 V to 5.5 V
Low On-Capacitance: 3.3 pF
Low On-Resistance: 2 Ω
High Bandwidth: 3 GHz
-40°C to +125°C Operating Temperature
1.8 V Logic Compatible
Supports Input Voltage Beyond Supply
Integrated Pull Down Resistor on Logic Pins
Bidirectional Signal Path
Fail-Safe Logic
Powered-off Protection up to 3.6 V
– Pinout compatible to SN74CBTLV3126
– Pinout compatible (logic variant) of
SN74CBTLV3125
Fail-Safe Logic circuitry allows voltages on the logic
control pins to be applied before the supply pin,
protecting the device from potential damage. All logic
control inputs have 1.8 V logic compatible thresholds,
ensuring both TTL and CMOS logic compatibility
when operating in the valid supply voltage range.
2 Applications
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Powered-off Protection up to 3.6 V on the signal path
of the TMUX1511 provides isolation when the supply
voltage is removed (VDD = 0 V). Without this
protection feature, switches can back-power the
supply rail through an internal ESD diode and cause
potential damage to the system.
Servers
Wired Networking
Wireless Infrastructure
Data Center Switches & Routers
PC/Notebooks
Building Automation
ePOS
Motor Drives
Appliances
Battery-Powered Equipment
JTAG Isolation
SPI Isolation
Device Information(1)
PART NUMBER
TMUX1511
TCK / SCLK / GPIO
TMS / SS / GPIO
2.60 mm x 1.80 mm
VI/O
TMUX1511
0.1µF
Processor
JTAG, SPI, GPIO
Port
TDO / MOSI / GPIO
QFN (16)
Block Diagram
VDD
TDI / MIS O / GPIO
BODY SIZE (NOM)
5.00 mm × 4.40 mm
(1) For all available packages, see the package option addendum
at the end of the data sheet.
Application Example
VDD
PACKAGE
TSSOP (14)
SEL1
SEL4
S1
S4
D1
D4
FLASH
S1
D1
S2
D2
S3
D3
S4
D4
SEL1
SEL2
SEL3
SEL4
GND
JTA G
DEBUG,
SPI, GPIO
RAM
SEL2
CPU
1.8V Logic
I/O
SEL3
S2
S3
D2
D3
Per ipheral s
GND
*Internal 6MO Pull-Down on Logic Pins
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
TMUX1511
SCDS390A – SEPTEMBER 2018 – REVISED DECEMBER 2018
www.ti.com
Table of Contents
1
2
3
4
5
6
7
Features ..................................................................
Applications ...........................................................
Description .............................................................
Revision History.....................................................
Pin Configuration and Functions .........................
Specifications.........................................................
1
1
1
2
3
4
6.1
6.2
6.3
6.4
6.5
6.6
6.7
6.8
4
4
4
4
5
6
6
7
Absolute Maximum Ratings ......................................
ESD Ratings..............................................................
Recommended Operating Conditions.......................
Thermal Information ..................................................
Electrical Characteristics...........................................
Dynamic Characteristics ...........................................
Timing Requirements ................................................
Typical Characteristics ..............................................
Parameter Measurement Information ................ 12
7.1
7.2
7.3
7.4
7.5
7.6
7.7
7.8
7.9
7.10
On-Resistance ........................................................
Off-Leakage Current ...............................................
On-Leakage Current ...............................................
IPOFF Leakage Current..........................................
Transition Time .......................................................
TON (VDD) and TOFF (VDD) Time ................................
Propagation Delay...................................................
Skew .......................................................................
Charge Injection ......................................................
Capacitance ..........................................................
12
12
13
13
14
14
15
15
16
16
7.11 Off Isolation ........................................................... 17
7.12 Channel-to-Channel Crosstalk .............................. 17
7.13 Bandwidth ............................................................. 18
8
Detailed Description ............................................ 19
8.1
8.2
8.3
8.4
8.5
9
Overview .................................................................
Functional Block Diagram .......................................
Feature Description.................................................
Device Functional Modes........................................
Truth Tables ............................................................
19
19
19
20
20
Application and Implementation ........................ 21
9.1 Application Information............................................ 21
9.2 Typical Application ................................................. 21
10 Power Supply Recommendations ..................... 23
11 Layout................................................................... 24
11.1 Layout Guidelines ................................................. 24
11.2 Layout Example .................................................... 25
12 Device and Documentation Support ................. 26
12.1
12.2
12.3
12.4
12.5
12.6
Documentation Support ........................................
Receiving Notification of Documentation Updates
Community Resources..........................................
Trademarks ...........................................................
Electrostatic Discharge Caution ............................
Glossary ................................................................
26
26
26
26
26
26
13 Mechanical, Packaging, and Orderable
Information ........................................................... 26
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Original (September 2018) to Revision A
•
2
Page
Changed the data sheet status From: Advanced Information To Production data ............................................................... 1
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SCDS390A – SEPTEMBER 2018 – REVISED DECEMBER 2018
5 Pin Configuration and Functions
PW Package
14-Pin TSSOP
Top View
D1
3
12
S4
SEL2
4
11
D4
S2
5
10
SEL3
D2
6
9
S3
GND
7
8
D3
SEL1
1
D4
SEL4
13
13
12
N.C.
11
SEL3
D1
3
10
S3
SEL2
4
9
D3
6
2
5
S1
8
2
S4
S1
14
VDD
7
14
SEL4
1
16
SEL1
15
VDD
RSV Package
16-Pin QFN
Top View
GND
N.C.
D2
S2
Not to scale
Not to scale
Pin Functions
PIN
TYPE (1)
DESCRIPTION
NAME
TSSOP
UQFN
SEL1
1
1
I
S1
2
2
I/O
Source pin 1. Can be an input or output.
D1
3
3
I/O
Drain pin 1. Can be an input or output.
SEL2
4
4
I
S2
5
5
I/O
Source pin 2. Can be an input or output.
D2
6
6
I/O
Drain pin 2. Can be an input or output.
N.C.
-
7
Not Connected
GND
7
8
P
D3
8
9
I/O
Drain pin 3. Can be an input or output.
S3
9
10
I/O
Source pin 3. Can be an input or output.
SEL3
10
11
I
N.C.
Select pin 1: controls state of switch #1 (logic low = OFF, logic high = ON). Internal 6 MΩ
pull-down to GND.
Select pin 2: controls state of switch #2 (logic low = OFF, logic high = ON). Internal 6 MΩ
pull-down to GND.
Not Connected - Can be shorted to GND or left floating
Ground (0 V) reference
Select pin 3: controls state of switch #3 (logic low = OFF, logic high = ON). Internal 6 MΩ
pull-down to GND.
-
12
Not Connected
D4
11
13
I/O
Drain pin 4. Can be an input or output.
S4
12
14
I/O
Source pin 4. Can be an input or output.
SEL4
13
15
I
Select pin 4: controls state of switch #4 (logic low = OFF, logic high = ON). Internal 6 MΩ
pull-down to GND.
VDD
14
16
P
Positive power supply. This pin is the most positive power-supply potential. For reliable
operation, connect a decoupling capacitor ranging from 0.1 µF to 10 µF between VDD and
GND.
(1)
Not Connected - Can be shorted to GND or left floating
I = input, O = output, I/O = input and output, P = power
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SCDS390A – SEPTEMBER 2018 – REVISED DECEMBER 2018
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6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted) (1)
(2) (3)
MIN
MAX
VDD
Supply voltage
–0.5
6
VSEL
Logic control input pin voltage (SEL1, SEL2, SEL3, SEL4)
–0.5
6
V
ISEL
Logic control input pin current (SEL1, SEL2, SEL3, SEL4)
–30
30
mA
VS or VD
Source or drain pin voltage
–0.5
6
V
IS or ID (CONT)
Source and drain pin continuous current: (S1 to S4, D1 to D4)
–25
25
mA
Tstg
Storage temperature
–65
150
°C
TJ
Junction temperature
150
°C
(1)
(2)
(3)
UNIT
V
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
The algebraic convention, whereby the most negative value is a minimum and the most positive value is a maximum.
All voltages are with respect to ground, unless otherwise specified.
6.2 ESD Ratings
VALUE
V(ESD)
(1)
(2)
Electrostatic discharge
Human body model (HBM), per
ANSI/ESDA/JEDEC JS-001 (1)
±2000
Charged-device model (CDM), per JEDEC
specification JESD22-C101 (2)
±750
UNIT
V
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
6.3 Recommended Operating Conditions
VDD
Supply voltage
(1)
MIN
MAX
1.5
5.5
UNIT
V
VS or VD
Signal path input/output voltage (source or drain pin), VDD ≥ 1.5 V
0
VDD x 2
V
VS_off or VD_off
Signal path input/output voltage (source or drain pin), VDD < 1.5 V (2)
0
3.6
V
VSEL
Logic control input voltage (SELx)
0
5.5
V
TA
Ambient temperature
–40
125
ºC
(1)
(2)
Device input/output can operate up to VDD x 2, with a maximum input/output voltage of 5.5 V.
VS_off and VD_off refers to the voltage at the source or drain pins when supply is less than 1.5 V
6.4 Thermal Information
THERMAL METRIC (1)
DEVICE
DEVICE
PW (TSSOP)
RSV (UQFN)
UNIT
14 PINS
16 PINS
RθJA
Junction-to-ambient thermal resistance
129.4
141.5
°C/W
RθJC(top)
Junction-to-case (top) thermal resistance
58.8
77.9
°C/W
RθJB
Junction-to-board thermal resistance
72.4
67.6
°C/W
ΨJT
Junction-to-top characterization parameter
11.6
5.1
°C/W
ΨJB
Junction-to-board characterization parameter
71.9
65.5
°C/W
RθJC(bot)
Junction-to-case (bottom) thermal resistance
N/A
N/A
°C/W
(1)
4
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
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SCDS390A – SEPTEMBER 2018 – REVISED DECEMBER 2018
6.5 Electrical Characteristics
VDD = 1.5 V to 5.5 V, GND = 0 V, TA = –40°C to +125°C,
Typical values are at VDD = 3.3 V, TA = 25°C, (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
POWER SUPPLY
VDD
IDD
Power supply voltage
Supply current
1.5
VSEL = 0 V, 1.4 V or VDD
VS = 0 V to 5.5 V
5.5
V
37
70
μA
2
4.5
Ω
DC CHARACTERISTICS
RON
On-resistance
VS = 0 V to VDD*2
VS(max) = 5.5 V
ISD = 8 mA
Refer to ON-State Resistance Figure
ΔRON
On-resistance match between channels
VS = VDD
ISD = 8 mA
Refer to ON-State Resistance Figure
0.07
0.28
Ω
RON
On-resistance flatness
VS = 0 V to VDD
ISD = 8 mA
Refer to ON-State Resistance Figure
1
1.8
Ω
Powered-off I/O pin leakage current
VDD = 0 V
VS = 0 V to 3 V
VD = 0 V
TA = 25℃
Refer to Ipoff Leakage Figure
–10
0.01
10
nA
Powered-off I/O pin leakage current
VDD = 0 V
VS = 0 V to 3.6 V
VD = 0 V
Refer to Ipoff Leakage Figure
–2
0.01
2
µA
OFF leakage current
Switch Off
VD = 0.8*VDD / 0.2*VDD
VS = 0.2*VDD / 0.8*VDD
Refer to Off Leakage Figure
–100
0.03
100
nA
ON leakage current
Switch On
VD = 0.8*VDD / 0.2*VDD, S pins floating
or
VS = 0.8*VDD / 0.2*VDD, D pins floating
Refer to On Leakage Figure
–50
0.01
50
nA
1.2
5.5
V
0
0.45
V
1
±2
μA
0.2
±2
μA
(FLAT)
IPOFF
IPOFF
IS(OFF)
ID(OFF)
ID(ON)
IS(ON)
LOGIC INPUTS
VIH
Input logic high
VIL
Input logic low
IIH
Input high leakage current
VSEL = 1.8 V, VDD
IIL
Input low leakage current
VSEL = 0 V
RPD
Internal pull-down resistor on logic input
pins
CI
Logic input capacitance
VSEL = 0 V, 1.8 V or VDD
f = 1 MHz
6
MΩ
3
pF
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6.6 Dynamic Characteristics
VDD = 1.5 V to 5.5 V, GND = 0 V, TA = –40°C to +125°C,
Typical values are at VDD = 3.3 V, TA = 25°C, (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Source and drain off capacitance
VS = VDD / 2
VSEL= 0 V
f = 1 MHz
Refer to Capacitance Figure
Switch
OFF
2.5
4
pF
CON
Source and drain on capacitance
VS = VDD / 2
VSEL = VDD
f = 1 MHz
Refer to Capacitance Figure
Switch
ON
3.3
6
pF
QC
Charge Injection
VS = VDD / 2
RS = 0 Ω, CL = 100 pF
Refer to Charge Injection Figure
Switch
ON
2
pC
RL = 50 Ω
f = 100 kHz
Refer to Off Isolation Figure
Switch
OFF
–90
dB
RL = 50 Ω
f = 1 MHz
Refer to Off Isolation Figure
Switch
OFF
–75
dB
dB
COFF
OISO
Off isolation
XTALK
Channel to Channel crosstalk
RL = 50 Ω
f = 100 kHz
Refer to Crosstalk Figure
Switch
ON
–90
BW
Bandwidth
RL = 50 Ω
Refer to Bandwidth Figure
Switch
ON
3
ILOSS
Insertion loss
RL = 50 Ω
f = 1 MHz
Refer to Bandwidth Figure
Switch
ON
–0.12
GHz
dB
6.7 Timing Requirements
VDD = 1.5 V to 5.5 V, GND = 0 V, TA = –40°C to +125°C,
Typical values are at VDD = 3.3 V, TA = 25°C, (unless otherwise noted)
PARAMETER
TYP
MAX
Device turn on time (VDD to output)
VS = 3.6 V
VDD rise time = 1us
RL = 200 Ω, CL = 15pF
Refer to Ton(vdd) & Toff(vdd) Figure
20
60
µs
Device turn off time (VDD to output)
VS = 3.6 V
VDD fall time = 1us
RL = 200 Ω, CL = 15pF
Refer to Ton(vdd) & Toff(vdd) Figure
1.2
4
µs
Transition time from control input
VDD = 2.5 V to 5.5 V
VS = VDD
RL = 200 Ω, CL = 15pF
Refer to Transition Time Figure
25
55
ns
tTRAN
Transition time from control input
VDD < 2.5 V
VS = VDD
RL = 200 Ω, CL = 15pF
Refer to Transition Time Figure
50
80
ns
tSK(P)
Inter - channel skew
Refer to Tsk Figure
10
ps
tPD
Propagation delay
Refer to Tpd Figure
67
ps
tON(VDD)
tOFF(VDD)
tTRAN
6
TEST CONDITIONS
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MIN
UNIT
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6.8 Typical Characteristics
5
5
4
4
On Resistance (:)
On Resistance (:)
at TA = 25°C, VDD = 5 V (unless otherwise noted)
3
VDD = 1.5 V
VDD = 5.5 V
2
1
3
2
1
VDD = 3.3 V
0
0
1
2
3
4
Source or Drain Voltage (V)
5
5.5
0
1
2
3
4
Source or Drain Voltage (V)
D001
TA = 25°C
5.5
D002
Figure 2. On-Resistance vs Source or Drain Voltage
4
3
3
On Resistance (:)
4
TA = 85qC
5
VDD = 5.5 V
Figure 1. On-Resistance vs Source or Drain Voltage
On Resistance (:)
TA = 25qC
TA = -40qC
0
TA = 125qC
2
1
TA = 85qC
TA = 125qC
2
1
TA = 25qC
TA = -40qC
TA = 25qC
TA = -40qC
0
0
0
0.5
1
1.5
2
2.5
Source or Drain Voltage (V)
3
3.5
0
0.5
1
Source or Drain Voltage (V)
D003
VDD = 3.3 V
1.5
D004
VDD = 1.5 V
Figure 3. On-Resistance vs Source or Drain Voltage
Figure 4. On-Resistance vs Source or Drain Voltage
60
70
TA = 125qC
65
55
60
55
Supply Current (PA)
Supply Current (PA)
TA = 125qC
TA = 85qC
VDD = 3.3 V
50
VDD = 5.5 V
45
40
TA = 85qC
50
45
TA = 25qC
40
35
35
VDD = 1.5 V
TA = -40qC
30
0
0.5
1
1.5
2
2.5 3 3.5
Logic Voltage (V)
4
4.5
5
5.5
30
1.5
2
D005
2.5
3
3.5
4
4.5
Supply Voltage (V)
5
5.5
TA = 25°C
Figure 5. Supply Current vs Logic Voltage
6
D006
Figure 6. Supply Current vs Supply Voltage
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Typical Characteristics (continued)
10
30
VDD = 5.5 V
VDD = 3.3 V
VDD = 1.5 V
8
6
25
VDD = 5.5 V
On Leakage (pA)
On Leakage (pA)
4
2
0
-2
20
15
10
-4
VDD = 3.3 V
VDD = 1.5 V
-6
5
-8
0
-50
-10
0
0.5
1
1.5 2
2.5 3
3.5 4
Source or Drain Voltage (V)
4.5
5
5.5
-25
0
25
50
75
Temperature (qC)
100
125
150
D008
D007
TA = 25°C
Figure 8. On-Leakage vs Temperature
Figure 7. On-Leakage vs Source or Drain Voltage
0.1
0.9
VDD = 5.5 V
VDD = 3.3 V
VDD = 1.5 V
0.8
0.7
Off Leakage (nA)
Off Leakage (nA)
0.05
0
-0.05
-0.1
2
3
Source or Drain Voltage (V)
4
0.4
0.3
0.2
0
-0.1
-40
-0.15
1
0.5
0.1
VDD = 5.5 V
VDD = 3.3 V
VDD = 1.5 V
0
0.6
5
-20
0
20
40
60
80
Temperature (qC)
100
120
140
D010
D009
TA = 25°C
Figure 10. Off-Leakage vs Temperature
Figure 9. Off-Leakage vs Source or Drain Voltage
1
10
0.9
8
IPOFF Leakage (nA)
0.8
IPOFF (nA)
0.7
0.6
0.5
0.4
0.3
0.2
6
4
2
0
0.1
0
0
0.5
1
1.5
2
2.5
3
Source or Drain Voltage (V)
3.5
4
-2
-40
-30
D011
TA = 25°C
-10
0
10
20
30
Temperature (qC)
40
50
60
D012
VSource = 3 V
Figure 11. IPOFF Leakage vs Source or Drain Voltage
8
-20
Figure 12. IPOFF Leakage vs Temperature
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Typical Characteristics (continued)
700
600
IPOFF Leakage (nA)
500
400
300
200
100
0
-100
-40
-20
0
20
40
60
80
Temperature (qC)
100
120
140
D013
TA = 25°C
RL= 200 Ω
VSource = 3.6 V
VDrain = 0 V
Figure 14. IPOFF Leakage vs Source or Drain Voltage
Figure 13. IPOFF Leakage vs Temperature
25
50
Transiton_Rising
Transiton_Falling
40
Transition Time (nS)
Transition Time (nS)
45
35
30
25
20
20
15
10
15
Transiton_Rising
Transiton_Falling
10
1.5
2
2.5
3
3.5
4
4.5
Supply Voltage (V)
5
5.5
5
-40
6
-20
0
20
D015
TA = 25°C
40
60
80
Temperature (qC)
100
120
140
D016
VDD = 5.5 V
Figure 15. TTRANSITION vs Supply Voltage
Figure 16. TTRANSITION vs Temperature
22.5
70
20
60
Propagation Delay
17.5
50
12.5
Time (pS)
Time (PS)
15
TON(VDD)
TOFF(VDD)
10
40
30
Skew
7.5
20
5
10
2.5
0
1.5
2
2.5
3
3.5
4
4.5
Supply Voltage (V)
5
5.5
6
0
1.5
2
D017
3
3.5
4
4.5
Supply Voltage (V)
5
5.5
6
D018
TA = 25°C
TA = 25°C
Figure 17. TON (VDD) and TOFF (VDD) vs Supply Voltage
2.5
Figure 18. Skew and Propagation Delay vs Supply Voltage
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Typical Characteristics (continued)
8
10
COFF
CON
9
VDD = 5.5 V
6
7
6
Capacitance (pF)
Charge Injection (pC)
8
VDD = 3.3 V
5
4
VDD = 1.5 V
3
4
2
2
1
0
1M
0
0
1
2
3
4
Source Voltage (V)
5
6
10M
D019
TA = 25°C
100M
Frequency (Hz)
1G
D020
TA = 25°C
Figure 19. Charge Injection vs Source or Drain Voltage
Figure 20. Capacitance vs Frequency
0
0
-10
-1
-30
Attenuation (dB)
Off Isolation (dB)
-20
-40
-50
-60
-70
-80
-2
-3
-4
-5
-90
-100
-6
1M
10M
100M
Frequency (Hz)
1G
1M
D021
TA = 25°C
Figure 21. Off Isolation vs Frequency
10M
100M
Frequency (Hz)
1G
D022
TA = 25°C
VDD = 1.5 V to 5.5 V
Figure 22. On-Response vs Frequency
10
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6.8.1 Eye Diagrams
TA = 25°C
Bias = 1.5 V
50 Ω Termination
TA = 25°C
Bias = 1.5 V
50 Ω Termination
Figure 23. Eye Pattern: 2.4 Gbps
Figure 24. Eye Pattern: 2.4 Gbps Through Path
TA = 25°C
Bias = 1.5 V
50 Ω Termination
TA = 25°C
Bias = 1.5 V
50 Ω Termination
Figure 25. Eye Pattern: 3 Gbps
Figure 26. Eye Pattern: 3 Gbps Through Path
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7 Parameter Measurement Information
7.1 On-Resistance
The on-resistance of a device is the ohmic resistance between the source (Sx) and drain (Dx) pins of the device.
The on-resistance varies with input voltage and supply voltage. The symbol RON is used to denote on-resistance.
The measurement setup used to measure RON is shown in Figure 27 . Voltage (V) and current (IDS) are
measured using this setup, and RON is computed as shown below with RON = V / ISD:
V
ISD
Sx
Dx
VS
Figure 27. On-Resistance Measurement Setup
7.2 Off-Leakage Current
Source off-leakage current is defined as the leakage current flowing into or out of the source pin when the switch
is off. This current is denoted by the symbol IS(OFF).
Drain off-leakage current is defined as the leakage current flowing into or out of the drain pin when the switch is
off. This current is denoted by the symbol ID(OFF).
The setup used to measure both off-leakage currents is shown in Figure 28.
VDD
VDD
VDD
D1
S1
A
A
VD
VS
D1
VD
IS (OFF)
A
A
VD
VS
S1
VS
ID (OFF)
D4
S4
VDD
IS (OFF)
ID (OFF)
S4
D4
VS
VD
GND
GND
Figure 28. Off-Leakage Measurement Setup
12
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7.3 On-Leakage Current
Source on-leakage current is defined as the leakage current flowing into or out of the source pin when the switch
is on. This current is denoted by the symbol IS(ON).
Drain on-leakage current is defined as the leakage current flowing into or out of the drain pin when the switch is
on. This current is denoted by the symbol ID(ON).
Either the source pin or drain pin is left floating during the measurement. Figure 29 shows the circuit used for
measuring the on-leakage current, denoted by IS(ON) or ID(ON).
VDD
VDD
VDD
N.C.
A
A
S4
D1
S4
D4
N.C.
IS (ON)
ID (ON)
N.C.
S1
VS
VD
D4
VDD
IS (ON)
ID (ON)
D1
S1
A
A
VD
N.C.
VS
GND
GND
Figure 29. On-Leakage Measurement Setup
7.4 IPOFF Leakage Current
IPOFF leakage current is defined as the leakage current flowing into or out of the source pin when the device is
powered off. This current is denoted by the symbol IPOFF.
The setup used to measure both IPOFF leakage current is shown in Figure 30.
VDD = 0 V
VDD
IPOFF
A
S1
D1
VD
VS
IPOFF
A
S4
D4
VS
VD
GND
Figure 30. IPOFF Leakage Measurement Setup
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7.5 Transition Time
Transition time is defined as the time taken by the output of the device to rise or fall 10% after the control select
signal has risen or fallen past the logic threshold. The 10% transition measurement is utilized to provide the
timing of the device. The time constant from the load resistance and load capacitance can be added to the
transition time to calculate system level timing. Figure 31 shows the setup used to measure transition time,
denoted by the symbol tTRANSITION.
VDD
0.1 F
VDD
ADDRESS
DRIVE
(VSEL)
VDD
tf < 5ns
tr < 5ns
VIH
VIL
0V
VS
S1
D1
OUTPUT
RL
CL
tTRANSITION
tTRANSITION
VS
S4
D4
90%
OUTPUT
RL
CL
SEL1 - SEL4
OUTPUT
10%
VSEL
GND
0V
Figure 31. Transition-Time Measurement Setup
7.6 TON (VDD) and TOFF (VDD) Time
TON (VDD) time is defined as the time taken by the output of the device to rise to 90% after the supply has risen
past the supply threshold. The 90% measurement is utilized to provide the timing of the device turning on in the
system. The time constant from the load resistance and load capacitance can be added to the turn-on-VDD time
to calculate system level timing. Figure 32 shows the setup used to measure transition time, denoted by the
symbol tON (VDD).
TOFF (VDD) time is defined as the time taken by the output of the device to fall to 90% after the enable has fallen
past the supply threshold. The 90% measurement is utilized to provide the timing of the device turning off in the
system. The time constant from the load resistance and load capacitance can be added to the turn-off-VDD time
to calculate system level timing. Figure 32 shows the setup used to measure transition time, denoted by the
symbol tOFF (VDD).
VDD
0.1 F
VDD
VDD
VDD
Supply
Ramp
(VDD)
1.5 V
1.5 V
VS
S1
D1
0V
OUTPUT
RL
CL
tOFF (VDD)
tON (VDD)
90%
90%
VS
OUTPUT
S4
D4
OUTPUT
RL
VDD
0V
CL
SEL1 - SEL4
GND
Figure 32. Turn-On-VDD and Turn-Off-VDD Time Measurement Setup
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7.7 Propagation Delay
Propagation delay is defined as the time taken by the output of the device to rise or fall 50% after the input signal
has risen or fallen past the 50% threshold. Figure 33 shows the setup used to measure propagation delay,
denoted by the symbol tPD.
VDD
0.1 F
VDD
250 mV
Input
(VS)
50%
50%
S1
VS
D1
0V
RL
50
tPD 1
tPD 2
S4
VS
Output
OUTPUT
50%
D4
OUTPUT
RL
50
50%
0V
GND
tProp D el ay = max ( tPD 1, tPD 2)
Figure 33. Propagation Delay Measurement Setup
7.8 Skew
Skew is defined as the difference between propagation delays of any two outputs of the same device. The skew
measurement is taken from the output of one channel rising or falling past 50% to a second channel rising or
falling past the 50% threshold when the input signals are switched at the same time. Figure 34 shows the setup
used to measure skew, denoted by the symbol tSK.
VDD
0.1 F
VDD
Output 1
50%
50%
VS
S1
D1
0V
RL
50
tSK 1
tSK 2
VS
Output 2
OUTPUT
50%
S4
D4
OUTPUT
RL
50
50%
0V
tSKEW = max ( tSK 1, tSK 2)
GND
Figure 34. Skew Measurement Setup
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7.9 Charge Injection
The amount of charge injected into the source or drain of the device during the falling or rising edge of the gate
signal is known as charge injection, and is denoted by the symbol QC. Figure 35 shows the setup used to
measure charge injection from source (Sx) to drain (Dx).
VDD
0.1 F
VDD
VDD
VSEL
S1
VS
D1
OUTPUT
VOUT
0V
CL
Output
VOUT
VS
QC = CL ×
VOUT
S4
VS
D4
OUTPUT
SEL1 - SEL4
VSEL
VOUT
CL
GND
Figure 35. Charge-Injection Measurement Setup
7.10 Capacitance
The parasitic capacitance of the device is captured at the source (Sx), drain (Dx), and select (SELx) pins. The
capacitance is measured in both the on and off state and is denoted by the symbol CON and COFF. Figure 36
shows the setup used to measure capacitance.
VDD
VDD
SEL1
S1
1 MHz
Capacitance
Meter
Capacitance is measured at SX, DX,
and SELX pins during ON and OFF
conditions
D1
SEL4
S4
D4
GND
Figure 36. Capacitance Measurement Setup
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7.11 Off Isolation
Off isolation is defined as the ratio of the signal at the drain pin (Dx) of the device when a signal is applied to the
source pin (Sx) of an off-channel. The characteristic impedance, Z0, for the measurement is 50 Ω. Figure 37
shows the setup used to measure off isolation. Use off isolation equation to compute off isolation.
0.1µF
NETWORK
VDD
ANALYZER
VS
50Ÿ
S
VSIG
D
VOUT
RL
50Ÿ
SX/DX
GND
RL
50Ÿ
Figure 37. Off Isolation Measurement Setup
Off Isolation
§V
·
20 ˜ Log ¨ OUT ¸
© VS ¹
(1)
7.12 Channel-to-Channel Crosstalk
Crosstalk is defined as the ratio of the signal at the drain pin (Dx) of a different channel, when a signal is applied
at the source pin (Sx) of an on-channel. The characteristic impedance, Z0, for the measurement is 50 Ω.
Figure 38 shows the setup used to measure, and the equation used to compute crosstalk.
VDD
0.1µF
NETWORK
VDD
ANALYZER
VOUT
S1
D1
S2
D2
RL
50Ÿ
RL
50Ÿ
VS
RL
50Ÿ
50Ÿ
SX / D X
VSIG = 200 mVpp
VBIAS = VDD / 2
RL
50Ÿ
GND
Figure 38. Channel-to-Channel Crosstalk Measurement Setup
Channel-to-Channel Crosstalk
§V
·
20 ˜ Log ¨ OUT ¸
V
© S ¹
(2)
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7.13 Bandwidth
Bandwidth is defined as the range of frequencies that are attenuated by less than 3 dB when the input is applied
to the source pin (Sx) of an on-channel, and the output is measured at the drain pin (Dx) of the device. The
characteristic impedance, Z0, for the measurement is 50 Ω. Figure 39 shows the setup used to measure
bandwidth.
VDD
0.1µF
NETWORK
VDD
VS
ANALYZER
50Ÿ
S
VSIG
D
VOUT
RL
50Ÿ
GND
Figure 39. Bandwidth Measurement Setup
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8 Detailed Description
8.1 Overview
The TMUX1511 is a high speed 1:1 (SPST) 4-channel switch with powered-off protection up to 3.6 V. Wide
operating supply of 1.5 V to 5.5 V allows for use in a broad array of applications from servers and
communication equipment to industrial applications. The device supports bidirectional analog and digital
signals on the source (Sx) and drain (Dx) pins. The wide bandwidth of this switch allows little or no
attenuation of the high-speed signals at the outputs to pass with minimum edge and phase distortion as well
as propagation delay.
The select (SELx) pins are active-high logic pins that control the connection between the source (Sx) and
drain (Dx) pins of the device. Each channel of the TMUX1511 can be controlled independently through the
associated select pin, or all four select pins can be tied together for simultaneous control of all channels with
a single GPIO. Fail-Safe Logic circuitry allows voltages on the logic control pins to be applied before the
supply pin, protecting the device from potential damage. All logic control inputs have 1.8V logic compatible
thresholds, ensuring both TTL and CMOS logic compatibility when operating in the valid supply voltage
range.
Powered-off protection up to 3.6 V on the signal path of the TMUX1511 provides isolation when the supply
voltage is removed (VDD = 0 V). Without this protection feature, the system can back-power the supply rail
through an internal ESD diode and cause potential damage to the system.
8.2 Functional Block Diagram
TMUX1511
SEL1
SEL4
S1
S4
D1
D4
SEL2
SEL3
S2
S3
D2
D3
*Internal 6MO Pull-Down on Logic Pins
8.3 Feature Description
8.3.1 Bidirectional Operation
The TMUX1511 conducts equally well from source (Sx) to drain (Dx) or from drain (Dx) to source (Sx). Each
channel has very similar characteristics in both directions and supports both analog and digital signals.
8.3.2 Beyond Supply Operation
When the TMUX1511 is powered from 1.5 V to 5.5 V, the valid signal path input/output voltage ranges from
GND to VDD x 2, with a maximum input/output voltage of 5.5 V.
Example 1: If the TMUX1511 is powered at 1.5V, the signal range is 0 V to 3 V.
Example 2: If the TMUX1511 is powered at 3V, the signal range is 0 V to 5.5 V.
Example 3: If the TMUX1511 is powered at 5.5V, the signal range is 0 V to 5.5 V.
Other voltage levels not mentioned in the examples will support Beyond Supply Operation as long as the supply
voltage falls within the recommended operation conditions of 1.5 V to 5.5 V.
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Feature Description (continued)
8.3.3 1.8 V Logic Compatible Inputs
The TMUX1511 has 1.8-V logic compatible control inputs. Regardless of the VDD voltage, the control input
thresholds remain fixed, allowing a 1.8-V processor GPIO to control the TMUX1511 without the need for an
external translator. This saves both space and BOM cost. For more information on 1.8 V logic implementations
refer to Simplifying Design with 1.8 V logic Muxes and Switches.
8.3.4 Powered-off Protection
Powered-off protection up to 3.6 V on the signal path of the TMUX1511 provides isolation when the supply
voltage is removed (VDD = 0 V). When the TMUX1511 is powered-off, the I/Os of the device remain in a high-Z
state. Powered-off protection minimizes system complexity by removing the need for power supply sequencing
on the signal path. The device performance remains within the leakage performance mentioned in the Electrical
Specifications. For more information on powered-off protection refer to Eliminate Power Sequencing with
Powered-off Protection Signal Switches
8.3.5 Fail-Safe Logic
The TMUX1511 has Fail-Safe Logic on the control input pins (SELx) which allows for operation up to 5.5 V,
regardless of the state of the supply pin. This feature allows voltages on the control pins to be applied before the
supply pin, protecting the device from potential damage. Fail-Safe Logic minimizes system complexity by
removing the need for power supply sequencing on the logic control pins. For example, the Fail-Safe Logic
feature allows the select pins of the TMUX1511 to be ramped to 5.5 V while VDD = 0 V. Additionally, the feature
enables operation of the TMUX1511 with VDD = 1.5 V while allowing the select pins to interface with a logic level
of another device up to 5.5 V.
8.3.6 Low Capacitance
The TMUX1511 has very low capacitance in both the ON and OFF states on the source and drain pins. The low
capacitance specification allows the TMUX1511 to be used in applications such as sample & hold circuits, and in
the feedback path of an operation amplifier. Low capacitance helps to reduce large overshoots and ringing of an
amplifier circuit when the switch is connected to the feedback network. Additionally, low capacitance improves
system settling time by reducing the switch time constant formed by the On-resistance and On-capacitance. For
more information on the benefits of low capacitance refer to Improve Stability Issues with Low CON Multiplexers.
8.3.7 Integrated Pull-Down Resistors
The TMUX1511 has internal weak pull-down resistors (6 MΩ) to GND to ensure the logic pins are not left
floating. This feature integrates up to four external components and reduces system size and cost.
8.4 Device Functional Modes
The select (SELx) pins are active-high logic pins that control the connection between the source (Sx) and drain
(Dx) pins of the device. The TMUX1511 has internal weak pull-down resistors (6 MΩ) to GND so that it powerson with the switches disabled. When a given select pin of the TMUX1511 is pulled high, the corresponding switch
conducts from the source to drain. When any of the select pins are pulled low, the corresponding switch is in an
open state (HI-Z). Each channel of the TMUX1511 can be controlled independently through the associated select
pin, or all four select pins can be tied together for simultaneous control of all channels with a single GPIO.
8.5 Truth Tables
Table 1 shows the truth table for the TMUX1511.
Table 1. TMUX1511 Truth Table
SELx
20
Sx / Dx: STATE
0
Hi-Z (OFF)
1
Conducting (ON)
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9 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
9.1 Application Information
The TMUX15xx family offers high-speed system performance across a wide operating supply (1.5 V to 5.5 V)
and operating temperature (-40°C to +125°C). The TMUX1511 supports a number of features that improve
system performance such as 1.8 V logic compatibility, input voltages beyond supply, Fail-Safe Logic, and
Powered-off Protection up to 3.6 V. These features make the TMUX15xx a family of protection multiplexers and
switches that can reduce system complexity, board size, and overall system cost.
9.2 Typical Application
9.2.1 Protocol / Signal Isolation
One useful application to take advantage of the TMUX1511 features is isolating various protocols from a
possessor or MCU such as JTAG, SPI, or standard GPIO signals. The device provides excellent isolation
performance when the device is powered. The added benefit of powered-off protection allows a system to
minimize complexity by eliminating the need for power sequencing in hot-swap and live insertion applications.
VDD
VDD
0.1µF
Processor
JTAG, SPI, GPIO
Port
TDI / MIS O / GPIO
TDO / MOSI / GPIO
TCK / SCLK / GPIO
TMS / SS / GPIO
VI/O
FLASH
S1
D1
S2
D2
S3
D3
S4
JTA G
DEBUG,
SPI, GPIO
RAM
CPU
D4
SEL1
SEL2
SEL3
SEL4
1.8V Logic
I/O
GND
Per ipheral s
GND
Figure 40. Isolation of JTAG, SPI, and GPIO Signals
9.2.1.1 Design Requirements
For this design example, use the parameters listed in Table 2.
Table 2. Design Parameters
PARAMETERS
VALUES
Supply (VDD)
3.3 V
Input / Output signal range
0 V to 3.3 V
Control logic thresholds
1.8 V compatible
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9.2.1.2 Detailed Design Procedure
The TMUX1511 can be operated without any external components except for the supply decoupling capacitors.
The device has internal weak pull-down resistors (6 MΩ) to GND so that it powers-on with the switches disabled.
All inputs signals passing through the switch must fall within the recommend operating conditions of the
TMUX1511 including signal range and continuous current. For this design example, with a supply of 3.3 V, the
signals can range from 0 V to 3.3 V when the device is powered. This example can also utilize the Powered-off
Protection feature and the inputs can range from 0 V to 3.3 V when VDD = 0 V. The max continuous current can
be 25 mA. Due to the voltage range and high speed capability, the TMUX1511example is suitable for use in
JTAG and SPI applications beyond the 100 MHz maximum in a typical application.
9.2.1.3 Application Curves
Two important specifications when using a switch or multiplexer to pass signals are the device propagation delay
and skew.
70
60
Propagation Delay
Time (pS)
50
40
30
Skew
20
10
0
1.5
2
2.5
3
3.5
4
4.5
Supply Voltage (V)
5
5.5
6
D018
Figure 41. Propagation Delay and Skew Measurement
9.2.2 Transimpedance Amplifier Feedback Control
Switches and multiplexers are commonly used in the feedback path of amplifier circuits to provide configurable
gain control. By using various resistor values on each switch path the TMUX1511 allows the system to have
multiple gain settings. An external resistor, or utilizing 1 channel always being closed, ensures the amplifier isn't
operating in an open loop configuration. A transimpedance amplifier (TIA) for photodiodes is a common circuit
that requires gain control using a multi-channel switch to convert the output current of the photodiode into a
voltage for the MCU or processor. The leakage current, capacitance, and charge injection performance of the
TMUX1511 are key specifications to evaluate when selecting a device for gain control.
0.1µF
VI/O
VDD
VDD
Processor
SEL1
SEL2
SEL3
SEL4
1.8V Logic I/O
RF_1
Digital Processin g
RF_2
RF_3
RF_4
VDD
VDD
IPD
+
OP
AMP
Gai n / Fil ter
Network
ADC
Figure 42. Multiplexing Gain for a TIA Circuit
22
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9.2.2.1 Design Requirements
For this design example, use the parameters listed in Table 3.
Table 3. Design Parameters
PARAMETERS
VALUES
Supply (VDD)
5V
Input / Output signal range
0 µA to 10 µA
Control logic thresholds
1.8 V compatible
9.2.2.2 Detailed Design Procedure
Photodiodes commonly have a current output that ranges from a few hundred picoamps to tens of microamps
based on the amount of light being absorbed. The TMUX1511 has a typical On-leakage current of less than 10
pA which would lead to an accuracy well within 1% of a full scale 10 µA signal. The low ON and OFF
capacitance of the TMUX1511 improves system stability by minimizing the total capacitance on the output of the
amplifier. Lower capacitance leads to less overshoot and ringing in the system which can cause the amplifier
circuit to go unstable if the phase margin is not at least 45°. Refer to Improve Stability Issues with Low CON
Multiplexers for more information on calculating the phase margin vs. percent overshoot.
9.2.2.3 Application Curves
10
8
8
6
Capacitance (pF)
6
On Leakage (pA)
COFF
CON
VDD = 5.5 V
VDD = 3.3 V
VDD = 1.5 V
4
2
0
-2
4
2
-4
-6
0
1M
-8
-10
0
0.5
1
1.5 2
2.5 3
3.5 4
Source or Drain Voltage (V)
4.5
5
5.5
D007
TA = 25°C
10M
100M
Frequency (Hz)
1G
D020
TA = 25°C
Figure 44. Capacitance vs Frequency
Figure 43. On-Leakage vs Source or Drain Voltage
10 Power Supply Recommendations
The TMUX1511 operates across a wide supply range of 1.5 V to 5.5 V. Do not exceed the absolute maximum
ratings because stresses beyond the listed ratings can cause permanent damage to the devices.
Power-supply bypassing improves noise margin and prevents switching noise propagation from the VDD supply to
other components. Good power-supply decoupling is important to achieve optimum performance. For improved
supply noise immunity, use a supply decoupling capacitor ranging from 0.1 μF to 10 μF from VDD to ground.
Place the bypass capacitors as close to the power supply pins of the device as possible using low-impedance
connections. TI recommends using multi-layer ceramic chip capacitors (MLCCs) that offer low equivalent series
resistance (ESR) and inductance (ESL) characteristics for power-supply decoupling purposes. For very sensitive
systems, or for systems in harsh noise environments, avoiding the use of vias for connecting the capacitors to
the device pins may offer superior noise immunity. The use of multiple vias in parallel lowers the overall
inductance and is beneficial for connections to ground planes.
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11 Layout
11.1 Layout Guidelines
When a PCB trace turns a corner at a 90° angle, a reflection can occur. A reflection occurs primarily because of
the change of width of the trace. At the apex of the turn, the trace width increases to 1.414 times the width. This
increase upsets the transmission-line characteristics, especially the distributed capacitance and self–inductance
of the trace which results in the reflection. Not all PCB traces can be straight and therefore some traces must
turn corners. Figure 45 shows progressively better techniques of rounding corners. Only the last example (BEST)
maintains constant trace width and minimizes reflections.
BETTER
BEST
2W
WORST
1W min.
W
Figure 45. Trace Example
Route the high-speed signals using a minimum of vias and corners which reduces signal reflections and
impedance changes. When a via must be used, increase the clearance size around it to minimize its
capacitance. Each via introduces discontinuities in the signal’s transmission line and increases the chance of
picking up interference from the other layers of the board. Be careful when designing test points, throughhole pins are not recommended at high frequencies.
Do not route high speed signal traces under or near crystals, oscillators, clock signal generators, switching
regulators, mounting holes, magnetic devices or ICs that use or duplicate clock signals.
Avoid stubs on the high-speed signals traces because they cause signal reflections.
Route all high-speed signal traces over continuous GND planes, with no interruptions.
Avoid crossing over anti-etch, commonly found with plane splits.
When working with high frequencies, a printed circuit board with at least four layers is recommended; two
signal layers separated by a ground and power layer as shown in Figure 46.
Signal 1
GND Plane
Power Plane
Signal 2
Figure 46. Example Layout
The majority of signal traces must run on a single layer, preferably Signal 1. Immediately next to this layer must
be the GND plane, which is solid with no cuts. Avoid running signal traces across a split in the ground or power
plane. When running across split planes is unavoidable, sufficient decoupling must be used. Minimizing the
number of signal vias reduces EMI by reducing inductance at high frequencies.
Figure 47 illustrates an example of a PCB layout with the TMUX1511. Some key considerations are:
24
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TMUX1511
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SCDS390A – SEPTEMBER 2018 – REVISED DECEMBER 2018
Layout Guidelines (continued)
Decouple the VDD pin with a 0.1-μF capacitor, placed as close to the pin as possible. Make sure that the
capacitor voltage rating is sufficient for the VDD supply.
High-speed switches require proper layout and design procedures for optimum performance.
Keep the input lines as short as possible.
Use a solid ground plane to help reduce electromagnetic interference (EMI) noise pickup.
Do not run sensitive analog traces in parallel with digital traces. Avoid crossing digital and analog traces if
possible, and only make perpendicular crossings when necessary.
11.2 Layout Example
Wide (low inductance)
trace for power
Via to GND plane
C
SEL1
VDD
S1
SEL4
D1
S4
SEL2
TMUX1511
D4
S2
SEL3
D2
S3
GND
D3
Figure 47. Example Layout
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25
TMUX1511
SCDS390A – SEPTEMBER 2018 – REVISED DECEMBER 2018
www.ti.com
12 Device and Documentation Support
12.1 Documentation Support
12.1.1 Related Documentation
Texas Instruments, Improve Stability Issues with Low CON Multiplexers.
Texas Instruments, Simplifying Design with 1.8 V logic Muxes and Switches.
Texas Instruments, Eliminate Power Sequencing with Powered-off Protection Signal Switches.
Texas Instruments, High-Speed Interface Layout Guidelines.
Texas Instruments, High-Speed Layout Guidelines.
Texas Instruments, QFN/SON PCB Attachment.
Texas Instruments, Quad Flatpack No-Lead Logic Packages.
12.2 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper
right corner, click on Alert me to register and receive a weekly digest of any product information that has
changed. For change details, review the revision history included in any revised document.
12.3 Community Resources
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
12.4 Trademarks
E2E is a trademark of Texas Instruments.
12.5 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
12.6 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
13 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
26
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Product Folder Links: TMUX1511
PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
(4/5)
(6)
TMUX1511PWR
ACTIVE
TSSOP
PW
14
2000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
MUX1511
TMUX1511RSVR
ACTIVE
UQFN
RSV
16
3000
RoHS & Green
NIPDAUAG
Level-1-260C-UNLIM
-40 to 125
1511
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of
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