TPA0112
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SLOS204C – MAY 1999 – REVISED SEPTEMBER 2004
2.6-W STEREO AUDIO POWER AMPLIFIER
WITH FOUR SELECTABLE GAIN SETTINGS
FEATURES
•
•
•
•
•
•
•
•
•
Compatible With PC 99 Desktop Line-Out Into
10-kΩ Load
Internal Gain Control, Which Eliminates
External Gain-Setting Resistors
2.6-W/Ch Output Power Into 3-Ω Load
PC-Beep Input
Depop Circuitry
Stereo Input MUX
Fully Differential Input
Low Supply Current and Shutdown Current
Surface-Mount Power Packaging 24-Pin
TSSOP PowerPAD™
PWP PACKAGE
(TOP VIEW)
GND
GAIN0
GAIN1
LOUT+
LLINEIN
LHPIN
PVDD
RIN
LOUT–
LIN
BYPASS
GND
1
2
3
4
5
6
7
8
9
10
11
12
24
23
22
21
20
19
18
17
16
15
14
13
GND
RLINEIN
SHUTDOWN
ROUT+
RHPIN
VDD
PVDD
PCB ENABLE
ROUT–
SE/BTL
PC-BEEP
GND
DESCRIPTION
The TPA0112 is a stereo audio power amplifier in a 24-pin TSSOP thermally enhanced package capable of
delivering 2.6 W of continuous RMS power per channel into 3-Ω loads. This device minimizes the number of
external components needed, simplifying the design, and freeing up board space for other features. When driving
1 W into 8-Ω speakers, the TPA0112 has less than 0.8% THD+N across its specified frequency range.
Included within this device is integrated depop circuitry that virtually eliminates transients that cause noise in the
speakers.
Amplifier gain is internally configured and controlled by way of two terminals (GAIN0 and GAIN1). BTL gain
settings of 2, 6, 12, and 24 V/V are provided, while SE gain is always configured as 1 V/V for headphone drive.
An internal input MUX allows two sets of stereo inputs to the amplifier. In notebook applications, where internal
speakers are driven as BTL and the line outputs (often headphone drive) are required to be SE, the TPA0112
automatically switches into SE mode when the SE/BTL input is activated, and this reduces the gain to 1 V/V.
The TPA0112 consumes only 6 mA of supply current during normal operation. A miserly shutdown mode
reduces the supply current to less than 150 µA.
The PowerPAD package (PWP) delivers a level of thermal performance that was previously achievable only in
TO-220-type packages. Thermal impedances of approximately 35°C/W are readily realized in multilayer PCB
applications. This allows the TPA0112 to operate at full power into 8-Ω loads at an ambient temperature of 85°C.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PowerPAD is a trademark of Texas Instruments.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 1999–2004, Texas Instruments Incorporated
TPA0112
www.ti.com
SLOS204C – MAY 1999 – REVISED SEPTEMBER 2004
These devices have limited built-in ESD protection. The leads should be shorted together or the device
placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates.
FUNCTIONAL BLOCK DIAGRAM
RHPIN
R
MUX
RLINEIN
Volume
Control
−
GAIN0
ROUT+
+
GAIN1
Volume
Control
RIN
−
ROUT−
PC-BEEP
PCB ENABLE
SE/BTL
+
PC
Beep
MUX
Control
LHPIN
L
MUX
LLINEIN
Depop
Circuitry
Power
Management
Volume
Control
PVDD
VDD
BYPASS
SHUTDOWN
GND
−
LOUT+
+
Volume
Control
LIN
−
LOUT−
+
AVAILABLE OPTIONS
TA
–40°C to 85°C
(1)
2
PACKAGED DEVICE
TSSOP (1) (PWP)
TPA0112PWP
The PWP package is available taped and reeled. To order a
taped and reeled part, add the suffix R to the part number
(e.g., TPA0112PWPR).
TPA0112
www.ti.com
SLOS204C – MAY 1999 – REVISED SEPTEMBER 2004
TERMINAL FUNCTIONS
TERMINAL
I/O
DESCRIPTION
NAME
NO.
BYPASS
11
GAIN0
2
I
Bit 0 of gain control
GAIN1
3
I
Bit 1 of gain control
GND
1, 12, 13,
24
Tap to voltage divider for internal mid-supply bias generator
Ground connection for circuitry. Connected to the thermal pad.
LHPIN
6
I
Left channel headphone input, selected when SE/BTL is held high
LIN
10
I
Common left input for fully differential input. AC ground for single-ended inputs.
LLINEIN
5
I
Left channel line input, selected when SE/BTL is held low
LOUT+
4
O
Left channel positive output in BTL mode and positive output in SE mode
LOUT–
9
O
Left channel negative output in BTL mode and high impedance in SE mode
PC-BEEP
14
I
The input for PC Beep mode. PC-BEEP is enabled when a > 1.5-V (peak-to-peak) square wave is
input to PC-BEEP or PCB ENABLE is high.
PCB ENABLE
17
I
If this terminal is high, the detection circuitry for PC-BEEP is overridden and passes PC-BEEP
through the amplifier, regardless of its amplitude. If PCB ENABLE is floating or low, the amplifier
continues to operate normally.
PVDD
7, 18
I
Power supply for output stage
RHPIN
20
I
Right channel headphone input, selected when SE/BTL is held high
RIN
8
I
Common right input for fully differential input. AC ground for single-ended inputs.
RLINEIN
23
I
Right channel line input, selected when SE/BTL is held low
ROUT+
21
O
Right channel positive output in BTL mode and positive output in SE mode
ROUT–
16
O
Right channel negative output in BTL mode and high-impedance in SE mode
SHUTDOWN
22
I
Places entire IC in shutdown mode when held low, except PC-BEEP remains active
SE/BTL
15
I
Input MUX control input. When this terminal is held high, the LHPIN or RHPIN and SE output is
selected. When this terminal is held low, the LLINEIN or RLINEIN and BTL output are selected.
VDD
19
I
Analog VDD input supply. This terminal needs to be isolated from PVDD to achieve highest
performance.
Thermal pad
Connect to ground. Must be soldered down in all applications to properly secure the device on the
PC board.
ABSOLUTE MAXIMUM RATINGS
over operating free-air temperature range (unless otherwise noted) (1)
VDD
Supply voltage
VI
Input voltage
Continuous total power dissipation
6V
–0.3 V to VDD +0.3 V
Internally Limited (see Dissipation Rating
Table)
TA
Operating free-air temperature range
–40°C to 85°C
TJ
Operating junction temperature range
–40°C to 150°C
Tstg
Storage temperature range
–65°C to 85°C
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds
(1)
260°C
Stresses beyond thoselisted under absolute maximum ratings may cause permanent damage to the device.These are stress ratings
only, and functional operation of the device at theseor any other conditions beyond those indicated under recommended
operatingconditions is not implied. Exposure to absolute-maximum-rated conditions forextended periods may affect device reliability.
3
TPA0112
www.ti.com
SLOS204C – MAY 1999 – REVISED SEPTEMBER 2004
DISSIPATION RATING TABLE
(1)
PACKAGE
TA≤ 25°C
DERATING FACTOR
TA = 70°C
TA = 85°C
PWP
2.7 W (1)
21.8 mW/°C
1.7 W
1.4 W
Please see the Texas Instrumentsdocument, PowerPAD Thermally EnhancedPackage Application
Report (literature number SLMA002), for moreinformation on the PowerPAD package. The thermal
data was measured on a PCBlayout based on the information in the section entitledTexas
Instruments Recommended Board forPowerPAD of the before-mentioned document.
RECOMMENDED OPERATING CONDITIONS
VDD
Supply voltage
VIH
SE/BTL, GAIN0, GAIN1
High-level input voltage
VIL
MAX
4.5
5.5
0.8 x VDD
SHUTDOWN
Low-level input voltage
MIN
V
V
2
SE/BTL
0.6 x VDD
GAIN0, GAIN1
0.4 x VDD
SHUTDOWN
TA
UNIT
V
0.8
Operating free-air temperature
–40
85
°C
ELECTRICAL CHARACTERISTICS
at specified free-air temperature, VDD = 5 V, TA = 25°C (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
25
mV
|VOO|
Output offset voltage (measured differentially)
VI = 0, AV = 2 V/V
PSRR
Power supply rejection ratio
VDD = 4.5 V to 5.5 V
|IIH|
High-level input current
VDD = 5.5 V, VI = VDD
900
nA
|IIL|
Low-level input current
VDD = 5.5 V, VI = 0 V
900
nA
IDD
Supply current
IDD(SD)
Supply current, shutdown mode
77
dB
BTL mode
6
8
SE mode
3
4
150
300
mA
µA
OPERATING CHARACTERISTICS
VDD = 5 V, TA = 25°C, RL = 8 Ω , Gain = 2 V/V, BTL mode
PARAMETER
TEST CONDITIONS
PO
Output power
RL = 3 Ω
THD + N
Total harmonic distortion plus noise
PO = 1 W,
BOM
Maximum output power bandwidth
THD = 5%
Supply ripple rejection ratio
f = 1 kHz,
CB = 0.47 µF
SNR
Signal-to-noise ratio
Vn
Noise output voltage
ZI
Input impedance (1)
(1)
4
See Table 1 and itsassociated text.
CB = 0.47 µF,
f = 20 Hz to 20 kHz
MIN
TYP
THD+N = 10%
2.6
THD+N = 1%
2.05
f = 20 Hz to 15 kHz
BTL mode
MAX
UNIT
W
0.75%
>15
kHz
–72
dB
105
dB
BTL mode
20
SE mode
18
µVRMS
TPA0112
www.ti.com
SLOS204C – MAY 1999 – REVISED SEPTEMBER 2004
TYPICAL CHARACTERISTICS
TABLE OF GRAPHS
FIGURE
vs Output power
1, 4-7, 10-13,
16-19, 21
vs Frequency
2, 3, 8, 9, 14,
15, 20, 22
THD+N
Total harmonic distortion plus noise
Vn
Output noise voltage
vs Bandwidth
24
Supply ripple rejection ratio
vs Frequency
25, 26
Crosstalk
vs Frequency
27-29
Shutdown attenuation
vs Frequency
30
Signal-to-noise ratio
vs Frequency
31
vs Output voltage
SNR
23
Closed-loop respone
PO
Output power
PD
Power dissipation
32-35
vs Load resistance
36, 37
vs Output power
38, 39
vs Ambient temperature
TOTAL HARMONIC DISTORTION PLUS NOISE
vs
OUTPUT POWER
TOTAL HARMONIC DISTORTION PLUS NOISE
vs
FREQUENCY
10%
10%
AV = 2 V/V
f = 1 kHz
BTL
THD+N −Total Harmonic Distortion + Noise
THD+N −Total Harmonic Distortion + Noise
40
RL = 4 Ω
1%
RL = 8 Ω
RL = 3 Ω
0.1%
0.01%
0.5 0.75
1
1.25 1.5 1.75
2
2.25 2.5 2.75
PO − Output Power − W
Figure 1.
3
PO = 1.75 W
RL = 3 Ω
BTL
AV = 24 V/V
1%
AV = 12 V/V
AV = 2 V/V
0.1%
AV = 6 V/V
0.01%
20
100
1k
10k 20k
f − Frequency − Hz
Figure 2.
5
TPA0112
www.ti.com
SLOS204C – MAY 1999 – REVISED SEPTEMBER 2004
TOTAL HARMONIC DISTORTION PLUS NOISE
vs
FREQUENCY
10%
10%
RL = 3 Ω
AV = 2 V/V
BTL
THD+N −Total Harmonic Distortion + Noise
THD+N −Total Harmonic Distortion + Noise
TOTAL HARMONIC DISTORTION PLUS NOISE
vs
OUTPUT POWER
1%
Po = 1.0 W
Po = 0.5 W
0.1%
Po = 1.75 W
0.01%
20
100
1k
f = 15 kHz
1%
f = 1 kHz
0.1%
f = 20 Hz
RL = 3 Ω
AV = 2 V/V
BTL
0.01%
0.01
10k 20k
f − Frequency − Hz
Figure 3.
Figure 4.
TOTAL HARMONIC DISTORTION PLUS NOISE
vs
OUTPUT POWER
TOTAL HARMONIC DISTORTION PLUS NOISE
vs
OUTPUT POWER
f = 15 kHz
1%
f = 1 kHz
f = 20 Hz
0.1%
RL = 3 Ω
AV = 6 V/V
BTL
0.01%
0.01
10
10%
THD+N −Total Harmonic Distortion + Noise
THD+N −Total Harmonic Distortion + Noise
10%
0.1
1
PO − Output Power − W
Figure 5.
6
0.1
1
PO − Output Power − W
10
f = 15 kHz
1%
f = 1 kHz
f = 20 Hz
0.1%
RL = 3 Ω
AV = 12 V/V
BTL
0.01%
0.01
0.1
1
PO − Output Power − W
Figure 6.
10
TPA0112
www.ti.com
SLOS204C – MAY 1999 – REVISED SEPTEMBER 2004
TOTAL HARMONIC DISTORTION PLUS NOISE
vs
OUTPUT POWER
10%
THD+N −Total Harmonic Distortion + Noise
f = 15 kHz
f = 1 kHz
1%
f = 20 Hz
0.1%
RL = 3 Ω
AV = 24 V/V
BTL
0.01%
0.01
0.1
1
PO − Output Power − W
PO = 1.75 W
RL = 3 Ω
BTL
AV = 24 V/V
1%
AV = 12 V/V
AV = 2 V/V
0.1%
AV = 6 V/V
0.01%
20
10
100
1k
10k 20k
f − Frequency − Hz
Figure 7.
Figure 8.
TOTAL HARMONIC DISTORTION PLUS NOISE
vs
FREQUENCY
TOTAL HARMONIC DISTORTION PLUS NOISE
vs
OUTPUT POWER
10%
10%
RL = 4 Ω
AV = 2 V/V
BTL
THD+N −Total Harmonic Distortion + Noise
THD+N −Total Harmonic Distortion + Noise
10%
THD+N −Total Harmonic Distortion + Noise
TOTAL HARMONIC DISTORTION PLUS NOISE
vs
FREQUENCY
1%
PO = 1.5 W
0.1%
PO = 0.25 W
PO = 1.0 W
0.01%
20
100
1k
f − Frequency − Hz
Figure 9.
10k 20k
RL = 4 Ω
AV = 2 V/V
BTL
f = 15 kHz
1%
f = 1 kHz
0.1%
f = 20 Hz
0.01%
0.01
0.1
1
PO − Output Power − W
10
Figure 10.
7
TPA0112
www.ti.com
SLOS204C – MAY 1999 – REVISED SEPTEMBER 2004
TOTAL HARMONIC DISTORTION PLUS NOISE
vs
OUTPUT POWER
TOTAL HARMONIC DISTORTION PLUS NOISE
vs
OUTPUT POWER
10%
THD+N −Total Harmonic Distortion + Noise
THD+N −Total Harmonic Distortion + Noise
10%
f = 15 kHz
1%
f = 1 kHz
0.1%
f = 20 Hz
RL = 4 Ω
AV = 6 V/V
BTL
0.01%
0.01
0.1
1
PO − Output Power − W
f = 1 kHz
f = 20 Hz
0.1%
RL = 4 Ω
AV = 12 V/V
BTL
0.1
1
PO − Output Power − W
10
Figure 11.
Figure 12.
TOTAL HARMONIC DISTORTION PLUS NOISE
vs
OUTPUT POWER
TOTAL HARMONIC DISTORTION PLUS NOISE
vs
FREQUENCY
10%
f = 15 kHz
THD+N −Total Harmonic Distortion + Noise
THD+N −Total Harmonic Distortion + Noise
1%
0.01%
0.01
10
10%
f = 1 kHz
1%
f = 20 Hz
0.1%
RL = 4 Ω
AV = 24 V/V
BTL
0.01%
0.01
0.1
1
PO − Output Power − W
Figure 13.
8
f = 15 kHz
10
RL = 8 Ω
AV = 2 V/V
BTL
1%
0.1%
PO = 0.25 W
PO = 1.0 W
0.01%
20
PO = 0.5 W
100
1k
f − Frequency − Hz
Figure 14.
10k 20k
TPA0112
www.ti.com
SLOS204C – MAY 1999 – REVISED SEPTEMBER 2004
TOTAL HARMONIC DISTORTION PLUS NOISE
vs
FREQUENCY
TOTAL HARMONIC DISTORTION PLUS NOISE
vs
OUTPUT POWER
10%
PO = 1 W
RL = 8 Ω
BTL
THD+N −Total Harmonic Distortion + Noise
THD+N −Total Harmonic Distortion + Noise
10%
AV = 24 V/V
1%
AV = 12 V/V
AV = 2 V/V
0.1%
AV = 6 V/V
0.01%
20
100
1k
RL = 8 Ω
AV = 2 V/V
BTL
f = 15 kHz
1%
f = 1 kHz
0.1%
f = 20 Hz
0.01%
0.01
10k 20k
f − Frequency − Hz
Figure 15.
Figure 16.
TOTAL HARMONIC DISTORTION PLUS NOISE
vs
OUTPUT POWER
TOTAL HARMONIC DISTORTION PLUS NOISE
vs
OUTPUT POWER
f = 15 kHz
1%
f = 1 kHz
0.1%
0.01%
0.01
10
10%
RL = 8 Ω
AV = 6 V/V
BTL
THD+N −Total Harmonic Distortion + Noise
10%
THD+N −Total Harmonic Distortion + Noise
0.1
1
PO − Output Power − W
f = 20 Hz
0.1
1
PO − Output Power − W
Figure 17.
10
f = 15 kHz
1%
f = 1 kHz
f = 20 Hz
0.1%
RL = 8 Ω
AV = 12 V/V
BTL
0.01%
0.01
0.1
1
PO − Output Power − W
10
Figure 18.
9
TPA0112
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SLOS204C – MAY 1999 – REVISED SEPTEMBER 2004
TOTAL HARMONIC DISTORTION PLUS NOISE
vs
OUTPUT POWER
TOTAL HARMONIC DISTORTION PLUS NOISE
vs
FREQUENCY
10%
1%
f = 1 kHz
f = 20 Hz
0.1%
RL = 8 Ω
AV = 24 V/V
BTL
0.01%
0.01
THD+N −Total Harmonic Distortion + Noise
0.1
1
PO − Output Power − W
RL = 32 Ω
AV = 1 V/V
SE
1%
Po = 25 mW
0.1%
Po = 50 mW
Po = 75 mW
0.01%
20
10
100
1k
10k 20k
f − Frequency − Hz
Figure 19.
Figure 20.
TOTAL HARMONIC DISTORTION PLUS NOISE
vs
OUTPUT POWER
TOTAL HARMONIC DISTORTION PLUS NOISE
vs
FREQUENCY
10%
10%
RL = 32 Ω
AV = 1 V/V
SE
1%
f = 15 kHz
0.1%
f = 1 kHz
f = 20 Hz
0.01%
0.01
0.1
PO − Output Power − W
Figure 21.
10
THD+N −Total Harmonic Distortion + Noise
f = 15 kHz
THD+N −Total Harmonic Distortion + Noise
THD+N −Total Harmonic Distortion + Noise
10%
1
RL = 10 kΩ
AV = 1 V/V
SE
1%
0.1%
Vo = 1 VRMS
0.01%
0.001%
20
100
1k
f − Frequency − Hz
Figure 22.
10k 20k
TPA0112
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SLOS204C – MAY 1999 – REVISED SEPTEMBER 2004
TOTAL HARMONIC DISTORTION PLUS NOISE
vs
OUTPUT VOLTAGE
OUTPUT NOISE VOLTAGE
vs
BANDWIDTH
100
RL = 10 kΩ
AV = 1 V/V
SE
1%
0.1%
VDD = 5 V
RL = 4Ω
90
V n − Output Noise Voltage − µ V
THD+N −Total Harmonic Distortion + Noise
10%
f = 20 Hz
f = 15 kHz
0.01%
f = 1 kHz
80
70
60
AV = 24 V/V
50
40
AV = 12 V/V
30
AV = 6 V/V
20
10
0.001%
0.1
AV = 2 V/V
0
1
10
3
Figure 23.
Figure 24.
SUPPLY RIPPLE REJECTION RATIO
vs
FREQUENCY
SUPPLY RIPPLE REJECTION RATIO
vs
FREQUENCY
0
RL = 8 Ω
CB = 0.47 µF
BTL
Supply Ripple Rejection Ratio − dB
Supply Ripple Rejection Ratio − dB
−20
−40
AV = 24 V/V
−60
AV = 2 V/V
−80
−100
−120
20
1k
100
1k
10k
BW − Bandwidth − Hz
VO − Output Voltage − VRMS
0
100
10k 20k
−20
RL = 32 Ω
CB = 0.47 µF
SE
−40
AV = 1 V/V
−60
−80
−100
−120
20
100
1k
f − Frequency − Hz
f − Frequency − Hz
Figure 25.
Figure 26.
10k 20k
11
TPA0112
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SLOS204C – MAY 1999 – REVISED SEPTEMBER 2004
CROSSTALK
vs
FREQUENCY
CROSSTALK
vs
FREQUENCY
0
−20
−40
Crosstalk − dB
Crosstalk − dB
−20
0
PO = 1 W
RL = 8 Ω
AV = 2 V/V
BTL
−60
−80
PO = 1 W
RL = 8 Ω
AV = 24 V/V
BTL
−40
−60
LEFT TO RIGHT
−80
LEFT TO RIGHT
RIGHT TO LEFT
−100
−100
RIGHT TO LEFT
−120
20
100
1k
−120
20
10k 20k
Figure 27.
Figure 28.
CROSSTALK
vs
FREQUENCY
SHUTDOWN ATTENUATION
vs
FREQUENCY
10k 20k
0
VO = 1 VRMS
RL = 10 kΩ
AV = 1 V/V
SE
VI = 1 VRMS
−20
RL = 10 kΩ, SE
−40
−60
LEFT TO RIGHT
−80
−100
Attenuation − dB
Crosstalk − dB
1k
f − Frequency − Hz
0
−20
100
f − Frequency − Hz
−40
−60
RL = 32 Ω, SE
−80
−100
RL = 8 Ω, BTL
RIGHT TO LEFT
−120
20
12
100
1k
10k 20k
−120
20
100
1k
f − Frequency − Hz
f − Frequency − Hz
Figure 29.
Figure 30.
10k 20k
TPA0112
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SLOS204C – MAY 1999 – REVISED SEPTEMBER 2004
SIGNAL-TO-NOISE RATIO
vs
FREQUENCY
140
SNR − Signal-To-Noise Ratio − dB
130
PO = 1 W
RL = 8 Ω
BTL
120
AV = 6 V/V
AV = 2 V/V
110
AV = 24 V/V
100
90
AV = 12 V/V
80
70
60
20
100
1k
10k 20k
f − Frequency − Hz
Figure 31.
CLOSED-LOOP RESPONSE
360°
10
7.5
Gain
270°
5
Phase
180°
0
Phase
Gain − dB
2.5
−2.5
−5
RL = 8 Ω
AV = 2 V/V
BTL
90°
−7.5
−10
10
0°
100
1k
10k
100k
1M
f − Frequency − Hz
Figure 32.
13
TPA0112
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SLOS204C – MAY 1999 – REVISED SEPTEMBER 2004
CLOSED-LOOP RESPONSE
360°
30
25
270°
20
Gain
Phase
180°
10
Phase
Gain − dB
15
5
0
RL = 8 Ω
AV = 6 V/V
BTL
90°
−5
−10
10
0°
100
1k
10k
100k
1M
f − Frequency − Hz
Figure 33.
CLOSED-LOOP RESPONSE
360°
30
25
Gain
270°
20
Phase
180°
10
5
0
RL = 8 Ω
AV = 12 V/V
BTL
90°
−5
−10
10
0°
100
1k
10k
f − Frequency − Hz
Figure 34.
14
100k
1M
Phase
Gain − dB
15
TPA0112
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SLOS204C – MAY 1999 – REVISED SEPTEMBER 2004
CLOSED-LOOP RESPONSE
360°
30
Gain
25
270°
20
Phase
180°
10
Phase
Gain − dB
15
5
0
RL = 8 Ω
AV = 24 V/V
BTL
90°
−5
−10
10
0°
100
1k
10k
1M
100k
f − Frequency − Hz
Figure 35.
OUTPUT POWER
vs
LOAD RESISTANCE
OUTPUT POWER
vs
LOAD RESISTANCE
3.5
1500
AV = 2 V/V
BTL
1250
PO− Output Power − mW
PO − Output Power − W
3
AV = 1 V/V
SE
2.5
2
10% THD+N
1.5
1
1% THD+N
0.5
1000
750
10% THD+N
500
250
1% THD+N
0
0
0
8
16
24
32
40
48
RL − Load Resistance − Ω
Figure 36.
56
64
0
8
16
24
32
40
48
RL − Load Resistance − Ω
56
64
Figure 37.
15
TPA0112
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SLOS204C – MAY 1999 – REVISED SEPTEMBER 2004
POWER DISSIPATION
vs
OUTPUT POWER
POWER DISSIPATION
vs
OUTPUT POWER
0.4
1.8
3Ω
0.35
PD − Power Dissipation − W
PD − Power Dissipation − W
1.6
1.4
1.2
4Ω
1
0.8
0.6
8Ω
0.3
0.25
0.2
0.15
f = 1 kHz
BTL
Each Channel
0
0
0.5
1
1.5
PO − Output Power − W
2
8Ω
0.1
0.4
0.2
4Ω
0.05
0
0
2.5
0.1
0.2
0.3
0.4
0.5
0.6
PO − Output Power − W
Figure 38.
Figure 39.
POWER DISSIPATION
vs
AMBIENT TEMPERATURE
7
ΘJA4
PD − Power Dissipation − W
6
ΘJA1 = 45.9°C/W
ΘJA2 = 45.2°C/W
ΘJA3 = 31.2°C/W
ΘJA4 = 18.6°C/W
5
4
ΘJA3
3
ΘJA1,2
2
1
0
−40 −20
0
20 40 60 80 100 120 140 160
TA − Ambient Temperature − °C
Figure 40.
16
f = 1 kHz
SE
Each Channel
32 Ω
0.7
0.8
TPA0112
www.ti.com
SLOS204C – MAY 1999 – REVISED SEPTEMBER 2004
THERMAL INFORMATION
The thermally enhanced PWP package is based on the 24-pin TSSOP, but includes a thermal pad (see Figure
41) to provide an effective thermal contact between the IC and the PWB.
Traditionally, surface mount and power have been mutually exclusive terms. A variety of scaled-down
TO-220-type packages have leads formed as gull wings to make them applicable for surface-mount applications.
These packages, however, have only two shortcomings: they do not address the low-profile requirements (< 2
mm) of many of today's advanced systems, and they do not offer a terminal-count high enough to accommodate
increasing integration. On the other hand, traditional low-power surface-mount packages require
power-dissipation derating that severely limits the usable range of many high-performance analog circuits.
The PowerPAD package (thermally enhanced TSSOP) combines fine-pitch surface-mount technology with
thermal performance comparable to much larger power packages.
The PowerPAD package is designed to optimize the heat transfer to the PWB. Because of the small size and
limited mass of a TSSOP package, thermal enhancement is achieved by improving the thermal conduction paths
that remove heat from the component. The thermal pad is formed using a patented lead-frame design and
manufacturing technique to provide a direct connection to the heat-generating IC. When this pad is soldered or
otherwise thermally coupled to an external heat dissipator, high power dissipation in the ultra-thin, fine-pitch,
surface-mount package can be reliably achieved.
DIE
Side View (a)
Thermal
Pad
DIE
End View (b)
Bottom View (c)
Figure 41. Views of Thermally Enhanced PWP Package
17
TPA0112
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SLOS204C – MAY 1999 – REVISED SEPTEMBER 2004
APPLICATION INFORMATION
SELECTION OF COMPONENTS
Figure 42 and Figure 43 are schematic diagrams of typical notebook computer application circuits.
Right CIRHP
Head− 0.47 µF
phone
Input
20
Signal
CIRLINE
Right 0.47 µF
Line
Input
Signal
23
RHPIN
RLINEIN
R
MUX
Volume
Control
−
+
8
RIN
CRIN
0.47 µF
PC-BEEP
14
Input
Signal
CPCB
0.47 µF 17
ROUT+
21
Volume
Control
COUTR
330 µF
PC-BEEP
PCB
ENABLE
−
+
PCBeep
ROUT−
16
VDD
1 kΩ
100 kΩ
2, 3
15
GAIN0
GAIN1
SE/BTL
Gain/
MUX
Control
Depop
Circuitry
Power
Management
Left CILHP
Head− 0.47 µF
phone
Input
Signal
CILLINE
Left 0.47 µF
Line
Input
Signal
6
LHPIN
5
LLINEIN
10
CLIN
0.47 µF
LIN
PVDD
18
VDD
19
BYPASS
SHUT−
DOWN
11
GND
L
MUX
Volume
Control
See Note A
VDD
CSR
0.1 µF
VDD
CSR
0.1 µF
22
CBYP
0.47 µF
To
System
Control
−
+
LOUT+
4
−
+
LOUT−
9
1 kΩ
1, 12,
13, 24
COUTL
330 µF
Volume
Control
100 kΩ
Figure 42. Typical TPA0112 Application Circuit Using Single-Ended Inputs and Input MUX
18
TPA0112
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SLOS204C – MAY 1999 – REVISED SEPTEMBER 2004
APPLICATION INFORMATION (continued)
CIRHP−
0.47 µF
Right
Negative
Differential
Input Signal
Right
Positive
Differential
Input Signal
PC-BEEP
Input
Signal
20
CIRIN−
0.47 µF
23
RHPIN
RLINEIN
R
MUX
Volume
Control
−
ROUT+
21
+
CIRIN+
0.47 µF
8
RIN
14
PC-BEEP
CPCB
0.47 µF 17
PCB
ENABLE
Volume
Control
COUTR
330 µF
−
PCBeep
ROUT−
16
VDD
+
1 kΩ
100 kΩ
2, 3
15
GAIN0
GAIN1
SE/BTL
Gain/
MUX
Control
Depop
Circuitry
Power
Management
CILHP
0.47 µF
Left
Negative
Differential
Input Signal
Left
Positive
Differential
Input Signal
6
LHPIN
5
LLINEIN
PVDD
18
VDD
19
BYPASS
SHUT−
DOWN
11
GND
L
MUX
CILIN−
0.47 µF
Volume
Control
−
LOUT+
See Note A
VDD
CSR
0.1 µF
VDD
CSR
0.1 µF
22
CBYP
0.47 µF
To
System
Control
4
1 kΩ
1, 12,
13, 24
+
10
LIN
COUTL
330 µF
Volume
Control
CILIN
0.47 µF
−
LOUT−
9
+
100 kΩ
A.
A 0.1-µF ceramic capacitor should be placed as close as possible to the IC. For filtering lower frequency noise
signals, a larger electrolytic capacitor of 10 µF or greater should be placed near the audio power amplifier.
Figure 43. Typical TPA0112 Application Circuit Using Differential Inputs
19
TPA0112
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SLOS204C – MAY 1999 – REVISED SEPTEMBER 2004
APPLICATION INFORMATION (continued)
GAIN-SETTING VIA GAIN0 AND GAIN1 INPUTS
The gain of the TPA0112 is set by two input terminals, GAIN0 and GAIN1.
Table 1. GAIN SETTINGS
GAIN0
GAIN1
SE/BTL
AV
0
0
0
2 V/V
0
1
0
6 V/V
1
0
0
12 V/V
1
1
0
24 V/V
X
X
1
1 V/V
The gains listed in Table 1 are realized by changing the taps on the input resistors inside the amplifier. This
causes the input impedance, ZI, to be dependant on the gain setting. The actual gain settings are controlled by
ratios of resistors, so the actual gain distribution from part-to-part is quite good. However, the input impedance
will shift by 30% due to shifts in the actual resistance of the input impedance.
For design purposes, the input network (discussed in the next section) should be designed assuming an input
impedance of 10 kΩ, which is the absolute minimum input impedance of the TPA0112. At the higher gain
settings, the input impedance could increase as high as 115 kΩ.
INPUT RESISTANCE
Each gain setting is achieved by varying the input resistance of the amplifier, which can range from its smallest
value to over 6 times that value. As a result, if a single capacitor is used in the input high-pass filter, the –3 dB or
cutoff frequency also changes by over 6 times. If an additional resistor is connected from the input pin of the
amplifier to ground, as shown in the following figure, the variation of the cutoff frequency will be much reduced.
ZF
C
IN
Input
Signal
ZI
R
The input impedance at each gain setting is given in the following table:
AV
ZI
24 V/V
14 kΩ
12 V/V
26 kΩ
6 V/V
45.5 kΩ
2 V/V
91 kΩ
The –3 dB frequency can be calculated using Equation 1:
f
–3 dB
1
2 CR R
I
(1)
If the filter must be more accurate, the value of the capacitor should be increased while the value of the resistor
to ground should be decreased. In addition, the order of the filter could be increased.
20
TPA0112
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SLOS204C – MAY 1999 – REVISED SEPTEMBER 2004
INPUT CAPACITOR, CI
In the typical application, an input capacitor, CI, is required to allow the amplifier to bias the input signal to the
proper dc level for optimum operation. In this case, CI and the input impedance of the amplifier, ZI, form a
high-pass filter with the corner frequency determined in Equation 2.
−3 dB
fc(highpass)
1
2 ZI C I
fc
(2)
The value of CI is important to consider as it directly affects the bass (low-frequency) performance of the circuit.
Consider the example where ZI is 26 kΩ and the specification calls for a flat bass response down to 65 Hz.
Equation 2 is reconfigured as Equation 3.
CI
1
2 Z I fc
(3)
In this example, CI is 94 nF so one would likely choose a value in the range of 0.1 µF to 1 µF. A further
consideration for this capacitor is the leakage path from the input source through the input network (CI) and the
feedback network to the load. This leakage current creates a dc-offset voltage at the input to the amplifier that
reduces useful headroom, especially in high gain applications. For this reason a low-leakage tantalum or ceramic
capacitor is the best choice. When polarized capacitors are used, the positive side of the capacitor should face
the amplifier input in most applications as the dc level there is held at VDD/2, which is likely higher than the
source dc level. Note that it is important to confirm the capacitor polarity in the application.
POWER SUPPLY DECOUPLING, CS
The TPA0112 is a high-performance CMOS audio amplifier that requires adequate power supply decoupling to
ensure that the output total harmonic distortion (THD) is as low as possible. Power supply decoupling also
prevents oscillations for long lead lengths between the amplifier and the speaker. The optimum decoupling is
achieved by using two capacitors of different types that target different types of noise on the power supply leads.
For higher frequency transients, spikes, or digital hash on the line, a good low equivalent-series-resistance (ESR)
ceramic capacitor, typically 0.1 µF placed as close as possible to the device VDD lead works best. For filtering
lower frequency noise signals, a larger aluminum electrolytic capacitor of 10 µF or greater placed near the audio
power amplifier is recommended.
MIDRAIL BYPASS CAPACITOR, CBYP
The midrail bypass capacitor, CBYP, is the most critical capacitor and serves several important functions. During
start-up or recovery from shutdown mode, CBYP determines the rate at which the amplifier starts up. The second
function is to reduce noise produced by the power supply caused by coupling into the output drive signal. This
noise is from the midrail generation circuit internal to the amplifier, which appears as degraded PSRR and
THD+N.
Bypass capacitor, CBYP, values of 0.47-µF to 1-µF ceramic or tantalum low-ESR capacitors are recommended for
the best THD and noise performance.
21
TPA0112
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SLOS204C – MAY 1999 – REVISED SEPTEMBER 2004
OUTPUT COUPLING CAPACITOR, CC
In the typical single-supply, SE configuration, an output coupling capacitor (CC) is required to block the dc bias at
the output of the amplifier, thus preventing dc currents in the load. As with the input coupling capacitor, the
output coupling capacitor and impedance of the load form a high-pass filter governed by Equation 4.
−3 dB
fc(high)
1
2 RL C C
fc
(4)
The main disadvantage, from a performance standpoint, is the load impedances are typically small, which drives
the low-frequency corner higher degrading the bass response. Large values of CC are required to pass low
frequencies into the load. Consider the example where a CC of 330 µF is chosen and loads vary from 3 Ω, 4 Ω,
8 Ω, 32 Ω , 10 kΩ, to 47 kΩ. Table 2 summarizes the frequency response characteristics of each configuration.
Table 2. COMMON-LOAD IMPEDANCES Vs LOW-FREQUENCY OUTPUT
CHARACTERISTICS IN SE MODE
RL
CC
LOWEST FREQUENCY
3Ω
330 µF
161 Hz
4Ω
330 µF
120 Hz
8Ω
330 µF
60 Hz
32 Ω
330 µF
15 Hz
10,000 Ω
330 µF
0.05 Hz
47,000 Ω
330 µF
0.01 Hz
As Table 2 indicates, most of the bass response is attenuated into a 4-Ω load, an 8-Ω load is adequate,
headphone response is good, and drive into line-level inputs (a home stereo for example) is exceptional.
USING LOW-ESR CAPACITORS
Low-ESR capacitors are recommended throughout this applications section. A real (as opposed to ideal)
capacitor can be modeled simply as a resistor in series with an ideal capacitor. The voltage drop across this
resistor minimizes the beneficial effects of the capacitor in the circuit. The lower the equivalent value of this
resistance the more the real capacitor behaves like an ideal capacitor.
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TPA0112
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SLOS204C – MAY 1999 – REVISED SEPTEMBER 2004
BRIDGE-TIED LOAD VERSUS SINGLE-ENDED MODE
Figure 44 shows a Class-AB audio power amplifier (APA) in a BTL configuration. The TPA0112 BTL amplifier
consists of two Class-AB amplifiers driving both ends of the load. There are several potential benefits to this
differential drive configuration but initially consider power to the load. The differential drive to the speaker means
that as one side is slewing up, the other side is slewing down, and vice versa. This, in effect, doubles the voltage
swing on the load as compared to a ground-referenced load. Plugging 2 × VO(PP) into the power equation, where
voltage is squared, yields 4× the output power from the same supply rail and load impedance (see Equation 5).
V(RMS)
V O(PP)
2 2
Power
V(RMS)
2
RL
(5)
VDD
VO(PP)
RL
2x VO(PP)
VDD
–VO(PP)
Figure 44. Bridge-Tied Load Configuration
In a typical computer sound channel operating at 5 V, bridging raises the power into an 8-Ω speaker from a
singled-ended (SE, ground reference) limit of 250 mW to 1 W. In sound power, that is a 6-dB improvement—which is loudness that can be heard. In addition to increased power there are frequency response
concerns. Consider the single-supply, SE configuration shown in Figure 45. A coupling capacitor is required to
block the dc-offset voltage from reaching the load. These capacitors can be quite large (approximately 33 µF to
1000 µF); so they tend to be expensive, heavy, occupy valuable PCB area, and have the additional drawback of
limiting low-frequency performance of the system. This frequency-limiting effect is due to the high-pass filter
network created with the speaker impedance and the coupling capacitance and is calculated with Equation 6.
fc
1
2 RL C C
(6)
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TPA0112
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SLOS204C – MAY 1999 – REVISED SEPTEMBER 2004
For example, a 68-µF capacitor with an 8-Ω speaker would attenuate low frequencies below 293 Hz. The BTL
configuration cancels the dc offsets, which eliminates the need for the blocking capacitors. Low-frequency
performance is then limited only by the input network and speaker response. Cost and PCB space are also
minimized by eliminating the bulky coupling capacitor.
VDD
–3 dB
VO(PP)
CC
RL
VO(PP)
fc
Figure 45. Single-Ended Configuration and Frequency Response
Increasing power to the load does carry a penalty of increased internal power dissipation. The increased
dissipation is understandable considering that the BTL configuration produces 4× the output power of the SE
configuration. Internal dissipation versus output power is discussed further in the Crest Factor and Thermal
Considerations section.
SINGLE-ENDED OPERATION
In SE mode (see Figure 44 and Figure 45), the load is driven from the primary amplifier output for each channel
(OUT+, terminals 21 and 4).
The amplifier switches single-ended operation when the SE/BTL terminal is held high. This puts the negative
outputs in a high-impedance state and reduces the amplifier's gain to 1 V/V.
BTL AMPLIFIER EFFICIENCY
Class-AB amplifiers are notoriously inefficient. The primary cause of these inefficiencies is voltage drop across
the output stage transistors. There are two components of the internal voltage drop. One is the headroom or dc
voltage drop that varies inversely to output power. The second component is due to the sine-wave nature of the
output. The total voltage drop can be calculated by subtracting the RMS value of the output voltage from VDD.
The internal voltage drop multiplied by the RMS value of the supply current, IDDrms, determines the internal
power dissipation of the amplifier.
An easy-to-use equation to calculate efficiency starts out as being equal to the ratio of power from the power
supply to the power delivered to the load. To accurately calculate the RMS and average values of power in the
load and in the amplifier, the current and voltage waveform shapes must first be understood (see Figure 46).
VO
IDD(avg)
VL(RMS)
Figure 46. Voltage and Current Waveforms for BTL Amplifiers
24
IDD
TPA0112
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SLOS204C – MAY 1999 – REVISED SEPTEMBER 2004
Although the voltages and currents for SE and BTL are sinusoidal in the load, currents from the supply are
different between SE and BTL configurations. In an SE application the current waveform is a half-wave rectified
shape, whereas in BTL it is a full-wave rectified waveform. This means RMS conversion factors are different.
Keep in mind that for most of the waveform, both the push and pull transistors are not on at the same time, which
supports the fact that each amplifier in the BTL device only draws current from the supply for half the waveform.
The following equations are the basis for calculating amplifier efficiency.
Efficiency of a BTL amplifier
Where:
PL
V L(RMS)
2
RL
PL
PSUP
2
V
V
, and VL(RMS) P , therefore, P L P
2
2 RL
and PSUP V DD IDD(avg)
IDD(avg) 1
and
2V P
VP
VP
1
[
cos(t)] 0
sin(t) dt
RL
RL
RL
0
Therefore,
PSUP
2 V DD VP
RL
substituting PL and PSUP into Equation 7,
2
Efficiency of a BTL amplifier
Where:
VP
VP
2 RL
2 VDD V P
RL
VP
4 V DD
PL = Power delivered to load
PSUP = Power drawn from power supply
VL(RMS) = RMS voltage on BTL load
RL = Load resistance
VP = Peak voltage on BTL load
IDD(avg) = Average current drawn from
the power supply
VDD = Power supply voltage
ηBTL = Efficiency of a BTL amplifier
2 P L RL
(7)
Therefore,
BTL
2 P L RL
4 VDD
(8)
Table 3 employs Equation 8 to calculate efficiencies for four different output power levels. Note that the efficiency
of the amplifier is quite low for lower power levels and rises sharply as power to the load is increased, resulting in
a nearly flat internal power dissipation over the normal operating range. Note that the internal dissipation at full
output power is less than in the half power range. Calculating the efficiency for a specific system is the key to
proper power supply design. For a stereo 1-W audio system with 8-Ω loads and a 5-V supply, the maximum draw
on the power supply is almost 3.25 W.
Table 3. EFFICIENCY Vs OUTPUT POWER IN 5-V, 8-Ω, BTL SYSTEMS
(1)
OUTPUT POWER
(W)
EFFICIENCY
(%)
PEAK VOLTAGE
(V)
INTERNAL DISSIPATION
(W)
0.25
31.4
2.00
0.55
0.50
44.4
2.83
0.62
1.00
62.8
4.00
0.59
1.25
70.2
4.47 (1)
0.53
High peak voltages cause theTHD to increase.
25
TPA0112
www.ti.com
SLOS204C – MAY 1999 – REVISED SEPTEMBER 2004
A final point to remember about Class-AB amplifiers (either SE or BTL) is how to manipulate the terms in the
efficiency equation to utmost advantage when possible. Note that in Equation 8, VDD is in the denominator. This
indicates that as VDD goes down, efficiency goes up.
CREST FACTOR AND THERMAL CONDITIONS
Class-AB power amplifiers dissipate a significant amount of heat in the package under normal operating
conditions. A typical music CD requires 12 dB to 15 dB of dynamic range, or headroom above the average power
output, to pass the loudest portions of the signal without distortion. In other words, music typically has a crest
factor between 12 dB and 15 dB. When determining the optimal ambient operating temperature, the internal
dissipated power at the average output power level must be used. From the TPA0112 data sheet, one can see
that when the TPA0112 is operating from a 5-V supply into a 3-Ω speaker that 4-W peaks are available.
Converting watts to dB:
P
P dB 10Log W 10Log 4 W 6 dB
1W
P ref
(9)
Subtracting the headroom restriction to obtain the average listening level without distortion yields:
• 6 dB – 15 dB = – 9 dB (15-dB crest factor) 6 dB – 12 dB = – 6 dB (12-dB crest factor) 6 dB – 9 dB = – 3 dB
(9-dB crest factor) 6 dB – 6 dB = 0 dB (6-dB crest factor) 6 dB – 3 dB = 3 dB (3-dB crest factor)
Converting dB back into watts:
P W 10PdB10 Pref
63 mW (18−dB crest factor)
125 mW (15−dB crest factor)
250 mW (9−dB crest factor)
500 mW (6−dB crest factor)
1000 mW (3−dB crest factor)
2000 mW (15−dB crest factor)
(10)
This is valuable information to consider when attempting to estimate the heat dissipation requirements for the
amplifier system. Comparing the absolute worst case, which is 2 W of continuous power output with a 3-dB crest
factor, against 12-dB and 15-dB applications drastically affects maximum ambient temperature ratings for the
system. Using the power dissipation curves for a 5-V, 3-Ω system, the internal dissipation in the TPA0112 and
maximum ambient temperatures is shown in Table 4.
Table 4. TPA0112 POWER RATING, 5-V, 3-Ω, STEREO
PEAK OUTPUT POWER
(W)
(1)
26
AVERAGE OUTPUT POWER
POWER DISSIPATION
(W/Channel)
MAXIMUM AMBIENT
TEMPERATURE (1)
4
2 W (3 dB)
1.7
–3°C
4
1000 mW (6 dB)
1.6
6°C
4
500 mW (9 dB)
1.4
24°C
4
250 mW (12 dB)
1.1
51°C
4
125 mW (15 dB)
0.8
78°C
4
63 mW (18 dB)
0.6
85°C
Package limited to85°C ambient.
TPA0112
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SLOS204C – MAY 1999 – REVISED SEPTEMBER 2004
Table 5. TPA0112 POWER RATING, 5-V, 8-Ω, STEREO
(1)
PEAK OUTPUT POWER
AVERAGE OUTPUT POWER
POWER DISSIPATION
(W/Channel)
MAXIMUM AMBIENT
TEMPERATURE (1)
2.5 W
1250 mW (3-dB crest factor)
0.55
85°C
2.5 W
1000 mW (4-dB crest factor)
0.62
85°C
2.5 W
500 mW (7-dB crest factor)
0.59
85°C
2.5 W
250 mW (10-dB crest factor)
0.53
85°C
Package limited to85°C ambient.
The maximum dissipated power, PDmax, is reached at a much lower output power level for a 3-Ω load than for an
8-Ω load. As a result, this simple formula for calculating PD(max) may be used for a 3-Ω application:
2V2
DD
P D(max)
2R L
(11)
However, in the case of an 8-Ω load, the PD(max) occurs at a point well above the normal operating power level.
The amplifier may therefore be operated at a higher ambient temperature than required by the PD(max) formula for
an 8-Ω load, but do not exceed the maximum ambient temperature of 85°C.
The maximum ambient temperature depends on the heat-sinking ability of the PCB system. The derating factor
for the PWP package is shown in the dissipation rating table (see page 4). Converting this to θ JA:
1
1
Θ JA
45°CW
0.022
Derating Factor
(12)
To calculate maximum ambient temperatures, first consider that the numbers from the dissipation graphs are per
channel so the dissipated power needs to be doubled for two-channel operation. Given θ JA, the maximum
allowable junction temperature, and the total internal dissipation, the maximum ambient temperature can be
calculated with the following equation. The maximum recommended junction temperature for the TPA0112 is
150°C. The internal dissipation figures are taken from the Power Dissipation vs Output Power graphs.
T A Max T J Max ΘJA P D
150 45(0.6 2) 96°C (15−dB crest factor)
A.
(13)
Internal dissipation of 0.6 W is estimated for a 2-W system with 15-dB crest factor per channel. Due to process
limitations, the actual TA Max is 85°C.
Tables 4 and 5 show that for some applications no airflow is required to keep junction temperatures in the
specified range. The TPA0112 is designed with thermal protection that turns the device off when the junction
temperature surpasses 150°C to prevent damage to the IC. Tables 4 and 5 were calculated for maximum
listening volume without distortion. When the output level is reduced, the numbers in the table change
significantly. Also, using 8-Ω speakers dramatically increases the thermal performance by increasing amplifier
efficiency.
SE/BTL OPERATION
The ability of the TPA0112 to easily switch between BTL and SE modes is one of its most important cost-saving
features. This feature eliminates the requirement for an additional headphone amplifier in applications where
internal stereo speakers are driven in BTL mode but external headphone or speakers must be accommodated.
Internal to the TPA0112, two separate amplifiers drive OUT+ and OUT–. The SE/BTL input (terminal 15) controls
the operation of the follower amplifier that drives LOUT– and ROUT– (terminals 9 and 16). When SE/BTL is held
low, the amplifier is on and the TPA0112 is in the BTL mode. When SE/BTL is held high, the OUT– amplifiers
are in a high output impedance state, which configures the TPA0112 as an SE driver from LOUT+ and ROUT+
(terminals 4 and 21). IDD is reduced by approximately one-half in SE mode. Control of the SE/BTL input can be
from a logic-level CMOS source or, more typically, from a resistor divider network as shown in Figure 47.
27
TPA0112
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SLOS204C – MAY 1999 – REVISED SEPTEMBER 2004
20
RHPIN
23
RLINEIN
R
MUX
Volume
Control
−
+
8
RIN
ROUT+
21
Volume
Control
VDD
−
+
ROUT−
16
100 kΩ
SE/BTL
COUTR
330 µF
15
1 kΩ
100 kΩ
Figure 47. TPA0112 Resistor Divider Network Circuit
Using a readily available 1/8-in. (3,5-mm) stereo headphone jack, the control switch is closed when no plug is
inserted. When closed, the 100-kΩ/1-kΩ divider pulls the SE/BTL input low. When a plug is inserted, the 1-kΩ
resistor is disconnected and the SE/BTL input is pulled high. When the input goes high, the OUT– amplifier is
shut down causing the speaker to mute (virtually open-circuits the speaker). The OUT+ amplifier then drives
through the output capacitor (CO) into the headphone jack.
PC-BEEP OPERATION
The PC-BEEP input allows a system beep to be sent directly from a computer through the amplifier to the
speakers with few external components. The input is normally activated automatically, but may be selected
manually by pulling PCB ENABLE high. When the PC-BEEP input is active, both of the LINEIN and HPIN inputs
are deselected and both the left and right channels are driven in BTL mode with the signal from PC-BEEP. The
gain from the PC-BEEP input to the speakers is fixed at 0.3 V/V and is independent of the volume setting. When
the PC-BEEP input is deselected, the amplifier returns to the previous operating mode and volume setting.
Furthermore, if the amplifier is in shutdown mode, activating PC-BEEP takes the device out of shutdown and
outputs the PC-BEEP signal, then returns the amplifier to shutdown mode.
When PCB ENABLE is held low, the amplifier automatically switches to PC BEEP mode after detecting a valid
signal at the PC BEEP input. The preferred input signal is a square wave or pulse train with an amplitude of 1.5
Vpp or greater. To be a accurately detected, the signal must have a minimum of 1.5-Vpp amplitude, rise and fall
times of less than 0.1 µs and a minimum of 8 rising edges. When the signal is no longer detected, the amplifier
returns to its previous operating mode and volume setting.
When PCB ENABLE is held high, PC BEEP is selected and the LINEIN and HPIN inputs are deactivated
regardless of the input signal. PCB ENABLE has an internal 100-kΩ pulldown resistor and trips at approximately
VDD/2.
28
TPA0112
www.ti.com
SLOS204C – MAY 1999 – REVISED SEPTEMBER 2004
If it is desired to ac-couple the PC-BEEP input, the value of the coupling capacitor should be chosen to satisfy
Equation 14:
C
PCB
2 f
1
(100 k)
PCB
(14)
The PC BEEP input can also be dc-coupled to avoid using this coupling capacitor. The pin normally sits at
midrail when no signal is present.
INPUT MUX OPERATION
CIRHP
0.47 µF
Right
Headphone
Input Signal
Right Line
Input Signal
CIRLINE
0.47 µF
20
RHPIN
23
RLINEIN
8
R
MUX
RIN
Volume
Control
−
+
ROUT+
21
−
+
ROUT−
16
Volume
Control
CRIN
0.47 µF
Figure 48. TPA0112 Example Input MUX Circuit
The input MUX provides the user with a means to select from two different audio sources. In BTL mode, the
LINE inputs are selected. In SE mode, the HP inputs are selected. RIN and LIN must be ac grounded in SE mode.
SHUTDOWN MODES
The TPA0112 employs a shutdown mode of operation designed to reduce supply current, IDD, to the absolute
minimum level during periods of nonuse for battery-power conservation. The SHUTDOWN input terminal should
be held high during normal operation when the amplifier is in use. Pulling SHUTDOWN low causes the outputs to
mute and the amplifier to enter a low-current state, IDD = 150 µA. SHUTDOWN should never be left unconnected
because amplifier operation would be unpredictable.
Table 6. SHUTDOWN AND MUTE MODE FUNCTIONS
INPUTS (1)
(1)
(2)
AMPLIFIER STATE
SE/BTL
SHUTDOWN
INPUT
Low
High
Line
OUTPUT
BTL
X (2)
Low
X (2)
Mute
High
High
HP
SE
Inputs should never be leftunconnected.
Stresses beyond thoselisted under absolute maximum ratings may cause permanent damage to the
device.These are stress ratings only, and functional operation of the device at theseor any other
conditions beyond those indicated under recommended operatingconditions is not implied. Exposure
to absolute-maximum-rated conditions forextended periods may affect device reliability.
29
THERMAL PAD MECHANICAL DATA
www.ti.com
PWP (R-PDSO-G24)
THERMAL INFORMATION
This PowerPAD™ package incorporates an exposed thermal pad that is designed to be attached directly to an
external heatsink. When the thermal pad is soldered directly to the printed circuit board (PCB), the PCB can be
used as a heatsink. In addition, through the use of thermal vias, the thermal pad can be attached directly to a
ground plane or special heatsink structure designed into the PCB. This design optimizes the heat transfer from
the integrated circuit (IC).
For additional information on the PowerPAD package and how to take advantage of its heat dissipating abilities,
refer to Technical Brief, PowerPAD Thermally Enhanced Package, Texas Instruments Literature No. SLMA002
and Application Brief, PowerPAD Made Easy, Texas Instruments Literature No. SLMA004. Both documents are
available at www.ti.com.
The exposed thermal pad dimensions for this package are shown in the following illustration.
13
24
Exposed Thermal Pad
2,40
1,65
1
12
4,48
3,75
Top View
NOTE: All linear dimensions are in millimeters
PPTD029
Exposed Thermal Pad Dimensions
PowerPAD is a trademark of Texas Instruments
PACKAGE OPTION ADDENDUM
www.ti.com
31-Jan-2005
PACKAGING INFORMATION
Orderable Device
Status (1)
Package
Type
Package
Drawing
Pins Package Eco Plan (2)
Qty
TPA0112PWP
ACTIVE
HTSSOP
PWP
24
60
None
CU NIPDAU
Level-1-220C-UNLIM
TPA0112PWPR
ACTIVE
HTSSOP
PWP
24
2000
None
CU NIPDAU
Level-1-220C-UNLIM
Lead/Ball Finish
MSL Peak Temp (3)
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - May not be currently available - please check http://www.ti.com/productcontent for the latest availability information and additional
product content details.
None: Not yet available Lead (Pb-Free).
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Green (RoHS & no Sb/Br): TI defines "Green" to mean "Pb-Free" and in addition, uses package materials that do not contain halogens,
including bromine (Br) or antimony (Sb) above 0.1% of total product weight.
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDECindustry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
Addendum-Page 1
IMPORTANT NOTICE
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www.ti.com/military
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