TPA3120D2
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SLOS507E – MARCH 2007 – REVISED SEPTEMBER 2007
25-W STEREO CLASS-D AUDIO POWER AMPLIFIER
FEATURES
1
•
•
•
•
2
•
•
•
•
•
DESCRIPTION
25-W/ch into a 4-Ω Load from a 27-V Supply
20-W/ch into a 4-Ω Load from a 24-V Supply
Operates from 10 V to 30 V
Efficient Class-D Operation Eliminates Need
for Heat Sinks
Four Selectable, Fixed-Gain Settings
Internal Oscillator (No External Components
Required)
Single-Ended Analog Inputs
Thermal and Short-Circuit Protection With
Auto Recovery
Space-Saving Surface-Mount 24-Pin TSSOP
Package
The TPA3120D2 is a 25-W (per channel) efficient,
Class-D audio power amplifier for driving stereo
speakers in a single-ended configuration or a mono
bridge-tied speaker. The TPA3120D2 can drive
stereo speakers as low as 4 Ω. The efficiency of the
TPA3120D2 eliminates the need for an external heat
sink when playing music.
The gain of the amplifier is controlled by two gain
select pins. The gain selections are 20, 26, 32,
36 dB.
The patented start-up and shut-down sequences
minimize pop noise in the speakers without additional
circuitry.
TPA3120D2
APPLICATIONS
•
Televisions
SIMPLIFIED APPLICATION CIRCUIT
TPA3120D2
1 mF
0.22 mF
Left Channel
LIN
BSR
Right Channel
RIN
ROUT
1 mF
PGNDR
PGNDL
1 mF
BYPASS
AGND
22 mH
470 mF
0.68 mF
0.68 mF
LOUT
22 mH
BSL
470 mF
0.22 mF
10 V to 30 V
AVCC
10 V to 30 V
PVCCL
PVCCR
VCLAMP
Shutdown
Control
Mute Control
SD
1 mF
MUTE
GAIN0
GAIN1
}
4-Step Gain
Control
1
2
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
System Two, Audio Precision are trademarks of Audio Precision, Inc.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2007, Texas Instruments Incorporated
TPA3120D2
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SLOS507E – MARCH 2007 – REVISED SEPTEMBER 2007
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
PWP (TSSOP) PACKAGE
(TOP VIEW)
PVCCL
SD
PVCCL
MUTE
LIN
RIN
BYPASS
AGND
AGND
PVCCR
VCLAMP
PVCCR
1
2
3
4
5
6
7
8
9
10
11
12
24
23
22
21
20
19
18
17
16
15
14
13
PGNDL
PGNDL
LOUT
BSL
AVCC
AVCC
GAIN0
GAIN1
BSR
ROUT
PGNDR
PGNDR
Table 1. TERMINAL FUNCTIONS
TERMINAL
24-PIN
(PWP)
I/O/P
DESCRIPTION
SD
2
I
Shutdown signal for IC (low = disabled, high = operational). TTL logic levels with compliance to
AVCC
RIN
6
I
Audio input for right channel
LIN
5
I
Audio input for left channel
GAIN0
18
I
Gain select least-significant bit. TTL logic levels with compliance to AVCC
GAIN1
17
I
Gain select most-significant bit. TTL logic levels with compliance to AVCC
MUTE
4
I
Mute signal for quick disable/enable of outputs (high = outputs switch at 50% duty cycle, low =
outputs enabled). TTL logic levels with compliance to AVCC
BSL
21
I/O
PVCCL
1, 3
P
Power supply for left-channel H-bridge, not internally connected to PVCCR or AVCC
LOUT
22
O
Class-D 1/2-H-bridge positive output for left channel
NAME
PGNDL
Bootstrap I/O for left channel
23, 24
P
Power ground for left-channel H-bridge
VCLAMP
11
P
Internally generated voltage supply for bootstrap capacitors
BSR
16
I/O
Bootstrap I/O for right channel
ROUT
15
O
Class-D 1/2-H-bridge negative output for right channel
PGNDR
13, 14
P
Power ground for right-channel H-bridge.
PVCCR
10, 12
P
Power supply for right-channel H-bridge, not connected to PVCCL or AVCC
AGND
9
P
Analog ground for digital/analog cells in core
AGND
8
P
Analog ground for analog cells in core
BYPASS
7
O
Reference for preamplifier inputs. Nominally equal to AVCC/8. Also controls start-up time via
external capacitor sizing.
19, 20
P
High-voltage analog power supply. Not internally connected to PVCCR or PVCCL
Die pad
P
Connect to ground. Thermal pad should be soldered down on all applications to secure the
device properly to the printed wiring board.
AVCC
Thermal pad
2
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ABSOLUTE MAXIMUM RATINGS
over operating free-air temperature range (unless otherwise noted)
(1)
VCC
Supply voltage
AVCC, PVCC
VI
Logic input voltage
SD, MUTE, GAIN0, GAIN1
VIN
Analog input voltage
RIN, LIN
Continuous total power dissipation
VALUE
UNIT
–0.3 to 36
V
–0.3 to VCC + 0.3
V
–0.3 to 7
V
See Dissipation Ratings table
TA
Operating free-air temperature range
–40 to 85
°C
TJ
Operating junction temperature range
–40 to 150
°C
Tstg
Storage temperature range
–65 to 150
°C
RL
Load resistance (minimum value)
3.2
Ω
±2
kV
ESD
Electrostatic Discharge
± 500
V
Human-body model (all pins)
(1)
Charged-device model (all
pins)
Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings
only, and functional operations of the device at these or any other conditions beyond those indicated under recommended operating
conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
DISSIPATION RATINGS
(1)
(2)
PACKAGE (1) (2)
TA ≤ 25°C
DERATING FACTOR
TA = 70°C
TA = 85°C
24-pin TSSOP
4.16 W
33.3 mW/°C
2.67 W
2.16 W
For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI
website at www.ti.com.
This data was taken using 1 oz trace and copper pad that is soldered directly to a JEDEC standard high-k PCB. The thermal pad must
be soldered to a thermal land on the printed-circuit board. See the PowerPAD Thermally Enhanced Package application note
(SLMA002).
RECOMMENDED OPERATING CONDITIONS
MIN
MAX
10
30
VCC
Supply voltage
PVCC, AVCC
VIH
High-level input voltage
SD, MUTE, GAIN0, GAIN1
VIL
Low-level input voltage
SD, MUTE, GAIN0, GAIN1
0.8
SD, VI = VCC, VCC = 30 V
125
IIH
High-level input current
MUTE, VI = VCC, VCC = 30 V
125
GAIN0, GAIN1, VI = VCC, VCC = 24 V
125
IIL
TA
Low-level input current
2
1
MUTE, VI = 0 V, VCC = 30 V
1
GAIN0, GAIN1, VI = 0 V, VCC = 24 V
1
–40
85
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V
V
SD, VI = 0, VCC = 30 V
Operating free-air temperature
UNIT
V
μA
μA
°C
3
TPA3120D2
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SLOS507E – MARCH 2007 – REVISED SEPTEMBER 2007
DC CHARACTERISTICS
TA = 25°C, VCC = 24 V, RL = 4 Ω (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
7.5
50
mV
37
mA
| VOS |
Class-D output offset voltage
(measured differentially in BTL
mode as shown in Fig 30)
VI = 0 V, AV = 36 dB
V(BYPASS)
Bypass output voltage
No load
ICC(q)
Quiescent supply current
SD = 2 V, MUTE = 0 V, No load
23
ICC(q)
Quiescent supply current in
mute mode
MUTE = 0.8 V, No load
23
ICC(q)
Quiescent supply current in
shutdown mode
SD = 0.8 V , No load
rDS(on)
Drain-source on-state
resistance
AVCC/8
Gain
GAIN = 2 V
Mute Attenuation
V
mA
1
200
GAIN1 = 0.8 V
G
0.39
mA
mΩ
GAIN0 = 0.8 V
18
20
22
GAIN0 = 2 V
24
26
28
GAIN0 = 0.8 V
30
32
34
GAIN0 = 2 V
34
36
38
VI = 1Vrms
UNIT
–82
dB
dB
AC CHARACTERISTICS
TA = 25°C, VCC = 24 V, RL = 4Ω (unless otherwise noted)
PARAMETER
ksvr
Supply ripple rejection
Output power at 1% THD+N
PO
Output power at 10% THD+N
THD+N
Vn
SNR
Total harmonic distortion +
noise
TEST CONDITIONS
VCC = 24, Vripple = 200 mVPP
Gain = 20 dB
MIN
100 Hz
–48
1 kHz
–52
VCC = 24 V, RL = 4 Ω, f = 1 kHz
16
VCC = 24 V, RL = 8 Ω, f = 1 kHz
8
VCC= 24 V, RL = 4 Ω, f = 1 kHz
20
VCC = 24 V, RL = 8 Ω, f = 1 kHz
10
RL = 4 Ω, f = 1 kHz, PO = 10 W
0.08%
RL = 8 Ω, f = 1 kHz, PO = 5 W
0.08%
UNIT
dB
W
Output integrated noise floor
85
μV
–80
dBV
Crosstalk
PO = 1 W, f = 1 kHz; Gain = 20 dB
–60
dB
Signal-to-noise ratio
Max output at THD+N < 1%, f = 1 kHz,
Gain = 20 dB
99
dB
150
°C
Thermal hysteresis
4
MAX
20 Hz to 22 kHz, A-weighted filter,
Gain = 20 dB
Thermal trip point
fOSC
TYP
°C
30
Oscillator frequency
230
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250
270
kHz
Copyright © 2007, Texas Instruments Incorporated
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SLOS507E – MARCH 2007 – REVISED SEPTEMBER 2007
FUNCTIONAL BLOCK DIAGRAM
FUNCTIONAL BLOCK DIAGRAM
BSL
AVCC
PVCCL
AVDD
REGULATOR
HS
LOUT
+
-
VCLAMP
LS
AVDD
AVDD
PGNDL
LIN
SC
DETECT
AVDD/2
AGND
CONTROL
SD
BIAS
VCLAMP
THERMAL
MUTE
MUTE
CONTROL
OSC/RAMP
BYPASS
GAIN1
BYPASS
AV
CONTROL
GAIN0
SC
DETECT
BSR
PVCCR
HS
ROUT
-
VCLAMP
+
LS
PGNDR
AVDD
AVDD
RIN
AVDD/2
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SLOS507E – MARCH 2007 – REVISED SEPTEMBER 2007
TYPICAL CHARACTERISTICS
All tests are made at frequency = 1 kHz unless otherwise noted.
TOTAL HARMONIC DISTORTION + NOISE
vs
FREQUENCY
TOTAL HARMONIC DISTORTION + NOISE
vs
FREQUENCY
10
THD+N - Total Harmonic Distortion + Noise - %
THD+N - Total Harmonic Distortion + Noise - %
10
VCC = 18 V
RL = 4 W (SE)
Gain = 20 dB
1
PO = 5 W
PO = 1 W
0.1
PO = 2.5 W
0.01
20
1k
100
1
PO = 10 W
PO = 1 W
0.1
PO = 5 W
100
1k
10k 20k
f − Frequency − Hz
f − Frequency − Hz
Figure 1.
Figure 2.
TOTAL HARMONIC DISTORTION + NOISE
vs
FREQUENCY
TOTAL HARMONIC DISTORTION + NOISE
vs
OUTPUT POWER
THD+N - Total Harmonic Distortion + Noise - %
THD+N - Total Harmonic Distortion + Noise - %
6
RL = 4 W (SE)
Gain = 20 dB
0.01
20
10k 20k
10
VCC = 24 V
RL = 8 W (SE)
Gain = 20 dB
1
PO = 2.5 W
PO = 5 W
0.1
PO = 1 W
0.01
20
VCC = 24 V
100
1k
10k 20k
10
RL = 4 W (SE)
Gain = 20 dB
VCC = 24 V
1
VCC = 18 V
VCC = 12 V
0.1
0.01
10 m
100 m
1
f − Frequency − Hz
PO − Output Power − W
Figure 3.
Figure 4.
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40
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TYPICAL CHARACTERISTICS (continued)
All tests are made at frequency = 1 kHz unless otherwise noted.
10
CROSSTALK
vs
FREQUENCY
0
RL = 8 W (SE)
Gain = 20 dB
VCC = 24 V
1
-10
VCC = 18 V
VO = 1 Vrms
-20
RL = 4 W (SE)
Gain = 20 dB
-30
VCC = 18 V
Crosstalk - dB
THD+N - Total Harmonic Distortion + Noise - %
TOTAL HARMONIC DISTORTION + NOISE
vs
OUTPUT POWER
VCC = 12 V
-40
-50
L to R
-60
0.1
-70
-80
R to L
-90
0.01
10 m
100 m
1
PO − Output Power − W
10
-100
20
40
100
10k 20k
1k
f − Frequency − Hz
Figure 5.
Figure 6.
CROSSTALK
vs
FREQUENCY
GAIN/PHASE
vs
FREQUENCY
0
200
-10
VCC = 18 V,
VO = 1 V,
-20
R L = 8 W,
Gain = 20 dB
Gain
20
100
-40
-50
L to R
0
Phase
10
-60
VCC = 24 V
-100
-70
RL = 4 W (SE)
Gain = 20 dB
Lfilt = 33 mH
-200
5
R to L
-80
Cfilt = 1 mF
-90
-100
0
20
100
1k
f − Frequency − Hz
10k 20k
20
Phase - o
15
Gain - dB
Crosstalk - dB
-30
Cdc = 470 mF
100 200
1k 2k
10k 20k
f − Frequency − Hz
Figure 7.
-300
100k
Figure 8.
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TYPICAL CHARACTERISTICS (continued)
All tests are made at frequency = 1 kHz unless otherwise noted.
GAIN/PHASE
vs
FREQUENCY
OUTPUT POWER
vs
SUPPLY VOLTAGE
200
22.5
32
30
150
Gain
20
0
15
Phase
-50
12.5
VCC = 24 V
RL = 8 W (SE)
Gain = 20 dB
Lfilt = 47 mH
10
7.5
-100
PO - Output Power - W
50
Phase - o
Gain - dB
26
100
17.5
24
22
18
16
14
12
THD = 1%
10
-150
8
6
-200
4
5
20
THD = 10%
20
Cfilt = 0.22 mF
Cdc = 470 mF
RL = 4 W (SE)
Gain = 20 dB
28
100 200
1k 2k
10k 20k
-250
100k
2
10
12
14
f − Frequency − Hz
16
18
20
22
24
26
28
30
VSS − Supply Voltage − V
Figure 9.
A.
Dashed
region.
line
represents
thermally
limited
Figure 10.
OUTPUT POWER
vs
SUPPLY VOLTAGE
17
16
15
EFFICIENCY
vs
OUTPUT POWER
100
RL = 8 W (SE)
Gain = 20 dB
90
THD = 10%
70
9
8
7
6
5
4
3
2
1
10
8
80
13
12
11
10
Efficiency - %
PO - Output Power - W
14
THD = 1%
24 V
18 V
60
12 V
50
40
30
20
RL = 4 W (SE)
Gain = 20 dB
10
0
12
14
16
18
20
22
24
26
28
30
0
2
4
6
8
10
12
14
VSS - Supply Voltage - V
PO − Output Power − W
Figure 11.
Figure 12.
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18
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TYPICAL CHARACTERISTICS (continued)
All tests are made at frequency = 1 kHz unless otherwise noted.
EFFICIENCY
vs
OUTPUT POWER
2
90
1.8
80
1.6
24 V
18 V
12 V
ICC − Supply Current − A
100
70
Efficiency - %
SUPPLY CURRENT
vs
OUTPUT POWER
60
50
40
30
RL = 4 W (SE)
Gain = 20 dB
1.4
1.2
1
24 V
0.8
0.6
18 V
0.4
20
12 V
RL = 8 W (SE)
Gain = 20 dB
10
0.2
0
0
0
1
2
3
4
5
6
7
8
9
10
11
12
0
4
8
PO − Output Power − W
16
20
24
28
32
Figure 13.
Figure 14.
SUPPLY CURRENT
vs
OUTPUT POWER
POWER SUPPLY REJECTION RATIO
vs
FREQUENCY
0.9
36
40
0
-10
24 V
Power Supply Rejection Ratio - dB
RL = 8 W,
Gain = 20 dB
0.8
ICC - Supply Current - A
12
PO − Output Power − W
0.7
18 V
0.6
0.5
12 V
0.4
0.3
0.2
0.1
-20
-30
VCC = 24 V
VO(ripple) = 0.2 VPP
RL = 4 W (SE)
Gain = 20 dB
-40
-50
-60
-70
-80
-90
-100
-110
0
0
2.5
5
7.5 10 12.5 15 17.5 20 22.5
PO - Output Power - W
25
-120
20
Figure 15.
100
1k
10k 20k
f − Frequency − Hz
Figure 16.
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TYPICAL CHARACTERISTICS (continued)
All tests are made at frequency = 1 kHz unless otherwise noted.
TOTAL HARMONIC DISTORTION + NOISE
vs
FREQUENCY
TOTAL HARMONIC DISTORTION + NOISE
vs
OUTPUT POWER
VCC = 24 V
RL = 8 W (BTL)
Gain = 20 dB
PO = 20 W
1
0.1
PO = 5 W
PO = 1 W
0.01
0.001
20
100
1k
1
VCC = 18 V
VCC = 12 V
0.1
1
10
Figure 17.
Figure 18.
GAIN/PHASE
vs
FREQUENCY
OUTPUT POWER
vs
SUPPLY VOLTAGE
40
65
Gain
55
0
200
100
VCC = 24 V,
0
RL = 8 W (BTL),
Gain = 20 dB,
Lfilt = 33 mH,
PO - Output Power - W
Phase
50
Phase - °
10
45
THD = 10%
40
35
30
THD = 1%
25
20
15
-100
10
Cfilt = 1 mF
5
-30
100
RL = 8 W (BTL)
Gain = 20 dB
60
300
20
100 m
PO − Output Power − W
20
Gain - dB
VCC = 24 V
f − Frequency − Hz
400
-20
RL = 8 W (BTL)
Gain = 20 dB
0.01
10 m
10k 20k
30
-10
10
THD+N - Total Harmonic Distortion + Noise - %
THD+N - Total Harmonic Distortion + Noise - %
10
1k
10k
f - Frequency - Hz
Figure 19.
-200
200k
0
10
12
14
16
18
20
22
24
26
28
30
VSS − Supply Voltage − V
A.
Dashed
region.
line
represents
thermally
limited
Figure 20.
10
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TYPICAL CHARACTERISTICS (continued)
All tests are made at frequency = 1 kHz unless otherwise noted.
EFFICIENCY
vs
OUTPUT POWER
POWER SUPPLY REJECTION RATIO
vs
FREQUENCY
100
0
Power Supply Rejection Ratio - dB
90
80
Efficiency - %
70
12 V
60
24 V
18 V
50
40
30
20
RL = 8 W (BTL)
Gain = 20 dB
10
0
0
4
8
12
16
20
24
28
32
36
40
-20
VCC = 24 V
VO(ripple) = 200 mV
RL = 8 W (BTL)
Gain = 20 dB
-40
-60
-80
-100
-120
-140
20
PO − Output Power − W
100
1k
10k 20k
f − Frequency − Hz
Figure 21.
Figure 22.
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APPLICATION INFORMATION
CLASS-D OPERATION
This section focuses on the class-D operation of the TPA3120D2.
Traditional Class-D Modulation Scheme
The TPA3120D2 operates in AD mode. There are two main configurations that may be used. For stereo
operation, the TPA3120D2 should be configured in a single-ended (SE) half-bridge amplifier. For mono
applications, TPA3120D2 may be used as a bridge-tied-load (BTL) amplifier. The traditional class-D modulation
scheme, which is used in the TPA3120D2 BTL configuration, has a differential output where each output is 180
degrees out of phase and changes from ground to the supply voltage, VCC. Therefore, the differential prefiltered
output varies between positive and negative VCC, where filtered 50% duty cycle yields
0 V across the load. The class-D modulation scheme with voltage and current waveforms is shown in Figure 23
and Figure 24.
+VCC
0V
Output Current
Figure 23. Class-D Modulation for TPA3120D2 SE Configuration
+VCC
0V
+VCC
0V
+VCC
Differential Voltage
Across Speaker
0V
–VCC
Output Current
Figure 24. Class-D Modulation for TPA3120D2 BTL Configuration
Supply Pumping
One issue encountered in single-ended (SE) class-D amplifier designs is supply pumping. Power-supply pumping
is a rise in the local supply voltage due to energy being driven back to the supply by operation of the class-D
amplifier. This phenomenon is most evident at low audio frequencies and when both channels are operating at
the same frequency and phase. At low levels, power-supply pumping results in distortion in the audio output due
to fluctuations in supply voltage. At higher levels, pumping can cause the overvoltage protection to operate,
which temporarily shuts down the audio output.
12
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Several things can be done to relieve power-supply pumping. The lowest impact is to operate the two inputs out
of phase 180° and reverse the speaker connections. Because most audio is highly correlated, this causes the
supply pumping to be out of phase and not as severe. If this is not enough, the amount of bulk capacitance on
the supply must be increased. Also, improvement is realized by hooking other supplies to this node, thereby,
sinking some of the excess current. Power-supply pumping should be tested by operating the amplifier at low
frequencies and high output levels.
Gain Setting via GAIN0 and GAIN1 Inputs
The gain of the TPA3120D2 is set by two input terminals, GAIN0 and GAIN1.
The gains listed in Table 2 are realized by changing the taps on the input resistors and feedback resistors inside
the amplifier. This causes the input impedance (Zi) to be dependent on the gain setting. The actual gain settings
are controlled by ratios of resistors, so the gain variation from part-to-part is small. However, the input impedance
from part-to-part at the same gain may shift by ±20% due to shifts in the actual resistance of the input resistors.
For design purposes, the input network (discussed in the next section) should be designed assuming an input
impedance of 8 kΩ, which is the absolute minimum input impedance of the TPA3120D2. At the higher gain
settings, the input impedance could increase as high as 72 kΩ.
Table 2. Gain Setting
GAIN1
GAIN0
AMPLIFIER GAIN (dB),
TYPICAL
INPUT IMPEDANCE
(kΩ),
TYPICAL
0
0
20
60
0
1
26
30
1
0
32
15
1
1
36
9
INPUT RESISTANCE
Changing the gain setting can vary the input resistance of the amplifier from its smallest value, 10 kΩ ±20%, to
the largest value, 60 kΩ ±20%. As a result, if a single capacitor is used in the input high-pass filter, the –3-dB
cutoff frequency may change when changing gain steps.
Zf
Ci
Input
Signal
IN
Zi
The –3-dB frequency can be calculated using Equation 1. Use the Zi values given in Table 2.
f =
1
2p Zi Ci
(1)
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INPUT CAPACITOR, Ci
In the typical application, an input capacitor (Ci) is required to allow the amplifier to bias the input signal to the
proper dc level for optimum operation. In this case, Ci and the input impedance of the amplifier (Zi) form a
high-pass filter with the corner frequency determined in Equation 2.
–3 dB
fc =
1
2p Zi Ci
fc
(2)
The value of Ci is important, as it directly affects the bass (low-frequency) performance of the circuit. Consider
the example where Zi is 20 kΩ and the specification calls for a flat bass response down to 20 Hz. Equation 2 is
reconfigured as Equation 3.
Ci =
1
2p Zi fc
(3)
In this example, Ci is 0.4 μF; so, one would likely choose a value of 0.47 μF as this value is commonly used. If
the gain is known and is constant, use Zi from Table 2 to calculate Ci. A further consideration for this capacitor is
the leakage path from the input source through the input network (Ci) and the feedback network to the load. This
leakage current creates a dc offset voltage at the input to the amplifier that reduces useful headroom, especially
in high-gain applications. For this reason, a low-leakage tantalum or ceramic capacitor is the best choice. When
polarized capacitors are used, the positive side of the capacitor should face the amplifier input in most
applications as the dc level there is held at 2 V, which is likely higher than the source dc level. Note that it is
important to confirm the capacitor polarity in the application. Additionally, lead-free solder can create dc offset
voltages, and it is important to ensure that boards are cleaned properly.
Single-Ended Output Capacitor, CO
In single-ended (SE) applications, the dc blocking capacitor forms a high-pass filter with the speaker impedance.
The frequency response rolls of with decreasing frequency at a rate of 20 dB/decade. The cutoff frequency is
determined by
fc = 1/2πCOZL
Table 3 shows some common component values and the associated cutoff frequencies:
Table 3. Common Filter Responses
Speaker Impedance (Ω)
14
CSE – DC Blocking Capacitor (μF)
fc = 60 Hz (–3 dB)
fc = 40 Hz (–3 dB)
fc = 20 Hz (–3 dB)
4
680
1000
2200
8
330
470
1000
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Output Filter and Frequency Response
For the best frequency response, a flat-passband output filter (second-order Butterworth) may be used. The
output filter components consist of the series inductor and capacitor to ground at the LOUT and ROUT pins.
There are several possible configurations, depending on the speaker impedance and whether the output
configuration is single-ended (SE) or bridge-tied load (BTL). Table 4 lists the recommended values for the filter
components. It is important to use a high-quality capacitor in this application. A rating of at least X7R is required.
Table 4. Recommended Filter Output Components
Output Configuration
Speaker Impedance (Ω)
Filter Inductor (μH)
Filter Capacitor (nF)
4
22
680
8
47
390
4
10
1500
8
22
680
Single Ended (SE)
Bridge Tied Load (BTL)
LOUT
Lfilter
LOUT / ROUT
Cfilter
Cfilter
ROUT
Lfilter
Lfilter
Cfilter
Figure 25. BTL Filter Configuration
Figure 26. SE Filter Configuration
Power-Supply Decoupling, CS
The TPA3120D2 is a high-performance CMOS audio amplifier that requires adequate power-supply decoupling
to ensure that the output total harmonic distortion (THD) is as low as possible. Power-supply decoupling also
prevents oscillations for long lead lengths between the amplifier and the speaker. The optimum decoupling is
achieved by using two capacitors of different types that target different types of noise on the power-supply leads.
For higher-frequency transients, spikes, or digital hash on the line, a good low equivalent-series-resistance (ESR)
ceramic capacitor, typically 0.1 μF to 1 μF, placed as close as possible to the device VCC lead works best. For
filtering lower frequency noise signals, a larger aluminum electrolytic capacitor of 470 μF or greater placed near
the audio power amplifier is recommended. The 470-μF capacitor also serves as local storage capacitor for
supplying current during large signal transients on the amplifier outputs. The PVCC terminals provide the power
to the output transistors, so a 470-μF or larger capacitor should be placed on each PVCC terminal. A 10-μF
capacitor on the AVCC terminal is adequate. These capacitors must be properly derated for voltage and
ripple-current rating to ensure reliability.
BSN and BSP Capacitors
The half H-bridge output stages use only NMOS transistors. Therefore, they require bootstrap capacitors for the
high side of each output to turn on correctly. A 220-nF ceramic capacitor, rated for at least 25 V, must be
connected from each output to its corresponding bootstrap input. Specifically, one 220-nF capacitor must be
connected from LOUT to BSL, and one 220-nF capacitor must be connected from ROUT to BSR.
The bootstrap capacitors connected between the BSx pins and their corresponding outputs function as a floating
power supply for the high-side N-channel power MOSFET gate-drive circuitry. During each high-side switching
cycle, the bootstrap capacitors hold the gate-to-source voltage high enough to keep the high-side MOSFETs
turned on.
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VCLAMP Capacitor
To ensure that the maximum gate-to-source voltage for the NMOS output transistors is not exceeded, one
internal regulator clamps the gate voltage. One 1-μF capacitor must be connected from VCLAMP (pin 11) to
ground and must be rated for at least 16 V. The voltages at the VCLAMP terminal may vary with VCC and may
not be used for powering any other circuitry.
VBYP Capacitor Selection
The scaled supply reference (VBYP) nominally provides an AVCC/8 internal bias for the preamplifier stages. The
external capacitor for this reference (CBYP) is a critical component and serves several important functions. During
start-up or recovery from shutdown mode, CBYP determines the rate at which the amplifier starts. The start up
time is proportional to 0.5 s per microfarad. Thus, the recommended 1-μF capacitor results in a start-up time of
approximately 500 ms. The second function is to reduce noise produced by the power supply caused by coupling
with the output drive signal. This noise could result in degraded power-supply rejection and THD+N.
The circuit is designed for a CBYP value of 1 μF for best pop performance. The input capacitors should have the
same value. A ceramic or tantalum low-ESR capacitor is recommended.
SHUTDOWN OPERATION
The TPA3120D2 employs a shutdown mode of operation designed to reduce supply current (ICC) to the absolute
minimum level during periods of nonuse for power conservation. The SHUTDOWN input terminal should be held
high (see specification table for trip point) during normal operation when the amplifier is in use. Pulling
SHUTDOWN low causes the outputs to mute and the amplifier to enter a low-current state. Never leave
SHUTDOWN unconnected, because amplifier operation would be unpredictable.
For the best power-up pop performance, place the amplifier in the shutdown or mute mode prior to applying the
power-supply voltage.
MUTE Operation
The MUTE pin is an input for controlling the output state of the TPA3120D2. A logic high on this terminal causes
the outputs to run at a constant 50% duty cycle. A logic low on this pin enables the outputs. This terminal may be
used as a quick disable/enable of outputs when changing channels on a television or transitioning between
different audio sources.
The MUTE terminal should never be left floating. For power conservation, the SHUTDOWN terminal should be
used to reduce the quiescent current to the absolute minimum level.
USING LOW-ESR CAPACITORS
Low-ESR capacitors are recommended throughout this application section. A real (as opposed to ideal) capacitor
can be modeled simply as a resistor in series with an ideal capacitor. The voltage drop across this resistor
minimizes the beneficial effects of the capacitor in the circuit. The lower the equivalent value of this resistance,
the more the real capacitor behaves like an ideal capacitor.
SHORT-CIRCUIT PROTECTION
The TPA3120D2 has short-circuit protection circuitry on the outputs that prevents damage to the device during
output-to-output shorts and output-to-GND shorts after the filter and output capacitor (at the speaker terminal.)
Directly at the device terminals, the protection circuitry prevents damage to device during output-to-output,
output-to-ground, and output-to-supply. When a short circuit is detected on the outputs, the part immediately
disables the output drive. This is an unlatched fault. Normal operation is restored when the fault is removed.
16
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THERMAL PROTECTION
Thermal protection on the TPA3120D2 prevents damage to the device when the internal die temperature
exceeds 150°C. There is a ±15°C tolerance on this trip point from device to device. Once the die temperature
exceeds the thermal set point, the device enters into the shutdown state and the outputs are disabled. This is not
a latched fault. The thermal fault is cleared once the temperature of the die is reduced by 30°C. The device
begins normal operation at this point with no external system interaction.
PRINTED-CIRCUIT BOARD (PCB) LAYOUT
Because the TPA3120D2 is a class-D amplifier that switches at a high frequency, the layout of the printed-circuit
board (PCB) should be optimized according to the following guidelines for the best possible performance.
• Decoupling capacitors—The high-frequency 0.1-μF decoupling capacitors should be placed as close to the
PVCC (pins 1, 3, 10, and 12) and AVCC (pins 19 and 20) terminals as possible. The VBYP (pin 7) capacitor
and VCLAMP (pin 11) capacitor should also be placed as close to the device as possible. Large (220-μF or
greater) bulk power-supply decoupling capacitors should be placed near the TPA3120D2 on the PVCCL and
PVCCR terminals.
• Grounding—The AVCC (pins 19 and 20) decoupling capacitor and VBYP (pin 7) capacitor should each be
grounded to analog ground (AGND, pins 8 and 9). The PVCCx decoupling capacitors and VCLAMP
capacitors should each be grounded to power ground (PGND, pins 13, 14, 23, and 24). Analog ground and
power ground should be connected at the thermal pad, which should be used as a central ground connection
or star ground for the TPA3120D2.
• Output filter—The reconstruction filter (L1, L2, C9, and C16) should be placed as close to the output terminals
as possible for the best EMI performance. The capacitors should be grounded to power ground.
• Thermal pad—The thermal pad must be soldered to the PCB for proper thermal performance and optimal
reliability. The dimensions of the thermal pad and thermal land are described in the mechanical section at the
back of the data sheet. See TI Technical Briefs SLMA002 and SLOA120 for more information about using the
thermal pad. For recommended PCB footprints, see figures at the end of this data sheet.
For an example layout, see the TPA3120D2 Evaluation Module (TPA3120D2EVM) User Manual, (SLOU189).
Both the EVM user manual and the thermal pad application note are available on the TI Web site at
http://www.ti.com.
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VCC
470 mF
22 mH
470 mF
+LOUT
1.0 mF
470 mF
1
2
3
4
5
6
7
8
9
10
11
12
Right In
1.0 mF
1.0 mF
PVCCL
SD
PVCCL
MUTE
LIN TPA3120
RIN
BYPASS
AGND
AGND
PVCCR
VCLAMP
PVCCR
THERMAL
1.0 mF
Left In
PGNDL
PGNDL
LOUT
BSL
AVCC
AVCC
GAIN0
GAIN1
BSR
ROUT
PGNDR
PGNDR
24
23
22
21
20
19
18
17
16
15
14
13
0.68 mF
0.22 mF
-LOUT
VCC
-ROUT
0.22 mF
0.68 mF
25
Shutdown
Control
22 mH
+ROUT
Mute
Control
470 mF
1.0 mF
1.0 mF
0.1 mF
10 mF
Figure 27. Schematic for Single-Ended (SE) Configuration
VCC
22 mH
470 mF
1.0 mF
1
2
3
4
5
6
7
8
9
10
11
12
+ In
- In
1.0 mF
+OUT
1.0 mF
1.0 mF
PVCCL
SD
PVCCL
MUTE
LIN TPA3120
RIN
BYPASS
AGND
AGND
PVCCR
VCLAMP
PVCCR
THERMAL
470 mF
PGNDL
PGNDL
LOUT
BSL
AVCC
AVCC
GAIN0
GAIN1
BSR
ROUT
PGNDR
PGNDR
24
23
22
21
20
19
18
17
16
15
14
13
0.68 mF
0.22 mF
VCC
0.22 mF
0.68 mF
25
Shutdown
Control
22 mH
-OUT
Mute
Control
1.0 mF
1.0 mF
0.1 mF
10 mF
Figure 28. Schematic for Bridge-Tied (BTL) Configuration
18
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BASIC MEASUREMENT SYSTEM
This section focuses on methods that use the basic equipment listed below:
• Audio analyzer or spectrum analyzer
• Digital multimeter (DMM)
• Oscilloscope
• Twisted-pair wires
• Signal generator
• Power resistor(s)
• Linear regulated power supply
• Filter components
• EVM or other complete audio circuit
Figure 29 shows the block diagrams of basic measurement systems for class-AB and class-D amplifiers. A sine
wave is normally used as the input signal because it consists of the fundamental frequency only (no other
harmonics are present). An analyzer is then connected to the audio power amplifier (APA) output to measure the
voltage output. The analyzer must be capable of measuring the entire audio bandwidth. A regulated dc power
supply is used to reduce the noise and distortion injected into the APA through the power pins. A System Two™
audio measurement system (AP-II) by Audio Precision™ includes the signal generator and analyzer in one
package.
The generator output and amplifier input must be ac-coupled. However, the EVMs already have the ac-coupling
capacitors, (CIN), so no additional coupling is required. The generator output impedance should be low to avoid
attenuating the test signal, and is important because the input resistance of APAs is not high. Conversely, the
analyzer input impedance should be high. The output resistance, ROUT, of the APA is normally in the hundreds of
milliohms and can be ignored for all but the power-related calculations.
Figure 29(a) shows a class-AB amplifier system. It takes an analog signal input and produces an analog signal
output. This amplifier circuit can be directly connected to the AP-II or other analyzer input.
This is not true of the class-D amplifier system shown in Figure 29(b), which requires low-pass filters in most
cases in order to measure the audio output waveforms. This is because it takes an analog input signal and
converts it into a pulse-width modulated (PWM) output signal that is not accurately processed by some
analyzers.
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Power Supply
Signal
Generator
APA
Analyzer
20 Hz - 20 kHz
RL
(a) Basic Class-AB
Power Supply
Lfilt
Signal
Generator
Class-D APA
Cfilt
RL
Analyzer
20 Hz - 20 kHz
(b) Traditional Class-D
Figure 29. Audio Measurement Systems
20
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SE Input and SE Output (TPA3120D2 Stereo Configuration)
The SE input and output configuration is used with class-AB amplifiers. A block diagram of a fully SE
measurement circuit is shown in Figure 30. SE inputs normally have one input pin per channel. In some cases,
two pins are present; one is the signal and the other is ground. SE outputs have one pin driving a load through
an output ac-coupling capacitor and the other end of the load is tied to ground. SE inputs and outputs are
considered to be unbalanced, meaning one end is tied to ground and the other to an amplifier input/output.
The generator should have unbalanced outputs, and the signal should be referenced to the generator ground for
best results. Unbalanced or balanced outputs can be used when floating, but they may create a ground loop that
affects the measurement accuracy. The analyzer should have balanced inputs to cancel out any common-mode
noise in the measurement.
Evaluation Module
Audio Power
Amplifier
Generator
Analyzer
CIN
VGEN
RIN
RGEN
Lfilt
Cfilt
Twisted-Pair Wire
CL
RL
RANA
CANA
RANA
CANA
Twisted-Pair Wire
Figure 30. SE Input—SE Output Measurement Circuit
The following general rules should be followed when connecting to APAs with SE inputs and outputs:
• Use an unbalanced source to supply the input signal.
• Use an analyzer with balanced inputs.
• Use twisted-pair wire for all connections.
• Use shielding when the system environment is noisy.
• Ensure the cables from the power supply to the APA, and from the APA to the load, can handle the large
currents (see Table 5).
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DIFFERENTIAL INPUT AND BTL OUTPUT (TPA3120D2 Mono Configuration)
Many of the class-D APAs and many class-AB APAs have differential inputs and bridge-tied-load (BTL) outputs.
Differential inputs have two input pins per channel and amplify the difference in voltage between the pins.
Differential inputs reduce the common-mode noise and distortion of the input circuit. BTL is a term commonly
used in audio to describe differential outputs. BTL outputs have two output pins providing voltages that are 180°
out of phase. The load is connected between these pins. This has the added benefits of quadrupling the output
power to the load and eliminating a dc-blocking capacitor.
A block diagram of the measurement circuit is shown in Figure 31. The differential input is a balanced input,
meaning the positive (+) and negative (–) pins have the same impedance to ground. Similarly, the SE output
equates to a balanced output.
Evaluation Module
Audio Power
Amplifier
Generator
Analyzer
CIN
RGEN
VGEN
Lfilt
RIN
Cfilt
CIN
RGEN
RL
Lfilt
RIN
Cfilt
Twisted-Pair Wire
RANA
CANA
RANA
CANA
Twisted-Pair Wire
Figure 31. Differential Input, BTL Output Measurement Circuit
The generator should have balanced outputs, and the signal should be balanced for best results. An unbalanced
output can be used, but it may create a ground loop that affects the measurement accuracy. The analyzer must
also have balanced inputs for the system to be fully balanced, thereby cancelling out any common-mode noise in
the circuit and providing the most accurate measurement.
The following general rules should be followed when connecting to APAs with differential inputs and BTL outputs:
• Use a balanced source to supply the input signal.
• Use an analyzer with balanced inputs.
• Use twisted-pair wire for all connections.
• Use shielding when the system environment is noisy.
• Ensure that the cables from the power supply to the APA, and from the APA to the load, can handle the large
currents (see Table 5).
Table 5 shows the recommended wire size for the power supply and load cables of the APA system. The real
concern is the dc or ac power loss that occurs as the current flows through the cable. These recommendations
are based on 12-inch (30.5-cm)-long wire with a 20-kHz sine-wave signal at 25°C.
Table 5. Recommended Minimum Wire Size for Power Cables
22
DC POWER LOSS
(mW)
AWG Size
AC POWER LOSS
(mW)
POUT (W)
RL(Ω)
10
4
18
22
16
40
18
42
2
4
18
22
3.2
8
3.7
8.5
1
8
22
28
2
8
2.1
8.1
< 0.75
8
22
28
1.5
6.1
1.6
6.2
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PACKAGE OPTION ADDENDUM
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10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
(4/5)
(6)
TPA3120D2PWP
NRND
HTSSOP
PWP
24
60
RoHS & Green
NIPDAU
Level-3-260C-168 HR
-40 to 85
TPA3120D2
TPA3120D2PWPR
NRND
HTSSOP
PWP
24
2000
RoHS & Green
NIPDAU
Level-3-260C-168 HR
-40 to 85
TPA3120D2
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of
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