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TPA6166A2
SLAS997B – MARCH 2014 – REVISED JANUARY 2015
TPA6166A2 3.5-mm Jack Detect and Headset Interface IC
1 Features
3 Description
•
The TPA6166A2 single-chip headset interface IC
simplifies the challenges of detecting what kind of
device an end user has plugged into the headphone
jack while delivering excellent audio quality. The
device enables smaller end products by integrating a
high-performance, low-power DirectPath variableattenuation class-G stereo headphone amplifier,
variable-gain microphone preamplifier with bias with
advanced accessory detection circuitry, all in a tiny
5-mm × 5-mm terminal, 0.4-mm pitch WCSP
package.
1
•
•
•
•
•
•
•
•
•
Ultra Low-Power, High-Performance DirectPath™
Class-G Headphone Amplifier
– Ground-Centered Output Eliminates DCBlocking Capacitors
– 30 mW/Ch into 32 Ω / Ch at 1% THD+N
– –42 dB to +6 dB Volume Control
– 2.0 µV Output Noise at –42 dB Gain
– 91-dB PSRR
– Ground Loop Rejection for Reducing Crosstalk
Fully Differential Mic Preamplifier With Variable
Gain and 3.4-µV Low Noise
– Integrated AC-Coupling Capacitor
– Ground Loop Rejection for Reducing
Headphone to Mic Crosstalk
Choice of Two Mic Bias Voltages: 2.0 V and 2.6 V
– 92-dB PSRR
– Integrated Programmable Mic Bias Resistor
Advanced Accessory Insertion, Removal, and
Type Detection
Passive Multi-button Support Using 10-Bit SAR
ADC
– Implements Proprietary Scheme to Reduce
Error Caused by Audio Playback Signal in
Presence of Finite Resistance on Headset
Ground Return Path
Integrated Level-4 IEC ESD Protection on Jack
Connected Pins (on EVM)
Ultra Low-Power Chip Shutdown Mode
I2C Interface
Short-Circuit Protection
0.4-mm Pitch 25-Ball WCSP
The class-G headphone amplifier maximizes battery
life by adjusting the supply voltage of the headphone
amplifier based on audio signal level. With 8-µV
output noise at 0-dB gain and PSRR of 91 dB, the
headphone amplifier provides excellent audio
performance. DirectPath eliminates the need for DCblocking capacitors. The microphone preamplifier has
two programmable gains of 12 dB and 24 dB, and
3.4 µV input referred noise.
The microphone bias voltage has two programmable
settings of 2 V and 2.6 V. The bias output drives up
to 1.2 mA of current, has a low output noise of 2 µV,
and 92-dB PSRR, providing excellent rejection of
power supply noise in wireless handsets.
The advanced accessory detection algorithm
automatically detects six supported accessories and
enables or disables internal components.
Device Information(1)
PART NUMBER
Smart Phones and Wireless Handsets
Portable Tablets
Notebook PCs and Docking Stations
WSCP (25)
BODY SIZE (NOM)
2.50 mm × 2.50 mm
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
Simplified Schematic
CPVDD CPVSS C1P C1N
2 Applications
•
•
•
PACKAGE
TPA6166A2
INL
INR
Class-G
Stereo Headphone
Amplifier
RING1
ESD
Prot.
Mic
Bias
Switch
Matrix
and
Detection
Circuit
MOUTP
MOUTN
SDA
SCL
IRQ
VDD MICVDD
Digital
Interface
and
Control
TIP
JACK_SENSE
RING2
SLEEVE
SAR
ADC
GND1
GND2 PGND
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
TPA6166A2
SLAS997B – MARCH 2014 – REVISED JANUARY 2015
www.ti.com
Table of Contents
1
2
3
4
5
6
7
Features ..................................................................
Applications ...........................................................
Description .............................................................
Revision History.....................................................
Pin Configuration and Functions .........................
Specifications.........................................................
1
1
1
2
3
4
6.1
6.2
6.3
6.4
6.5
6.6
6.7
6.8
6.9
4
4
4
4
5
6
7
8
9
Absolute Maximum Ratings ......................................
ESD Ratings..............................................................
Recommended Operating Conditions.......................
Thermal Information ..................................................
Electrical Characteristics...........................................
Electrical Characteristics, Audio Amplifiers...............
Electrical Characteristics, Mic Preamplifier and Bias
Timing Requirements ................................................
Typical Characteristics ..............................................
Detailed Description ............................................ 13
7.1 Overview ................................................................. 13
7.2 Functional Block Diagram ....................................... 13
7.3 Feature Description................................................. 13
7.4 Device Functional Modes........................................ 19
7.5 Register Maps ......................................................... 23
8
Application and Implementation ........................ 38
8.1 Application Information............................................ 38
8.2 Typical Application .................................................. 38
9
Power Supply Recommendations...................... 40
9.1 Decoupling Capacitors ............................................ 40
10 Layout................................................................... 41
10.1 Layout Guidelines ................................................. 41
10.2 Layout Example .................................................... 42
11 Device and Documentation Support ................. 43
11.1
11.2
11.3
11.4
Development Support ...........................................
Trademarks ...........................................................
Electrostatic Discharge Caution ............................
Glossary ................................................................
43
43
43
43
12 Mechanical, Packaging, and Orderable
Information ........................................................... 43
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision A (June 2014) to Revision B
•
Page
Added Pin Configuration and Functions section, ESD Ratings table, Feature Description section, Device Functional
Modes, Application and Implementation section, Power Supply Recommendations section, Layout section, Device
and Documentation Support section, and Mechanical, Packaging, and Orderable Information section .............................. 1
Changes from Original (January 2014) to Revision A
Page
•
Changed to new data sheet format ........................................................................................................................................ 1
•
Added specifications and application information ................................................................................................................. 1
•
Changed status to Production Data ...................................................................................................................................... 1
2
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SLAS997B – MARCH 2014 – REVISED JANUARY 2015
5 Pin Configuration and Functions
YFF Package
Top View
A1
A2
A3
GND1
INR
INL
A4
A5
CPVDD JACK_SENSE
B1
B2
B3
B4
B5
NC*
GND2
IRQ
MOUTN
TIP
C1
C2
C3
C4
C5
CPVSS
SCL
GND
MOUTP
RING1
D1
D2
D3
D4
D5
C1N
SDA
PGND
NC*
MICVDD
E1
E2
E3
E4
E5
C1P
PGND
VDD
RING2
SLEEVE
All NC pins should be left floating. Do not connect them to GND.
Pin Functions
PIN
I/O / TYPE
DESCRIPTION
NAME
NO.
GND1
A1
P
Analog / digital ground 1
INR
A2
I
Headphone right channel input
INL
A3
I
Headphone left channel input
CPVDD
A4
I
Headphone charge-pump positive supply (internally generated). Connect a 1-µF capacitor
to ground.
JACK_SENSE
A5
I/O
Connect to headset jack terminal 5 (for mechanical switch). If mechanical switch is not
available, then this terminal can be kept floating.
NC (Floating)
B1
O
Leave floating (no connection)
GND2
B2
I
Ground 2 - Connect to ground 1 on board.
IRQ
B3
O
Active low interrupt output
MOUTN
B4
O
Microphone preamplifier negative output
TIP
B5
O
Left headphone / line output. Connect to headset jack TIP (terminal 1).
CPVSS
C1
I
Headphone charge-pump negative supply (internally generated). Connect a 1-µF capacitor
to ground.
SCL
C2
I
I2C clock line
GND
C3
I
Connect to ground
MOUTP
C4
O
Microphone preamplifier positive output
RING1
C5
O
Right headphone / line output. Connect to headset jack RING1 (terminal 2).
C1N
D1
P
Charge pump flying capacitor positive terminal
SDA
D2
I/O
PGND
I2C data line
D3, E2
P
Power ground
NC (Floating)
D4
O
Leave floating (no connection)
MICVDD
D5
P
Analog supply
C1P
E1
P
Charge pump flying capacitor negative terminal
VDD
E3
P
Analog / digital supply
RING2
E4
I/O
Connect to headset jack RING2 (terminal 3)
SLEEVE
E5
I/O
Connect to headset jack SLEEVE (terminal 4)
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6 Specifications
6.1 Absolute Maximum Ratings
over operating temperature range, TA = 25°C (unless otherwise noted)
(1)
Supply voltage, VDD
Microphone supply voltage, MICVDD
Output continuous total power dissipation
MAX
UNIT
2
V
–0.3
3.9
V
See Thermal Information
Storage temperature, Tstg
(1)
MIN
–0.3
–65
85
°C
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
6.2 ESD Ratings
VALUE
V(ESD)
(1)
(2)
Electrostatic discharge
Human body model (HBM), per ANSI/ESDA/JEDEC JS-001 (1)
±2000
Charged-device model (CDM), per JEDEC specification JESD22C101 (2)
±500
UNIT
V
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
6.3 Recommended Operating Conditions
MIN
MAX
UNIT
VDD
Supply voltage
1.7
1.9
MICVDD
Microphone supply voltage
2.4
3.6
V
TA
Operating temperature
–25
85
°C
Line Driver Application, RL = 10 kΩ, AV ≥ 0 dB, specified by design
470
pF
CL,Max
Maximum load
capacitance
Line Driver Application, RL = 10 kΩ, AV ≤ 0 dB, LO_EXT_STAB = 1,
specified by design
470
Headphone Application, RL = 32 Ω, specified by design
200
TJ
Operating junction temperature
–25
150
V
°C
6.4 Thermal Information
TPA6166A2
THERMAL METRIC (1)
YFF (WSCP)
UNIT
25 PINS
RθJA
Junction-to-ambient thermal resistance
67
RθJC(top)
Junction-to-case (top) thermal resistance
18
RθJB
Junction-to-board thermal resistance
38
ψJT
Junction-to-top characterization parameter
0.1
ψJB
Junction-to-board characterization parameter
36
(1)
4
°C/W
For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.
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SLAS997B – MARCH 2014 – REVISED JANUARY 2015
6.5 Electrical Characteristics
VDD =00 1.8 V, MICVDD = 3.0 V, AV = 0 dB, CIN = 0.47 µF, CFLY = 1.0 μF, CCPVDD = CCPVSS = 1.0 μF, RHP = 32 Ω, outputs in
phase, TA = 25°C (unless otherwise noted).
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
VIH
Input logic high
SDA, SCL
VIL
Input logic low
SDA, SCL
VOL
Output logic low
IRQ
|IIH|
Logic high input
leakage current
SDA, SCL
1
|IIL|
Logic low input
leakage current
SDA, SCL
1
|IOH|
Logic high output
leakage current
IRQ
0.4
IOL = 3 mA pullup current
Audio playback (both
channels), 100-µW output into
32 Ω
2-way call, no signal into 32 Ω
2-way call, 100-µW output into
32 Ω
Accessory not inserted,
mechanical switch is open
(JACK_SENSE=1)
(1)
µA
1
IVDD
2.38
IMICVDD
0.21
mA
PCONS (1)
4.91
mW
IVDD
3.74
mA
IMICVDD
0.21
mA
PCONS (1)
7.35
mW
IVDD
2.36
mA
IMICVDD
0.96
mA
PCONS (1)
6.35
mW
IVDD
3.68
mA
IMICVDD
0.96
mA
PCONS (1)
8.74
mW
10.84
µA
IVDD
Accessory not inserted
V
0.2×VDD
VIRQ = 3.3 V
Audio playback (both
channels), no signal into 32 Ω
Power consumption
UNIT
1.4
mA
IMICVDD
1.05
µA
PCONS (1)
22.7
µW
150.9
µA
IVDD
IMICVDD
1.05
µA
PCONS (1)
278.3
µW
IVDD
Accessory inserted and in sleep
IMICVDD
mode
PCONS (1)
108.1
µA
1.06
µA
197.8
µW
Total power consumption from VDD and MICVDD.
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6.6 Electrical Characteristics, Audio Amplifiers
VDD = 1.8 V, MICVDD = 3.0 V, AV = 0 dB, CIN = 0.47 µF, CFLY = 1.0 μF, CCPVDD = CCPVSS = 1.0 μF, RL = 32 Ω, outputs in
phase, TA = 25°C (unless otherwise noted).
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
HEADPHONE AND LINE-OUT AMPLIFIERS
6
dB
AV,Max
Programmable gain range
AV = 6 dB
5.0
6.0
7.0
dB
AV,Min
AV = -42 dB
-43
-42
-41
dB
ΔAV
-42
Gain step size
-42 dB ≤ AV ≤ 6 dB
Gain matching
Between left and right channels
1
–0.5
Mute attenuation
PO
Total harmonic distortion plus
noise
THD+N = 1%, f = 1 kHz, RL = 32 Ω, single
channel on
29.1
THD+N = 1%, f = 1 kHz, RL = 32 Ω,
C both channels on
23.2
THD+N = 1%, f = 1 kHz, RL = 16 Ω, single
channel on
43.0
THD+N = 1%, f = 1 kHz, RL = 16 Ω, The
processing of Request 596221 was completed at
10:19 on 28 Jan 2015. Click here to access the
data Click here to access the HTML data both
channels on
30.2
RL = 16 Ω, PO = 10 mW, f = 1 kHz
0.021%
RL = 16 Ω, PO = 0.1 mW, f = 1 kHz
0.057%
RL = 10 kΩ, VOUT = 1 VRMS, f = 1 kHz
Power supply rejection ratio
EN
Output noise
(1)
Crosstalk between left and right
channels
88
71
AV = 0 dB
8.0
AV = -30 dB
2.0
AV = -42 dB
2.0
RL = 16 Ω, f = 1 kHz, PO = 5 mW
–56
RL = 32 Ω, f = 1 kHz, PO = 25 mW
–62
Amplifier input resistance
Output offset voltage
AV = 0 dB
VOUT,Max
Max line output voltage
RL = 10 kΩ
fC,LPF
Input low-pass filter 3-dB cutoff
frequency (2)
µVRMS
dB
kΩ
0.5
mV
VRMS
AV = 0 dB
45.1
kHz
Low-pass filter passband gain (2)
f = 10 Hz to 15 kHz, dc-coupled inputs with
VCM = 0 V
–0.4
dB
Low-pass filter stopband gain (2)
f = 145 kHz
–16
dB
1.3
MHz
Charge pump frequency
Power consumption
6
dB
20
–0.5
AV = 0 dB, Volume Slewing
Enabled, RL = 32 Ω, peak
voltage, 32 samples / second
Into shutdown
–83
Out of
shutdown
–69
PO = 0.5 mW, RL = 32 Ω
(1)
(2)
(3)
mW
1
Click and pop (1)
RL
dB
91
f = 10 kHz, 100 mVP-P ripple on VDD
VOOS
fCP
70
f = 217 Hz, 100 mVP-P ripple on VDD
RIN
dB
0.014%
f = dc, VDD = 1.7 V to 1.9 V, AV = 0 dB
PSRR
0.5
103.7
Output power
THD+N
dB
(3)
6.2
PO = 5 mW, RL = 32 Ω, THRH = 1
13.3
PO = 30 mW, RL = 32 Ω, THRH = 0
56.9
Minimum headphone load
dBV
32
mW
7.8
Ω
A-weighted
Measured with respect to gain at 997 Hz
Per output channel
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6.7 Electrical Characteristics, Mic Preamplifier and Bias
VDD = 1.8 V, MICVDD = 3.0 V, TA = 25°C (unless otherwise noted).
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
Programmed for high value, MICVDD ≥ 2.8 V
2.45
2.6
2.75
Programmed for low value
1.88
2.0
2.12
UNIT
MICROPHONE BIAS
VBIAS
Microphone bias voltage
IOUT
Max bias output current
RBIAS
Bias output resistance
Internal bias resistor bypassed (MICR = 011)
1.2
Bias output noise (1)
EN
PSRR
MicZ
Power supply rejection ratio
Microphone Capsule Impedance
mA
MICR = 000
2.09
2.2
2.31
MICR = 001
2.47
2.6
2.73
MICR = 010
2.85
3.0
3.15
MICR = 011
kΩ
0.13
Between SLEEVE and RING2, BW = 100 Hz to 7 kHz,
2.2 kΩ load between SLEEVE and RING2, MICR = 000,
VBIAS = 2.0 V
Measured between SLEEVE and
RING2, 2.2 kΩ load between
SLEEVE and RING2,
MICR = 000, VBIAS = 2.6 V
V
2.0
µVRMS
f = dc,
MICVDD = 2.8 V to
3.6 V
92
f = 2 kHz, 100 mVP-P
ripple,
MICVDD = 3.0 V
73
f = 2 kHz, 100 mVP-P
ripple,
MICVDD = 2.8 V
73
Measured between Mic and GND
before insertion
dB
1500
20000
Ω
MICROPHONE PREAMPLIFIER
Programmed for high value, f = 997 Hz
23
24
25
Programmed for low value, f = 997 Hz
11
12
13
AV
Preamplifier gain
EN
Input referred noise (1)
f = 100 Hz to 7 kHz, AV = 24 dB, Mic on SLEEVE, 2.2 kΩ
load between SLEEVE and RING2, MICR = 000,
VBIAS = 2.0 V
THD+N
Total harmonic distortion plus
noise
VOUT = 1 VRMS
Power supply rejection ratio
VCMO
Output Common Mode
fC,LO
Lower -3 dB frequency of HPF (2)
fC,HI
Upper -3 dB frequency of
amplifier (2)
(1)
(2)
Measured between MOUTPMOUTN, 2.2 kΩ between
SLEEVE and RING2,
MICR = 000, VBIAS = 2.6 V
µVRMS
0.095
%
Measured between MOUTP-MOUTN, 6.04 kΩ between
SLEEVE and RING2, MICR = 010, VBIAS = 2.0 V, f = dc,
MICVDD = 2.4 V to 3.6 V
PSRR
3.4
dB
f = dc,
MICVDD = 2.8 V to
3.6 V
f = 2 kHz, 100 mVP-P
ripple on MICVDD
MICVDD = 2.4 V – 3.6V
74
109.5
dB
78
0.4×MICVDD
V
20
Hz
260
kHz
A-weighted
Measured with respect to gain at 997 Hz
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6.8 Timing Requirements
For I2C interface signals and voltage power-up sequence, over recommended operating conditions (unless otherwise noted).
Timing is specified by design.
MIN MAX
No wait states
400
UNIT
fSCL
Frequency, SCL
tw(H)
Pulse duration, SCL high
0.6
μs
tw(L)
Pulse duration, SCL low
1.3
μs
tsu1
Setup time, SDA to SCL
100
ns
th1
Hold time, SCL to SDA
10
ns
t(buf)
Bus free time between stop and start condition
1.3
μs
tsu2
Setup time, SCL to start condition
0.6
μs
th2
Hold time, start condition to SCL
0.6
μs
tsu3
Setup time, SCL to stop condition
0.6
tSP
Pulse width of surpressed spike
0
tw(H)
kHz
μs
50
ns
tw(L)
SCL
tsu1
th1
SDA
T0027-02
Figure 1. SCL and SDA Timing
SCL
t(buf)
th2
tsu2
tsu3
SDA
Start
Condition
Stop
Condition
T0028-01
Figure 2. Start and Stop Conditions Timing
8
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6.9 Typical Characteristics
10
In Phase
Out of Phase
1
0.1
0.01
0.1
1
10
THD+N − Total Harmonic Distortion + Noise − %
THD+N − Total Harmonic Distortion + Noise − %
VDD = 1.8 V, MICVDD = 3.0 V, AV = 0 dB, CIN = 0.47 µF, CFLY = 1.0 μF, CCPVDD = CCPVSS = 1.0 μF, RHP = 32 Ω, outputs in
phase, TA = 25°C (unless otherwise noted).
50
10
In Phase
Out of Phase
1
0.1
0.01
0.1
1
PO − Output Power per Channel − mW
RL = 16 Ω
VDD = 1.8 V
f - 1 kHz
Gain = 0 dB
50
RL = 32 Ω
VDD = 1.8 V
f - 1 kHz
Gain = 0 dB
Figure 4. Headphone Total Harmonic Distortion + Noise vs
Output Power
40
10
PO = 100 uW per Channel
PO = 10 mW per Channel
1
0.1
0.01
PO − Output Power per Channel − mW
THD+N − Total Harmonic Distortion + Noise − %
Figure 3. Headphone Total Harmonic Distortion + Noise vs
Output Power
10
1
Both Channels On − In phase
0.1
0.001
20
100
1k
f − Frequency − Hz
10k
10
20k
100
1000
10000
RL − Load Resistance − W
RL = 16 Ω
VDD = 1.8 V
Gain = 0 dB
Figure 5. Headphone Total Harmonic Distortion + Noise vs
Frequency
VDD = 1.8 V
THD+N = 1%
f = 1 kHz
Gain = 0 dB
Figure 6. Headphone Output Power vs Load Resistance
200
100
100
80
IDD − Supply Current − mA
PSRR − Power Supply Rejection Ratio − dB
10
PO − Output Power per Channel − mW
60
40
10
20
Both Channels On − In phase
0
20
100
VDD = 1.8 V
1k
f − Frequency − Hz
RL = 16 Ω
10k
20k
1
0.001
0.01
0.1
1
10
50
PO − Output Power per Channel− mW
Gain = 0 dB
Figure 7. Headphone Psrr vs Frequency
VDD = 1.8 V
f = 1kHz
RL = 16 Ω
THRH = 0
Gain = 0 dB
Figure 8. Headphone Supply Current vs Total Output Power
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Typical Characteristics (continued)
VDD = 1.8 V, MICVDD = 3.0 V, AV = 0 dB, CIN = 0.47 µF, CFLY = 1.0 μF, CCPVDD = CCPVSS = 1.0 μF, RHP = 32 Ω, outputs in
phase, TA = 25°C (unless otherwise noted).
2
1
V − Voltage − V
IDD − Supply Current − mA
100
10
0
−1
Both Channels On − In phase
1
0.001
0.01
0.1
1
10
−2
−100
40
0
100
PO − Output Power per Channel− mW
RL = 32 Ω
THRH = 0
VDD = 1.8 V
f = 1kHz
Gain = 0 dB
VIN = 0.5 VRMS
200
300
400
t − Time − ms
500
600
700
RL = 16 Ω
Volume slewing enabled
Device enabled at 0 ms
Figure 10. Headphone Start-up Waveforms vs Time
Figure 9. Headphone Supply Current vs Total Output Power
−20
2
VO − Output Amplitude − dBV
−40
V − Voltage − V
1
0
−1
−60
−80
−100
−120
−140
−160
−2
−50
VIN = 0.5 VRMS
−180
0
50
100
t − Time − ms
150
200
RL = 16 Ω
Volume slewing enabled
Device enabled at 0 ms
10
−40
0
−60
−80
−100
−120
−140
10k
f − Frequency − Hz
15k
20k
RL = 16 Ω
A weighted
Gain = 0 dB
Figure 12. Headphone Output Spectrum vs Frequency
−20
AC Response − dB
VO − Output Amplitude − dBV
5k
VDD = 1.8 V
Figure 11. Headphone Shutdown Waveforms vs Time
−10
−20
−30
−40
−50
−160
−60
−180
0
VDD = 1.8 V
5k
10k
f − Frequency − Hz
RL = 16 Ω
A weighted
15k
20k
Gain = –30 dB
Figure 13. Headphone Output Spectrum vs Frequency
10
0
250
10
100
VDD = 1.8 V
1k
10k
f − Frequency − Hz
RL = 16 Ω
100k
500k
Gain = 0 dB
Figure 14. Audio Filter Frequency Response
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Typical Characteristics (continued)
1
MICVDD = 2.4 V
MICVDD = 3.0 V
MICVDD = 3.6 V
0.1
0.01
0.001
20
100
VDD = 1.8 V
1k
f − Frequency − Hz
10k
VOUT = 1 VRMS
THD+N − Total Harmonic Distortion + Noise − %
THD+N − Total Harmonic Distortion + Noise − %
VDD = 1.8 V, MICVDD = 3.0 V, AV = 0 dB, CIN = 0.47 µF, CFLY = 1.0 μF, CCPVDD = CCPVSS = 1.0 μF, RHP = 32 Ω, outputs in
phase, TA = 25°C (unless otherwise noted).
1
VDD = 1.8 V
Gain = 24 dB
VOUT = 1 VRMS
0.1
0.01
0.001
20
20k
Gain = 12 dB
Figure 15. Mic Preamplifier Total Harmonic Distortion +
Noise vs Frequency
VDD = 1.8 V
28
14
24
AC Response − dB
8
6
4
10k
VOUT = 1 VRMS
20k
Gain = 24 dB
20
16
12
8
4
2
0
0
10
MIC VDD = 3.0 V
100
1k
10k
f − Frequency − Hz
100k
500k
Gain = 12 dB
10
100
MIC VDD = 3.0 V
Figure 17. Mic Preamplifier Frequency Response
1k
10k
f − Frequency − Hz
100k
500k
Gain = 24 dB
Figure 18. Mic Preamplifier Frequency Response
0
100
−20
80
VO − Output Amplitude − dBV
PSRR − Power Supply Rejection Ratio − dB
1k
f − Frequency − Hz
Figure 16. Mic Preamplifier Total Harmonic Distortion +
Noise vs Frequency
12
AC Response − dB
100
16
10
MICVDD = 2.4 V
MICVDD = 3.0 V
MICVDD = 3.6 V
60
40
20
Gain = 12 dB
Gain = 24 dB
0
100
VDD = 1.8 V
−40
−60
−80
−100
−120
−140
−160
1k
f − Frequency − Hz
7k
MIC VDD = 3.0 V
0
MIC VDD = 3.0 V
Figure 19. Mic Preamplifier + Micbias PSRR vs Frequency
5k
10k
f − Frequency − Hz
Gain = 12 dB
15k
20k
No signal input
Figure 20. Mic Preamplifier + Micbias Output Frequency
Spectrum
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Typical Characteristics (continued)
VDD = 1.8 V, MICVDD = 3.0 V, AV = 0 dB, CIN = 0.47 µF, CFLY = 1.0 μF, CCPVDD = CCPVSS = 1.0 μF, RHP = 32 Ω, outputs in
phase, TA = 25°C (unless otherwise noted).
0
VO − Output Amplitude − dBV
−20
−40
−60
−80
−100
−120
−140
−160
0
MIC VDD = 3.0 V
5k
10k
f − Frequency − Hz
15k
Gain = 24 dB
20k
No signal input
Figure 21. Mic Preamplifier + Micbias Output Frequency Spectrum
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7 Detailed Description
7.1 Overview
The TPA6166A2 is a small device that serves a large number of complex functions in a portable audio device. It
identifies an accessory plugged into the jack, and configures the internal subsystems to take full advantage of its
capabilities.
• Headphone-jack accessory detection and identification
• Switch matrix
• Class-G ground-centered stereo headphone amplifier
• Mic preamplifier and bias
• SAR ADC for various analog sense functions
• ESD protection
• Convenient I2C host interface
7.2 Functional Block Diagram
CPVDD CPVSS C1P C1N
Class-G
Stereo Headphone
Amplifier
INL
INR
RING1
ESD
Prot.
Mic
Bias
Switch
Matrix
and
Detection
Circuit
MOUTP
MOUTN
SDA
SCL
IRQ
VDD MICVDD
Digital
Interface
and
Control
TIP
JACK_SENSE
RING2
SLEEVE
SAR
ADC
GND1
GND2 PGND
7.3 Feature Description
7.3.1 I2C Interface
The TPA6166A2 I2C address is 0x40 (7-bit).
The I2C bus employs two signals, SDA (data) and SCL (clock), to communicate between integrated circuits in a
system. The bus transfers data serially, one bit at a time. The most significant bit (MSB) is transferred first for the
8-bit address and data bytes. In addition, each byte transferred on the bus is acknowledged by the receiving
device with an acknowledge bit. Each transfer operation begins with the master device driving a start condition
on the bus and ends with the master device driving a stop condition on the bus. The bus uses transitions on the
data terminal (SDA) while the clock is at logic high to indicate start and stop conditions. A high-to-low transition
on SDA indicates a start and a low-to-high transition indicates a stop. Normal data-bit transitions must occur
within the low time of the clock period.
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Feature Description (continued)
Figure 22 shows a typical sequence. The master generates the 7-bit slave address and the read/write (R/W) bit
to open communication with another device, and then waits for an acknowledge condition. The TPA6166A2
holds SDA low during the acknowledge clock period to indicate acknowledgment. When acknowledgment occurs,
the master transmits the next byte of the sequence. Each device is addressed by a unique 7-bit slave address
plus R/W bit (1 byte). All compatible devices share the same signals via a bidirectional bus using a wired-AND
connection.
An external pullup resistor must be used for the SDA and SCL signals to set the logic high level for the bus.
When the bus level is 3.3 V, use pullup resistors between 1 kΩ and 2 kΩ.
There is no limit on the number of bytes that can be transmitted between start and stop conditions. When the last
word transfers, the master generates a stop condition to release the bus. A generic data transfer sequence is
shown in Figure 22.
SDA
R/
A
W
7-Bit Slave Address
7
5
6
4
3
2
1
0
8-Bit Register Address (N)
7
6
5
4
3
2
1
8-Bit Register Data For
Address (N)
A
0
7
6
5
4
3
2
1
8-Bit Register Data For
Address (N)
A
7
0
6
5
4
3
2
1
A
0
SCL
Start
Stop
T0035-01
Figure 22. Typical I2C Sequence
7.3.1.1 Single and Multiple Byte Transfers
The serial control interface supports both single-byte and multiple byte read/write operations for all registers.
During multiple-byte read operations, the TPA6166A2 responds with data, 1 byte at a time, starting at the register
assigned, as long as the master device continues to respond with acknowledgments.
The TPA6166A2 supports sequential I2C addressing. For write transactions, if a register is issued followed by
data for that register and all the remaining registers that follow, a sequential I2C write transaction has occurred.
For I2C sequential write transactions, the register issued then serves as the starting point, and the amount of
data subsequently transmitted, before a stop or start is transmitted, determines the number of registers written.
7.3.1.2 Single-Byte Write
As Figure 23 shows, a single-byte data write transfer begins with the master device transmitting a start condition
followed by the I2C device address and the read/write bit. The read/write bit determines the direction of the data
transfer. For a write data transfer, the read/write bit must be set to 0. After receiving the correct I2C device
address and the read/write bit, the TPA6166A2 responds with an acknowledge bit. Next, the master transmits the
register byte corresponding to the TPA6166A2 internal memory address being accessed. After receiving the
register byte, the TPA6166A2 again responds with an acknowledge bit. Next, the master device transmits the
data byte to be written to the memory address being accessed. After receiving the register byte, the TPA6166A2
again responds with an acknowledge bit. Finally, the master device transmits a stop condition to complete the
single-byte data write transfer.
Start
Condition
Acknowledge
A6
A5
A4
A3
A2
A1
A0
2
I C Device Address and
Read/Write Bit
R/W ACK A7
Acknowledge
A6
A5
A4
A3
A2
A1
A0 ACK D7
Acknowledge
D6
Subaddress
D5
D4
D3
Data Byte
D2
D1
D0 ACK
Stop
Condition
T0481-01
Figure 23. Single-Byte Write Transfer
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Feature Description (continued)
7.3.1.3 Multiple-Byte Write and Incremental Multiple-Byte Write
A multiple-byte data write transfer is identical to a single-byte data write transfer except that multiple data bytes
are transmitted by the master device to the TPA6166A2 as shown in Figure 24. After receiving each data byte,
the TPA6166A2 responds with an acknowledge bit.
Start
Condition
Acknowledge
A6
A5
A1
A6
A0 R/W ACK A7
A5
2
I C Device Address and
Read/Write Bit
A4
A3
A1
Acknowledge
Acknowledge
Acknowledge
Acknowledge
A0 ACK D7
D0 ACK D7
D0 ACK D7
D0 ACK
Other Data Bytes
First Data Byte
Subaddress
Last Data Byte
Stop
Condition
T0482-01
Figure 24. Multiple-Byte Write Transfer
7.3.1.4 Single-Byte Read
As Figure 25 shows, a single-byte data read transfer begins with the master device transmitting a start condition
followed by the I2C device address and the read/write bit. For the data read transfer, both a write followed by a
read are actually executed. Initially, a write is executed to transfer the address byte of the internal memory
address to be read. As a result, the read/write bit is set to a 0.
After receiving the TPA6166A2 address and the read/write bit, the TPA6166A2 responds with an acknowledge
bit. The master then sends the internal memory address byte, after which the TPA6166A2 issues an
acknowledge bit. The master device transmits another start condition followed by the TPA6166A2 address and
the read/write bit again. This time the read/write bit is set to 1, indicating a read transfer. Next, the TPA6166A2
transmits the data byte from the memory address being read. After receiving the data byte, the master device
transmits a not-acknowledge followed by a stop condition to complete the single-byte data read transfer.
Repeat Start
Condition
Start
Condition
Acknowledge
A6
A5
A1
A0 R/W ACK A7
Acknowledge
A6
2
I C Device Address and
Read/Write Bit
A5
A4
A0 ACK
Not
Acknowledge
Acknowledge
A6
A5
A1
A0 R/W ACK D7
D6
2
I C Device Address and
Read/Write Bit
Subaddress
D1
D0 ACK
Stop
Condition
Data Byte
T0483-01
Figure 25. Single-Byte Read Transfer
7.3.1.5 Multiple-Byte Read
A multiple-byte data read transfer is identical to a single-byte data read transfer except that multiple data bytes
are transmitted by the TPA6166A2 to the master device as shown in Figure 26. With the exception of the last
data byte, the master device responds with an acknowledge bit after receiving each data byte.
Repeat Start
Condition
Start
Condition
Acknowledge
A6
2
A0 R/W ACK A7
I C Device Address and
Read/Write Bit
Acknowledge
A6
A5
A6
A0 ACK
Subaddress
2
Acknowledge
Acknowledge
Acknowledge
Not
Acknowledge
A0 R/W ACK D7
D0 ACK D7
D0 ACK D7
D0 ACK
I C Device Address and
Read/Write Bit
First Data Byte
Other Data Bytes
Last Data Byte
Stop
Condition
T0484-01
Figure 26. Multiple-Byte Read Transfer
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Feature Description (continued)
7.3.2 Accessory Detection
The TPA6166A2 has an advanced accessory jack detection circuitry which determines insertion, removal, as well
as type detection of accessories with a 3.5-mm headset jack. The jack and its internal connections are shown in
Figure 27.
2 (RING1)
1 (TIP)
5 (JACK_SENSE,
Normally Closed)
1
2
3
4
3 (RING2)
4 (SLEEVE)
Figure 27. Connecting to a 3.5-mm Headset Jack
When the insertion of a jack is detected, the accessory type detection algorithm runs until two consecutive type
detections produce the same result. In general, the type detection algorithm is not run again after this point of
time. Hence, on-the-fly change of accessory type is not detected. The following accessories can be detected.
Table 6 has specific detection details.
• Stereo Headset (HP with mic)
• Line Out Audio Cable
• Mono Headset
• Stereo Headphone
• Line Out Audio Cable
The limits of detection are shown in Table 1.
Table 1. Limits of Detection
PARAMETER
SYMBOL
MIN
MAX
UNIT
Cable Shield Capacitance
CCABLE
150
500
pF
Headphone Load Resistance
RHP
8
700/1500*
Ω
Audio Line Load Resistance
RLINE
10
50
kΩ
Microphone Load Resistance
RMIC
1.5
20
kΩ
200K || 70 pF
10 G || 5 pF
kΩ
Open/Float
As a result of accessory detection, appropriate blocks are automatically turned on ensuring lower possible power
consumption. When accessory is removed, all blocks are turned off ensuring ultra low power. The TPA6166A2
achieves 22.7 µW when no accessory is inserted.
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7.3.3 Audio Playback Channel
The TPA6166A2 includes stereo audio channel with integrated low pass filter and class-G headphone amplifier.
Figure 28 shows the block diagram for the Audio Channel. The channel includes volume control block. The
volume level can be varied from +6 dB to –42 dB in 1-dB steps, in addition to a mute bit, independently for each
channel. The volume level of both channels can also be changed simultaneously by the master volume control,
which can be achieved by setting Register 0x07, Bit 7 (L=R) to 1. Gain changes are implemented with a softstepping algorithm, which only changes the actual volume by one step in every 3.25 ms, either up or down, until
the desired volume is reached.
0 to -30dB (steps of -6dB)
-
INL
LPF
16 dB Attenuation
at 145 kHz
+6 to -12dB (steps of -1dB)
+
TIP
+
RING2
SLEEVE
+
-
RING1
+
INR
-
+6 to -12dB (steps of -1dB)
LPF
16 dB Attenuation
at 145 kHz
0 to -30dB (steps of -6dB)
Figure 28. Audio Playback Channel
Because of soft-stepping, the system does not know when the audio channel has been actually muted. This may
be important if the system wishes to mute the channel before making a significant change. To help with this
situation, the device provides a flag back to the system through a read-only register bit that alerts the system
when the part has completed the soft-stepping and the actual volume has reached the desired volume level.
Soft-stepping feature can be disabled by setting Register 0x1E, Bit 5 (VSEN) to 1.
The TPA6166A2 integrates switches on RING2 (terminal 3) and SLEEVE (terminal 4) to ground. Based on
accessory detection result, either RING2 or SLEEVE is selected as accessory ground, and appropriate switch is
turned on. As switches have finite resistance, it can give rise to crosstalk between left and right channel. The
TPA6166A2 integrates ground loop rejection circuitry, which reduces crosstalk to a great extent.
The left channel audio output can be routed to TIP. For right channel, audio output is routed to RING1.
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7.3.3.1 Class-G Headphone Amplifier
Class-G is a linear amplifier using a modulating supply voltage. A high-efficiency step-down converter regulates
the headphone amplifier supply voltage. The headphone amplifier supply voltage increases as the audio output
voltage increases. This prevents signal clipping and distortion. The headphone amplifier supply voltage
decreases during softer audio periods, reducing battery current and improving overall efficiency. The class-G
amplifier has more than twice the efficiency of an equivalent class-AB amplifier. This increases battery life during
audio playback.
Figure 29 shows the block diagram for the class-G headphone amplifier. The class-G control examines the
amplifier output voltage and determines the optimum headphone supply voltage. CPVDD and CPVSS voltages
increase fast enough to avoid any output clipping or distortion. The class-G control operates automatically and
does not require programming.
VDD
CPVDD
IDD
IDD/2
IOUT
Charge
Pump
VOUT
Audio Input
RL
IDD/2
CPVSS
Class G
Control
Figure 29. Class-G Headphone Block Diagram
7.3.3.1.1 Headphone Charge Pump
The TPA6166A2 includes a high-efficiency step-down charge pump and an inverting charge pump to generate
power supplies for the headphone amplifier. These charge pumps use a common flying capacitor, thus
minimizing components. The step-down charge pump regulates CPVDD; the inverting charge pump regulates
CPVSS. These are designed to only drive the TPA6166A2 headphone amplifier. Do not use CPVDD or CPVSS
as a voltage supply to drive an external device.
7.3.3.2 Out-of-Band and Input RF Noise Rejection
When using amplifiers with CODECs and DACs, sometimes there is an increase in the output noise floor from
the audio amplifier. This occurs when the output out-of-band noise of the CODEC/DAC folds back into the audio
frequency due to the limited gain bandwidth product of the audio amplifier. Single-ended RF noise can also fold
back into the audio band thus degrading the audio signal even further.
The TPA6166A2 has a built-in low-pass filter to reduce CODEC/DAC out-of-band noise and RF noise, that could
fold back into the audio frequency.
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7.3.4 Mic Channel
The TPA6166A2 includes microphone preamplifier with selectable gain of 12 dB and 24 dB. The device uses
architecture, which removes requirement of external AC coupling capacitor by integrating it inside. The
TPA6166A2 also includes Mic-bias with integrated bias resistor. A mic bias voltage can be programmed to 2.0 V
or 2.6 V. Mic-bias resistor can be programmed to 2.2 kΩ, 2.6 kΩ, 3.0 kΩ or bypass. Based on accessory
detection result, either RING2 (terminal 3 of jack) or SLEEVE (terminal 4 of jack) is selected as Mic input, and
appropriate switch is turned on. Figure 30 shows the block diagram for the Mic Channel. Note that Bias resistor
bypass mode, accessory detection, removal detection, and mic amp will not function.
Micbias
(2.0 V / 2.6 V)
2.2 / 2.6 / 3.0 k
RING2
MOUTP
12/24 dB
MOUTN
Mic PreAmplifier
SLEEVE
Figure 30. Mic Channel
7.3.5 Button Press Detection
The TPA6166A2 supports button press detection of different types:
• Single button press/release: When pressed, this typically creates an equivalent resistance of 1 Ω between
RING2 and SLEEVE.
• Passive button press/release: When pressed, this creates an equivalent resistance between RING2 and
SLEEVE. The TPA6166A2 reports press and release event along with resistance value (KEYDATA_DIV and
KEYDATA in Register 0x17).
The impedance seen by the ADC is calculated using the following data
• Bias voltage
• Bias resistor
• Parallel impedance of the switch pressed and the microphone capsule impedance
The button press detection is done in a two-stage process. The device remains in a low power mode until a
comparator is tripped. The comparator threshold is set to 100 pF).
1 = Audio Channel supports all gains for line-out load with max capacitive load of
470 pF.
6
MUTER
R/W
1
Right Headphone Mute
0 = Disable.
1 = Enable, output is muted.
5-0
RVOL
R/W
00 0000
Right Headphone Volume Control
00 xxxx = –42 dB
01 0000 = –41 dB
01 0001 = –40 dB
01 0010 = –39 dB
...
11 1001 = 0 dB
...
11 1111 = +6 dB
7.5.6.10 Register 0x09: Microphone Bias Control Register
The microphone bias register controls which microphone bias voltage and bias resistors are used, as well as the
debounce time when a key press is detected.
BIT
NAME
READ /
WRITE
DEFAULT
DESCRIPTION
7
DIS_MIC_MUTE
R/W
0
Mic preamplifier Mute Control during button press
Enable/Disable of Mic preamplifier Mute, when button (active/passive multibutton headset) is pressed.
0 – Mic Preamplifier is muted during button press. (Default)
1 – Mic Preamplifier is not muted during button press.
6
GAIN
R/W
0
Microphone Preamplifier Gain Select
0 = 12dB
1 = 24dB
5-3
MICR
R/W
000
Microphone Bias Resistor Select
000 = 2.2 kΩ
001 = 2.6 kΩ
010 = 3.0 kΩ
011 = Bypassed
1xx = Invalid
2
BIAS
R/W
0
Microphone Bias Voltage Select
0 = 2.0 V
1 = 2.6 V
R/W
11
Reserved. Always write 00. Needs to be initialized to 00 after device power up.
1-0
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7.5.6.11 Register 0x0a: Reserved
BIT
NAME
7-0
READ /
WRITE
DEFAULT
DESCRIPTION
R
0000 0000
Reserved.
7.5.6.12 Register 0x0b: Revision ID Register
BIT
NAME
READ /
WRITE
DEFAULT
7-4
REV
R
0011
3-0
R
DESCRIPTION
Revision ID
Reserved.
7.5.6.13 Register 0x0c: Reserved Register
BIT
NAME
7-0
READ /
WRITE
DEFAULT
DESCRIPTION
R/W
0001 1100
Reserved.
7.5.6.14 Registers 0x0d to 0x10: Reserved Registers
BIT
NAME
7-0
READ /
WRITE
DEFAULT
DESCRIPTION
R/W
0000 0000
Reserved.
READ /
WRITE
DEFAULT
DESCRIPTION
R/W
0000 0000
Reserved. Always write 0 to this register.
READ /
WRITE
DEFAULT
DESCRIPTION
R/W
0000 0000
Reserved. Always write 0x01.
READ /
WRITE
DEFAULT
DESCRIPTION
R/W
0000 0000
Reserved. Always write 0x45.
7.5.6.15 Register 0x11: Reserved
BIT
NAME
7-0
7.5.6.16 Register 0x12: Reserved
BIT
NAME
7-0
7.5.6.17 Register 0x13: Reserved
BIT
NAME
7-0
7.5.6.18 Register 0x14: Reserved Register
BIT
7-0
32
NAME
READ /
WRITE
DEFAULT
DESCRIPTION
R
0000 0000
Reserved.
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7.5.6.19 Register 0x15: Keyscan Debounce Register
The keyscan debounce register controls the debounce time when a keypress is detected.
BIT
7-0
NAME
KEY_DEB
READ /
WRITE
R/W
DEFAULT
DESCRIPTION
0000 0000
Keyscan Debounce Register
Debounce time set from 0.25 ms to 63.75 ms in 0.25 ms increments. The
programmed code plus 0.25 represents the debounce time directly, i.e. code
0x4F represents 20 ms of debounce.
7.5.6.20 Register 0x16: Keyscan Delay Register
The keyscan delay register sets the timeout that the mic button press is masked from the system. At the end of
the delay time, the TPA6166A2 checks to see if a microphone is still present. If the mic is present, the system is
alerted by setting the MCSW bit in the status register, flagging an interrupt if IMCSW is set. If the mic is not
present after the delay time, then the system is flagged with an interrupt by setting MIC_IN, which signifies the
mic has been removed and no keypress was made. This prevents accessory removal from being detected as a
button press (due to RING2 and SLEEVE getting shorted during removal).
BIT
7-0
NAME
KEY_DEL
READ /
WRITE
R/W
DEFAULT
DESCRIPTION
0000 0000
Keyscan Delay Register
Delay time set from 1 ms to 256 ms in 1-ms increments. The programmed code
plus one multiplied by 1 ms represents the delay time, that is, code 0xC7
represents 200 ms of delay.
7.5.6.21 Register 0x17: Passive Multi Button Keyscan Data Register
The keyscan data register contains the data read from a keypress after the 10-bit ADC encodes the input voltage
level. The read keypress could come from a single switch or a passive multi-button device.
BIT
NAME
READ /
WRITE
DEFAULT
DESCRIPTION
7
KEYDATA_DIV
R
0
Keyscan Data Divider
Keyscan data should be inferred based on Equation 1. When the 10-bit ADC
output is less than 128 (that is, 3 MSBs will be equal to 0), KEYDATA_DIV is set
to 0 and 7 LSBs are reported in KEYDATA.
When 10-bit ADC output is more than or equal to 128, KEYDATA_DIV is set to 1
and 9 LSBs of ADC Data divided by 4 (and rounded off) are reported in
KEYDATA. This loses resolution for high value of Rswitch||Rmic, which is
acceptable.
6-0
KEYDATA
R
000 0000
Keyscan Data
B6-B0 are read only bits that contain the data read from a passive keypress that
shorts the microphone to ground.
æ
ö
ç
÷
RBIAS
RSWITCH || RMIC = ç
÷ (If KEYDATA_DIV = 0)
3072
çç
-1 ÷÷
è KEYDATA ø
æ
ö
ç
÷
RBIAS
RSWITCH || RMIC = ç
÷ (If KEYDATA_DIV = 1)
768
-1 ÷÷
çç
è KEYDATA ø
(1)
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7.5.6.22 Register 0x18: Jack Detect Test Hardware Settings
BIT
7
6
NAME
SHORT_Z
HP_LO_TH
READ /
WRITE
DEFAULT
DESCRIPTION
0
Maximum Impedance During Short
Defines maximum impedance below which terminal is considered short. This
information is used while detecting whether RING1 (terminal 2) is ground.
0=4Ω
1=7Ω
R/W
0
Threshold Impedance to Distinguish Between Headphone and line-out Load
Defines impedance below which load is Headphone and above is line-out.
0 = 700 Ω
1 = 1.5 kΩ
R
00 0000
R/W
5-0
Reserved.
7.5.6.23 Register 0x19:State Register
BIT
NAME
READ /
WRITE
DEFAULT
DESCRIPTION
Load State Force Enable
0 = Force configuration of the load into the state programmed by B6-B0.
1 = State forcing disabled. B6-B0 reports the configuration reported by the jack
configuration algorithm.
When FORCE bit is changed from 0 to 1, the TPA6166A2 will not re-un
accessory detection algorithm and configuration will continue to set to value
already written in STATE bits. System will need to reset and then set SHDN to
rerun accessory detection algorithm.
7
FORCE
R/W
1
6-0
STATE
R/W
000 0000
Accessory State
Bits B6-B0 represents accessory type
Refer to Table 6 for the state table.
Table 6. State Lookup for Register 0x19, Bits 6-0
B6-B0
COMMENTS
TIP
RING1
RING2
SLEEVE
JACK_SEN
SE
HEX
BIN
0x00
000 0000
Nothing
Float
Float
Float
Float
Short
0x01
000 0001
Stereo Headset (HP with mic)
HPL
HPR
Ground
Mic
Open
0x02
000 0010
HPL
HPR
Mic
Ground
Open
0x0A
000 1010
HPL
Ground
Ground
Mic
Open
0x0B
000 1011
HPL
Ground
Mic
Ground
Open
0x0C
000 1100
HPL
HPL
Ground
Mic
Open
0x0D
000 1101
HPL
HPL
Mic
Ground
Open
0x0E
000 1110
HPL
Float
Ground
Mic
Open
0x0F
000 1111
HPL
Float
Mic
Ground
Open
0x10
001 0000
HPL
HPR
Ground
Ground
Open
0x11
001 0001
HPL
Float
Ground
Ground
Open
0x12
001 0010
Float
HPR
Ground
Ground
Open
0x1A
001 1010
LOL
LOR
Ground
Ground
Open
0x1B
001 1011
Cap / Float
LOR
Ground
Ground
Open
0x1C
001 1100
LOL
Cap / Float
Ground
Ground
Open
0x1F
001 1111
Cap / Float
Cap / Float
Ground
Ground
Open
34
Mono Headset
Stereo Headphone
Stereo Line Out Audio Cable
Unsupported
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7.5.6.24 Register 0x1a: Jack Detect Test Hardware Settings
BIT
7
NAME
JACK_DEB
6
5-4
3-2
1-0
AC_REPEAT
PULSE_WIDTH
PULSE_AMP
READ /
WRITE
DEFAULT
DESCRIPTION
R/W
0
Debounce Time during Jack Insertion/Removal Detection
Controls debounce time on comparators output during Jack Insertion / Removal
Detection
0 = 3 ms (insertion and Sleep mode button press); 12 ms (removal detection)
1 = 20 ms (insertion and Sleep mode button press); 80 ms (removal detection)
R
0
Reserved.
01
Pulse Test Repeat
Control the number of times the pulse test is repeated. The more times the test
is repeated, the more accurate the results will be. The final result is the average
of all the tests.
00 = Test runs once
01 = Test runs 2 times
10 = Test runs 4 times
11 = Test runs 8 times
01
Pulse Width Control
00 = 50 µs
01 = 25 µs
10 = 100 µs
11 = 200 µs
01
Pulse Amplitude Control
00 = VDD / 36 (50 mV)
01 = VDD / 72 (25 mV)
10 = VDD / 18 (100 mV)
11 = VDD / 9 (200 mV)
R/W
R/W
R/W
7.5.6.25 Registers 0x1b: Reserved
BIT
NAME
7-0
READ /
WRITE
DEFAULT
DESCRIPTION
R/W
0000 0000
Reserved.
7.5.6.26 Register 0x1c: Clock Control
Write 0x00 to this register at power-up. This ensures best performance from the TPA6166A2.
BIT
7
7-0
NAME
CLOCK_CONTRO
L
READ /
WRITE
DEFAULT
DESCRIPTION
Clock control for passive multi-button headset
0 = Clock is not turned on.
1 = Clock is turned on. Write this bit when passive multi-button functionality is
required with headset inserted and device is not in Sleep/Shutdown mode.
Along-with this bit, also write following sequence:
Register: 0x66, Value: 0xF1
Register: 0x6F, Value: 0x01
Register: 0x66, Value: 0x00
When CLOCK_CONTROL is set to 0 (due to device going into Sleep/Shutdown
mode), write following sequence:
Register: 0x66, Value: 0xF1
Register: 0x6F, Value: 0x00
Register: 0x66, Value: 0x00
R/W
0
R/W
000 0001
Reserved. Always write 000 0000
7.5.6.27 Register 0x1d: Enable Register 1
The Enable registers contain all of the bits that control the separate functional blocks for the TPA6166A2. The
system can either directly control these bits, or it can allow TPA6166A2 to automatically configure itself and
report in the Enable register which blocks are enabled. When the AUTO bits (B1-B0) are set to 01 or 10, the
Enable Registers are read only. The block enable bits do not need to be set to sense a jack removal. The jack
removal circuitry is active as soon as an inserted jack is detected.
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BIT
NAME
READ /
WRITE
www.ti.com
DEFAULT
DESCRIPTION
0
Full Device Shutdown Control
SHDN turns TPA6166A2 on and off. When SHDN is low, the device is in low
power mode and the jack insertion detect circuitry is active. Pull SHDN high to
turn on the device and run the jack configuration detect algorithm. Typically
SHDN will be held low until the system gets an interrupt from the indicating that
a jack has been inserted. The system will then pull SHDN high.
0 = TPA6166A2 in lowest power shutdown mode. During this mode, accessory
insertion/removal detection works only if jack switch not broken. If switch is
broken, status will be reported as if accessory is inserted (even if accessory is
not inserted or it is removed). SLEEP setting is ignored during this mode.
1 = TPA6166A2 is active. The jack configuration algorithm runs immediately
after SHDN is pulled high.
R/W
0
Sleep Mode Enable
Pull SLEEP high to enable the circuitry that looks for accessory insertion/removal
and button press (for headset with Mic) when TPA6166A2 is shutdown. When a
button press (for headset with Mic) is sensed, the MCSW bit in the status
register is set, generating an interrupt if IMCSW is set.
0 = TPA6166A2 is in normal mode as long as SHDN is set.
1 = TPA6166A2 is in sleep mode. During this mode, accessory insertion and
removal detection works even for broken Jack switch. For Headset with Mic
cases, button press will generate an interrupt, which can be used for system
wakeup.
When device is programmed in Sleep mode (SLEEP=1), following sequence
must to used to ensure best performance:
Disable Auto mode and headphone amplifiers by programming register 0x1E,
bits D1D0 to 00 and bits D7D6 to 00
Enable Auto mode by programming register 0x1E, bit D1D0 to 01
R
0
Reserved.
0
Microphone Bias Enable/Status
Set MIC_BIAS to enable the mic bias block. This bit is read only when AUTO
(B1-B0) is set to 01 or 10.
0 = Microphone bias is disabled.
1 = Microphone bias is active.
0
Microphone Amplifier Enable/Status
Set MIC_AMP to enable the mic amp. This bit is read only when AUTO (B1-B0)
is set to 01 or 10.
0 = Microphone amp is disabled.
1 = Microphone amp is active.
R
0
Keyscan Enable/Status
KS enables the circuitry that decodes passive multi-button keypad or simple
microphone switch.
0 = Keyscan ADC is disabled.
1 = Keyscan ADC is enabled.
This bit is always Read Only (regardless of AUTO bits setting).
1
R
0
Reserved.
0
R
0
Reserved.
7
6
SHDN
SLEEP
5
4
3
2
MIC_BIAS
MIC_AMP
KS
R/W
R/W
R/W
7.5.6.28 Register 0x1e: Enable Register 2
Set Register 0x1E, Bit 4 to 1 to ensure the best performance from the TPA6166A2.
BIT
7
6
36
NAME
LFTEN
RGHEN
READ /
WRITE
R/W
R/W
DEFAULT
DESCRIPTION
0
Left Headphone Enable/Status
Set LFTEN to enable the left channel of the DirectDrive headphone amplifier.
This bit is read only when AUTO (B1-B0) is set to 01 or 10.
0 = Headphone amp left channel disabled
1 = Headphone amp left channel enabled
0
Right Headphone Enable/Status
Set RGHEN to enable the right channel of the DirectDrive headphone amplifier.
This bit is read only when AUTO (B1-B0) is set to 01 or 10.
0 = Headphone amp right channel disabled
1 = Headphone amp right channel enabled
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BIT
5
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NAME
VSEN
4
3
2
1-0
FAST
THRH
AUTO
READ /
WRITE
DEFAULT
DESCRIPTION
R/W
0
Volume Adjustment Slewing
Volume changes are smoothed by stepping through intermediate steps. VSEN
also ensures that the volume automatically ramps from the minimum setting to
the programmed value at turnon and back to the minimum value at turnoff.
0 = Enabled
1 = Disabled
R/W
0
Reserved. Always write 1.
0
Jack Insertion Polling Speed
A fast polling speed tests for a jack insertion 3 times per second while a slow
polling speed tests for jack insertion every 2 seconds. This setting is valid only
when mechanical TERMINAL5 switch is not operational. When mechanical
TERMINAL5 switch is operational, detection is instantaneous (excluding
debounce time and detection time).
0 = Slow polling mode, 2-sec delay between polls
1 = Fast polling mode, 333-ms delay between polls
0
Class-G Threshold
Select THRH selects the threshold at which the power supplies switch from
±0.9 V to ±1.8 V. A higher threshold allows the TPA6166A2 output stage to be
powered from ±0.9 V for a higher percentage of the audio waveform, decreasing
power dissipation at the expense of dynamic distortion.
0 = Low Threshold
1 = High Threshold
01
Automatic Mode
Select Set AUTO to allow the TPA6166A2 to enable functional blocks depending
on the load. In auto mode the system merely reads the status of registers 0x1D
and 0x1E to find out what blocks are enabled. Setting AUTO makes bits register
0x1D and 0x01E read only. Clear AUTO to give the system control of what
functional blocks are active. The system would need to allow the jack
configuration detect algorithm to complete before enabling functional blocks.
00 = System controls which functional blocks are on. Registers 0x1D and 0x1E
are R/W. SHDN and SLEEP settings are ignored.
01 = TPA6166A2 enables functional blocks automatically depending on the
results of the jack configuration detect algorithm provided that SLEEP is set to 0
(SHDN must be set to 1, otherwise device will go into low power state).
10 = TPA6166A2 enables functional blocks automatically depending on the
results of the jack configuration detect algorithm regardless of settings of SHDN
and SLEEP.
11 = Invalid.
R/W
R/W
R/W
7.5.6.29 Register 0x1F: Reserved
BIT
NAME
7-0
READ /
WRITE
DEFAULT
DESCRIPTION
R
0000 0000
Reserved.
7.5.6.30 Register 0x66: Clock Flex Register
BIT
NAME
READ /
WRITE
DEFAULT
DESCRIPTION
7-0
CLOCK_FLEX
R/W
0000 0000
Reserved. Write 0xF1 to use Register 0x6F, then set back to zero.
7.5.6.31 Register 0x6F: Clock Set Register
BIT
NAME
READ /
WRITE
DEFAULT
DESCRIPTION
7-0
CLOCK_SET
R/W
0000 0000
Write 0x01 when passive button detection is needed in Active mode. (accessory
is inserted, and device is not in Sleep/Shutdown mode). Reset to 0x00 when the
device is going to sleep to save power.
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8 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
8.1 Application Information
This section describes a typical application of TPA6166A2 with a standard audio jack with battery voltage level
supply. The circuit detects what kind of device is plugged into the jack and delivers excellent audio quality.
8.2 Typical Application
Figure 32 shows a typical application circuit for the TPA6166A2 with a 5-terminal audio jack. Accessory
Detection describes all the accessory jack configurations the TPA6166A2 automatically detects.
1.0 pF 1.0 pF
CPVDD CPVSS
0.47 pF
Analog
Baseband
0.47 pF
C1P C1N
GND1
MICVDD
RING1
TIP
Switch
Matrix
and
Detection
Circuit
Mic
Bias
MOUTP
MOUTN
ESD
Prot.
2
EMI
Filter
1
5
JACK_SENSE
RING2
SLEEVE
EMI
Filter
1
2
3
4
3
4
10 kW
SDA
SCL
Digital
Baseband
VDD
Class-G
Stereo Headphone
Amplifier
INL
INR
GND2
10 kW
1.8 V Supply
2.4 - 3.6 V Supply
1.0 pF
IRQ
SAR
ADC
Digital
Interface
and
Control
PGND
Figure 32. Typical Application Circuit
8.2.1 Design Requirements
Table 7. Design Parameters
DESIGN PARAMETERS
VALUE
VDD Supply voltage
1.7 V to 1.9 V
MICVDD Microphone supply voltage
2.4 V to 3.6 V
8.2.2 Detailed Design Procedure
8.2.2.1 Charge Pump Capacitors
The CPVDD and CPVSS capacitor must be at least equal in value to the flying capacitor to allow maximum
charge transfer. Use low ESR (example: < 20 mΩ at 1.3 MHz) ceramic capacitors to maximize charge pump
efficiency. X5R-type capacitors or better are required for best performance. Typical values are 1 µF to 2.2 µF for
the charge pump capacitors.
38
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Charge pump capacitors should be able to handle up to 2 V during normal operation. During IEC ESD strike on
jack terminals, voltage on these capacitors can go as high as 12 V for 30 to 40 ns. Capacitors rated for 6.3 V or
higher can typically handle such voltages for short durations without getting damaged.
8.2.2.2 Audio Input ac Coupling Capacitors
Input coupling capacitors block any dc bias from the audio source and ensure maximum dynamic range. Input
coupling capacitors also minimize TPA6166A2 turnon pop to an inaudible level. The input capacitors are in series
with TPA6166A2 internal input resistors, creating a high-pass filter. Equation 2 calculates the high-pass filter
corner frequency. The TPA6166A2 typical input impedance, RIN, is 20 kΩ.
1
fC =
2pRINCIN
(2)
For a given high-pass cutoff frequency, the minimum input coupling capacitor is:
1
CIN =
2pfCRIN
(3)
Example: Select input coupling capacitor values to achieve a 20 Hz high-pass corner frequency. Equation 3
shows the input coupling capacitors must be at least 0.4 μF. Choose a 0.47-μF standard value capacitor for each
TPA6166A2 input. Use X5R-type or better capacitors for best performance.
8.2.2.3 Suggested Output EMI Filter
To prevent noise getting radiated from headphone, EMI filters are often included on terminals connected to the
Jack. Figure 33 illustrates typical connection diagram of EMI filter implemented using ‘pi’ configuration.
120W 1.2A (such as BLM18BB220SN1)
Jack Connector
Pin1/2/3/4 from IC
33pF
33pF
Figure 33. EMI Filter
High-frequency impedance of RF beads in range of 100 MHz can impact IEC ESD performance on TPA6166A2
jack outputs (LOUT, PIN2_ROUT, PIN3, and PIN4). Higher impedances change the waveform during IEC strike
to make it wider, which subjects internal circuit to stress for longer duration. Use RF beads which are equal to or
less than 22-Ω impedance at 100 MHz.
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8.2.3 Application Curve
THD+N − Total Harmonic Distortion + Noise − %
The high quality and low distortion of the TPA6166A2 mic preamplifier is shown in Figure 34.
1
MICVDD = 2.4 V
MICVDD = 3.0 V
MICVDD = 3.6 V
0.1
0.01
0.001
20
100
1k
f − Frequency − Hz
10k
20k
Figure 34. Mic Preamplifier Total Harmonic Distortion + Noise vs Frequency
9 Power Supply Recommendations
The TPA6166A2 has two power-supply domains, VDD and MICVDD. The TPA6166A2 allows VDD and MICVDD
supplies to come up in any order. The Internal circuit of the TPA6166A2 has diodes between VDD and MICVDD
supply domain, which are reversed bias during normal operation. If MICVDD voltage is less than VDD, these
diodes can get forward bias and drive MICVDD. If the application requires that the MICVDD terminal not be
driven in such a condition, an external switch on MICVDD can be used. I2C read/write and the accessorydetection algorithm is disabled until both VDD and MICVDD supplies are up. During operation, if the MICVDD
supply goes below its normal operating voltage, the control-register contents are still preserved. Once the supply
comes up again, the accessory detection algorithm runs again to ensure the correct state. If the MICVDD supply
is not powered up, the SDA line can be clamped by TPA6166A2. This is due to the internal ESD protection
structure on SDA being biased based on MICVDD.
9.1 Decoupling Capacitors
The TPA6166A2 requires adequate power supply decoupling to ensure that output noise and total harmonic
distortion (THD) remain low. Use quality low equivalent-series-resistance (ESR) ceramic capacitors (X5R
material or better is required for best performance). Place a 1-μF capacitor within 5 mm of the VDD and MICVDD
terminal. Reducing the distance between the decoupling capacitor and VDD/MICVDD minimizes parasitic
inductance and resistance, improving TPA6166A2 supply rejection performance. Use 0402 or smaller size
capacitors if possible. Ensure that the ground connection of each of the capacitors has a minimum-length return
path to the device. Failure to properly decouple the TPA6166A2 may degrade audio or EMC performance.
40
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10 Layout
10.1 Layout Guidelines
The ground terminal must be connected to the ground plane as close as possible to the TPA6166A2, to minimize
any inductance in the path. Place the decoupling capacitor as close as possible to the supply terminal,
minimizing trace length (and thus the inductance) on the decoupling capacitor connection to ground.
Because INL and INR are single-ended inputs, take care to minimize noise on INL and INR with respect to
TPA6166A2 ground. This is best achieved by using then same ground plane for the signal source and the
TPA6166A2 with a minimum inductance between them.
The accessory-detection algorithm requires trace capacitance to be minimized between TPA6166A2 and the
jack. Depending upon headphone impedance, trace resistance between TPA6166A2 and the jack impacts power
delivered to load. If trace resistance is much smaller than headphone impedance, power loss is given by
Equation 4. Trace resistance should be minimized based on acceptable power loss.
Power Loss =
Trace Resistance
Headphone Resistance
(4)
To minimize crosstalk, trace resistance on RING2 (terminal 3) and SLEEVE (terminal 4) should be minimized.
This can be achieved by placing TPA6166A2 close to the jack. For cases where trace resistance is not small,
crosstalk is given by Equation 5. In such scenarios, best balance can be achieved by increasing trace width of
SLEEVE. RING2 has no constraint on maximum capacitance, and its trace width can be maximized to achieve
desired crosstalk performance.
æ
ö
Trace Resistance
Crosstalk (dB) = 20 log10 ç
÷
+
Headphone
Resistance
Trace
Resistance
è
ø
(5)
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10.2 Layout Example
10.2.1 Pad Sizing
When determining the pad size for the WCSP terminals, use nonsolder mask defined (NSMD) land. With this
method, the solder mask opening is made larger than the desired land area, and the opening size is defined by
the copper pad width. Figure 35 and Table 8 show the appropriate diameters for a WCSP layout.
Copper Trace Width
Solder Pad Width
Solder Mask Opening
Copper Trace Thickness
Solder Mask Thickness
M0200-01
Figure 35. Land Pattern Dimensions
Table 8. Land Pattern Dimensions
(1)
(2)
(3)
(4)
(5)
(6)
(7)
(1) (2) (3) (4)
SOLDER PAD
DEFINITION
COPPER PAD
SOLDER MASK (5)
OPENING
COPPER
THICKNESS
STENCIL (6) (7)
OPENING
STENCIL
THICKNESS
Nonsolder mask
defined (NSMD)
230 μm
310 μm
1 oz. max. (32 μm)
275 μm × 275 μm sq.
(rounded corners)
100 μm thick
Circuit traces from NSMD-defined PWB lands should be 75 μm to 100 μm wide in the exposed area inside the solder mask opening.
Wider trace widths reduce device standoff and impact reliability.
Best reliability results are achieved when the PWB laminate glass transition temperature is above the operating range of the intended
application.
Recommended solder paste is type 3 or type 4.
For a PWB using a Ni/Au surface finish, the gold thickness should be less 0.5 mm to avoid a reduction in thermal fatigue performance.
Solder mask thickness should be less than 20 µm on top of the copper circuit pattern.
Best solder stencil performance is achieved using laser-cut stencils with electro polishing. Use of chemically etched stencils results in
inferior solder paste volume control.
Trace routing away from WCSP device should be balanced in X and Y directions to avoid unintentional component movement due to
solder wetting forces.
Table 9. Package Dimensions
42
D
E
Max. = 2470 µm
Max. = 2470 µm
Typ. = 2440 µm
Typ. = 2440 µm
Min. = 2410 µm
Min. = 2410 µm
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11 Device and Documentation Support
11.1 Development Support
See TPA6166A2EVM User's Guide, SLOU381.
11.2 Trademarks
DirectPath is a trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
11.3 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
11.4 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
12 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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PACKAGE OPTION ADDENDUM
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10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
(4/5)
(6)
TPA6166A2YFFR
ACTIVE
DSBGA
YFF
25
3000
RoHS & Green
SNAGCU
Level-1-260C-UNLIM
-40 to 85
SMB
TPA6166A2YFFT
ACTIVE
DSBGA
YFF
25
250
RoHS & Green
SNAGCU
Level-1-260C-UNLIM
-40 to 85
SMB
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of
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