TPD2E1B06DRLR

Product Folder Sample & Buy Support & Community Tools & Software Technical Documents TPD2E1B06 SLVSC77D – AUGUST 2013 – REVISED APRIL 2016 TPD2E1B06 Dual-Channel High-Speed ESD Protection Device 1 Features 3 Description • The TPD2E1B06 device is a dual-channel, ultra-low capacitance ESD protection device. It offers ±10-KV IEC contact ESD protection. Its 1-pF line capacitance makes it suitable for a wide range of applications. Typical application interfaces are USB 2.0, LVDS, and I2C. The TPD2E1B06 device has two common layout methods, and both are highlighted in Layout. 1 • • • • • • • Provides System Level ESD Protection for Low Voltage IO Interface IEC 61000-4-2 Level 4 ESD Rating Low IO Capacitance: 0.85 pF (Typical) DC Breakdown Voltage: 7 V (Minimum) Ultra-Low Leakage Current: 10 nA (Maximum) Low ESD Clamping Voltage Temperature Range: –40°C to 125°C Small Easy-to-Route DRL package Device Information(1) PART NUMBER TPD2E1B06 BODY SIZE (NOM) 1.60 mm × 1.20 mm (1) For all available packages, see the orderable addendum at the end of the data sheet. 2 Applications • • • • PACKAGE SOT (6) Gaming Machines eBooks Portable Media Players Digital Cameras Schematic IOA1 IOB1 IOA2 IOB2 Copyright © 2016, Texas Instruments Incorporated 1 An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. PRODUCTION DATA. TPD2E1B06 SLVSC77D – AUGUST 2013 – REVISED APRIL 2016 www.ti.com Table of Contents 1 2 3 4 5 6 7 Features .................................................................. Applications ........................................................... Description ............................................................. Revision History..................................................... Pin Configuration and Functions ......................... Specifications......................................................... 1 1 1 2 3 3 6.1 6.2 6.3 6.4 6.5 6.6 3 3 4 4 4 5 Absolute Maximum Ratings ...................................... ESD Ratings.............................................................. Recommended Operating Conditions....................... Thermal Information .................................................. Electrical Characteristics........................................... Typical Characteristics .............................................. Detailed Description .............................................. 7 7.1 Overview ................................................................... 7 7.2 Functional Block Diagram ......................................... 7 7.3 Feature Description................................................... 7 7.4 Device Functional Modes.......................................... 7 8 Application and Implementation .......................... 8 8.1 Application Information.............................................. 8 8.2 Typical Application ................................................... 8 9 Power Supply Recommendations...................... 10 10 Layout................................................................... 10 10.1 Layout Guidelines ................................................. 10 10.2 Layout Examples................................................... 10 11 Device and Documentation Support ................. 11 11.1 11.2 11.3 11.4 Community Resources.......................................... Trademarks ........................................................... Electrostatic Discharge Caution ............................ Glossary ................................................................ 11 11 11 11 12 Mechanical, Packaging, and Orderable Information ........................................................... 11 4 Revision History NOTE: Page numbers for previous revisions may differ from page numbers in the current version. Changes from Revision C (September 2013) to Revision D • Added ESD Ratings table, Feature Description section, Device Functional Modes, Application and Implementation section, Power Supply Recommendations section, Layout section, Device and Documentation Support section, and Mechanical, Packaging, and Orderable Information section. ................................................................................................. 1 Changes from Revision B (September 2013) to Revision C • 2 Page Added TYPICAL CHARACTERISTICS section...................................................................................................................... 5 Changes from Original (July 2013) to Revision A • Page Added air gap ESD specification to the ABSOLUTE MAXIMUM RATINGS table. ................................................................ 3 Changes from Revision A (August 2013) to Revision B • Page Page Revised document from PREVIEW to PRODUCTION DATA. ............................................................................................... 1 Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated Product Folder Links: TPD2E1B06 TPD2E1B06 www.ti.com SLVSC77D – AUGUST 2013 – REVISED APRIL 2016 5 Pin Configuration and Functions DRL Package 6-Pin SOT Top View IOA1 1 6 NC IOB1 2 5 IOA2 NC 3 4 IOB2 Pin Functions PIN NAME NO. TYPE IOA1 1 I/O IOA2 5 I/O IOB1 2 I/O IOB2 NC 4 I/O 3, 6 NC DESCRIPTION USAGE ESD protected channel See Application Information. No connect Can be left floating, grounded, or connected to VCC 6 Specifications 6.1 Absolute Maximum Ratings over operating free-air temperature range (unless otherwise noted) (1) Operating temperature Peak pulse current (tp = 8/20 μs) PPP Peak pulse power (tp = 8/20 μs) (2) Tstg Storage temperature (2) MAX UNIT –40 125 °C (2) IPP (1) MIN –65 2.5 A 35 W 155 °C Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. Using Routing Option 1 or 2 as shown in Figure 13 or Figure 14. 6.2 ESD Ratings VALUE V(ESD) (1) Electrostatic discharge IEC 61000-4-2 contact discharge (1) ±10000 IEC 61000-4-2 air-gap discharge (1) ±15000 UNIT V Using Routing Option 1 or 2 as shown in Figure 13 or Figure 14. Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated Product Folder Links: TPD2E1B06 3 TPD2E1B06 SLVSC77D – AUGUST 2013 – REVISED APRIL 2016 www.ti.com 6.3 Recommended Operating Conditions over operating free-air temperature range (unless otherwise noted) MIN MAX UNIT VIO Pin IOA1 to IOA2; Pin IOB1 to IOB2 –5.5 5.5 V TA Operating free-air temperature –40 125 °C 6.4 Thermal Information over operating free-air temperature range (unless otherwise noted) TPD2E1B06 THERMAL METRIC (1) DRL (SOT) UNIT 6 PINS RθJA Junction-to-ambient thermal resistance 349.7 ºC/W RθJC(top) Junction-to-case (top) thermal resistance 120.5 ºC/W RθθJB Junction-to-board thermal resistance 171.4 ºC/W ψJT Junction-to-top characterization parameter 10.8 ºC/W ψJB Junction-to-board characterization parameter 169.4 ºC/W (1) For more information about traditional and new thermal metrics, the Semiconductor and IC Package Thermal Metrics application report, SPRA953. 6.5 Electrical Characteristics over operating free-air temperature range. (unless otherwise noted) PARAMETER VRWM TEST CONDITIONS MIN TYP Reverse standoff voltage 5.5 VCLAMP Clamp voltage with ESD strike IPP = 1 A, TLP, I/O to GND (1) (2) Clamp voltage with ESD strike IPP = 1 A, TLP, GND to I/O (1) (2) VCLAMP 11 IPP = 5 A, TLP, GND to I/O (1) (2) 15 RDYN Dynamic resistance 11 IPP = 5 A, TLP, I/O to GND (1) (2) 15 V V V 0.9 Ω 0.85 pF 1.05 Pin 2 and 5 capacitance Pin 1 and 4 = GND, f = 1 MHz, VBIAS = 2.5 V CL2 Pin 1 and 4 capacitance Pin 2 and 5 = GND, f = 1 MHz, VBIAS = 2.5 V (2) (4) VBR Break-down voltage IIO = 1 mA ILEAK Leakage current VBIAS = +2.5 V 4 UNIT (2) (3) CL1 (1) (2) (3) (4) MAX 7 1 pF 9.5 V 10 nA Transmission line pulse with rise time 10 ns and pulse width 100 ns. TA = 25°C Using Routing Option 1, Figure 13. Using Routing Option 2, Figure 14. Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated Product Folder Links: TPD2E1B06 TPD2E1B06 www.ti.com SLVSC77D – AUGUST 2013 – REVISED APRIL 2016 6.6 Typical Characteristics 3.5 1.0 0.8 50 Current Power TA = 25ƒC 3.0 45 40 0.6 2.5 0.2 0.0 ±0.2 ±0.4 35 30 2.0 25 1.5 20 Power (W) Current (A) Current (mA) 0.4 15 1.0 10 ±0.6 0.5 ±0.8 5 0.0 ±1.0 ±10 ±8 ±6 ±4 ±2 0 2 4 6 8 Voltage (V) 10 0 0 ±5 5 10 15 20 25 30 35 40 45 50 Time ( s) C001 Figure 1. IV Curve C002 Figure 2. Maximum Surge Rating 400 160 140 300 120 250 100 Voltage (V) Current (pA) VIN = 2.5 V 350 200 150 80 60 100 40 50 20 0 0 ±40 0 ±20 20 40 60 80 100 Temperature (ƒC) 0 120 25 50 75 100 125 150 Time (ns) C003 Figure 3. ILEAK vs Temperature C004 Figure 4. +8-kV Contact ESD Clamping 3 0 0 ±20 ±3 Insertion Loss (dB) Voltage (V) ±40 ±60 ±80 ±100 ±120 ±6 ±9 ±12 ±15 ±18 ±21 ±24 ±140 ±27 ±160 0 25 50 75 100 125 Time (ns) 150 ±30 100k C005 Figure 5. –8-kV Contact ESD Clamping 1M 10M 100M 1000M 1G 10000M 10G Frequency (Hz) Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated Product Folder Links: TPD2E1B06 C006 Figure 6. Insertion Loss 5 TPD2E1B06 SLVSC77D – AUGUST 2013 – REVISED APRIL 2016 www.ti.com Typical Characteristics (continued) 2.0 1.9 Capacitance (pF) 1.8 1.7 1.6 1.5 1.4 1.3 1.2 1.1 1.0 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 VBIAS (V) 4.5 5.0 C007 Figure 7. Capacitance vs VBIAS Figure 8. Eye Diagram Without TPD2E1B06DRL on EVM Figure 9. Eye Diagram With TPD2E1B06DRL on EVM 6 Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated Product Folder Links: TPD2E1B06 TPD2E1B06 www.ti.com SLVSC77D – AUGUST 2013 – REVISED APRIL 2016 7 Detailed Description 7.1 Overview The TPD2E1B06 is a bidirectional, low-capacitance, two-channel ESD clamping device. It has more than IEC 61000-4-2 Level 4 ESD Rating. The low IO capacitance makes the device a good fit for a wide range of data speeds. Common applications include USB 2.0, LVDS, and I2C. 7.2 Functional Block Diagram IOA1 IOB1 IOA2 IOB2 Copyright © 2016 Texas Instruments Incorporated 7.3 Feature Description The TPD2E1B06 device provides robust system level IEC protection. This device protects circuit from ESD strikes up to ±10-kV contact and ±15-kV air-gap specified in the IEC 61000-4-2 level 4. It also handles up to 2.5-A surge current (IEC61000-4-5 8/20 µs). The I/O capacitance of 0.85 pF supports high data rates. The device has a small dynamic resistance of 0.9 Ω, making clamping voltage low when the device is actively protecting other circuits. With low capacitance and dynamic resistance, the TPD2E1B06 is a good fit for interfaces like USB 2.0, LVDS, and I2C. The breakdown is bidirectional so that this protection device is especially good for bidirectional signals like audio lines. Low leakage allows the diode to conserve power when working below the VRWM. The temperature range of –40°C to 125°C makes this ESD device work at extensive temperatures in most environments. 7.4 Device Functional Modes The TPD2E1B06 is a passive clamp that has low leakage during normal operation when the voltage across each channel is below VRWM and activates when the it goes above VBR. During IEC ESD events, transient voltages will be clamped. When the voltages on the protected lines fall below the trigger voltage, the device reverts back to the low-leakage passive state. Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated Product Folder Links: TPD2E1B06 7 TPD2E1B06 SLVSC77D – AUGUST 2013 – REVISED APRIL 2016 www.ti.com 8 Application and Implementation NOTE Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes. Customers should validate and test their design implementation to confirm system functionality. 8.1 Application Information When a system contains a human interface connector, the system becomes vulnerable to large system-level ESD strikes that standard ICs cannot survive. TVS ESD protection diodes are typically used to suppress ESD at these connectors. There are 2 channels of back-to-back diodes in TPD2E1B06. The device is typically used to provide a path to ground for dissipating ESD events between a human interface connector and a system. As the current from ESD passes through the device, only a small voltage drop is present across the diode structure. This is the voltage presented to the protected IC. The low RDYN of the triggered TVS holds this voltage, VCLAMP, to a tolerable level to the protected IC. 8.2 Typical Application IO Line 1 L IO Line 2 Connector (Source of ESD) IOA1 R IOB1 TPD2E1B06 IOA2 IOB2 GND Line Copyright © 2016, Texas Instruments Incorporated Figure 10. Typical Application Schematic 8.2.1 Design Requirements In this design example, a TPD2E1B06 is used to protect audio channels. Table 1 lists the system parameters. Table 1. Design Parameters DESIGN PARAMETER VALUE Audio Amplifier Class AB Audio signal voltage range –3 V to 3 V Audio frequency content 20 Hz to 20 kHz Required IEC 61000-4-2 ESD Protection ±8-kV Contact/ ±15-kV Air-Gap 8.2.2 Detailed Design Procedure For some parameters, the designer must ensure the following before designing: • Voltage range on the protected line must not exceed the reverse standoff voltage of the TVS diode(s) (VRWM) • Operating frequency is supported by the I/O capacitance CIO of the TVS diode 8 Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated Product Folder Links: TPD2E1B06 TPD2E1B06 www.ti.com • SLVSC77D – AUGUST 2013 – REVISED APRIL 2016 IEC 61000-4-2 protection requirement is covered by the IEC performance of the TVS diode For this application, the audio signal voltage range is –3 V to 3 V. The VRWM for the TVS is –5.5 V to 5.5 V; therefore, the bidirectional TVS will not break down during normal operation. Next, consider the frequency content of this audio signal. In this application with the class AB amplifier, the frequency content is from 20 Hz to 20 kHz; ensure that the TVS I/O capacitance will not distort this signal by filtering it. With TPD2E1B06 typical capacitance of 0.85 pF, which leads to a typical 3-dB bandwidth of more than 3 GHz, this diode has way sufficient bandwidth to pass the audio signal without distorting it. Finally, the human interface in this application requires above standard Level 4 IEC 61000-4-2 system-level ESD protection (±8-kV Contact and ±15-kV Air-Gap). TPD2E1B06 can survive at least ±10-kV Contact and ±15-kV Air-Gap. Therefore, the device can provide sufficient ESD protection for the interface, even though the requirements are stringent. For any TVS diode to provide the full range of ESD protection capabilities, as well as to minimize the noise and EMI disturbances the board will see during ESD events, a system designer must use proper board layout of their TVS ESD protection diodes. See Layout for instructions on properly laying out the TPD2E1B06. 160 0 140 ±20 120 ±40 100 ±60 Voltage (V) Voltage (V) 8.2.3 Application Curves 80 60 ±80 ±100 40 ±120 20 ±140 0 ±160 0 25 50 75 100 125 Time (ns) 150 0 25 Figure 11. +8-kV Contact ESD Clamping 50 75 100 125 Time (ns) C004 150 C005 Figure 12. –8-kV Contact ESD Clamping Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated Product Folder Links: TPD2E1B06 9 TPD2E1B06 SLVSC77D – AUGUST 2013 – REVISED APRIL 2016 www.ti.com 9 Power Supply Recommendations This TPD2E1B06 is a passive TVS diode-based ESD protection device so it does not have any power requirements. Take care not to violate the maximum voltage specifications for each pin. 10 Layout 10.1 Layout Guidelines • The optimum placement of the TPD2E1B06 is as close to the connector as possible. EMI during an ESD event can couple from the trace being struck to other nearby unprotected traces, resulting in early system failures. The printed-circuit board (PCB) designer must minimize the possibility of EMI coupling by keeping any unprotected traces away from the protected traces, which are between the TVS and the connector. • Route the protected traces as straight as possible. • Avoid sharp corners on the protected traces. Electric fields tend to build up on corners, increasing EMI coupling. • Use thick and short traces for the ground pins 10.2 Layout Examples GND Line 1 1 6 2 5 3 4 Line 2 GND Figure 13. Routing Option 1 Figure 14. Routing Option 2 10 Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated Product Folder Links: TPD2E1B06 TPD2E1B06 www.ti.com SLVSC77D – AUGUST 2013 – REVISED APRIL 2016 11 Device and Documentation Support 11.1 Community Resources The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of Use. TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help solve problems with fellow engineers. Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and contact information for technical support. 11.2 Trademarks E2E is a trademark of Texas Instruments. All other trademarks are the property of their respective owners. 11.3 Electrostatic Discharge Caution This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. 11.4 Glossary SLYZ022 — TI Glossary. This glossary lists and explains terms, acronyms, and definitions. 12 Mechanical, Packaging, and Orderable Information The following pages include mechanical, packaging, and orderable information. This information is the most current data available for the designated devices. This data is subject to change without notice and revision of this document. For browser-based versions of this data sheet, refer to the left-hand navigation. Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated Product Folder Links: TPD2E1B06 11 PACKAGE OPTION ADDENDUM www.ti.com 28-Feb-2023 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan (2) Lead finish/ Ball material MSL Peak Temp Op Temp (°C) Device Marking (3) Samples (4/5) (6) TPD2E1B06DRLR ACTIVE SOT-5X3 DRL 6 4000 RoHS & Green NIPDAU | NIPDAUAG Level-1-260C-UNLIM -40 to 125 (DUH, DUL) DUG (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of