TPD2E2U06DRLR

Product Folder Order Now Support & Community Tools & Software Technical Documents TPD2E2U06 SLLSEG9C – JUNE 2013 – REVISED DECEMBER 2019 TPD2E2U06 Dual-Channel High-Speed ESD Protection Device 1 Features 3 Description • The TPD2E2U06 is a dual-channel low capacitance TVS diode ESD protection device. The device offers ±25-kV contact and ±30-kV air-gap ESD protection in accordance with the IEC 61000-4-2 standard. The 1.5-pF line capacitance of the TPD2E2U06 makes the device suitable for a wide range of applications. Typical application interfaces are USB 2.0, LVDS, and I2C™. 1 • • • • • • • IEC 61000-4-2 Level 4 – ±25 kV (Contact discharge) – ±30 kV (Air-gap discharge) IEC 61000-4-5 Surge protection – 5.5-A Peak pulse current (8/20 µs Pulse) IO Capacitance 1.5 pF (Typ) DC Breakdown voltage 6.5 V (Min) Ultra-Low leakage current 10 nA (Max) Low ESD clamping voltage Industrial temperature range: –40°C to +125°C Small easy-to-route DRL and DCK package • PART NUMBER PACKAGE BODY SIZE (NOM) TPD2E2U06DRL SOT (5) 1.60 mm × 1.20 mm TPD2E2U06DCK SC70 (3) 2.0 mm × 1.25 mm (1) For all available packages, see the orderable addendum at the end of the data sheet. 2 Applications • Device Information(1) End Equipment – Set Top Box – Notebook – Server – Electronic Point of Sale (EPOS) Interfaces – USB 2.0 – Ethernet – MIPI Bus – LVDS – I2C Simplified Schematic Power Supply D+ USB 2.0 Transceiver USB 2.0 Connector Vbus DGND 3 5 TPD2E2U06 4 GND 1 An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. PRODUCTION DATA. TPD2E2U06 SLLSEG9C – JUNE 2013 – REVISED DECEMBER 2019 www.ti.com Table of Contents 1 2 3 4 5 6 7 Features .................................................................. Applications ........................................................... Description ............................................................. Revision History..................................................... Pin Configuration and Functions ......................... Specifications......................................................... 1 1 1 2 3 3 6.1 6.2 6.3 6.4 6.5 6.6 3 4 4 4 4 6 Absolute Maximum Ratings ...................................... ESD Ratings.............................................................. Recommended Operating Conditions....................... Thermal Information .................................................. Electrical Characteristics........................................... Typical Characteristics .............................................. Detailed Description .............................................. 8 7.1 Overview ................................................................... 8 7.2 Functional Block Diagram ......................................... 8 7.3 Feature Description................................................... 8 7.4 Device Functional Modes.......................................... 9 8 Application and Implementation ........................ 10 8.1 Application Information............................................ 10 8.2 Typical Application ................................................. 10 9 Power Supply Recommendations...................... 11 10 Layout................................................................... 11 10.1 Layout Guidelines ................................................. 11 10.2 Layout Example .................................................... 12 11 Device and Documentation Support ................. 12 11.1 11.2 11.3 11.4 Trademarks ........................................................... Receiving Notification of Documentation Updates Support Resources ............................................... Glossary ................................................................ 12 12 12 12 12 Mechanical, Packaging, and Orderable Information ........................................................... 12 4 Revision History Changes from Revision B (May 2015) to Revision C Page • Added DCK Package to the Pin Configuration and Functions section................................................................................... 3 • Added DCK Package to the Electrical Characteristics table ................................................................................................. 4 Changes from Revision A (June 2013) to Revision B • 2 Page Added ESD Ratings table, Feature Description section, Device Functional Modes, Application and Implementation section, Power Supply Recommendations section, Layout section, Device and Documentation Support section, and Mechanical, Packaging, and Orderable Information section. ................................................................................................ 1 Submit Documentation Feedback Copyright © 2013–2019, Texas Instruments Incorporated Product Folder Links: TPD2E2U06 TPD2E2U06 www.ti.com SLLSEG9C – JUNE 2013 – REVISED DECEMBER 2019 5 Pin Configuration and Functions DRL Package 5-Pin SOT Top View NC NC IO1 5 1 IO2 2 3 4 GND DCK Package 3-Pin SC70 Top View IO1 1 3 IO2 GND 2 Pin Functions PIN NAME I/O DESCRIPTION DRL DCK IO1 3 1 I/O IO2 5 2 I/O NC 1, 2 — - This pin is not connected and is left floating, grounded, or connected to VCC. 4 3 G The GND (ground) pin is connected to ground. GND The IO1 and IO2 pins are an ESD protected channel. Connect these pins to the data line as close to the connector as possible. 6 Specifications 6.1 Absolute Maximum Ratings over operating free-air temperature range (unless otherwise noted) MIN MAX UNIT IPP Peak pulse current (tp = 8/20 μs) 5.5 (1) A PPP Peak pulse power (tp = 8/20 μs) DRL package 85 (1) W PPP Peak pulse power (tp = 8/20 μs) DCK package 75 (1) W (1) Operating temperature –40 125 °C Storage temperature –65 155 °C Measured at 25°C. Submit Documentation Feedback Copyright © 2013–2019, Texas Instruments Incorporated Product Folder Links: TPD2E2U06 3 TPD2E2U06 SLLSEG9C – JUNE 2013 – REVISED DECEMBER 2019 www.ti.com 6.2 ESD Ratings VALUE V(ESD) (1) (2) Electrostatic discharge Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001 (1) ±4000 Charged-device model (CDM), per JEDEC specification JESD22C101 (2) ±1500 EC 61000-4-2 contact ±25000 EC 61000-4-2 air-gap ±30000 UNIT V JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. Manufacturing with less than 500-V HBM is possible with the necessary precautions. JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process. Manufacturing with less than 250-V CDM is possible with the necessary precautions. 6.3 Recommended Operating Conditions over operating free-air temperature range (unless otherwise noted) MIN VIO Input Pin Voltage TA Operating Free Air Temperature NOM MAX UNIT 0 5.5 V -40 125 °C 6.4 Thermal Information TPD2E2U06 THERMAL METRIC (1) DRL DCK 5 PINS 3 PINS RθJA Junction-to-ambient thermal resistance 286.8 308.3 RθJC(top) Junction-to-case (top) thermal resistance 130.7 170.7 RθJB Junction-to-board thermal resistance 104.8 89.2 ψJT Junction-to-top characterization parameter 25.6 34.2 ψJB Junction-to-board characterization parameter 104.3 88.6 (1) UNIT °C/W For more information about traditional and new thermal metrics, see the Semiconductor and IC package thermal metrics application report. 6.5 Electrical Characteristics over operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP VRWM Reverse stand-off voltage IIO < 10 µA VCLAMP IO to GND IPP = 1 A, TLP (1) 9.7 IPP = 5 A, TLP (1) 12.4 IPP = 1 A, TLP (1) 1.9 (1) 4 VCLAMP GND to IO IPP = 5 A, TLP MAX 5.5 UNIT V V V RDYN Dynamic resistance DRL package IO to GND (2) 0.5 Ω RDYN Dynamic resistance DRL package GND to IO (2) 0.25 Ω RDYN Dynamic resistance DCK package IO to GND (2) 0.6 Ω RDYN Dynamic resistance DCK package GND to IO (2) 0.4 Ω CL Line capacitance f = 1 MHz, VBIAS = 2.5 V (3) 1.5 1.9 pF CCROSS Channel-to-channel input capacitance Pin 4 = 0 V, f = 1 MHz, VBIAS = 2.5 V, between channel pins (3) 0.02 0.03 pF (1) (2) (3) 4 Transmission Line Pulse with 10-ns rise time, 100-ns width. Extraction of RDYN Using least squares fit of TLP characteristics between I = 20 A and I = 30 A. Measured at 25°C. Submit Documentation Feedback Copyright © 2013–2019, Texas Instruments Incorporated Product Folder Links: TPD2E2U06 TPD2E2U06 www.ti.com SLLSEG9C – JUNE 2013 – REVISED DECEMBER 2019 Electrical Characteristics (continued) over operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS ∆CIO-TO-GND Variation of channel input capacitance Pin 4 = 0 V, f = 1 MHz, VBIAS = 2.5 V, channel_x pin to GND – channel_y pin to GND (3) VBR Break-down voltage IIO = 1 mA ILEAK Leakage current VIO = 2.5 V MIN TYP MAX 0.03 0.1 6.5 1 UNIT 8.5 V 10 nA Submit Documentation Feedback Copyright © 2013–2019, Texas Instruments Incorporated Product Folder Links: TPD2E2U06 pF 5 TPD2E2U06 SLLSEG9C – JUNE 2013 – REVISED DECEMBER 2019 www.ti.com 30 30 25 25 20 20 Current (A) Current (A) 6.6 Typical Characteristics 15 15 10 10 5 5 0 0 0 5 10 15 20 25 30 35 40 45 Voltage (V) 50 0 5 10 Figure 1. TLP, Data to GND 30 35 40 45 50 C003 Figure 2. TLP, GND to Data 0 ±15 90 ±30 75 Voltage (V) Voltage (V) 25 15 105 60 45 30 ±45 ±60 ±75 ±90 ±105 15 ±120 0 ±135 ±15 ±150 0 25 50 75 100 125 150 175 200 Time (ns) ±10 15 40 65 90 115 140 165 Time (ns) C004 Figure 3. IEC 61000-4-2 Clamping Voltage, +8 kV Contact 190 C005 Figure 4. IEC 61000-4-2 Clamping Voltage, –8 kV Contact 500 0.001 400 Current (pA) 0.0005 Current (A) 20 Voltage (V) 120 0 -0.0005 300 200 100 0 -0.001 ±2 ±1 0 1 2 3 4 5 6 Voltage (V) 7 8 9 10 0 20 40 60 80 100 Temperature (ƒC) C006 120 C007 VIN 2.5 V TA = 25°C Figure 6. ILEAK vs Temperature Figure 5. IV Curve 6 15 C002 Submit Documentation Feedback Copyright © 2013–2019, Texas Instruments Incorporated Product Folder Links: TPD2E2U06 TPD2E2U06 www.ti.com SLLSEG9C – JUNE 2013 – REVISED DECEMBER 2019 Typical Characteristics (continued) 2.2 6.5 100 Current 90 Power 5.2 80 1.6 3.9 60 50 2.6 40 Power (W) 70 1.8 Current (A) Capacitance (pF) 2 30 1.4 1.3 20 1.2 10 F = 1 MHz 0.0 1 0 0 ±5 0 1 2 3 4 5 10 15 5 IO Voltage (V) 20 25 30 35 40 45 50 Time ( S) C009 C008 f = 1 MHz Gain (dB) Figure 7. Capacitance Across VBIAS 1 0 ±1 ±2 ±3 ±4 ±5 ±6 ±7 ±8 ±9 ±10 ±11 ±12 100k Figure 8. Surge Curve (tp = 8/20 μs) IO to GND 1M 10M 100M 1000M Frequency (Hz) 10000M C010 Figure 9. Insertion Loss Submit Documentation Feedback Copyright © 2013–2019, Texas Instruments Incorporated Product Folder Links: TPD2E2U06 7 TPD2E2U06 SLLSEG9C – JUNE 2013 – REVISED DECEMBER 2019 www.ti.com 7 Detailed Description 7.1 Overview The TPD2E2U06 is a dual-channel low capacitance TVS diode ESD protection device. The device offers ±25-kV contact and ±30-kV air-gap ESD protection in accordance with the IEC 61000-4-2 standard. The 1.5-pF line capacitance of the TPD2E2U06 makes the device suitable for a wide range of applications. Typical application interfaces are USB 2.0, LVDS, and I2C. 7.2 Functional Block Diagram IO1 IO2 GND 7.3 Feature Description The TPD2E2U06 is a dual-channel low capacitance TVS diode ESD protection device. The device offers ±25-kV contact and ±30-kV air-gap ESD protection in accordance with the IEC 61000-4-2 standard. The 1.5-pF line capacitance of the TPD2E2U06 makes the device suitable for a wide range of applications. Typical application interfaces are USB 2.0, LVDS, and I2C. 7.3.1 IEC 61000-4-2 Level 4 The I/O pins can withstand ESD events up to ±25-kV contact and ±30-kV air. An ESD/surge clamp diverts the current to ground. 7.3.2 IO Capacitance The capacitance between each I/O pin to ground is 1.5 pF. These capacitances support data rates in excess of 1.5 Gbps. 7.3.3 DC Breakdown Voltage The DC breakdown voltage of each I/O pin is a minimum of 6.5 V. This ensures that sensitive equipment is protected from surges above the reverse standoff voltage of 5.5 V. 7.3.4 Ultra-Low Leakage Current The I/O pins feature an ultra-low leakage current of 10 nA (Max) with a bias of 2.5 V. 7.3.5 Low ESD Clamping Voltage The I/O pins feature an ESD clamp that is capable of clamping the voltage to 9.7 V (IPP = 1 A). 8 Submit Documentation Feedback Copyright © 2013–2019, Texas Instruments Incorporated Product Folder Links: TPD2E2U06 TPD2E2U06 www.ti.com SLLSEG9C – JUNE 2013 – REVISED DECEMBER 2019 Feature Description (continued) 7.3.6 Industrial Temperature Range This device is designed to operate from –40°C to 125°C. 7.3.7 Small Easy-to-Route Package The layout of this device makes it simple and easy to add protection to an existing layout. The packages offers flow-through routing, requiring minimal modification to an existing layout. 7.4 Device Functional Modes TPD2E2U06 is a passive integrated circuit that triggers when voltages are above VBR or below the lower diodes Vf (–0.6 V). During ESD events, voltages as high as ±30 kV (air) can be directed to ground via the internal diode network. Once the voltages on the protected line fall below the trigger levels of TPD2E2U06 (usually within 10’s of nano-seconds) the device reverts to passive. Submit Documentation Feedback Copyright © 2013–2019, Texas Instruments Incorporated Product Folder Links: TPD2E2U06 9 TPD2E2U06 SLLSEG9C – JUNE 2013 – REVISED DECEMBER 2019 www.ti.com 8 Application and Implementation NOTE Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes. Customers should validate and test their design implementation to confirm system functionality. 8.1 Application Information TPD2E2U06 is a diode type TVS which is typically used to provide a path to ground for dissipating ESD events on hi-speed signal lines between a human interface connector and a system. As the current from ESD passes through the TVS, only a small voltage drop is present across the diode. This is the voltage presented to the protected IC. The low RDYN of the triggered TVS holds this voltage, VCLAMP, to a safe level for the protected IC. 8.2 Typical Application Power Supply D+ USB 2.0 Transceiver USB 2.0 Connector Vbus D3 GND 5 TPD2E2U06 4 GND Figure 10. Typical USB Application Diagram 8.2.1 Design Requirements For this design example, one TPD2E2U06 device will be used in a USB 2.0 application. This will provide complete port protection. Given the USB 2.0 application, the following parameters are known. DESIGN PARAMETER VALUE Signal range on Pins 3 or 5 0 V to 3.3 V Operating Frequency 240 MHz 8.2.2 Detailed Design Procedure To begin the design process, some parameters must be decided upon; the designer needs to know the following: • Signal range of all the protected lines • Operating frequency 10 Submit Documentation Feedback Copyright © 2013–2019, Texas Instruments Incorporated Product Folder Links: TPD2E2U06 TPD2E2U06 www.ti.com SLLSEG9C – JUNE 2013 – REVISED DECEMBER 2019 8.2.2.1 Signal Range The TPD2E2U06 has 2 identical protection channels for signal lines. The symmetry of the device provides flexibility when selecting which of the 2 I/O channels will protect which signal lines. Any I/O will support a signal range of 0 to 5.5 V. 8.2.2.2 Operating Frequency The TPD2E2U06 has a capacitance of 1.5 pF (Typ), supporting USB 2.0 data rates. 8.2.3 Application Curves 1 Gain (dB) 0 ±1 ±2 ±3 ±4 100k 1M 10M 100M 1000M Frequency (Hz) 10000M C011 Figure 11. Insertion Loss Graph 9 Power Supply Recommendations This device is a passive ESD protection device and there is no need to power it. Care should be taken to make sure that the maximum voltage specifications for each line are not violated. 10 Layout 10.1 Layout Guidelines • • • The optimum placement is as close to the connector as possible. – EMI during an ESD event can couple from the trace being struck to other nearby unprotected traces, resulting in early system failures. – The PCB designer needs to minimize the possibility of EMI coupling by keeping any unprotected traces away from the protected traces which are between the TVS and the connector. Route the protected traces as straight as possible. Eliminate any sharp corners on the protected traces between the TVS and the connector by using rounded corners with the largest radii possible. – Electric fields tend to build up on corners, increasing EMI coupling. Submit Documentation Feedback Copyright © 2013–2019, Texas Instruments Incorporated Product Folder Links: TPD2E2U06 11 TPD2E2U06 SLLSEG9C – JUNE 2013 – REVISED DECEMBER 2019 www.ti.com 10.2 Layout Example IO2 IO1 GND = VIA to GND Figure 12. Routing with DRL Package 11 Device and Documentation Support 11.1 Trademarks E2E is a trademark of Texas Instruments. I2C is a trademark of NXP Semiconductors. All other trademarks are the property of their respective owners. 11.2 Receiving Notification of Documentation Updates To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper right corner, click on Alert me to register and receive a weekly digest of any product information that has changed. For change details, review the revision history included in any revised document. 11.3 Support Resources TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight from the experts. Search existing answers or ask your own question to get the quick design help you need. Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of Use. 11.4 Glossary SLYZ022 — TI Glossary. This glossary lists and explains terms, acronyms, and definitions. 12 Mechanical, Packaging, and Orderable Information The following pages include mechanical, packaging, and orderable information. This information is the most current data available for the designated devices. This data is subject to change without notice and revision of this document. For browser-based versions of this data sheet, refer to the left-hand navigation. 12 Submit Documentation Feedback Copyright © 2013–2019, Texas Instruments Incorporated Product Folder Links: TPD2E2U06 PACKAGE OPTION ADDENDUM www.ti.com 10-Dec-2020 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan (2) Lead finish/ Ball material MSL Peak Temp Op Temp (°C) Device Marking (3) (4/5) (6) TPD2E2U06DCKR ACTIVE SC70 DCK 3 3000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 1GH TPD2E2U06DRLR ACTIVE SOT-5X3 DRL 5 4000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 DT (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of