TPS2110A
TPS2111A
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SBVS043A – MARCH 2004 – REVISED MARCH 2010
AUTOSWITCHING POWER MUX
Check for Samples: TPS2110A, TPS2111A
FEATURES
APPLICATIONS
•
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•
•
•
1
2
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•
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Two-Input, One-Output Power Multiplexer with
Low rDS(on) Switches:
– 84 mΩ Typ (TPS2111A)
– 120 mΩ Typ (TPS2110A)
Reverse and Cross-Conduction Blocking
Wide Operating Voltage Range: 2.8 V to 5.5 V
Low Standby Current: 0.5 mA Typ
Low Operating Current: 55 mA Typ
Adjustable Current Limit
Controlled Output Voltage Transition Time:
Limits Inrush Current
Minimizes Output Voltage Hold-Up
Capacitance
CMOS- and TTL-Compatible Control Inputs
Manual and Auto-Switching Operating Modes
Thermal Shutdown
Available in a TSSOP-8 Package
space
space
space
PCs
PDAs
Digital Cameras
Modems
Cell Phones
Digital Radios
MP3 Players
DESCRIPTION
The TPS211xA family of power multiplexers enables
seamless transition between two power supplies,
such as a battery and a wall adapter, each operating
at 2.8 V to 5.5 V and delivering up to 1 A. The
TPS211xA family includes extensive protection
circuitry, including user-programmable current
limiting, thermal protection, inrush current control,
seamless
supply
transition,
cross-conduction
blocking, and reverse-conduction blocking. These
features greatly simplify designing power multiplexer
applications.
space
TYPICAL APPLICATION
IN1: 2.8 V to 5.5 V
C1
0.1 mF
TPS2110A/TPS2111A
1
2
EN1
8
D0
IN1
D1
OUT
7
3
6
VSNS
IN2
5
4
ILIM
CL
RL
GND
RILIM
IN2: 2.8 V to 5.5 V
C2
0.1 mF
1
2
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
All trademarks are the property of their respective owners.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2004–2010, Texas Instruments Incorporated
TPS2110A
TPS2111A
SBVS043A – MARCH 2004 – REVISED MARCH 2010
www.ti.com
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
AVAILABLE OPTIONS
FEATURE
TPS2110A
TPS2111A
TPS2112A
TPS2113A
TPS2114A
TPS2115A
0.31 A to
0.75 A
0.63 A to
1.25 A
0.31 A to
0.75 A
0.63 A to
1.25 A
0.31 A to
0.75 A
0.63 A to
1.25 A
Manual
Yes
Yes
No
No
Yes
Yes
Automatic
Yes
Yes
Yes
Yes
Yes
Yes
No
No
Yes
Yes
Yes
Yes
Current Limit Adjustment Range
Switching Modes
Switch Status Output
ORDERING INFORMATION (1)
(1)
TA
PACKAGE
−40°C to 85°C
TSSOP-8 (PW)
ORDERING NUMBER
PACKAGE MARKING
TPS2110APW
2110A
TPS2111APW
2111A
For the most current package and ordering information see the Package Option Addendum at the end of this document, or see the TI
web site at www.ti.com.
ABSOLUTE MAXIMUM RATINGS (1)
Over recommended operating junction temperature range, unless otherwise noted.
TPS2110A, TPS2111A
UNIT
−0.3 to 6
V
−0.3 to 6
V
Input voltage range at pins IN1, IN2, D0, D1, VSNS, ILIM (2)
Output voltage range, VO(OUT)
(2)
Continuous output current, IO
TPS2110A
0.9
TPS2111A
1.5
Continuous total power dissipation
See Dissipation Ratings table
Operating virtual junction temperature range, TJ
ESD
(1)
(2)
A
Internally Limited
Human body model (HBM)
Charged device model (CDM)
2
kV
500
V
Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating
conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
All voltages are with respect to GND.
DISSIPATION RATINGS
2
PACKAGE
DERATING FACTOR
ABOVE TA = 25°C
TA ≤ 25°C POWER
RATING
TA = 70°C POWER
RATING
TA = 85°C POWER
RATING
TSSOP-8 (PW)
3.9 mW/°C
387 mW
213 mW
155 mW
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Copyright © 2004–2010, Texas Instruments Incorporated
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SBVS043A – MARCH 2004 – REVISED MARCH 2010
RECOMMENDED OPERATING CONDITIONS
TPS2110A, TPS2111A
MIN
Input voltage at IN1, VI(IN1)
Input voltage at IN2, VI(IN2)
MAX
1.5
5.5
VI(IN2) < 2.8 V
2.8
5.5
VI(IN1) ≥ 2.8 V
1.5
5.5
VI(IN1) < 2.8 V
2.8
5.5
Input voltage: VI(DO), VI(D1), VI(VSNS)
Current limit adjustment range, IO(OUT)
NOM
VI(IN2) ≥ 2.8 V
0
5.5
TPS2110A
0.31
0.75
TPS2111A
0.63
1.25
–40
125
Operating virtual junction temperature, TJ
UNIT
V
V
V
A
°C
ELECTRICAL CHARACTERISTICS: Power Switch
Over recommended operating junction temperature, VI(IN1) = VI(IN2) = 5.5 V, and RILIM = 400 Ω, unless otherwise noted.
TPS2110A
PARAMETER
Drain-source
on-state
resistance
(INx−OUT)
(1)
TEST CONDITIONS
TJ = 25°C,
IL = 500 mA
rDS(on) (1)
TJ = 125°C,
IL = 500 mA
MIN
TPS2111A
TYP
MAX
MIN
TYP
MAX
VI(IN1) = VI(IN2) = 5.0 V
120
140
84
110
VI(IN1) = VI(IN2) = 3.3 V
120
140
84
110
VI(IN1) = VI(IN2) = 2.8 V
120
140
84
110
VI(IN1) = VI(IN2) = 5.0 V
220
150
VI(IN1) = VI(IN2) = 3.3 V
220
150
VI(IN1) = VI(IN2) = 2.8 V
220
150
UNIT
mΩ
mΩ
The TPS211xA can switch a voltage as low as 1.5 V as long as there is a minimum of 2.8 V at one of the input power pins. In this
specific case, the lower supply voltage has no effect on the IN1 and IN2 switch on-resistances.
ELECTRICAL CHARACTERISTICS
Over recommended operating junction temperature, VI(IN1) = VI(IN2) = 5.5 V, IO(OUT) = 0 A, and RILIM = 400 Ω, unless otherwise
noted.
TPS2110A, TPS2111A
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
LOGIC INPUTS (D0 AND D1)
High-level input voltage
VIH
Low-level input voltage
VIL
Input current at D0 or D1
2
V
0.7
D0 or D1 = High, sink current
D0 or D1 = Low, source current
1
0.5
1.4
5
D1 = High, D0 = Low (IN1 active),
VI(IN2) = 3.3 V
55
90
D1 = High, D0 = Low (IN1 active),
VI(IN1) = 3.3 V
1
12
V
mA
SUPPLY AND LEAKAGE CURRENTS
Supply current from IN1 (operating)
Supply current from IN2 (operating)
D0 = D1 = Low (IN2 active), VI(IN2) = 3.3 V
75
D0 = D1 = Low (IN2 active), VI(IN1) = 3.3 V
1
D1 = High, D0 = Low (IN1 active),
VI(IN2) = 3.3 V
1
D1 = High, D0 = Low (IN1 active),
VI(IN1) = 3.3 V
75
D0 = D1 = Low (IN2 active), VI(IN2) = 3.3 V
1
12
D0 = D1 = Low (IN2 active), VI(IN1) = 3.3 V
55
90
Copyright © 2004–2010, Texas Instruments Incorporated
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mA
mA
3
TPS2110A
TPS2111A
SBVS043A – MARCH 2004 – REVISED MARCH 2010
www.ti.com
ELECTRICAL CHARACTERISTICS (continued)
Over recommended operating junction temperature, VI(IN1) = VI(IN2) = 5.5 V, IO(OUT) = 0 A, and RILIM = 400 Ω, unless otherwise
noted.
TPS2110A, TPS2111A
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
0.5
2
UNIT
SUPPLY AND LEAKAGE CURRENTS, continued
Quiescent current from IN1 (standby)
Quiescent current from IN2 (standby)
D0 = D1 = High (inactive), VI(IN2) = 3.3 V
D0 = D1 = High (inactive), VI(IN1) = 3.3 V
1
D0 = D1 = High (inactive), VI(IN2) = 3.3 V
1
mA
mA
D0 = D1 = High (inactive), VI(IN1) = 3.3 V
0.5
2
Forward leakage current from IN1
(measured from OUT to GND)
D0 = D1 = High (inactive), IN2 open, VO(OUT)
= 0 V (shorted), TJ = 25°C
0.1
5
mA
Forward leakage current from IN2
(measured from OUT to GND)
D0 = D1 = High (inactive), IN1 open, VO(OUT)
= 0 V (shorted), TJ = 25°C
0.1
5
mA
Reverse leakage current to INx (measured
from INx to GND)
D0 = D1 = High (inactive), VI(INx) = 0 V,
VO(OUT) = 5.5 V, TJ = 25°C
0.3
5
mA
CURRENT LIMIT CIRCUIT
TPS2110A
Current limit accuracy
TPS2111A
Current limit settling time
td
Input current at ILIM
RILIM = 400 Ω
0.51
0.63
0.80
RILIM = 700 Ω
0.30
0.36
0.50
RILIM = 400 Ω
0.95
1.25
1.56
RILIM = 700 Ω
0.47
0.71
0.99
Time for short-circuit output current to settle
within 10% of its steady state value.
1
A
A
ms
VI(ILIM) = 0 V, IO(OUT) = 0 A
–15
0
VI(VSNS) ↑
0.78
0.80
0.82
VI(VSNS) ↓
0.735
0.755
0.775
60
mV
150
220
ms
1
mA
mA
VSNS COMPARATOR
VSNS threshold voltage
VSNS comparator hysteresis
30
Deglitch of VSNS comparator (both ↑ ↓ )
90
0 V ≤ VI(VSNS) ≤ 5.5 V
Input current
–1
V
UVLO
Falling edge
IN1 and IN2 UVLO
1.15
Rising edge
IN1 and IN2 UVLO hysteresis
Falling edge
Internal VDD UVLO
(the higher of IN1 and IN2)
1.30
1.35
30
57
65
2.4
2.53
Rising edge
Internal VDD UVLO hysteresis
30
UVLO deglitch for IN1, IN2
1.25
Falling edge
2.58
2.8
50
75
110
V
mV
V
mV
ms
REVERSE CONDUCTION BLOCKING
Minimum output-to-input
voltage difference to block
switching
ΔVO(I_block)
D0 = D1 = high, VI(INx) = 3.3 V. Connect OUT
to a 5-V supply through a series 1-kΩ resistor.
Let D0 = low. Slowly decrease the supply
voltage until OUT connects to IN1.
80
100
120
mV
THERMAL SHUTDOWN
Thermal shutdown threshold
TPS211xA is in current limit.
135
°C
Recovery from thermal shutdown
TPS211xA is in current limit.
125
°C
Hysteresis
10
°C
IN2−IN1 COMPARATORS
Hysteresis of IN2−IN1 comparator
0.1
Deglitch of IN2−IN1 comparator (both ↑ ↓)
10
4
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20
0.2
V
50
ms
Copyright © 2004–2010, Texas Instruments Incorporated
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TPS2111A
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SBVS043A – MARCH 2004 – REVISED MARCH 2010
SWITCHING CHARACTERISTICS
Over recommended operating junction temperature, VI(IN1) = VI(IN2) = 5.5 V, and RILIM = 400 Ω, unless otherwise noted.
TPS2110A
PARAMETER
TEST CONDITIONS
tR
Output rise
time from an
enable
VI(IN1) = VI(IN2) = 5 V
TJ = 25°C,
CL = 1 mF,
IL = 500 mA; see
Figure 1(a).
tF
Output fall time
VI(IN1) = VI(IN2) = 5 V
from a disable
TJ = 25°C,
CL = 1 mF,
IL = 500 mA; see
Figure 1(a).
IN1 to IN2 transition,
VI(IN1) = 3.3 V,
VI(IN2) = 5 V
tT
Transition time
IN2 to IN1 transition,
VI(IN1) = 5 V,
VI(IN2) = 3.3 V
TPS2111A
MIN
TYP
MAX
MIN
TYP
MAX
0.5
1.0
1.5
1
1.8
3
ms
0.35
0.5
0.7
0.5
1
2
ms
40
60
40
60
TJ = 125°C,
CL = 10 mF,
IL = 500 mA;
measure transition
time as 10% to 90%
rise time or from 3.4
V to 4.8 V on
VO(OUT). See
Figure 1(b).
UNIT
ms
40
60
40
60
tPLH1
Turn-on
propagation
delay from an
enable
VI(IN1) = VI(IN2) = 5 V
Measured from
enable to 10% of
VO(OUT)
TJ = 25°C,
CL = 10 mF,
IL = 500 mA; see
Figure 1(a).
0.5
1
ms
tPHL1
Turn-off
propagation
delay from a
disable
VI(IN1) = VI(IN2) = 5 V
Measured from
disable to 90% of
VO(OUT)
TJ = 25°C,
CL = 10 mF,
IL = 500 mA; see
Figure 1(a).
3
5
ms
tPLH2
Switch-over
rising
propagation
delay
Logic 1 to Logic 0
transition on D1,
VI(IN1) = 1.5 V,
VI(IN2) = 5 V,
VI(D0) = 0 V,
Measured from D1 to
10% of VO(OUT)
TJ = 25°C,
CL = 10 mF,
IL = 500 mA; see
Figure 1(c).
40
100
tPHL2
Switch-over
falling
propagation
delay
Logic 0 to Logic 1
transition on D1,
VI(IN1) = 1.5 V,
VI(IN2) = 5 V,
VI(D0) = 0 V,
Measured from D1 to
90% of VO(OUT)
TJ = 25°C,
CL = 10 mF,
IL = 500 mA; see
Figure 1(c).
3
10
2
Copyright © 2004–2010, Texas Instruments Incorporated
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2
40
100
ms
5
10
ms
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TPS2110A
TPS2111A
SBVS043A – MARCH 2004 – REVISED MARCH 2010
www.ti.com
PARAMETER MEASUREMENT INFORMATION
TIMING WAVEFORMS
VO(OUT)
90%
90%
10%
0V
10%
tR
tPLH1
tF
tPHL1
DO, D1
Switch Off
Switch Enabled
Switch Off
(a)
5V
4.8 V
VO(OUT)
3.4 V
3.3 V
tT
DO, D1
Switch #1 Enabled
Switch #2 Enabled
(b)
5V
VO(OUT)
4.65 V
1.85 V
1.5 V
tPLH2
tPHL2
DO, D1
Switch #1 Enabled
Switch #2 Enabled
Switch #1 Enabled
(c)
Figure 1. Propagation Delays and Transition Timing Waveforms
6
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SBVS043A – MARCH 2004 – REVISED MARCH 2010
DEVICE INFORMATION
TRUTH TABLE
(1)
(2)
VI(VSNS) > 0.8 V (1)
VI(IN2) > VI(IN1)
OUT (2)
0
X
X
IN2
1
Yes
X
IN1
0
1
No
No
IN1
0
1
No
Yes
IN2
1
0
X
X
IN1
1
1
X
X
Hi-Z
D1
D0
0
0
X = Don’t care.
The undervoltage lockout circuit causes the output to go Hi-Z if the selected power supply does not exceed the IN1/IN2 UVLO, or if
neither of the supplies exceeds the internal VDD UVLO.
PIN CONFIGURATIONS
PW PACKAGE
TSSOP-8
(TOP VIEW)
D0
1
8
IN1
D1
2
7
OUT
VSNS
3
6
IN2
ILIM
4
5
GND
Table 1. TERMINAL FUNCTIONS
TERMINAL
NAME
NO.
I/O
D0
1
I
DESCRIPTION
D1
2
I
GND
5
Power
IN1
8
I
Primary power switch input. The IN1 switch can be enabled only if the IN1 supply is above
the UVLO threshold and at least one supply exceeds the internal VDD UVLO.
IN2
6
I
Secondary power switch input. The IN2 switch can be enabled only if the IN2 supply is
above the UVLO threshold and at least one supply exceeds the internal VDD UVLO.
ILIM
4
I
A resistor (RILIM) from ILIM to GND sets the current limit IL to 250/RILIM and 500/RILIM for the
TPS2110A and TPS2111A, respectively.
OUT
7
O
Power switch output
VSNS
3
I
In the auto-switching mode (D0 = 1, D1 = 0), an internal power FET connects OUT to IN1 if
the VSNS voltage is greater than 0.8 V. Otherwise, the FET connects OUT to the higher of
IN1 and IN2. The Truth Table illustrates the functionality of VSNS.
TTL- and CMOS-compatible input pins. Each pin has a 1-mA pull-up. The Truth Table
illustrates the functionality of D0 and D1.
Ground
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TPS2110A
TPS2111A
SBVS043A – MARCH 2004 – REVISED MARCH 2010
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FUNCTIONAL BLOCK DIAGRAM
Internal VDD
1 mA
1 mA
Vf = 0 V
Vf = 0 V
IN1
7
OUT
Q2
6
IN2
IO(OUT)
Q1
8
Charge
Pump
k ´ IO(OUT)
TPS2110A: k = 0.2%
TPS2111A: k = 0.1%
VDD
UVLO
ILIM
0.5 V
EN2
Q2 is on
EN1
Q1 is on
100 mV
UVLO (VDD)
VO(OUT) > VI(INx)
UVLO (IN2)
+
IN1
UVLO
0.6 V
Cross-Conduction
Detector
+
IN2
UVLO
4
UVLO (IN1)
1
D0
D0
2
D1
D1
3
VSNS
Control
Logic
EN1
Thermal
Sense
VI(SNS) > 0.8 V
IN2
0.8 V
GND
8
IN1
5
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SBVS043A – MARCH 2004 – REVISED MARCH 2010
TYPICAL CHARACTERISTICS
OUTPUT SWITCHOVER RESPONSE
5V
TPS2111APW
VI(D0)
2 V/div
1
2
f = 28 Hz
78% Duty Cycle
3
VI(D1)
2 V/div
4
0.1 mF
D0
IN1
D1
OUT
VSNS
ILIM
IN2
GND
8
7
6
5
1 mF
50 W
400 W
3.3 V
VO(OUT)
2 V/div
0.1 mF
t - Time - 1 ms/div
Output Switchover Response Test Circuit
Figure 2.
OUTPUT TURN-ON RESPONSE
5V
VI(D0)
2 V/div
TPS2111APW
f = 28 Hz
78% Duty Cycle
1
2
VI(D1)
2 V/div
3
4
D0
IN1
D1
OUT
VSNS
ILIM
IN2
GND
0.1 mF
8
7
6
5
1 mF
50 W
400 W
VO(OUT)
2 V/div
3.3 V
0.1 mF
Output Turn-On Response Test Circuit
t - Time - 2 ms/div
Figure 3.
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TPS2110A
TPS2111A
SBVS043A – MARCH 2004 – REVISED MARCH 2010
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TYPICAL CHARACTERISTICS (continued)
OUTPUT SWITCHOVER VOLTAGE DROOP
5V
TPS2111APW
VI(D0)
2 V/div
1
f = 580 Hz
90% Duty Cycle
VI(D1)
2 V/div
2
3
CL = 1 mF
4
0.1 mF
D0
IN1
D1
OUT
VSNS
ILIM
IN2
GND
8
7
6
5
CL
50 W
400 W
VO(OUT)
2 V/div
0.1 mF
C L = 0 mF
Output Switchover Voltage Droop Test Circuit
t - Time - 40 ms/div
Figure 4.
10
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SBVS043A – MARCH 2004 – REVISED MARCH 2010
TYPICAL CHARACTERISTICS (continued)
OUTPUT SWITCHOVER VOLTAGE DROOP
vs
LOAD CAPACITANCE
5.0
VI = 5 V
DVO(OUT) - Output Voltage Droop - V
4.5
4.0
3.5
3.0
RL= 10 W
2.5
2.0
1.5
RL= 50 W
1.0
0.5
0
0.1
1
10
100
CL - Load Capacitance - mF
VI
TPS2111APW
1
f = 28 Hz
50% Duty Cycle
2
3
4
0.1 mF
D0
IN1
D1
OUT
VSNS
ILIM
IN2
GND
8
7
6
5
400 W
0.1 mF
0.1 mF
1 mF
10 mF
47 mF
100 mF
50 W
10 W
Output Switchover Voltage Droop Test Circuit
Figure 5.
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TPS2110A
TPS2111A
SBVS043A – MARCH 2004 – REVISED MARCH 2010
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TYPICAL CHARACTERISTICS (continued)
AUTO SWITCHOVER VOLTAGE DROOP
VI(IN1)
2 V/div
5V
TPS2111A
0.1 mF
1 kW
1
2
f = 220 Hz
20% Duty Cycle
3
4
VO(OUT)
2 V/div
D0
IN1
OUT
D1
VSNS
IN2
GND
ILIM
8
7
6
VOUT
3.3 V
10 mF
5
50 W
0.1 mF
400 W
75% less output voltage
droop compared to TPS2111
Auto Switchover Voltage Droop Test Circuit
t - Time - 250 ms/div
Figure 6.
12
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SBVS043A – MARCH 2004 – REVISED MARCH 2010
TYPICAL CHARACTERISTICS (continued)
INRUSH CURRENT
vs
LOAD CAPACITANCE
300
II - Inrush Current - mA
250
200
VI = 5 V
150
VI = 3.3 V
100
50
0
20
0
60
40
80
100
CL - Load Capacitance - mF
VI
TPS2111APW
1
f = 28 Hz
90% Duty Cycle
NC
2
3
4
D0
0.1 mF
IN1
OUT
D1
VSNS
IN2
GND
ILIM
8
To Oscilloscope
7
6
50 W
5
400 W
0.1 mF
0.1 mF
1 mF
10 mF
47 mF
100 mF
Output Capacitor Inrush Current Test Circuit
Figure 7.
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TPS2110A
TPS2111A
SBVS043A – MARCH 2004 – REVISED MARCH 2010
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TYPICAL CHARACTERISTICS (continued)
SWITCH ON-RESISTANCE
vs
JUNCTION TEMPERATURE
SWITCH ON-RESISTANCE
vs
SUPPLY VOLTAGE
180
120
TPS2110A
rDS(on) - Switch-On Resistance - mW
rDS(on) - Switch-On Resistance - mW
115
160
140
TPS2110A
120
100
TPS2111A
80
110
105
100
95
90
TPS2111A
85
60
80
-50
0
50
100
150
2
5
6
VI(INx) - Supply Voltage - V
Figure 8.
Figure 9.
IN1 SUPPLY CURRENT
vs
SUPPLY VOLTAGE
IN1 SUPPLY CURRENT
vs
SUPPLY VOLTAGE
60
0.96
Device Disabled
VI(IN2) = 0 V
IO(OUT) = 0 A
IN1 Switch is On
VI(IN2) = 0 V
IO(OUT) = 0 A
58
II(IN1) - IN1 Supply Current - mA
0.94
II(IN1) - IN1 Supply Current - mA
4
3
TJ - Junction Temperature - °C
0.92
0.90
0.88
0.86
56
54
52
50
48
46
44
0.84
42
40
0.82
2
3
4
5
6
2
3
VI(IN1) - IN1 Supply Voltage - V
Figure 10.
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4
5
6
VI(IN1) - Supply Voltage - V
Figure 11.
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Product Folder Link(s): TPS2110A TPS2111A
TPS2110A
TPS2111A
www.ti.com
SBVS043A – MARCH 2004 – REVISED MARCH 2010
TYPICAL CHARACTERISTICS (continued)
SUPPLY CURRENT
vs
JUNCTION TEMPERATURE
SUPPLY CURRENT
vs
JUNCTION TEMPERATURE
1.2
70
II(INx) - Supply Current - mA
II(INx) - Supply Current - mA
1.0
80
Device Disabled
VI(IN1) = 5.5 V
VI(IN2) = 3.3 V
IO(OUT) = 0 A
II(IN1) = 5.5 V
0.8
0.6
0.4
60
IN1 Switch is On
VI(IN1) = 5.5 V
VI(IN2) = 3.3 V
IO(OUT) = 0 A
II(IN1)
50
40
30
20
0.2
10
II(IN2) = 3.3 V
0
-50
0
50
100
150
0
-50
TJ - Junction Temperature - °C
Figure 12.
II(IN2)
0
50
100
150
TJ - Junction Temperature - °C
Figure 13.
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TPS2110A
TPS2111A
SBVS043A – MARCH 2004 – REVISED MARCH 2010
www.ti.com
APPLICATION INFORMATION
Some applications have two energy sources, one of which should be used in preference to another. Figure 14
shows a circuit that will connect IN1 to OUT until the voltage at IN1 falls below a user-specified value. Once the
voltage on IN1 falls below this value, the TPS211xA will select the higher of the two supplies. This usually means
that the TPS211xA will swap to IN2.
IN1: 2.8 V to 5.5 V
C1
0.1 mF
TPS2110A/TPS2111A
1
NC
2
R1
8
D0
IN1
D1
OUT
7
3
6
VSNS
IN2
CL
5
4
R2
ILIM
RL
GND
RILIM
IN2: 2.8 V to 5.5 V
C2
0.1 mF
Figure 14. Auto-Selecting for a Dual Power-Supply Application
In Figure 15, the multiplexer selects between two power supplies based upon the EN1 logic signal. OUT
connects to IN1 if EN1 is logic '1'; otherwise, OUT connects to IN2. The logic thresholds for the D1 terminal are
compatible with both TTL and CMOS logic.
IN1: 2.8 V to 5.5 V
C1
0.1 mF
TPS2110A/TPS2111A
1
2
EN1
8
D0
IN1
D1
OUT
7
3
6
VSNS
IN2
CL
5
4
ILIM
RL
GND
RILIM
IN2: 2.8 V to 5.5 V
C2
0.1 mF
Figure 15. Manually Switching Power Sources
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Product Folder Link(s): TPS2110A TPS2111A
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TPS2111A
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SBVS043A – MARCH 2004 – REVISED MARCH 2010
DETAILED DESCRIPTION
AUTO-SWITCHING MODE
D0 equal to logic '1' and D1 equal to logic '0' selects the auto-switching mode. In this mode, OUT connects to
IN1 if VI(VSNS) is greater than 0.8 V; otherwise, OUT connects to the higher of IN1 and IN2.
The VSNS terminal includes hysteresis equal to 3.75% to 7.5% of the threshold selected for transition from the
primary supply to the higher of the two supplies. This hysteresis helps avoid repeated switching from one supply
to the other due to resistive drops.
MANUAL SWITCHING MODE
D0 equal to logic '0' selects the manual-switching mode. In this mode, OUT connects to IN1 if D1 is equal to logic
'1'; otherwise, OUT connects to IN2.
N-CHANNEL MOSFETs
Two internal high-side power MOSFETs implement a single-pole double-throw (SPDT) switch. Digital logic
selects the IN1 switch, IN2 switch, or no switch (Hi-Z state). The MOSFETs have no parallel diodes so
output-to-input current cannot flow when the FET is off. An integrated comparator prevents turn-on of a FET
switch if the output voltage is greater than the input voltage.
CROSS-CONDUCTION BLOCKING
The switching circuitry ensures that both power switches will never conduct at the same time. A comparator
monitors the gate-to-source voltage of each power FET and allows a FET to turn on only if the gate-to-source
voltage of the other FET is below the turn-on threshold voltage.
REVERSE-CONDUCTION BLOCKING
When the TPS211xA switches from a higher-voltage supply to a lower-voltage supply, current can potentially
flow back from the load capacitor into the lower-voltage supply. To minimize such reverse conduction, the
TPS211xA will not connect a supply to the output until the output voltage has fallen to within 100 mV of the
supply voltage. Once a supply has been connected to the output, it will remain connected regardless of output
voltage.
CHARGE PUMP
The higher of supplies IN1 and IN2 powers the internal charge pump. The charge pump provides power to the
current limit amplifier and allows the output FET gate voltage to be higher than the IN1 and IN2 supply voltages.
A gate voltage that is higher than the source voltage is necessary to turn on the N-channel FET.
CURRENT LIMITING
A resistor RILIM from ILIM to GND sets the current limit to 250/RILIM and 500/RILIM for the TPS2110A and
TPS2111A, respectively. Setting resistor RILIM equal to zero is not recommended as that disables current limiting.
OUTPUT VOLTAGE SLEW-RATE CONTROL
The TPS211xA slews the output voltage at a slow rate when OUT switches to IN1 or IN2 from the Hi-Z state (see
the Truth Table). A slow slew rate limits the inrush current into the load capacitor. High inrush currents can glitch
the voltage bus and cause a system to hang up or reset. It can also cause reliability issues—like pit the
connector power contacts, when hot-plugging a load such as a PCI card. The TPS211xA slews the output
voltage at a much faster rate when OUT switches between IN1 and IN2. The fast rate minimizes the output
voltage droop and reduces the output voltage hold-up capacitance requirement.
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Product Folder Link(s): TPS2110A TPS2111A
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TPS2110A
TPS2111A
SBVS043A – MARCH 2004 – REVISED MARCH 2010
www.ti.com
REVISION HISTORY
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Original (March, 2004) to Revision A
Page
•
Updated document to current format .................................................................................................................................... 1
•
Deleted package information from Available Options table .................................................................................................. 2
•
Revised Ordering Information table ...................................................................................................................................... 2
•
Deleted lead temperature and storage temperature specifications from, added electrostatic discharge specifications
to Absolute Maximum Ratings table; changed operating virtual junction temperature specification; deleted ESD
Protection table ..................................................................................................................................................................... 2
•
Updated conditions for Electrical Characteristics ................................................................................................................. 3
•
Deleted footnote 1 for Electrical Characteristics table .......................................................................................................... 3
•
Deleted footnote 1 for Switching Characteristics table ......................................................................................................... 5
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Product Folder Link(s): TPS2110A TPS2111A
PACKAGE OPTION ADDENDUM
www.ti.com
14-Oct-2022
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
Samples
(4/5)
(6)
TPS2110APW
ACTIVE
TSSOP
PW
8
150
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 85
2110A
Samples
TPS2110APWR
ACTIVE
TSSOP
PW
8
2000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 85
2110A
Samples
TPS2111APW
ACTIVE
TSSOP
PW
8
150
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 85
2111A
Samples
TPS2111APWR
ACTIVE
TSSOP
PW
8
2000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 85
2111A
Samples
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of
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