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TPS3700
SBVS187G – FEBRUARY 2012 – REVISED FEBRUARY 2019
TPS3700 High voltage (18V) window voltage detector with internal reference
for over and undervoltage monitoring
1 Features
3 Description
•
•
•
The TPS3700 wide-supply window voltage detector
operates over a 1.8-V to 18-V range. The device has
two high-accuracy comparators with an internal 400mV reference and two open-drain outputs rated to 18
V for over- and undervoltage detection. The TPS3700
can be used as a window voltage detector or as two
independent voltage monitors; the monitored voltage
can be set with the use of external resistors.
Wide supply voltage range: 1.8 V to 18 V
Adjustable threshold: down to 400 mV
High threshold accuracy:
– 1.0% over temperature
– 0.25% (Typical)
Low quiescent current: 5.5 µA (Typical)
Open-drain outputs for overvoltage and
undervoltage detection
Internal hysteresis: 5.5 mV (Typ)
Temperature range: –40°C to 125°C
Packages:
– SOT-6
– 1.5-mm × 1.5-mm WSON-6
•
•
•
•
•
2 Applications
•
•
•
•
The TPS3700 is available in a SOT-6 and a 1.5-mm
× 1.5-mm WSON-6 package and is specified over the
junction temperature range of –40°C to 125°C.
Industrial control systems
Automotive systems
Embedded computing modules
DSP, microcontroller, or microprocessor
applications
Notebook and desktop computers
Portable- and battery-powered products
FPGA and ASIC applications
•
•
•
OUTA is driven low when the voltage at INA+ drops
below (VITP – VHYS), and goes high when the voltage
returns above the respective threshold (VITP). OUTB
is driven low when the voltage at INB– rises above
VITP, and goes high when the voltage drops below the
respective threshold (VITP – VHYS). Both comparators
in the TPS3700 include built-in hysteresis for filtering
to reject brief glitches, thereby ensuring stable output
operation without false triggering.
Device Information(1)
PART NUMBER
TPS3700
WSON (6)
1.50 mm × 1.50 mm
Output vs Input Thresholds and Hysteresis
OUTA
1.8 V to 18 V
0.1 µF
VDD
R1
RP1
OUTA
INA+
INA+
RP2
R2
Device
VIT+
INB±
VIT+
To a reset
or enable
input of
the system.
OUTB
INB–
R3
BODY SIZE (NOM)
2.90 mm × 1.60 mm
(1) For all available packages, see the orderable addendum at
the end of the datasheet.
Simplified Schematic
VMON
PACKAGE
SOT (6)
OUTB
1
GND
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
TPS3700
SBVS187G – FEBRUARY 2012 – REVISED FEBRUARY 2019
www.ti.com
Table of Contents
1
2
3
4
5
6
7
Features ..................................................................
Applications ...........................................................
Description .............................................................
Revision History.....................................................
Pin Configuration and Functions .........................
Specifications.........................................................
1
1
1
3
4
5
6.1
6.2
6.3
6.4
6.5
6.6
6.7
6.8
5
5
5
5
6
7
7
8
Absolute Maximum Ratings ......................................
ESD Ratings..............................................................
Recommended Operating Conditions.......................
Thermal Information ..................................................
Electrical Characteristics...........................................
Timing Requirements ................................................
Switching Characteristics ..........................................
Typical Characteristics ..............................................
Detailed Description ............................................ 10
7.1 Overview ................................................................. 10
7.2 Functional Block Diagram ....................................... 10
7.3 Feature Description................................................. 10
2
7.4 Device Functional Modes........................................ 12
8
Application and Implementation ........................ 13
8.1 Application Information............................................ 13
8.2 Typical Application .................................................. 16
8.3 Do's and Don'ts ....................................................... 18
9 Power-Supply Recommendations...................... 19
10 Layout................................................................... 19
10.1 Layout Guidelines ................................................. 19
10.2 Layout Example .................................................... 19
11 Device and Documentation Support ................. 20
11.1
11.2
11.3
11.4
11.5
11.6
11.7
Device Support......................................................
Documentation Support ........................................
Receiving Notification of Documentation Updates
Community Resources..........................................
Trademarks ...........................................................
Electrostatic Discharge Caution ............................
Glossary ................................................................
20
20
20
20
20
20
21
12 Mechanical, Packaging, and Orderable
Information ........................................................... 21
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4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision F (January 2018) to Revision G
•
Page
Changed comparator to voltage detector throughout datasheet ............................................................................................ 1
Changes from Revision E (February 2017) to Revision F
•
Page
Changed comparator to supervisor throughout datasheet .................................................................................................... 1
Changes from Revision D (January 2015) to Revision E
Page
•
Added maximum specification to Start-up delay parameter .................................................................................................. 6
•
Changed at least 150 µs to 450 µs (max) in footnote 2 of Electrical Characteristics table .................................................. 6
Changes from Revision C (May 2013) to Revision D
Page
•
Added ESD Ratings table, Feature Description section, Device Functional Modes, Application and Implementation
section, Power Supply Recommendations section, Layout section, Device and Documentation Support section, and
Mechanical, Packaging, and Orderable Information section ................................................................................................. 5
•
Changed HBM maximum specification from 2 kV to 2.5 kV in ESD Ratings ......................................................................... 5
•
Changed Functional Block Diagram; added hysteresis symbol .......................................................................................... 10
Changes from Revision B (April 2012) to Revision C
Page
•
Changed Packages Features bullet ....................................................................................................................................... 1
•
Added SON-6 package option to Description section ............................................................................................................ 1
•
Added DSE pin out graphic to front page............................................................................................................................... 1
•
Added DSE pin out graphic .................................................................................................................................................... 4
•
Added DSE package to Thermal Information table ................................................................................................................ 5
Changes from Revision A (February 2012) to Revision B
•
Page
Moved to Production Data ...................................................................................................................................................... 1
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5 Pin Configuration and Functions
DDC Package
SOT-6
Top View
DSE Package
WSON-6
Top View
OUTA
1
6
OUTB
GND
2
5
VDD
INA+
3
4
INB-
OUTB
1
6
OUTA
VDD
2
5
GND
INB-
3
4
INA+
Pin Functions
PIN
NAME
I/O
DESCRIPTION
DDC
DSE
GND
2
5
—
INA+
3
4
I
This pin is connected to the voltage to be monitored with the use of an external resistor
divider. When the voltage at this terminal drops below the threshold voltage (VITP –
VHYS), OUTA is driven low.
INB–
4
3
I
This pin is connected to the voltage to be monitored with the use of an external resistor
divider. When the voltage at this terminal exceeds the threshold voltage (VITP), OUTB is
driven low.
OUTA
1
6
O
INA+ comparator open-drain output. OUTA is driven low when the voltage at this
comparator is below (VITP – VHYS). The output goes high when the sense voltage returns
above the respective threshold (VITP).
OUTB
6
1
O
INB– comparator open-drain output. OUTB is driven low when the voltage at this
comparator exceeds VITP. The output goes high when the sense voltage returns below
the respective threshold (VITP – VHYS).
VDD
5
2
I
Supply voltage input. Connect a 1.8-V to 18-V supply to VDD to power the device. Good
analog design practice is to place a 0.1-µF ceramic capacitor close to this pin.
4
Ground
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6 Specifications
6.1 Absolute Maximum Ratings
over operating temperature range (unless otherwise noted) (1)
Voltage
(2)
Current
MIN
MAX
UNIT
VDD
–0.3
20
V
OUTA, OUTB
–0.3
20
V
INA+, INB–
–0.3
7
V
40
mA
Output terminal current
Operating junction temperature, TJ
–40
125
°C
Storage temperature, Tstg
–65
150
°C
(1)
(2)
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
All voltages are with respect to network ground terminal.
6.2 ESD Ratings
VALUE
V(ESD)
(1)
(2)
Electrostatic discharge
Human body model (HBM), per ANSI/ESDA/JEDEC JS-001, all pins (1)
±2500
Charged device model (CDM), per JEDEC specification JESD22-C101,
all pins (2)
±1000
UNIT
V
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
6.3 Recommended Operating Conditions
over operating temperature range (unless otherwise noted)
MIN
VDD
Supply voltage
VI
Input voltage
VO
Output voltage
NOM
MAX
UNIT
1.8
18
V
INA+, INB–
0
6.5
V
OUTA, OUTB
0
18
V
6.4 Thermal Information
TPS3700
THERMAL METRIC (1)
DDC (SOT)
DSE (WSON)
6 PINS
6 PINS
UNIT
RθJA
Junction-to-ambient thermal resistance
204.6
194.9
°C/W
RθJC(top)
Junction-to-case (top) thermal resistance
50.5
128.9
°C/W
RθJB
Junction-to-board thermal resistance
54.3
153.8
°C/W
ψJT
Junction-to-top characterization parameter
0.8
11.9
°C/W
ψJB
Junction-to-board characterization parameter
52.8
157.4
°C/W
RθJC(bot)
Junction-to-case (bottom) thermal resistance
N/A
N/A
°C/W
(1)
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
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6.5 Electrical Characteristics
Over the operating temperature range of TJ = –40°C to 125°C, and 1.8 V < VDD < 18 V, unless otherwise noted.
Typical values are at TJ = 25°C and VDD = 5 V.
PARAMETER
VDD
TEST CONDITIONS
Supply voltage range
V(POR)
Power-on reset voltage
MIN
TYP
1.8
(1)
VOLmax = 0.2 V, I(OUTA/B) = 15 µA
MAX
UNIT
18
V
0.8
V
VDD = 1.8 V
396
400
404
VDD = 18 V
396
400
404
VDD = 1.8 V
387
394.5
400
VDD = 18 V
387
394.5
400
VIT+
Positive-going input threshold voltage
VIT–
Negative-going input threshold voltage
Vhys
Hysteresis voltage (hys = VIT+ – VIT–)
5.5
12
I(INA+)
Input current (at the INA+ terminal)
VDD = 1.8 V and 18 V, VI = 6.5 V
–25
1
25
nA
I(INB–)
Input current (at the INB– terminal)
VDD = 1.8 V and 18 V, VI = 0.1 V
–15
1
15
nA
VOL
Low-level output voltage
Ilkg(OD)
Open-drain output leakage-current
VDD = 1.3 V, IO = 0.4 mA
250
VDD = 1.8 V, IO = 3 mA
250
VDD = 5 V, IO = 5 mA
250
VDD = 1.8 V and 18 V, VO = VDD
300
VDD = 1.8 V, VO = 18 V
300
VDD = 1.8 V, no load
IDD
Supply current
Start-up delay
UVLO
(1)
(2)
(3)
6
mV
mV
nA
5.5
11
VDD = 5 V
6
13
VDD = 12 V
6
13
VDD = 18 V
7
13
150
450
µs
1.7
V
(2)
Undervoltage lockout (3)
mV
VDD falling
1.3
µA
The lowest supply voltage (VDD) at which output is active; tr(VDD) > 15 µs/V. Below V(POR), the output cannot be determined.
During power on, VDD must exceed 1.8 V for 450 µs (max) before the output is in a correct state.
When VDD falls below UVLO, OUTA is driven low and OUTB goes to high impedance. The outputs cannot be determined below V(POR).
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6.6 Timing Requirements
over operating temperature range (unless otherwise noted)
MIN
NOM
MAX
UNIT
tPHL
High-to-low propagation delay (1)
VDD = 5 V, 10-mV input overdrive,
RP = 10 kΩ, VOH = 0.9 × VDD, VOL = 400 mV,
see Figure 1
18
µs
tPLH
Low-to-high propagation delay (1)
VDD = 5 V, 10-mV input overdrive,
RP = 10 kΩ, VOH = 0.9 × VDD, VOL = 400 mV,
see Figure 1
29
µs
(1)
High-to-low and low-to-high refers to the transition at the input terminals (INA+ and INB–).
6.7 Switching Characteristics
Over operating temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
tr
Output rise time
VDD = 5 V, 10-mV input overdrive,
RP = 10 kΩ, VO = (0.1 to 0.9) × VDD
tf
Output fall time
VDD = 5 V, 10-mV input overdrive,
RP = 10 kΩ, VO = (0.1 to 0.9) × VDD
TYP
MAX
UNIT
2.2
µs
0.22
µs
VDD
VIT+
Vhys
INA+
OUTA
tPHL
tPLH
tPLH
VIT+
Vhys
INB–
OUTB
tPLH
tPHL
Figure 1. Timing Diagram
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6.8 Typical Characteristics
at TJ = 25°C and VDD = 5 V (unless otherwise noted)
10
401
Positive-Going Input Threshold (mV)
9
Supply Current (µA)
8
7
6
5
4
3
40qC
0qC
25qC
85qC
125qC
2
1
0
0
2
4
6
8
10
12
Supply Voltage (V)
14
16
400.6
399.4
-25
-10
5
D001
20
35
50
65
Temperature (qC)
80
95
110 125
D003
Figure 3. Rising Input Threshold Voltage (VIT+) vs
Temperature
9
Low-to-High Propagation Delay (µs)
31
8
Hysteresis Voltage (mV)
1.8 V
5V
1.2 V
18 V
399.8
Figure 2. Supply Current (IDD) vs Supply Voltage (VDD)
7
6
5
VDD
VDD
VDD
VDD
4
3
-40
-25
-10
5
20
35
50
65
Temperature (qC)
80
95
=
=
=
=
1.8 V
5V
12 V
18 V
27
25
23
21
19
17
15
13
11
9
-40
110 125
VDD = 1.8 V, INB to OUTB
VDD = 18 V, INB to OUTB
VDD = 1.8 V, INA+ to OUTA
VDD = 18 V, INA+ to OUTA
29
-25
D004
20
28
18
26
16
Input Pulse Duration (µs)
30
24
22
20
18
16
14
VDD = 1.8 V, INB to OUTB
VDD = 18 V, INB to OUTB
VDD = 1.8 V, INA+ to OUTA
VDD = 18 V, INA+ to OUTA
12
10
8
-40
-25
-10
5
20 35 50 65
Temperature (qC)
80
95
-10
5
20 35 50 65
Temperature (qC)
80
95
110 125
D005
Figure 5. Propagation Delay vs Temperature
(High-to-Low Transition at the Inputs)
Figure 4. Hysteresis (Vhys) vs Temperature
Low-to-High Propagation Delay (µs)
=
=
=
=
400.2
399
-40
18
VDD
VDD
VDD
VDD
INA+
INB–
14
12
10
8
6
4
2
110 125
D006
0
2.5
4
5.5
7
8.5
10
11.5
13
14.5
Positive-Going Input Threshold Overdrive (%)
16
D007
INA+ = negative spike below VIT–
INB– = positive spike above VIT+
Figure 6. Propagation Delay vs Temperature
(Low-to-High Transition at the Inputs)
8
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Figure 7. Minimum Pulse Duration vs
Threshold Overdrive Voltage
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Typical Characteristics (continued)
at TJ = 25°C and VDD = 5 V (unless otherwise noted)
11
2000
Low-Level Output Voltage(mV)
10
Supply Current (µA)
9
8
7
6
5
4
40qC
0qC
25qC
85qC
125qC
3
2
VDD = 1.8 V
VDD = 5 V
VDD = 18 V
1750
1500
1250
1000
750
500
250
1
0
0
4
8
12
16
20
24
28
Output Sink Current (mA)
32
36
40
0
Figure 8. Supply Current (IDD) vs
Output Sink Current
15
20
25
30
Output Sink Current (mA)
35
40
D009
2000
VDD = 1.8 V
VDD = 5 V
VDD = 18 V
1750
Low-Level Output Voltage (mV)
Low-Level Output Voltage(mV)
10
Figure 9. Output Voltage Low (VOL) vs
Output Sink Current (–40°C)
2000
1500
1250
1000
750
500
250
0
VDD = 1.8 V
VDD = 5 V
VDD = 18 V
1750
1500
1250
1000
750
500
250
0
0
5
10
15
20
25
30
Output Sink Current (mA)
35
40
0
5
10
D010
Figure 10. Output Voltage Low (VOL) vs
Output Sink Current (0°C)
15
20
25
30
Output Sink Current (mA)
35
40
D011
Figure 11. Output Voltage Low (VOL) vs
Output Sink Current (25°C)
2000
2000
VDD = 1.8 V
VDD = 5 V
VDD = 18 V
VDD = 1.8 V
VDD = 5 V
VDD = 18 V
1750
Low-level output voltage (mV)
1750
Low-level output voltage (mV)
5
D008
1500
1250
1000
750
500
1500
1250
1000
750
500
250
250
0
0
0
5
10
15
20
25
30
Output Sink Current (mA)
35
40
0
D012
Figure 12. Output Voltage Low (VOL) vs
Output Sink Current (85°C)
5
10
15
20
25
30
Output Sink Current (mA)
35
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D013
Figure 13. Output Voltage Low (VOL) vs
Output Sink Current (125°C)
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7 Detailed Description
7.1 Overview
The TPS3700 device combines two voltage detectors for overvoltage and undervoltage detection. The TPS3700
device is a wide-supply voltage range (1.8 V to 18 V) device with a high-accuracy rising input threshold of
400 mV (1% over temperature) and built-in hysteresis. The outputs are also rated to 18 V and can sink up to
40 mA.
The TPS3700 device is designed to assert the output signals, as shown in Table 1. Each input terminal can be
set to monitor any voltage above 0.4 V using an external resistor divider network. With the use of two input
terminals of different polarities, the TPS3700 device forms a window voltage detector. Broad voltage thresholds
can be supported that allow the device to be used in a wide array of applications.
Table 1. TPS3700 Truth Table
CONDITION
OUTPUT
STATUS
INA+ > VIT+
OUTA high
Output A not asserted
INA+ < VIT–
OUTA low
Output A asserted
INB– > VIT+
OUTB low
Output B asserted
INB– < VIT–
OUTB high
Output B not asserted
7.2 Functional Block Diagram
VDD
INA+
OUTA
OUTB
INB–
Reference
GND
7.3 Feature Description
7.3.1 Inputs (INA+, INB–)
The TPS3700 device is a voltage detector that combines two comparators. Each comparator has one external
input (inverting and noninverting); the other input is connected to the internal reference. The comparator rising
threshold is designed and trimmed to be equal to the reference voltage (400 mV). Both comparators also have a
built-in falling hysteresis that makes the device less sensitive to supply rail noise and ensures stable operation.
The INA+ and INB- inputs can swing from ground to 6.5 V, regardless of the device supply voltage used.
Although not required in most cases, good analog design practice is to place a 1-nF to 10-nF bypass capacitor at
the comparator input for extremely noisy applications to reduce sensitivity to transients and layout parasitics.
For comparator A, the corresponding output (OUTA) is driven to logic low when the input INA+ voltage drops
below (VIT+ – Vhys). When the voltage exceeds VIT+, the output (OUTA) goes to a high-impedance state; see
Figure 1.
10
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Feature Description (continued)
For comparator B, the corresponding output (OUTB) is driven to logic low when the voltage at input INB–
exceeds VIT+. When the voltage drops below VIT+ – Vhys the output (OUTB) goes to a high-impedance state; see
Figure 1. Together, these comparators form a window-detection function as discussed in the Window Voltage
Detector section.
7.3.2 Outputs (OUTA, OUTB)
In a typical TPS3700 application, the outputs are connected to a reset or enable input of the processor (such as
a digital signal processor [DSP], central processing unit [CPU], field-programmable gate array [FPGA], or
application-specific integrated circuit [ASIC]) or the outputs are connected to the enable input of a voltage
regulator (such as a DC-DC or low-dropout regulator [LDO]).
The TPS3700 device provides two open-drain outputs (OUTA and OUTB). Pullup resistors must be used to hold
these lines high when the output goes to high impedance (not asserted). By connecting pullup resistors to the
proper voltage rails, the outputs can be connected to other devices at the correct interface-voltage levels. The
TPS3700 outputs can be pulled up to 18 V, independent of the device supply voltage. By using wired-OR logic,
OUTA and OUTB can merge into one logic signal that goes low if either outputs are asserted because of a fault
condition.
Table 1 and the Inputs (INA+, INB–) section describe how the outputs are asserted or deasserted. See Figure 1
for a timing diagram that describes the relationship between threshold voltages and the respective output.
7.3.3 Window Voltage Detector
The inverting and noninverting configuration of the comparators forms a window-voltage detection circuit using a
resistor divider network, as illustrated in Figure 14 and Figure 15. The input terminals can monitor any system
voltage above 400 mV with the use of a resistor divider network. The INA+ and INB– terminals monitor for
undervoltage and overvoltage conditions, respectively.
VMON
1.8 V to 18 V
VDD
RP1
(50 kW)
IN
OUTA
INA+
Voltage
Regulator VO
R2
(13.7 kW)
OUTB
INB–
R3
(69.8 kW)
EN
Device
OUT
R1
(2.21 MW)
UV VMON OV
OUT
GND
Figure 14. Window Voltage Detector Block Diagram
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Feature Description (continued)
Overvoltage
Limit
VMON
Undervoltage
Limit
OUTB
OUTA
Figure 15. Window Voltage Detector Timing Diagram
7.3.4 Immunity to Input Terminal Voltage Transients
The TPS3700 device is relatively immune to short voltage transient spikes on the input terminals. Sensitivity to
transients depends on both transient duration and amplitude; see the Minimum Pulse Duration vs Threshold
Overdrive Voltage curve (Figure 7) in the Typical Characteristics section.
7.4 Device Functional Modes
7.4.1 Normal Operation (VDD > UVLO)
When the voltage on VDD is greater than 1.8 V for at least 150 µs, the OUTA and OUTB signals correspond to
the voltage on INA+ and INB– as listed in Table 1.
7.4.2 Undervoltage Lockout (V(POR) < VDD < UVLO)
When the voltage on VDD is less than the device UVLO voltage, and greater than the power-on reset voltage,
V(POR), the OUTA and OUTB signals are asserted and high impedance, respectively, regardless of the voltage on
INA+ and INB–.
7.4.3
Power-On Reset (VDD < V(POR))
When the voltage on VDD is lower than the required voltage to internally pull the asserted output to GND (V(POR)),
both outputs are in a high-impedance state.
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8 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
8.1 Application Information
The TPS3700 device is a wide-supply window voltage detector that operates over a VDD range of 1.8 V to 18 V.
The device has two high-accuracy comparators with an internal 400-mV reference and two open-drain outputs
rated to 18 V for overvoltage and undervoltage detection. The device can be used either as a window voltage
detector or as two independent voltage monitors. The monitored voltages are set with the use of external
resistors.
8.1.1 VPULLUP to a Voltage Other Than VDD
The outputs are often tied to VDD through a resistor. However, some applications may require the outputs to be
pulled up to a higher or lower voltage than VDD to correctly interface with the reset and enable terminals of other
devices.
VPULLUP
(Up To 18 V)
1.8 V to 18 V
VDD
OUTA
INA+
To a reset or enable input
of the system.
Device
OUTB
INB–
GND
Figure 16. Interfacing to Voltages Other Than VDD
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Application Information (continued)
8.1.2 Monitoring VDD
Many applications monitor the same rail that is powering VDD. In these applications the resistor divider is simply
connected to the VDD rail.
1.8 V to 18 V
VDD
OUTA
INA+
To a reset or enable input
of the system.
Device
OUTB
INB–
GND
Figure 17. Monitoring the Same Voltage as VDD
8.1.3 Monitoring a Voltage Other Than VDD
Some applications monitor rails other than the one that is powering VDD. In these types of applications the
resistor divider used to set the desired thresholds is connected to the rail that is being monitored.
VMON
(26.4 V to 21.7 V)
1.8 V to 18 V
R1
(2.61 MW)
VDD
OUTA
INA+
R2
(8.06 kW)
Device
OUTB
INB–
R3
(40.2 kW)
To a reset or enable input
of the system.
GND
NOTE: The inputs can monitor a voltage higher than VDDmax with the use of an external resistor divider network.
Figure 18. Monitoring a Voltage Other Than VDD
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Application Information (continued)
8.1.4 Monitoring Overvoltage and Undervoltage for Separate Rails
Some applications may want to monitor for overvoltage conditions on one rail while also monitoring for
undervoltage conditions on a different rail. In these applications two independent resistor dividers must be used.
1.8 V to 18 V
OUTA
INA+
To a reset or enable
input of the system.
Device
12 V
OUTB
INB–
INA+
VIT+
INB–
VIT+
OUTB
5V
OUTA
VDD
GND
NOTE: In this case, OUTA is driven low when an undervoltage condition is detected at the 5-V rail and OUTB is driven low
when an overvoltage condition is detected at the 12-V rail.
Figure 19. Monitoring Overvoltage for One Rail and Undervoltage for a Different Rail
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8.2 Typical Application
The TPS3700 device is a wide-supply window voltage detector that operates over a VDD range of 1.8 to 18 V.
The monitored voltages are set with the use of external resistors, so the device can be used either as a window
voltage detector or as two independent overvoltage and undervoltage monitors.
VDD
C1
0.1 µF
VPULLUP
R4
49.9 k
U1
TPS3700DDC
R1
2.21 M
VDD
INA+
INB±
R2
13.7 k
5
1
3
6
4
2
R5
49.9 k
OUTA
OUTB
GND
R3
69.8 k
Figure 20. Typical Application Schematic
8.2.1 Design Requirements
For this design example, use the values summarized in Table 2 as the input parameters.
Table 2. Design Parameters
PARAMETER
DESIGN REQUIREMENT
DESIGN RESULT
Monitored voltage
12-V nominal rail with maximum rising and
falling thresholds of ±10%
VMON(UV)= 10.99 V (8.33%) ±2.94%,
VMON(OV)= 13.14 V (8.33%) ±2.94%
8.2.2 Detailed Design Procedure
8.2.2.1 Resistor Divider Selection
Use Equation 1 through Equation 4 to calculate the resistor divider values and target threshold voltages.
RT = R1 + R2 + R3
(1)
Select a value for RT such that the current through the divider is approximately 100 times higher than the input
current at the INA+ and INB– terminals. The resistors can have high values to minimize current consumption as
a result of low-input bias current without adding significant error to the resistive divider. See the application note
Optimizing Resistor Dividers at a Comparator Input (SLVA450) for details on sizing input resistors.
Use Equation 2 to calculate the value of R3.
RT
R3 =
´ VIT+
VMON(OV)
where:
VMON(OV) is the target voltage at which an overvoltage condition is detected
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Use Equation 3 or Equation 4 to calculate the value of R2.
RT
R2 =
´ VIT+ - R3
VMON (no UV)
where:
VMON(no
R2 =
UV)
is the target voltage at which an undervoltage condition is removed as VMON rises
RT
VMON(UV)
´ (VIT+ - Vhys)
(3)
- R3
where:
VMON(UV) is the target voltage at which an undervoltage condition is detected
(4)
The worst-case tolerance can be calculated by referring to Equation 13 in application report SLVA450,
Optimizing Resistor Dividers at a Comparator Input (available for download at www.ti.com). An example of the
rising threshold error, VMON(OV), is given in Equation 5.
V
% ACC = % TOL(VIT+(INB)) + 2 ´ 1- IT+(INB) ´ % TOLR = 1% + 2 ´ 1- 0.4 ´ 1% = 2.94%
VMON(OV)
13.2
(5)
8.2.2.2 Pullup Resistor Selection
To ensure proper voltage levels, the pullup resistor value is selected by ensuring that the pullup voltage divided
by the resistor does not exceed the sink-current capability of the device. This confirmation is calculated by
verifying that the pullup voltage minus the output-leakage current (Ilkg(OD)) multiplied by the resistor is greater the
desired logic-high voltage. These values are specified in the Electrical Characteristics table.
Use Equation 6 to calculate the value of the pullup resistor.
VPU
(VHI - VPU)
³ RPU ³
IO
Ilkg(OD)
(6)
8.2.2.3 Input Supply Capacitor
Although an input capacitor is not required for stability, connecting a 0.1-μF low equivalent series resistance
(ESR) capacitor across the VDD terminal and GND terminal is good analog design practice. A higher-value
capacitor may be necessary if large, fast rise-time load transients are anticipated, or if the device is not located
close to the power source.
8.2.2.4 Input Capacitors
Although not required in most cases, for extremely noisy applications, placing a 1-nF to 10-nF bypass capacitor
from the comparator inputs (INA+, INB–) to the GND terminal is good analog design practice. This capacitor
placement reduces device sensitivity to transients.
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8.2.3 Application Curves
At TJ = 25°C
OUTB
C2
(2 V/div)
C1
(2 V/div)
C2
(2 V/div)
OUTB
OUTA
C3
(2 V/div)
C3
(2 V/div)
VDD
VDD = 5 V
OUTA
C1
(2 V/div)
Time (100 µs/div)
V(INA+) = 390 mV
VDD
G013
V(INB–) = 410 mV
VDD = 5 V
Figure 21. Start-Up Delay
(Outputs Pulled Up to VDD)
Time (100 µs/div)
V(INA+) = 410 mV
G014
V(INB–) = 390 mV
Figure 22. Start-Up Delay
(Outputs Pulled Up to VDD)
8.3 Do's and Don'ts
It is good analog design practice to have a 0.1-µF decoupling capacitor from VDD to GND.
If the monitored rail is noisy, connect decoupling capacitors from the comparator inputs to GND.
Do not use resistors for the voltage divider that cause the current through them to be less than 100 times the
input current of the comparators without also accounting for the effect to the accuracy.
Do not use pullup resistors that are too small, because the larger current sunk by the output then exceeds the
desired low-level output voltage (VOL).
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9 Power-Supply Recommendations
These devices are designed to operate from an input voltage supply range between 1.8 V and 18 V.
10 Layout
10.1 Layout Guidelines
Placing a 0.1-µF capacitor close to the VDD terminal to reduce the input impedance to the device is good analog
design practice. The pullup resistors can be separated if separate logic functions are needed (as shown in
Figure 23) or both resistors can be tied to a single pullup resistor if a logical AND function is desired.
VPULLUP
VPULLUP
10.2 Layout Example
Figure 23. TPS3700 Layout Schematic
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11 Device and Documentation Support
11.1 Device Support
11.1.1 Development Support
11.1.1.1 Evaluation Modules
Two evaluation modules (EVMs) are available to assist in the initial circuit performance evaluation using the
TPS3700. The TPS3700EVM-114 evaluation module and the TPS3700EVM-202 evaluation module (and the
related user's guides) can be requested at the Texas Instruments website through the TPS3700 product folder or
purchased directly from the TI eStore.
11.1.2 Device Nomenclature
Table 3. Device Nomenclature
PRODUCT
TPS3700yyyz
DESCRIPTION
yyy is package designator
z is package quantity
11.2 Documentation Support
11.2.1 Related Documentation
For related documentation, see the following:
• Using the TPS3700 as a negative rail over- and undervoltage detector
• Optimizing resistor dividers at a comparator input
• TPS3700EVM-114 Evaluation module user guide
• TPS3700EVM-202 Evaluation module user guide
11.3 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper
right corner, click on Alert me to register and receive a weekly digest of any product information that has
changed. For change details, review the revision history included in any revised document.
11.4 Community Resources
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
11.5 Trademarks
E2E is a trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
11.6 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
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11.7 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
12 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
Figure 0. UNDEFINED
Figure 0. UNDEFINED
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Figure 0. UNDEFINED
Figure 0. UNDEFINED
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PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
(4/5)
(6)
TPS3700DDCR
ACTIVE
SOT-23-THIN
DDC
6
3000
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 125
PXVQ
TPS3700DDCR2
ACTIVE
SOT-23-THIN
DDC
6
3000
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 125
PB4Q
TPS3700DDCT
ACTIVE
SOT-23-THIN
DDC
6
250
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 125
PXVQ
TPS3700DSER
ACTIVE
WSON
DSE
6
3000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
(7I, BE)
TPS3700DSET
ACTIVE
WSON
DSE
6
250
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
(7I, BE)
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of
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