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TPS43335-Q1, TPS43336-Q1
SLVSAV6E – JUNE 2011 – REVISED DECEMBER 2015
TPS4333x-Q1 Low-IQ, Single-Boost, Dual Synchronous-Buck Controller
1 Features
2 Applications
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Qualified for Automotive Applications
AEC-Q100 Test Guidance With the Following
Results:
– Device Temperature Grade 1: –40°C to 125°C
Ambient Operating Temperature
– Device HBM ESD Classification Level H2
– Device CDM ESD Classification Level C2
Two Synchronous Buck Controllers
One Pre-Boost Controller
Input Range up to 40 V, (Transients up to 60 V),
Operation Down to 2 V When Boost is Enabled
Low-Power-Mode IQ: 30 µA (One Buck On), 35 µA
(Two Bucks On)
Low Shutdown Current Ish < 4 µA
Buck Output Range 0.9 V to 11 V
Boost Output Selectable: 7 V, 10 V, or 11 V
Programmable Frequency and External
Synchronization Range 150 kHz to 600 kHz
Separate Enable Inputs (ENA, ENB)
Frequency Spread Spectrum (TPS43336-Q1)
Selectable Forced Continuous Mode or Automatic
Low-Power Mode at Light Loads
Sense Resistor or Inductor DCR Sensing
Out-of-Phase Switching Between Buck Channels
Peak Gate-Drive Current 0.7 A
Thermally Enhanced 38-Pin HTSSOP (DAP)
PowerPAD™ Package
•
Automotive Start-Stop, Infotainment, Navigation
Instrument Cluster Systems
Industrial and Automotive Multi-Rail DC Power
Distribution Systems and Electronic Control Units
3 Description
The TPS43335-Q1 and TPS43336-Q1 include two
current-mode synchronous buck controllers and a
voltage-mode boost controller. The devices are
ideally suited as a pre-regulator stage with low Iq
requirements and for applications that must survive
supply drops due to cranking events. The integrated
boost controller allows the devices to operate down to
2 V at the input without seeing a drop on the buck
regulator output stages. At light loads, one can
enable the buck controllers to operate automatically
in low-power mode, consuming just 30 µA of
quiescent current.
The buck controllers have independent soft-start
capability and power-good indicators. Current
foldback in the buck controllers and cycle-by-cycle
current limitation in the boost controller provide
external MOSFET protection. One can program the
switching frequency over 150 kHz to 600 kHz or
synchronize it to an external clock in the same range.
Additionally, the TPS43336-Q1 offers frequencyhopping spread-spectrum operation.
Device Information(1)
PART NUMBER
TPS43335-Q1
TPS43336-Q1
PACKAGE
HTSSOP (38)
BODY SIZE (NOM)
6.20 mm × 12.50 mm
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
Figure 1. Typical Application Diagram
VBAT
VBAT
TPS43335-Q1
or
TPS43336-Q1
VBuckA
VBuckA
2V
VBuckB
VBuckB
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
TPS43335-Q1, TPS43336-Q1
SLVSAV6E – JUNE 2011 – REVISED DECEMBER 2015
www.ti.com
Table of Contents
1
2
3
4
5
6
Features ..................................................................
Applications ...........................................................
Description .............................................................
Revision History.....................................................
Pin Configuration and Functions .........................
Specifications.........................................................
6.1
6.2
6.3
6.4
6.5
6.6
7
Absolute Maximum Ratings ...................................... 6
ESD Ratings.............................................................. 6
Recommended Operating Conditions....................... 7
Thermal Information .................................................. 7
DC Electrical Characteristics .................................... 8
Typical Characteristics ............................................ 12
Detailed Description ............................................ 15
7.1 Overview ................................................................
7.2 Functional Block Diagram .......................................
7.3 Feature Description.................................................
7.4 Device Functional Modes........................................
8
1
1
1
2
3
6
15
16
17
24
Application and Implementation ........................ 26
8.1 Application Information............................................ 26
8.2 Typical Applications ................................................ 26
9 Power Supply Recommendations...................... 38
10 Layout................................................................... 38
10.1 Layout Guidelines ................................................. 38
10.2 Layout Example .................................................... 39
10.3 Power Dissipation Derating Profile, 38-Pin HTTSOP
PowerPAD Package ................................................ 40
11 Device and Documentation Support ................. 41
11.1
11.2
11.3
11.4
11.5
11.6
11.7
Device Support......................................................
Documentation Support ........................................
Related Links ........................................................
Community Resources..........................................
Trademarks ...........................................................
Electrostatic Discharge Caution ............................
Glossary ................................................................
41
41
41
41
41
41
41
12 Mechanical, Packaging, and Orderable
Information ........................................................... 42
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision D (May 2013) to Revision E
•
Page
Added ESD Ratings table, Feature Description section, Device Functional Modes, Application and Implementation
section, Power Supply Recommendations section, Layout section, Device and Documentation Support section, and
Mechanical, Packaging, and Orderable Information section. ................................................................................................ 1
Changes from Revision C (June 2011) to Revision D
Page
•
Corrected pinout drawing ....................................................................................................................................................... 3
•
Changed descriptions for pins DIV, ENA, and ENB ............................................................................................................... 3
•
Revised Absolute Maximum Ratings table ............................................................................................................................. 6
•
Changed specification names for HBM and CDM classification ratings ................................................................................ 6
•
Replaced curve in Load Step Response (Boost) graph ....................................................................................................... 12
•
Revised functional block diagram......................................................................................................................................... 16
•
Revised last paragraph of Light-Load PFM Mode section ................................................................................................... 20
•
Corrected R1 + R2... equation in Resistor Divider Selection... section................................................................................ 35
2
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Copyright © 2011–2015, Texas Instruments Incorporated
Product Folder Links: TPS43335-Q1 TPS43336-Q1
TPS43335-Q1, TPS43336-Q1
www.ti.com
SLVSAV6E – JUNE 2011 – REVISED DECEMBER 2015
5 Pin Configuration and Functions
DAP Package
38-Pin HTSSOP With Thermal Pad
Top View
VBAT
1
38
VIN
DS
2
37
GC1
3
36
DIV
GC2
4
35
VREG
CBA
5
34
CBB
GA1
6
33
GB1
PHA
7
32
PHB
GA2
8
31
GB2
PGNDA
EXTSUP
PGNDB
9
30
SA1
10
29
SA2
11
28
SB2
FBA
12
27
FBB
COMPA
SB1
COMPB
13
26
SSA
14
25
PGA
15
24
PGB
ENA
16
23
AGND
ENB
17
22
RT
18
21
DLYAB
19
20
SYNC
COMPC
ENC
SSB
Pin Functions
PIN
I/O
DESCRIPTION
NAME
NO.
AGND
23
O
Analog ground reference
CBA
5
I
A capacitor on this pin acts as the voltage supply for the high-side N-channel MOSFET gate-drive circuitry in buck
controller BuckA. When the buck is in a dropout condition, the device automatically reduces the duty cycle of the
high-side MOSFET to approximately 95% on every fourth cycle to allow the capacitor to recharge.
CBB
34
I
A capacitor on this pin acts as the voltage supply for the high-side N-channel MOSFET gate-drive circuitry in buck
controller BuckB. When the buck is in a dropout condition, the device automatically reduces the duty cycle of the
high-side MOSFET to approximately 95% on every fourth cycle to allow the capacitor to recharge.
COMPA
13
O
Error amplifier output of BuckA and compensation node for voltage-loop stability. The voltage at this node sets the
target for the peak current through the inductor of BuckA. Clamping his voltage on the upper and lower ends
provides current-limit protection for the external MOSFETs.
COMPB
26
O
Error amplifier output of BuckB and compensation node for voltage-loop stability. The voltage at this node sets the
target for the peak current through the inductor of BuckB. Clamping his voltage on the upper and lower ends
provides current-limit protection for the external MOSFETs.
COMPC
18
O
Error-amplifier output and loop-compensation node of the boost regulator
DIV
36
I
The status of this pin defines the output voltage of the boost regulator. A high input regulates the boost converter
at 11 V, a low input sets the value at 7 V, and a floating pin sets 10 V. NOTE: DIV = high and ENC = high inhibits
low-power mode on the bucks.
DLYAB
21
O
The capacitor at the DLYAB pin sets the power-good delay interval used to de-glitch the outputs of the powergood comparators. Leaving this pin open sets the power-good delay to an internal default value of 20 µs typical.
DS
2
I
This input monitors the voltage on the external boost-converter low-side MOSFET for overcurrent protection. An
alternative connection for better noise immunity is to place a sense resistor between the source of the low-side
MOSFET and ground via a filter network.
Copyright © 2011–2015, Texas Instruments Incorporated
Product Folder Links: TPS43335-Q1 TPS43336-Q1
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TPS43335-Q1, TPS43336-Q1
SLVSAV6E – JUNE 2011 – REVISED DECEMBER 2015
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Pin Functions (continued)
PIN
NAME
NO.
I/O
DESCRIPTION
ENA
16
I
Enable input for BuckA (active-high with an internal pullup current source). An input voltage higher than 1.7 V
enables the controller, whereas an input voltage lower than 1.7 V disables the controller. When both ENA and
ENB are low, the device shuts down and consumes less than 4 µA of current. NOTE: DIV = high and ENC = high
inhibits low-power mode on the bucks.
ENB
17
I
Enable input for BuckB (active-high with an internal pullup current source). An input voltage higher than 1.7 V
enables the controller, whereas an input voltage lower than 1.7 V disables the controller. When both ENA and
ENB are low, the device shuts down and consumes less than 4 µA of current. NOTE: DIV = high and ENC = high
inhibits low-power mode on the bucks.
ENC
19
I
This input enables and disables the boost regulator. An input voltage higher than 1.7 V enables the controller.
Voltages lower than 0.7 V disable the controller. Because this pin provides an internal pulldown resistor (500 kΩ),
enabling the boost function requires pulling it high. When enabled, the controller starts switching as soon as VBAT
falls below the boost threshold, depending on the programmed output voltage.
EXTSUP
37
I
One can use EXTSUP to supply the VREG regulator from one of the TPS43335-Q1 or TPS43336-Q1 buck
regulator rails to reduce power dissipation in cases where there is an expectation of high VIN. If EXTSUP is
unused, leave the pin open without a capacitor installed.
FBA
12
I
Feedback voltage pin for BuckA. The buck controller regulates the feedback voltage to the internal reference of
0.8 V. A suitable resistor divider network between the buck output and the feedback pin sets the desired output
voltage.
FBB
27
I
Feedback voltage pin for BuckB. The buck controller regulates the feedback voltage to the internal reference of
0.8 V. A suitable resistor-divider network between the buck output and the feedback pin sets the desired output
voltage.
GA1
6
O
This output can drive the external high-side N-channel MOSFET for buck regulator BuckA. The output provides
high peak currents to drive capacitive loads. The gate drive reference is to a floating ground provided by PHA that
has a voltage swing provided by CBA.
GA2
8
O
This output can drive the external low-side N-channel MOSFET for buck regulator BuckA. The output provides
high peak currents to drive capacitive loads. VREG provides the voltage swing on this pin.
GB1
33
O
This output can drive the external high-side N-channel MOSFET for buck regulator BuckB. The output provides
high peak currents to drive capacitive loads. The gate drive reference is to a floating ground provided by PHB that
has a voltage swing provided by CBB.
GB2
31
O
This output can drive the external low-side N-channel MOSFET for buck regulator BuckB. The output provides
high peak currents to drive capacitive loads. VREG provides the voltage swing on this pin.
GC1
3
O
This output can drive an external low-side N-channel MOSFET for the boost regulator. This output provides high
peak currents to drive capacitive loads. VREG provides the voltage swing on this pin.
GC2
4
O
This pin makes a floating output drive available to control the external P-channel MOSFET. This MOSFET can
bypass the boost rectifier diode or a reverse-protection diode when the boost is not switching or if boost is
disabled, and thus reduce power losses.
PGA
15
O
Open-drain power-good indicator pin for BuckA. An internal power-good comparator monitors the voltage at the
feedback pin and pulls this output low when the output voltage falls below 93% of the set value, or if either VIN or
VBAT drops below its respective undervoltage threshold.
PGB
24
O
Open-drain power-good indicator pin for BuckB. An internal power-good comparator monitors the voltage at the
feedback pin and pulls this output low when the output voltage falls below 93% of the set value, or if either VIN or
VBAT drops below its respective undervoltage threshold.
PGNDA
9
O
Power ground connection to the source of the low-side N-channel MOSFET of BuckA
PGNDB
30
O
Power ground connection to the source of the low-side N-channel MOSFET of BuckB
PHA
7
O
Switching terminal of buck regulator BuckA, providing a floating ground reference for the high-side MOSFET gatedriver circuitry and used to sense current reversal in the inductor when discontinuous-mode operation is desired.
PHB
32
O
Switching terminal of buck regulator BuckB, providing a floating ground reference for the high-side MOSFET gatedriver circuitry and used to sense current reversal in the inductor when discontinuous-mode operation is desired.
RT
22
O
Connecting a resistor to ground on this pin sets the operational switching frequency of the buck and boost
controllers. A short circuit to ground on this pin defaults operation to 400 kHz for the buck controllers and 200 kHz
for the boost controller.
SA1
10
I
SA2
11
I
4
High-impedance differential-voltage inputs from the current-sense element (sense resistor or inductor DCR) for
each buck controller. Choose the current-sense element to set the maximum current through the inductor based
on the current-limit threshold (subject to tolerances) and considering the typical characteristics across duty cycle
and VIN. (SA1 positive node, SA2 negative node).
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Product Folder Links: TPS43335-Q1 TPS43336-Q1
TPS43335-Q1, TPS43336-Q1
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SLVSAV6E – JUNE 2011 – REVISED DECEMBER 2015
Pin Functions (continued)
PIN
NAME
NO.
I/O
DESCRIPTION
SB1
29
I
High-impedance differential voltage inputs from the current-sense element (sense resistor or inductor DCR) for
each buck controller. Choose the current-sense element to set the maximum current through the inductor based
on the current-limit threshold (subject to tolerances) and considering the typical characteristics across duty cycle
and VIN. (SB1 positive node, SB2 negative node).
SB2
28
I
SSA
14
O
Soft-start or tracking input for buck controller BuckA. The buck controller regulates the FBA voltage to the lower of
0.8 V or the SSA pin voltage. An internal pullup current source of 1 µA is present at the pin, and an appropriate
capacitor connected here sets the soft-start ramp interval. Alternatively, a resistor divider connected to another
supply can provide a tracking input to this pin.
SSB
25
O
Soft-start or tracking input for buck controller BuckB. The buck controller regulates the FBB voltage to the lower of
0.8 V or the SSB pin voltage. An internal pullup current source of 1 µA is present at the pin, and an appropriate
capacitor connected here sets the soft-start ramp interval. Alternatively, a resistor divider connected to another
supply can provide a tracking input to this pin.
SYNC
20
I
If an external clock is present on this pin, the device detects it and the internal PLL locks onto the external clock,
thus overriding the internal oscillator frequency. The device can synchronize to frequencies from 150 kHz to 600
kHz. A high logic level on this pin ensures forced continuous-mode operation of the buck controllers and inhibits
transition to low-power mode. An open or low allows discontinuous-mode operation and entry into low-power
mode at light loads. On the TPS43336-Q1, a high level enables frequency-hopping spread spectrum, whereas an
open or a low level disables it.
VBAT
1
I
Battery input sense for the boost controller. If, with the boost controller enabled, the voltage at VBAT falls below
the boost threshold, the device activates the boost controller and regulates the voltage at VIN to the programmed
boost output voltage.
VIN
38
I
Main input pin. This is the buck controller input pin as well as the output of the boost regulator. Additionally, VIN
powers the internal control circuits of the device.
VREG
35
O
The device requires an external capacitor on this pin to provide a regulated supply for the gate drivers of the buck
and boost controllers. TI recommends capacitance on the order of 4.7 µF. The regulator obtains its power from
either VIN or EXTSUP. This pin has current-limit protection; do not use it to drive any other loads.
Copyright © 2011–2015, Texas Instruments Incorporated
Product Folder Links: TPS43335-Q1 TPS43336-Q1
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TPS43335-Q1, TPS43336-Q1
SLVSAV6E – JUNE 2011 – REVISED DECEMBER 2015
www.ti.com
6 Specifications
6.1 Absolute Maximum Ratings
See
(1)
Voltage
MIN
MAX
UNIT
Input voltage: VIN, VBAT
–0.3
60
V
Ground: PGNDA–AGND, PGNDB–AGND
–0.3
0.3
Enable inputs: ENA, ENB
–0.3
60
Bootstrap inputs: CBA, CBB
–0.3
68
Bootstrap inputs: CBA–PHA, CBB–PHB
–0.3
8.8
Phase inputs: PHA, PHB
–0.7
60
–1
60
Feedback inputs: FBA, FBB
–0.3
13
Error amplifier outputs: COMPA, COMPB
–0.3
13
High-side MOSFET driver: GA1–PHA, GB1–PHB
–0.3
8.8
Low-side MOSFET drivers: GA2–PGNDA, GB2–PGNDB
–0.3
8.8
Current-sense voltage: SA1, SA2, SB1, SB2
–0.3
13
Soft start: SSA, SSB
–0.3
13
Power-good output: PGA, PGB
–0.3
13
Power-good delay: DLYAB
–0.3
13
Switching-frequency timing resistor: RT
–0.3
13
SYNC, EXTSUP
–0.3
13
Low-side MOSFET driver: GC1–PGNDA
–0.3
8.8
Error-amplifier output: COMPC
–0.3
13
Enable input: ENC
–0.3
13
Current-limit sense: DS
–0.3
60
Output-voltage select: DIV
–0.3
8.8
P-channel MOSFET driver: GC2
–0.3
60
P-channel MOSFET driver: VIN–GC2
–0.3
8.8
Gate-driver supply: VREG
–0.3
8.8
Junction temperature, TJ
–40
150
Operating temperature, TA
–40
125
Storage temperature, Tstg
–55
165
Phase inputs: PHA, PHB (for 150 ns)
Voltage
(buck function:
BuckA and BuckB)
Voltage (boost function)
Voltage (PMOS driver)
Voltage
Temperature
(1)
V
V
V
V
°C
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
6.2 ESD Ratings
VALUE
Human-body model (HBM), per AEC Q100-002
V(ESD)
Electrostatic discharge
Charged-device model (CDM),
per AEC Q100-011
Machine model (MM)
(1)
6
(1)
UNIT
±2000
FBA, FBB, RT, DLYAB
±400
VBAT, ENC, SYNC, VIN
±750
All other pins
±500
PGA, PGB
±150
All other pins
±200
V
AEC Q100-002 indicates that HBM stressing shall be in accordance with the ANSI/ESDA/JEDEC JS-001 specification.
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Product Folder Links: TPS43335-Q1 TPS43336-Q1
TPS43335-Q1, TPS43336-Q1
www.ti.com
SLVSAV6E – JUNE 2011 – REVISED DECEMBER 2015
6.3 Recommended Operating Conditions
Buck function:
BuckA and BuckB voltage
Boost function
MIN
MAX
Input voltage: VIN, VBAT
4
40
Enable inputs: ENA, ENB
0
40
Boot inputs: CBA, CBB
4
48
Phase inputs: PHA, PHB
–0.6
40
Current-sense voltage: SA1, SA2, SB1, SB2
0
11
Power-good output: PGA, PGB
0
11
SYNC, EXTSUP
0
9
Enable input: ENC
0
DIV
V
9
Voltage sense: DS
Operating temperature, TA
UNIT
40
0
VREG
–40
125
V
°C
6.4 Thermal Information
TPS4333x-Q1
THERMAL METRIC (1)
DAP (HTSSOP)
UNIT
38 PINS
RθJA
Junction-to-ambient thermal resistance
27.3
°C/W
RθJC(top)
Junction-to-case (top) thermal resistance
19.6
°C/W
RθJB
Junction-to-board thermal resistance
15.9
°C/W
ψJT
Junction-to-top characterization parameter
0.24
°C/W
ψJB
Junction-to-board characterization parameter
6.6
°C/W
RθJC(bot)
Junction-to-case (bottom) thermal resistance
1.2
°C/W
(1)
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report, SPRA953.
Copyright © 2011–2015, Texas Instruments Incorporated
Product Folder Links: TPS43335-Q1 TPS43336-Q1
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6.5 DC Electrical Characteristics
VIN = 8 V to 18 V, TJ = –40°C to 150°C (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
INPUT SUPPLY
VBAT
Boost controller enabled, after satisfying initial start-up
condition
Supply voltage
Input voltage required for device on
initial start-up
VIN
VIN falling. After a reset, initial start-up conditions may
apply. (1)
Buck undervoltage lockout
VBOOST_UNLOCK
Boost unlock threshold
VBAT rising
(2)
LPM quiescent current:
Iq_LPM
6.5
40
4
40
3.5
VIN rising. After a reset, initial start-up conditions may
apply. (1)
LPM quiescent current:
Iq_LPM_
40
(2)
8.2
Quiescent current:
normal (PWM) mode (2)
3.6
3.8
V
3.8
4
V
V
8.5
8.8
VIN = 13 V, BuckA: LPM, BuckB: off, TA = 25°C
30
40
VIN = 13 V, BuckB: LPM, BuckA: off, TA = 25°C
30
40
VIN = 13 V, BuckA, B: LPM, TA = 25°C
35
45
VIN = 13 V, BuckA: LPM, BuckB: off, TA = 125°C
40
50
VIN = 13 V, BuckB: LPM, BuckA: off, TA = 125°C
40
50
VIN = 13 V, BuckA, B: LPM, TA = 125°C
Iq_NRM
V
V
Buck regulator operating range after
initial start-up
VIN(UV)
2
45
55
SYNC = HIGH, TA = 25°C
4.85
5.3
VIN = 13 V, BuckA: CCM, BuckB: off, TA = 25°C
4.85
5.3
VIN = 13 V, BuckB: CCM, BuckA: off, TA = 25°C
4.85
5.3
VIN = 13 V, BuckA, B: CCM, TA = 25°C
7
7.6
SYNC = HIGH, TA = 125°C
5
5.5
VIN = 13 V, BuckA: CCM, BuckB: off, TA = 125°C
5
5.5
VIN = 13 V, BuckB: CCM, BuckA: off, TA = 125°C
5
5.5
µA
µA
µA
µA
mA
Iq_NRM
Quiescent current:
normal (PWM) mode (2)
VIN = 13 V, BuckA, B: CCM, TA = 125°C
7.5
8
Ibat_sh
Shutdown current
BuckA, B: off, VBAT = 13 V , TA = 25°C
2.5
4
µA
Ibat_sh
Shutdown current
BuckA, B: off, VBAT = 13 V, TA = 125°C
3
5
µA
mA
INPUT VOLTAGE VBAT - UNDERVOLTAGE LOCKOUT
VBAT(UV)
Boost-input undervoltage
UVLOHys
Hysteresis
UVLOfilter
Filter time
VBAT falling. After a reset, initial start-up conditions may
apply. (1)
1.8
1.9
2
V
VBAT rising. After a reset, initial start-up conditions may
apply. (1)
2.4
2.5
2.6
V
500
600
700
mV
5
µs
INPUT VOLTAGE VIN - OVERVOLTAGE LOCKOUT
VOVLO
Overvoltage shutdown
OVLOHys
Hysteresis
OVLOfilter
Filter time
(1)
(2)
8
VIN rising
45
46
47
VIN falling
43
44
45
1
2
3
5
V
V
µs
If VBAT and VREG remain adequate, the buck can continue to operate if VIN is > 3.8 V.
Quiescent current specification is non-switching current consumption without including the current in the external-feedback resistor
divider.
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SLVSAV6E – JUNE 2011 – REVISED DECEMBER 2015
DC Electrical Characteristics (continued)
VIN = 8 V to 18 V, TJ = –40°C to 150°C (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
BOOST CONTROLLER
Vboost7V
Vboost7V-th
Vboost10V
Vboost10V-th
Vboost11V
Vboost11V-th
Boost VOUT = 7 V
DIV = low, VBAT = 2 V to 7 V
6.8
7
7.3
Boost-enable threshold
Boost VOUT = 7 V, VBAT falling
7.5
8
8.5
Boost-disable threshold
Boost VOUT = 7 V, VBAT rising
Boost hysteresis
Boost VOUT = 7 V, VBAT rising or falling
Boost VOUT = 10 V
Boost-enable threshold
8
8.5
9
0.4
0.5
0.6
DIV = open, VBAT = 2 V to 10 V
9.7
10
10.4
Boost VOUT = 10 V, VBAT falling
10.5
11
11.5
Boost-disable threshold
Boost VOUT = 10 V, VBAT rising
11
11.5
12
Boost hysteresis
Boost VOUT = 10 V, VBAT rising or falling
0.4
0.5
0.6
Boost VOUT = 11 V
DIV = VREG, VBAT = 2 V to 11 V
10.7
11
11.4
Boost-enable threshold
Boost VOUT = 11 V, VBAT falling
11.5
12
12.5
Boost-disable threshold
Boost VOUT = 11 V, VBAT rising
12
12.5
13
Boost hysteresis
Boost VOUT = 11 V, VBAT rising or falling
0.4
0.5
0.6
0.2
0.225
V
V
V
V
V
V
BOOST-SWITCH CURRENT LIMIT
VDS
Current-limit sensing
tDS
Leading-edge blanking
DS input with respect to PGNDA
0.175
200
V
ns
GATE DRIVER FOR BOOST CONTROLLER
IGC1
Peak
rDS(on)
Gate-driver peak current
1.5
Source and sink driver
VREG = 5.8 V, IGC1 current = 200 mA
A
2
Ω
GATE DRIVER FOR PMOS
rDS(on)
PMOS OFF
IPMOS_ON
Gate current
VIN = 13.5 V, VGS = –5 V
10
tdelay_ON
Turnon delay
C = 10 nF
20
10
Ω
mA
5
10
µs
BOOST-CONTROLLER SWITCHING FREQUENCY
fsw-Boost
Boost switching frequency
DBoost
Boost duty cycle
fSW_Buck / 2
kHz
90%
ERROR AMPLIFIER (OTA) FOR BOOST CONVERTERS
GmBOOST
Forward transconductance
VBAT = 12 V
0.8
1.35
VBAT = 5 V
0.35
0.65
mS
BUCK CONTROLLERS
VBuckA or VBuckB Adjustable output-voltage range
Vref,
NRM
Internal reference and tolerance
voltage in normal mode
Vref,
LPM
Internal reference and tolerance
voltage in low-power mode
0.9
Measure FBX pin
Measure FBX pin
0.784
V sense for reverse-current limit in
CCM
VI-Foldback
V sense for output short
tdead
Shoot-through delay, blanking time
Maximum duty cycle (digitally
controlled)
DCLPM
Duty cycle, LPM
ILPM_Entry
LPM entry-threshold load current as
fraction of maximum set load current
ILPM_Exit
LPM exit-threshold load current as
fraction of maximum set load current
V
V
0.800
0.816
V
2%
60
75
90
mV
FBx = 1 V
–65
–37.5
–23
mV
FBx = 0 V
17
32.5
48
mV
High-side minimum on-time
DCNRM
11
0.808
1%
–2%
FBx = 0.75 V (low duty cycle)
(3)
0.800
–1%
V sense for forward-current limit in
CCM
Vsense
0.792
20
ns
100
ns
98.75%
80%
1%
See (3)
See (3)
10%
The exit threshold specification is to be always higher than the entry threshold.
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DC Electrical Characteristics (continued)
VIN = 8 V to 18 V, TJ = –40°C to 150°C (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
HIGH-SIDE EXTERNAL NMOS GATE DRIVERS FOR BUCK CONTROLLER
IGX1_peak
Gate-driver peak current
rDS(on)
Source and sink driver
0.7
VREG = 5.8 V, IGX1 current = 200 mA
A
4
Ω
4
Ω
LOW-SIDE NMOS GATE DRIVERS FOR BUCK CONTROLLER
IGX2_peak
Gate driver peak current
RDS
Source and sink driver
ON
0.7
VREG = 5.8 V, IGX2 current = 200 mA
A
ERROR AMPLIFIER (OTA) FOR BUCK CONVERTERS
GmBUCK
Transconductance
COMPA, COMPB = 0.8 V,
source/sink = 5 µA, test in feedback loop
IPULLUP_FBx
Pullup current at FBx pins
0.72
1
1.35
mS
FBx = 0 V
50
100
200
nA
1.7
DIGITAL INPUTS: ENA, ENB, ENC, SYNC
VIH
Higher threshold
VIN= 13 V
VIL
Lower threshold
VIN = 13 V
V
RIH_SYNC
Pulldown resistance on SYNC
VSYNC = 5 V
500
RIL_ENC
Pulldown resistance on ENC
VENC = 5 V
500
IIL_ENx
Pullup current source on ENA, ENB
VENx = 0 V,
0.5
0.7
V
kΩ
kΩ
2
µA
BOOST OUTPUT VOLTAGE: DIV
VIH_DIV
Higher threshold
VIL_DIV
Lower threshold
Voz_DIV
Voltage on DIV if unconnected
VREG = 5.8 V
VREG – 0.2
V
0.2
Voltage on DIV if unconnected
VREG / 2
V
V
SWITCHING PARAMETER – BUCK DC-DC CONTROLLERS
fSW_Buck
Buck switching frequency
RT pin: GND
360
400
440
kHz
fSW_Buck
Buck switching frequency
RT pin: 60-kΩ external resistor
360
400
440
kHz
fSW_adj
Buck adjustable range with external
resistor
RT pin: external resistor
150
600
kHz
fSYNC
Buck synchronization range
External clock input
150
600
kHz
fSS
Spread-spectrum spreading
TPS43336-Q1 only
5.8
6.1
V
0.2%
1%
7.5
7.8
0.2%
1%
4.6
4.8
V
5%
INTERNAL GATE-DRIVER SUPPLY
Internal regulated supply
VIN = 8 V to 18 V, VEXTSUP = 0 V, SYNC = high
Load regulation
IVREG = 0 mA to 100 mA, VEXTSUP = 0 V,
SYNC = high
Internal regulated supply
VEXTSUP = 8.5 V
Load regulation
IEXTSUP = 0 mA to 125 mA, SYNC = High
VEXTSUP = 8.5 V to 13 V
VEXTSUP-th
EXTSUP switch-over voltage
threshold
IVREG = 0 mA to 100 mA,
VEXTSUP ramping positive
VEXTSUP-Hys
EXTSUP switch-over hysteresis
150
250
mV
IVREG-Limit
Current limit on VREG
VEXTSUP = 0 V, normal mode as well as LPM
100
400
mA
IVREG_EXTSUP-
Current limit on VREG when using
EXTSUP
IVREG = 0 mA to 100 mA,
VEXTSUP = 8.5 V, SYNC = High
125
400
mA
Soft-start source current
VSSA and VSSB = 0 V
0.75
1.25
µA
VREG
VREG(EXTSUP)
Limit
5.5
7.2
4.4
V
SOFT START
ISSx
1
OSCILLATOR (RT)
VRT
10
Oscillator reference voltage
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1.2
V
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SLVSAV6E – JUNE 2011 – REVISED DECEMBER 2015
DC Electrical Characteristics (continued)
VIN = 8 V to 18 V, TJ = –40°C to 150°C (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
–5%
–7%
MAX
UNIT
POWER GOOD / DELAY
PGpullup
Pullup for A and B to Sx2
PGth1
Power-good threshold
PGhys
Hysteresis
PGdrop
Voltage drop
50
FBx falling
kΩ
–9%
2%
IPGA = 5 mA
450
mV
IPGA = 1 mA
100
mV
1
µA
16
µs
PGleak
Power-good leakage
VSx2 = VPGx = 13 V
tdeglitch
Power-good deglitch time
tdelay
Reset delay
External capacitor = 1 nF
VBuckX < PGth1
tdelay_fix
Fixed reset delay
No external capacitor, pin open
IOH
Activate current source (current to
charge external capacitor)
IIL
Activate current sink (current to
discharge external capacitor)
2
1
ms
20
50
µs
30
40
50
µA
30
40
50
µA
150
165
°C
15
°C
OVERTEMPERATURE PROTECTION
Tshutdown
Junction-temperature shutdown
threshold
Thys
Junction-temperature hysteresis
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6.6 Typical Characteristics
10000
100
Forced Continuous Mode (Sync = 1), 200-mA Load
Efficiency,
Sync = Low
90
Power Loss,
Sync = High
60
100
50
40
10
Power Loss,
Sync = Low
30
20
0
0.0001
Discontinuous Mode (Sync = 0), 200-mA Load
1 A/DIV
1
Efficiency,
Sync = High
10
Power Loss (mw)
70
Efficiency (%)
1 A/DIV
1000
80
1 A/DIV
Low-Power Mode (Sync = 0), 20-mA Load
0.1
0.001
VIN = 12 V
VOUT = 5 V
0.01
0.1
Output Current (a)
1
10
2 µs/DIV
L= 4.7 µH
RSENSE = 10 Ω
fSW = 400 kHz
VIN = 12 V
VOUT = 5 V
L= 4.7 µH
RSENSE = 10 Ω
fSW = 400 kHz
Figure 3. Inductor Currents (Buck)
Figure 2. Efficiency Across Output Currents (Bucks)
VOUT AC-Coupled
VOUTA
100 mV/DIV
VOUTB
1 V/DIV
2 A/DIV
IIND
2 ms/DIV
50 µs/DIV
VIN = 12 V
VOUT = 5 V
L= 4.7 µH
RSENSE = 10 Ω
fSW = 400 kHz
Figure 5. Soft-Start Outputs (Buck)
Figure 4. Buck Load Step: Forced Continuous Mode
(0 to 4 A at 2.5 A/µs)
VOUT AC-Coupled
100 mV/DIV
100 mV/DIV
VOUT AC-Coupled
2 A/DIV
IIND
IIND
2 A/DIV
50 µs/DIV
VIN = 12 V
VOUT = 5 V
L= 4.7 µH
RSENSE = 10 Ω
50 µs/DIV
fSW = 400 kHz
Figure 6. Buck Load Step: Low-Power-Mode Entry
(4 A to 90 mA at 2.5 A/µs)
12
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VIN = 12 V
VOUT = 5 V
L= 4.7 µH
RSENSE = 10 Ω
fSW = 400 kHz
Figure 7. Buck Load Step: Low-Power-Mode Exit
(90 mA to 4 A at 2.5 A/µs)
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SLVSAV6E – JUNE 2011 – REVISED DECEMBER 2015
Typical Characteristics (continued)
100
90
VBAT
VBAT = 8 V
80
Efficiency (%)
70
VBOOST
VBAT = 5 V
60
VBAT = 3 V
50
40
I(Load)
30
20
I(L)
10
0
0.01
10
1
Output Current (A)
VIN (BOOST OUTPUT) = 10 V
L = 1 µH
RSENSE = 7.5 mΩ
fSW = 200 kHz
CIN
VBAT (BOOST INPUT) = 5 V
VIN (BOOST OUTPUT) = 10 V
= 440 µF
COUT = 660 µF
Figure 9. Load Step Response (Boost)
(0 to 5 A at 10 A/µs)
Figure 8. Efficiency Across Output Currents (Boost)
5 V/DIV
0V
200 mV/DIV
VBAT (Boost Input)
fSW = 200 kHz
L = 680 nH
RSENSE = 10 mΩ
5 V/DIV
0V
VOUT BuckA AC-Coupled
VBAT (Boost Input)
VIN (Boost Output)
5 V/DIV
VOUT BuckB AC-Coupled
200 mV/DIV
10 A/DIV
0V
10 A/DIV
IIND
0A
IIND
0A
20 ms/DIV
VIN (BOOST OUTPUT) = 10 V
BuckA = 5 V AT 1.5 A
CIN = 440 µF
BuckB = 3.3 V AT 3.5 A
COUT = 660 µF
20 ms/DIV
fSW = 200 kHz
L = 1 µH
RSENSE = 7.5 mΩ
VIN (BOOST OUTPUT) = 10 V
BuckA = 5 V AT 1.5 A
CIN = 440 µF
BuckB = 3.3 V AT 3.5 A
COUT = 660 µF
Figure 10. Cranking Pulse Boost Response
(12 V to 3 V in 1 ms at Buck Outputs 7.5 W / 11.5 W)
fSW = 200 kHz
L = 1 µH
RSENSE = 7.5 mΩ
Figure 11. Cranking Pulse Boost Response
(12 V to 4 V in 1 ms at Boost Direct Output 25 W)
60
Quiescent Current (µA)
3-A Load
5 A/DIV
100-mA Load
5 A/DIV
50
40
BOTH BUCKS ON
30
ONE BUCK ON
20
10
NEITHER BUCK ON
0
-40
2 µs/DIV
CIN
VBAT (BOOST INPUT) = 5 V
VIN (BOOST OUTPUT) = 10 V
= 440 µF
COUT = 660 µF
-15
10
fSW = 200 kHz
L = 1 µH
RSENSE = 7.5 mΩ
Figure 12. Inductor Currents (Boost)
85
35
60
Temperature (°C)
110
135
160
Figure 13. No-Load Quiescent Current vs Temperature
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Typical Characteristics (continued)
0.9
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0
–0.1
–0.2
–0.3
62.5
50
Sense Current (µA)
Peak Current Sense Voltage (mV)
75
37.5
25
12.5 SYNC = LOW
0
–12.5
–25
SYNC = HIGH
–37.5
0.65
0.8
0.95
1.1
1.25
1.55
1.4
150°C
25°C
0
1
3
2
COMPx Voltage (V)
Figure 14. Buckx Peak Current Limit vs Compx Voltage
5
6
7
8
9
10 11 12
Figure 15. Current-Sense Pins Input Current (Buck)
80
805
70
804
Regulated FBx Voltage (mV)
Peak Current Sense Voltage (mV)
4
Output Voltage (V)
60
50
40
30
20
10
803
802
801
800
799
798
797
796
0
795
0
0.2
0.4
0.8
0.6
–40
–15
10
35
60
85
110
135
160
FBx Voltage (V)
Temperature (°C)
Figure 16. Foldback Current Limit (Buck)
Figure 17. Regulated Fbx Voltage vs Temperature (Buck)
Peak Current Sense Voltage (mV)
80
70
60
VIN = 8 V
50
40
VIN = 12 V
30
20
10
0
0
10
20
30
40
50
60
70
80
90 100
Duty Cycle (%)
Figure 18. Current Limit vs Duty Cycle (Buck)
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SLVSAV6E – JUNE 2011 – REVISED DECEMBER 2015
7 Detailed Description
7.1
Overview
The TPS43335-Q1 and TPS43336-Q1 devices include two current-mode synchronous buck controllers and a
voltage mode boost controller. The integrated boost controller allows the devices to operate down to 2 V at the
input without seeing a drop on the buck regulator output stages. At light loads, one can enable the buck
controllers to operate automatically in low-power mode, consuming just 30 μA of quiescent current. The buck
controllers have independent soft-start capability and power-good indicators. Current foldback in the buck
controllers and cycle-by-cycle current limitation in the boost controller provide external MOSFET protection. The
switching frequency is programmable over 150 kHz to 600 kHz or can be synchronized to an external clock in the
same range. The TPS43336-Q1 device also offers frequency-hopping spread-spectrum operation.
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7.2 Functional Block Diagram
VIN
EXTSUP
VREG
SYNC
Gate Driver
Supply
37
PWM
Logic
5
CBA
6
GA1
7
PHA
8
GA2
9
PGNDA
10
SA1
11
SA2
12
FBA
13
COMPA
15
PGA
21
DLYAB
34
CBB
33
GB1
32
PHB
31
GB2
30
PGNDB
29
SB1
28
SB2
27
FBB
26
COMPB
24
PGB
VREG
35
Internal
Oscillator
22
180 deg
RT
Duplicate for second
Buck controller channel
Internal ref
(Band gap)
38
Slope
Comp
PWM
comp
SYNC and
LPM
20
Current sense
Amp
OTA
GC2
Gm 0.8 V
Source
and
Sink
Logic
4
SSA
FBA
SA2
ENC
1 µA
SSA
14
ENA
16
ENA
25
ENB
17
DS
2
Filter timer
500 nA
40 µA
VIN
1 µA
SSB
VIN
40 µA
ENB
500 nA
OCP
VIN
VboostxV
0.2 V
COMPC
18
DIV
36
Gm
Second
Buck
Controller
Channel
Ramp
Vboost7V-th
VBAT
OTA
1
MUX
Vboost10V-th
Vboost11V-th
GC1
3
ENC
19
AGND
23
VREG
PWM
comp
PWM
Logic
PGNDA
Figure 19. Functional Block Diagram
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7.3 Feature Description
7.3.1 Buck Controllers: Normal Mode PWM Operation
7.3.1.1 Frequency Selection and External Synchronization
The buck controllers operate using constant-frequency peak-current-mode control for optimal transient behavior
and ease of component choices. The switching frequency is programmable between 150 kHz and 600 kHz,
depending upon the resistor value at the RT pin. A short circuit to ground at this pin sets the default switching
frequency to 400 kHz. Using a resistor at RT, one can set another frequency according to the formula:
X
fSW =
(X = 24 kW ´ MHz)
RT
fSW = 24 ´
109
RT
(1)
For example,
600 kHz requires 40 kΩ
150 kHz requires 160 kΩ
It is also possible to synchronize to an external clock at the SYNC pin in the same frequency range of 150 kHz to
600 kHz. The device detects clock pulses at this pin, and an internal PLL locks on to the external clock within the
specified range. The device can also detect a loss of clock at this pin, and when this condition is detected, the
device sets the switching frequency to the internal oscillator. The two buck controllers operate at identical
switching frequencies, 180 degrees out-of-phase.
7.3.1.2 Enable Inputs
Independent enable inputs from the ENA and ENB pins enable the buck controllers. These are high-voltage pins,
with a threshold of 1.7 V for the high level, and with direct connection to the battery permissible for self-bias. The
low threshold is 0.7 V. Both these pins have internal pullup currents of 0.5 µA (typical). As a result, an open
circuit on these pins enables the respective buck controllers. When both buck controllers are disabled, the device
shuts down and consumes a current of less than 4 µA.
7.3.1.3 Feedback Inputs
The right resistor feedback divider network connected to the FBx (feedback) pins sets the output voltage. Choose
this network such that the regulated voltage at the FBx pin equals 0.8 V. The FBx pins have a 100-nA pullup
current source as a protection feature in case the pins open up as a result of physical damage.
7.3.1.4 Soft-Start Inputs
In order to avoid large inrush currents, each buck controller has an independent programmable soft-start timer.
The voltage at the SSx pin acts as the soft-start reference voltage. The 1-µA pullup current available at the SSx
pins, in combination with a suitably chosen capacitor, generates a ramp of the desired soft-start speed. After
start-up, the pullup current ensures that SSx is higher than the internal reference of 0.8 V; 0.8 V then becomes
the reference for the buck controllers. Use Equation 2 to calculate the soft-start ramp time.
I SS ´ Dt
CSS =
(Farads)
DV
where
•
•
•
ISS = 1 µA (typical)
∆V = 0.8 V
CSS is the required capacitor for ∆t, the desired soft-start time.
(2)
An alternative use of the soft-start pins is as tracking inputs. In this case, connect them to the supply to be
tracked via a suitable resistor-divider network.
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Feature Description (continued)
7.3.1.5 Current-Mode Operation
Peak-current-mode control regulates the peak current through the inductor to maintain the output voltage at its
set value. The error between the feedback voltage at FBx and the internal reference produces a signal at the
output of the error amplifier (COMPx) which serves as the target for the peak inductor current. The device
senses the current through the inductor as a differential voltage at Sx1–Sx2 and compares voltage with this
target during each cycle. A fall or rise in load current produces a rise or fall in voltage at FBx, causing VCOMPx to
fall or rise respectively, thus increasing or decreasing the current through the inductor until the average current
matches the load. This process maintains the output voltage in regulation.
The top N-channel MOSFET turns on at the beginning of each clock cycle and stays on until the inductor current
reaches its peak value. Once this MOSFET turns off, and after a small delay (shoot-through delay) the lower Nchannel MOSFET turns on until the start of the next clock cycle. In dropout operation, the high-side MOSFET
stays on continuously. In every fourth clock cycle, there is a limit on the duty cycle of 95% in order to charge the
bootstrap capacitor at CBx. This allows a maximum duty cycle of 98.75% for the buck regulators. During dropout,
the buck regulator switches at one-fourth of its normal frequency.
7.3.1.6 Current Sensing and Current Limit With Foldback
Clamping of the maximum value of COMPx is such as to limit the maximum current through the inductor to a
specified value. When the output of the buck regulator (and hence the feedback value at FBx) falls to a low value
due to a short circuit or overcurrent condition, the clamped voltage at COMPx successively decreases, thus
providing current foldback protection, which protects the high-side external MOSFET from excess current
(forward-direction current limit).
Similarly, if a fault condition shorts the output to a high voltage and the low-side MOSFET turns fully on, the
COMPx node drops low. A clamp is on its lower end as well, in order to limit the maximum current in the low-side
MOSFET (reverse-direction current limit).
An external resistor senses the current through the inductor. Choose the sense resistor such that the maximum
forward peak current in the inductor generates a voltage of 75 mV across the sense pins. This specified value is
for low duty cycles only. At typical duty-cycle conditions around 40% (assuming 5-V output and 12-V input), 50
mV is a more reasonable value, considering tolerances and mismatches. The Typical Characteristics section
provides a guide for using the correct current-limit sense voltage.
The current-sense pins Sx1 and Sx2 are high-impedance pins with low leakage across the entire output range,
thus allowing DCR current sensing using the dc resistance of the inductor for higher efficiency. Figure 20 shows
DCR sensing. Here, the series resistance (DCR) of the inductor is the sense element. Place the filter
components close to the device for noise immunity. Remember that while the DCR sensing gives high efficiency,
it is inaccurate due to the temperature sensitivity and a wide variation of the parasitic inductor series resistance.
Hence, it may often be advantageous to use the more-accurate sense resistor for current sensing.
Inductor, L
TPS43335-Q1
or
TPS43336-Q1
VBUCKx
DCR
R1
C1
Sx2
VC
Sx1
Figure 20. DCR Sensing Configuration
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Feature Description (continued)
7.3.1.7 Slope Compensation
Optimal slope compensation which is adaptive to changes in input voltage and duty cycle allows stable operation
under all conditions. For optimal performance of this circuit, choose the inductor and sense resistor according to
the following:
L ´ f SW
= 200
RS
where
•
•
•
L is the buck regulator inductor in henries.
RS is the sense resistor in ohms.
fsw is the buck-regulator switching frequency in hertz.
(3)
7.3.1.8 Power-Good Outputs and Filter Delays
Each buck controller has an independent power-good comparator monitoring the feedback voltage at the FBx
pins and indicating whether the output voltage has fallen below a specified power-good threshold. This threshold
has a typical value of 93% of the regulated output voltage. The power-good indicator is available as an opendrain output at the PGx pins. An internal 50-kΩ pullup resistor to Sx2 is available, or use of an external resistor is
possible. Shutdown of a buck controller causes an internal pulldown of the power-good indicator. Connecting the
pullup resistor to a rail other than the output of that particular buck channel causes a constant current flow
through the resistor when the buck controller is powered down.
In order to avoid triggering the power-good indicators due to noise or fast transients on the output voltage, the
device uses an internal delay circuit for de-glitching. Similarly, when the output voltage returns to its set value
after a long negative transient, assertion of the power-good indicator (release of the open-drain pin) occurs after
the same delay. Use of this delay can pause the reset of circuits powered from the buck regulator rail. Program
the duration of the delay of by using a suitable capacitor at the DLYAB pin according to the equation:
tDELAY
1 ms
=
C DLYAB
1 nF
(4)
When the DLYAB pin is open, the delay setting is for a default value of 20 µs typical. The power-good delay
timing is common to both the buck rails, but the power-good comparators and indicators function independently.
7.3.1.9 Light-Load PFM Mode
An external clock or a high level on the SYNC pin results in forced continuous-mode operation of the bucks. An
open or low on the SYNC pin allows the buck controllers to operate in discontinuous mode at light loads by
turning off the low-side MOSFET on detection of a zero-crossing in the inductor current.
In discontinuous mode, as the load decreases, the duration when both the high-side and low-side MOSFETs turn
off increases (deep discontinuous mode). In case the duration exceeds 60% of the clock period and VBAT > 8 V,
the buck controller switches to a low-power operation mode. The design ensures that this typically occurs at 1%
of the set full-load current if the choice of the inductor and sense resistor is as recommended in the slope
compensation section.
In low-power PFM mode, the buck monitors the FBx voltage and compares it with the 0.8-V internal reference.
Whenever the FBx value falls below the reference, the high-side MOSFET turns on for a pulse duration inversely
proportional to the difference VIN – Sx2. At the end of this on-time, the high-side MOSFET turns off and the
current in the inductor decays until it becomes zero. The low-side MOSFET does not turn on. The next pulse
occurs the next time FBx falls below the reference value. This results in a constant volt-second ton hysteretic
operation with a total device quiescent current consumption of 30 µA when a single buck channel is active and
35 µA when both channels are active.
As the load increases, the pulses become more and more frequent and move closer to each other until the
current in the inductor becomes continuous. At this point, the buck controller returns to normal fixed-frequency
current-mode control. Another criterion to exit the low-power mode is when VIN falls low enough to require higher
than 80% duty cycle of the high-side MOSFET.
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Feature Description (continued)
The TPS43335-Q1 and TPS43336-Q1 can support the full-current load during low-power mode until the
transition to normal mode takes place. The design ensures that exit of the low-power mode occurs at 10%
(typical) of full-load current if the selection of inductor and sense resistor is as recommended. Moreover, there is
always a hysteresis between the entry and exit thresholds to avoid oscillating between the two modes.
In the event that both buck controllers are active, low-power mode is only possible when both buck controllers
have light loads that are low enough for low-power mode entry. With the boost controller enabled, low-power
mode is possible only if VBAT is high enough to prevent the boost from switching and if DIV is open or set to
GND. A high (VREG) level on DIV inhibits low-power mode, unless ENC is set to low.
7.3.2 Boost Controller
The boost controller has a fixed-frequency voltage-mode architecture and includes cycle-by-cycle current-limit
protection for the external N-channel MOSFET. The boost-controller switching-frequency setting is one-half of the
buck-controller switching frequency. An internal resistor-divider network programmable to 7 V, 10 V, or 11 V sets
the output voltage of the boost controller at the VIN pin, based on the low, open, or high status, respectively, of
the DIV pin. The device does not recognize a change of the DIV setting while the in the low-power mode.
The active-high ENC pin enables the boost controller, which is active when the input voltage at the VBAT pin has
crossed the unlock threshold of 8.5 V at least once. A single threshold crossing arms the boost controller, which
starts switching as soon as VIN falls below the value set by the DIV pin, regulating the VIN voltage. Thus, the
boost regulator maintains a stable input voltage for the buck regulators during transient events such as a
cranking pulse at VBAT.
The voltage at the DS pin exceeding 200 mV pulls the CG1 pin low, turning off the boost external MOSFET.
Connecting the DS pin to the drain of the MOSFET or to a sense resistor between the MOSFET source and
ground achieves cycle-by-cycle overcurrent protection for the MOSFET. Choose the on-resistance of the
MOSFET or the value of the sense resistor in such a way that the on-state voltage at the DS does not exceed
200 mV at the maximum-load and minimum-input-voltage conditions. When using a sense resistor, TI
recommends connecting a filter network between the DS pin and the sense resistor for better noise immunity.
One can use the boost output (VIN) to supply other circuits in the system. However, they should be high-voltage
tolerant. The device regulates the boost output to the programmed value only when VIN is low, and so VIN can
reach battery levels.
VBAT
VBAT
TPS43335-Q1
or
TPS43336-Q1
VIN
TPS43335-Q1
or
TPS43336-Q1
DS
GC1
GC1
DS
RIFLT
CIFLT
Figure 21. External Drain-Source Voltage Sensing
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Figure 22. External Current Shunt Resistor
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Feature Description (continued)
7.3.3 Frequency-Hopping Spread Spectrum (TPS43336-Q1 Only)
The TPS43336-Q1 features a frequency-hopping pseudo-random spectrum-spreading architecture. On this
device, whenever the SYNC pin is high, the internal oscillator frequency varies from one cycle to the next within
a band of ±5% around the value programmed by the resistor at the RT pin. The implementation uses a linearfeedback shift register that changes the frequency of the internal oscillator based on a digital code. The shift
register is long enough to make the hops pseudo-random in nature and has a design such that the frequency
shifts only by one step at each cycle to avoid large jumps in the buck and boost switching frequencies.
Table 1. Frequency-Hopping Control
SYNC
TERMINAL
FREQUENCY SPREAD SPECTRUM (FSS)
COMMENTS
External clock
Not active
Device in forced continuous mode, internal PLL locks into external clock
between 150 kHz and 600 kHz.
Low or open
Not active
Device can enter discontinuous mode. Automatic LPM entry and exit,
depending on load conditions
High
TPS43335-Q1: FSS not active
Device in forced continuous mode
TPS43336-Q1: FSS active
7.3.4 Gate-Driver Supply (VREG, EXTSUP)
The gate-driver supplies of the buck and boost controllers are from an internal linear regulator whose output (5.8
V typical) is on the VREG pin and requires decoupling with a ceramic capacitor in the range of 3.3 µF to 10 µF.
This pin has internal current-limit protection; do not use it to power any other circuits.
NOTE
VREG is not powered if no regulator is enabled, therefore it is not suitable to enable the
regulators.
VIN powers the VREG linear regulator by default when the EXTSUP voltage is lower than 4.6 V (typical). If there
is an expectation of VIN going to high levels, there can be excessive power dissipation in this regulator, especially
at high switching frequencies and when using large external MOSFETs. In this case, it is advantageous to power
this regulator from the EXTSUP pin, which can have a connection to a supply lower than VIN but high enough to
provide the gate drive. When the voltage on EXTSUP is greater than 4.6 V, the linear regulator automatically
switches to EXTSUP as its input, to provide this advantage. Efficiency improvements are possible when using
one of the switching regulator rails from the TPS43335-Q1 or TPS43336-Q1 or any other voltage available in the
system to power EXTSUP. The maximum voltage for application to EXTSUP is 9 V.
VIN
5.8 V
(typical)
LDO
VIN
EXTSUP
7.5 V
(typical)
LDO
EXTSUP
4.6 V (typical)
VREG
Figure 23. Internal Gate-Driver Supply
Using a voltage above 5.8 V (sourced by VIN) for EXTSUP is advantageous, as it provides a large gate drive
and hence better on-resistance of the external MOSFETs.
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When using EXTSUP, always keep the buck rail supplying EXTSUP enabled. Alternatively, if it is necessary to
switch off the buck rail supplying EXTSUP, place a diode between the buck rail and EXTSUP.
During low-power mode, the EXTSUP functionality is not available. The internal regulator operates as a shunt
regulator powered from VIN and has a typical value of 7.5 V. Current-limit protection for VREG is available in
low-power mode as well. If EXTSUP is unused, leave the pin open without a capacitor installed.
7.3.5 External P-Channel Drive (GC2) and Reverse Battery Protection
The TPS43335-Q1 and TPS43336-Q1 include a gate driver for an external P-channel MOSFET which can
connect across the rectifier diode of the boost regulator. Such connection is useful to reduce power losses when
the boost controller is not switching. The gate driver provides a swing of 6 V typical below the VIN voltage in
order to drive a P-channel MOSFET. When VBAT falls below the boost-enable threshold, the gate driver turns off
the P-channel MOSFET, eliminating the diode bypass.
Another use for the gate driver is to bypass any additional protection diodes connected in series, as shown in
Figure 24.
The bypass-design should be chosen with the following considerations in mind:
The FETs need to have a current-rating to support the maximum output power at minimum voltage (before
Boost gets activated, typically 1 V above the set boost-voltage). The FETs Drain-Source-Voltage also needs
to support the worst case transients on VBAT, potentially causing a reverse voltage due to capacitors on the
Source.
The Zener-Diode protects the FET against a too high Gate-Source-voltage. Typically a rating of ~7.5 V is
suitable.
The resistor limits the current to the FET and over the diode. Considering the deep boost mode and a high
boost-output voltage, up to 9 V may be present between GC2 and VBAT, reduced by the Zener-voltage. As
GC2 has a drive capability of 10 mA, the current needs to be limited by a series resistance of about 1kOhm
(depending on Vbat(min), V(boost) and Zener-voltage).
R10
GC2
Q7
VBAT
TPS43335-Q1
Q6
D3
or
TPS43336-Q1
Fuse (S1)
L3
VIN
D2
C16
C17
D1
C15
C14
DS
GC1
COMPC
C13
R9
VBAT
Figure 24. Reverse Battery Protection Option 1 for Buck Boost Configuration
Figure 25 also shows a different scheme of reverse battery protection, which may require only a smaller-sized
diode to protect the N-channel MOSFET, as the diode conducts only for a part of the switching cycle. Because
the diode is not always in the series path, the system efficiency can be improved.
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GC2
TPS43335-Q1
or
TPS43336-Q1
VBAT
VIN
Fuse
DS
GC1
COMPC
VBAT
Figure 25. Reverse Battery Protection Option 2 for Buck Boost Configuration
7.3.6 Undervoltage Lockout and Overvoltage Protection
The TPS43335-Q1 and TPS43336-Q1 start up at a VIN voltage of 6.5 V (minimum), required for the internal
supply (VREG). Once it has started up, the device operates down to a VIN voltage of 3.6 V; below this voltage
level, the undervoltage lockout disables the device. Note: if VIN drops, VREGdrops as well; hence, the gate-drive
voltage is reduced, whereas the digital logic is fully functional. Note as well, even if ENC is high, there is a
requirement to exceed the boost-unlock voltage of typically 8.5 V once, before boost activation can take place
(see the Boost Controller section herein). A voltage of 46 V at VIN triggers the overvoltage comparator, which
shuts down the device. In order to prevent transient spikes from shutting down the device, the under- and
overvoltage protection have filter times of 5 µs (typical).
When the voltages return to the normal operating region, the enabled switching regulators start including a new
soft-start ramp for the buck regulators.
With the boost controller enabled, a voltage less than 1.9 V (typical) on VBAT triggers an undervoltage lockout
and pulls the boost gate driver (GC1) low (this action has a filter delay of 5 µs, typical). As a result, VIN falls at a
rate dependent on its capacitor and load, eventually triggering VIN undervoltage. A short falling transient at
VBAT even lower than 2 V can thus be survived, if VBAT returns above 2.5 V before VIN is discharged to the
undervoltage threshold.
7.3.7 Thermal Protection
The TPS43335-Q1 or TPS43336-Q1 protects itself from overheating using an internal thermal shutdown circuit. If
the die temperature exceeds the thermal shutdown threshold of 165ºC due to excessive power dissipation (for
example, due to fault conditions such as a short circuit at the gate drivers or VREG), the controllers turn off and
then restart when the temperature has fallen by 15ºC.
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7.4 Device Functional Modes
Table 2 lists the enable and inhibit pin configurations for the modes of operation.
Table 2. Mode of Operation
ENABLE AND INHIBIT PINS
DRIVER STATUS
DEVICE STATUS
ENA
ENB
ENC
Low
Low
Low
SYNC
X
BUCK CONTROLLERS
Shut down
Disabled
Shutdown
Approximately 4 µA
BuckB: LPM enabled
Approximately 30 µA (light loads)
High
BuckB: LPM inhibited
mA range
Low
BuckA: LPM enabled
Approximately 30 µA (light loads)
High
BuckA: LPM inhibited
mA range
Low
BuckA and BuckB: LPM enabled
Approximately 35 µA (light loads)
BuckA and BuckB: LPM inhibited
mA range
Low
Low
High
High
High
Low
High
Low
BuckB running
Low
Disabled
BuckA running
Low
Disabled
BuckA and BuckB running
Disabled
High
Low
Low
Low
Low
High
High
X
Shut down
Disabled
Shutdown
Approximately 4 µA
Boost running for
VIN < set boost output
BuckB: LPM enabled
BuckB running
Approximately 50 µA
(no boost, light loads)
BuckB: LPM inhibited
mA range
Boost running for
VIN < set boost output
BuckA: LPM enabled
Approximately 50 µA
(no boost, light loads)
BuckA: LPM inhibited
mA range
Boost running for
VIN < set boost output
BuckA and BuckB: LPM enabled
Approximately 60 µA
(no boost, light loads)
BuckA and BuckB: LPM inhibited
mA range
Low
High
Low
High
Low
High
BuckA running
High
Low
High
High
QUIESCENT CURRENT
BOOST CONTROLLER
High
BuckA and BuckB running
High
7.4.1 Buck Controllers: Current-Mode Operation
Peak-current-mode control regulates the peak current through the inductor to maintain the output voltage at its
set value. The error between the feedback voltage at FBx and the internal reference produces a signal at the
output of the error amplifier (COMPx) which serves as the target for the peak inductor current. The device
senses the current through the inductor as a differential voltage at Sx1–Sx2 and compares voltage with this
target during each cycle. A fall or rise in load current produces a rise or fall in voltage at FBx, causing VCOMPx to
fall or rise respectively, thus increasing or decreasing the current through the inductor until the average current
matches the load. This process maintains the output voltage in regulation.
The top N-channel MOSFET turns on at the beginning of each clock cycle and stays on until the inductor current
reaches its peak value. Once this MOSFET turns off, and after a small delay (shoot-through delay) the lower Nchannel MOSFET turns on until the start of the next clock cycle. In dropout operation, the high-side MOSFET
stays on continuously. In every fourth clock cycle, a limit exists on the duty cycle of 95% to charge the bootstrap
capacitor at CBx which allows a maximum duty cycle of 98.75% for the buck regulators. During dropout, the buck
regulator switches at one-fourth of the normal frequency.
7.4.2 Buck Controllers: Light-Load PFM Mode
An external clock or a high level on the SYNC pin results in forced continuous-mode operation of the bucks. An
open or low on the SYNC pin allows the buck controllers to operate in discontinuous mode at light loads by
turning off the low-side MOSFET on detection of a zero-crossing in the inductor current.
In discontinuous mode, as the load decreases, the duration when both the high-side and low-side MOSFETs turn
off increases (deep discontinuous mode). In case the duration exceeds 60% of the clock period and VBAT > 8 V,
the buck controller switches to a low-power operation mode. The design ensures that this typically occurs at 1%
of the set full-load current if the choice of the inductor and sense resistor is as recommended in the slopecompensation section.
In low-power PFM mode, the buck monitors the FBx voltage and compares it with the 0.8-V internal reference.
Whenever the FBx value falls below the reference, the high-side MOSFET turns on for a pulse duration inversely
proportional to the difference VIN – Sx2. At the end of this on-time, the high-side MOSFET turns off and the
current in the inductor decays until it becomes zero. The low-side MOSFET does not turn on. The next pulse
occurs the next time FBx falls below the reference value. This results in a constant volt-second ton hysteretic
operation with a total device quiescent current consumption of 30 µA when a single buck channel is active and
35 µA when both channels are active.
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As the load increases, the pulses become more and more frequent and move closer to each other until the
current in the inductor becomes continuous. At this point, the buck controller returns to normal fixed-frequency
current-mode control. Another criterion to exit the low-power mode is when VIN falls low enough to require higher
than 80% duty cycle of the high-side MOSFET.
The TPS4333x-Q1 family of devices can support the full-current load during low-power mode until the transition
to normal mode takes place. The design ensures that exit of the low-power mode occurs at 10% (typical) of fullload current if the selection of inductor and sense resistor is as recommended. Moreover, a hysteresis also exists
between the entry and exit thresholds to avoid oscillating between the two modes.
In the event that both buck controllers are active, low-power mode is only possible when both buck controllers
have light loads that are low enough for low-power mode entry. With the boost controller enabled, low-power
mode is possible only if VBAT is high enough to prevent the boost from switching and if DIV is open or set to
GND. A high (VREG) level on DIV inhibits low-power mode, unless the ENC pin is set to low.
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8 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
8.1 Application Information
The TPS43335-Q1 and TPS43336-Q1 devices are ideally suited as a pre-regulator stage with low Iq
requirements and for applications that must survive supply drops due to cranking events. The integrated boost
controller allows the devices to operate down to 2 V at the input without seeing a drop on the buck regulator
output stages. Below component values and calculations are a good starting point and theoretical representation
of the values for use in the application; improving the performance of the device may require further optimization
of the derived components.
8.2 Typical Applications
8.2.1 Automotive Infotainment Supply
This is a starting point and theoretical representation of the values for use in the application; improving the
performance of the device may require further optimization of the derived components.
2.5 to 40 V
D1
L1
VBAT
BOOST: 10 V, 25 W
3.9 µH
CIN
10 µF
220 µF
COUT1
680 µF
TOP-SW3
1k
VBAT
BOT-SW3
DS
1.5 k
0.02
1 nF
TOP-SW1
VBuckA: 5 V, 15 W
0.015
L2
BOT-SW1
100 µF
GC1
DIV
GC2
VREG
CBA
CBB
GA1
GB1
PHA
PHB
GA2
GB2
0.1 µF
8.2 µH
COUTA
84 k
PGNDA
SA1
SA2
FBA
16 k
33 pF
1.5 nF 24 k
10 nF
5k
COMPA
22 nF 7.2 k
4.7 µF
0.1 µF
TOP-SW2
L3
0.03
VBuckB: 3.3 V, 6.6 W
15 µH
COUTB
BOT-SW2
100 µF
PGNDB
TPS43335-Q1
or
SB1
TPS43336-Q1
SB2
50 k
FBB
COMPB
SSA
SSB
PGA
PGB
ENA
AGND
ENB
220 pF
VIN
EXTSUP
30 k
16 k
27 pF
1.1 nF
10 nF
5k
RT
COMPC
DLYAB
ENC
SYNC
1 nF
Figure 26. Simplified Automotive Infotainment Supply Schematic
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Typical Applications (continued)
8.2.1.1 Design Requirements
Table 3 lists the design-goal parameters.
Table 3. Design-Goal Parameters
PARAMETER
Input voltage
VBuckA
VBuckB
BOOST
VIN = 6 V to 30 V
12 V - typical
VIN = 6 V to 30 V
12 V - typical
VBAT = 5 V (cranking pulse
input) to 30 V
5V
3.3 V
10 V
Output voltage, VOUTx
Maximum output current, IOUTx
Load-step output tolerance, ∆VOUT + ∆VOUT(Ripple)
Current output load step, ∆IOUTx
Converter switching frequency, fSW
3A
2A
2.5 A
±0.2 V
±0.12 V
±0.5 V
0.1 A to 3 A
0.1 A to 2 A
0.1 A to 2.5 A
400 kHz
400 kHz
200 kHz
8.2.1.2 Detailed Design Procedure
Table 4 illustrates the design process and component selection for the TPS43335-Q1 and TPS43336-Q1.
Table 4. Automotive Infotainment Supply – Component Proposals
NAME
COMPONENT PROPOSAL
VALUE
L1
MSS1278T-392NL (Coilcraft)
4 µH
L2
MSS1278T-822ML (Coilcraft)
8.2 µH
L3
MSS1278T-153ML (Coilcraft)
15 µH
D1
SK103 (Micro Commercial Components)
TOP_SW3
IRF7416 (International Rectifier)
TOP_SW1, TOP_SW2
Si4840DY-T1-E3 (Vishay)
BOT_SW1, BOT_SW2
Si4840DY-T1-E3 (Vishay)
BOT_SW3
IRFR3504ZTRPBF (International Rectifier)
COUT1
EEVFK1J681M (Panasonic)
680 µF
COUTA, COUTB
ECASD91A107M010K00 (Murata)
100 µF
CIN
EEEFK1V331P (Panasonic)
220 µF
8.2.1.2.1 Boost Component Selection
A boost converter operating in continuous-conduction mode (CCM) has a right-half-plane (RHP) zero in its
transfer function. The RHP zero relates inversely to the load current and inductor value and directly to the input
voltage. The RHP zero limits the maximum bandwidth achievable for the boost regulator. If the bandwidth is too
close to the RHP zero frequency, the regulator may become unstable.
Thus, for high-power systems with low input voltages, choose a low inductor value. A low value increases the
amplitude of the ripple currents in the N-channel MOSFET, the inductor, and the capacitors for the boost
regulator. Select these components with the ripple-to-RHP zero trade-off in mind and considering the power
dissipation effects in the components due to parasitic series resistance.
A boost converter that operates always in the discontinuous mode does not contain the RHP zero in its transfer
function. However, designing for the discontinuous mode demands an even lower inductor value that has high
ripple currents. Also, ensure that the regulator never enters the continuous-conduction mode; otherwise, it may
become unstable.
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VIN
CO
7V
OTA-gmEA
COMPx
+
C1
RESR
10 V
VREF
12 V
C2
R3
Figure 27. Boost Compensation Components
This design assumes operation in continuous-conduction mode. During light load conditions, the boost converter
operates in discontinuous mode without affecting stability. Hence, the assumptions here cover the worst case for
stability.
8.2.1.2.2 Boost Maximum Input Current IIN_MAX
The maximum input current flows at the minimum input voltage and maximum load. The efficiency for VBAT = 5 V
at 2.5 A is 80%, based on the typical characteristics plot.
POUT
25 W
PINmax =
=
= 31.3 W
Efficiency
0.8
(5)
Hence,
IINmax (at VBAT = 5 V) =
31.3 W
= 6.3 A
5V
(6)
8.2.1.2.3 Boost Inductor Selection, L
Allow input ripple current of 40% of IIN max at VBAT = 5 V.
L=
VBAT ´ t ON
IINripple max
=
VBAT
5V
=
= 4.9 mH
IINripple max ´ 2 ´ fSW 2.52 A ´ 2 ´ 200 kHz
(7)
Choose a lower value of 4 µH in order to ensure a high RHP-zero frequency while making a compromise that
expects a high current ripple. This inductor selection also makes the boost converter operate in discontinuous
conduction mode, where it is easier to compensate.
The inductor saturation current must be higher than the peak inductor current and some percentage higher than
the maximum current-limit value set by the external resistive sensing element.
Determine the saturation rating at the minimum input voltage, maximum output current, and maximum core
temperature for the application.
8.2.1.2.4 Inductor Ripple Current, IRIPPLE
Based on an inductor value of 4 µH, the ripple current is approximately 3.1 A.
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8.2.1.2.5 Peak Current in Low-Side FET, IPEAK
I PEAK = IINmax +
I RIPPLE
3.1 A
= 6.3 A +
= 7.85 A
2
2
(8)
Based on this peak current value, calculate the external current-sense resistor RSENSE.
0.2 V
RSENSE =
= 25 mW
7.85 A
(9)
Select 20 mΩ, allowing for tolerance.
The filter component values RIFLT and CIFLT for current sense are 1.5 kΩ and 1 nF, respectively, which allows for
good noise immunity.
8.2.1.2.6 Right Half-Plane Zero RHP Frequency, fRHP
fRHP =
VBAT min
= 32 kHz
2p ´ IINmax ´ L
(10)
8.2.1.2.7 Output Capacitor, COUTx
To ensure stability, choose output capacitor COUTx such that
fRHP
fLC £
10
10
2p ´ L ´ COUTx
£
V BAT min
2p ´ IINmax ´ L
æ 10 ´ IINmax
³ç
ç VBAT min
è
COUTx
2
2
ö
æ 10 ´ 6.3 A ö
÷ ´L = ç
´ 4 mH
÷
÷
5V
è
ø
ø
COUTx min ³ 635 mF
(11)
Select COUTx = 680 µF.
This capacitor is usually aluminum electrolytic with ESR in the tens of milliohms. ESR in this range is good for
loop stability, because it provides a phase boost. The output filter components, L and C, create a double pole
(180-degree phase shift) at a frequency fLC and the ESR of the output capacitor RESR creates a zero for the
modulator at frequency fESR. These frequencies can be determined by the following:
f ESR =
f ESR =
f LC =
1
2p ´ COUTx ´ RESR
Hz, assume RESR = 40 mW
1
= 6 kHz
2p ´ 660 mF ´ 0.04 W
1
2p ´ L ´ COUTx
=
1
2p ´ 4 mH ´ 660 mF
= 3.1 kHz
(12)
This satisfies fLC ≤ 0.1 fRHP.
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8.2.1.2.8 Bandwidth of Boost Converter, fC
Use the following guidelines to set the frequency poles, zeroes, and crossover values for the trade-off between
stability and transient response:
fLC < fESR< fC< fRHP Zero
fC< fRHP Zero / 3
fC< fSW / 6
fLC< fC / 3
8.2.1.2.9 Output Ripple Voltage Due to Load Transients, ∆VOUTx
Assume a bandwidth of fC = 10 kHz.
DVOUTx = R ESR ´ DI OUTx +
= 0.04 W ´ 2.5 A +
DI OUTx
4 ´ COUTx ´ f C
2.5 A
= 0.19 V
4 ´ 660 mF ´ 10 kHz
(13)
Because the boost converter is active only during brief events such as a cranking pulse, and the buck converters
are high-voltage tolerant, a higher excursion on the boost output may be tolerable in some cases. In such cases,
one can choose smaller components for the boost output.
8.2.1.2.10 Selection of Components for Type II Compensation
The required loop gain for unity-gain bandwidth (UGB) is
æ fC ö
æ fC ö
G = 40 log ç
÷ - 20 log ç
÷÷
çf
ç fLC ÷
è ESR ø
è
ø
æ 10 kHz ö
æ 10 kHz ö
÷ - 20 log ç
÷ = 15.9 dB
è 3.1 kHz ø
è 6 kHz ø
G = 40 log ç
(14)
The boost-converter error amplifier (OTA) has a Gm that is proportional to the VBAT voltage. This allows a
constant loop response across the input-voltage range and makes it easier to compensate by removing the
dependency on VBAT.
R3 =
C1 =
C2 =
30
10G/20
85 ´ 10-6 A / V 2 ´ VOUTx
= 7.2 kW
10
10
=
= 22 nF
2p ´ f C ´ R3 2p ´ 10 kHz ´ 7.2 kW
C1
æf
2p ´ R3 ´ C1´ ç SW
è 2
ö
÷ -1
ø
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=
22 nF
æ 200 kHz ö
2p ´ 7.2 kW ´ 22 nF ´ ç
÷ -1
2
è
ø
= 223 pF
(15)
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8.2.1.2.11 Input Capacitor, CIN
The input ripple required is lower than 50 mV.
IRIPPLE
DVC1 =
= 10 mV
8 ´ fSW ´ CIN
CIN =
IRIPPLE
8 ´ fSW ´ DVC1
= 194-μF
DVESR = IRIPPLE ´ R ESR = 40 mV
(16)
Therefore, TI recommends 220 µF with 10-mΩ ESR.
8.2.1.2.12 Output Schottky Diode D1 Selection
Maximizing efficiency requires a Schottky diode with low forward-conducting voltage VF over temperature and
fast switching characteristics. The reverse breakdown voltage should be higher than the maximum input voltage,
and the component should have low reverse leakage current. Additionally, the peak forward current should be
higher than the peak inductor current. The power dissipation in the Schottky diode is given by:
PD = ID(PEAK) ´ VF ´ (1 - D)
D = 1-
VINMIN
VOUT + VF
= 1-
5V
= 0.53
10 V + 0.6 V
PD = 7.85 A ´ 0.6 V ´ (1 - 0.53) = 2.2 W
(17)
8.2.1.2.13 Low-Side MOSFET (BOT_SW3)
æ VI ´ IPk
PBOOSTFET = (IPk )2 ´ rDS(on) (1 + TC) ´ D + ç
ç 2
è
ö
÷÷ ´ (tr + t f ) ´ fSW
ø
æ VI ´ IPk ö
PBOOSTFET = (7.85 A)2 ´ 0.02 W ´ (1 + 0.4) ´ 0.53 + ç
÷ ´ (20 ns + 20 ns) ´ 200 kHz = 1.07 W
è 2 ø
(18)
The times tr and tf denote the rising and falling times of the switching node and relate to the gate-driver strength
of the TPS43335-Q1 and TPS43336-Q1 and the gate Miller capacitance of the MOSFET. The first term denotes
the conduction losses, which the low on-resistance of the MOSFET minimizes. The second term denotes the
transition losses which arise due to the full application of the input voltage across the drain-source of the
MOSFET as it turns on or off. Transition losses are higher at high output currents and low input voltages (due to
the large input peak current) and when the switching time is low.
Note: The on-resistance, rDS(on), has a positive temperature coefficient, which produces the (TC = d × ΔT) term
that signifies the temperature dependence. (Temperature coefficient d is available as a normalized value from
MOSFET data sheets and can have an assumed starting value of 0.005 / °C.)
8.2.1.2.14 BuckA Component Selection
8.2.1.2.14.1 BuckA Component Selection
t ON min =
VOUTA
3.3 V
=
= 275 ns
VIN max ´ f SW 30 V ´ 400 kHz
(19)
tON minis higher than the minimum duty cycle specified (100 ns typical). Hence, the minimum duty cycle is
achievable at this frequency.
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8.2.1.2.14.2 Current-Sense Resistor RSENSE
Based on the typical characteristics for the VSENSE limit with VIN versus duty cycle, the sense limit is
approximately 65 mV (at VIN = 12 V and duty cycle of 5 V / 12 V = 0.416). Allowing for tolerances and ripple
currents, choose a VSENSE maximum of 50 mV.
50 mV
RSENSE =
= 17 mW
3A
(20)
Select 15 mΩ.
8.2.1.2.15 Inductor Selection L
As explained in the description of the buck controllers, for optimal slope compensation and loop response,
choose the inductor such that:
R SENSE
15 mW
L = K FLR ´
= 200 ´
= 7.5 mH
f SW
400 kHz
(21)
KFLR = coil-selection constant = 200
Choose a standard value of 8.2 µH. For the buck converter, choose the inductor saturation currents and core to
sustain the maximum currents.
8.2.1.2.16 Inductor Ripple Current IRIPPLE
At the nominal input voltage of 12 V, this inductor value causes a ripple current of 30% of IOUT max ≈ 1 A.
8.2.1.2.17 Output Capacitor COUTA
Select an output capacitance COUTA of 100 µF with low ESR in the range of 10 mΩ, giving ∆VOUT(Ripple) ≈ 15 mV
and a ∆V drop of ≈ 180 mV during a load step, which does not trigger the power-good comparator and is within
the required limits.
2 ´ DI OUTA
2 ´ 2.9 A
COUTA »
=
= 72.5 mF
f SW ´ DVOUTA 400 kHz ´ 0.2 V
(22)
VOUTA(Ripple) =
DVOUTA =
I OUTA(Ripple)
8 ´ f SW ´ COUTA
DI OUTA
4 ´ f C ´ COUTA
+ I OUTA(Ripple) ´ ESR =
+ DI OUTA ´ ESR =
1A
+ 1 A ´ 10 mW = 13.1mV
8 ´ 400 kHz ´ 100 mF
2.9 A
+ 2.9 A ´ 10 mW = 174 mV
4 ´ 50 kHz ´ 100 mF
(23)
(24)
8.2.1.2.18 Bandwidth of Buck Converter fC
Use the following guidelines to set frequency poles, zeroes, and crossover values for the trade-off between
stability and transient response.
• Crossover frequency fC between fSW / 6 and fSW / 10. Assume fC = 50 kHz.
• Select the zero fz ≈ fC / 10
• Make the second pole fP2 ≈ fSW / 2
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8.2.1.2.19 Selection of Components for Type II Compensation
VOUT
RESR
RL
R1
VSENSE
GmBUCK
COUT
COMP
VREF
R2
Type 2A
R3
R0
C2
C1
Figure 28. Buck Compensation Components
2p ´ f C ´ VOUT ´ COUTx
R3 =
=
2p ´ 50 kHz ´ 5 V ´ 100μF
GmBUCK ´ K CFB ´ VREF
GmBUCK ´ K CFB ´ VREF
= 23.57 kW
where
•
•
•
•
•
VOUT = 5 V
COUT = 100 µF
GmBUCK = 1 mS
VREF = 0.8 V
KCFB = 0.125 / RSENSE = 8.33 S (0.125 is an internal constant)
(25)
Use the standard value of R3 = 24 kΩ.
C1 =
10
2p ´ R3 ´ fC
=
10
= 1.33 nF
2p ´ 24 kW ´ 50 kHz
(26)
Use the standard value of 1.5 nF.
C1
1.5 nF
=
= 33 pF
C2 =
æ fSW ö
æ 400 kHz ö
2p ´ R3 ´ C1ç
÷ -1
÷ - 1 2p ´ 24kW ´ 1.5 nF ç
2
è
ø
è 2 ø
The resulting bandwidth of buck converter f
(27)
C
GmBUCK ´ R3 ´ K CFB VREF
fC =
´
2p ´ COUTx
VOUT
fC =
1mS ´ 24 kW ´ 8.33 S ´ 0.8 V
= 50.9 kHz
2p ´ 100 μF ´ 5 V
(28)
fC is close to the target bandwidth of 50 kHz.
The resulting zero frequency fZ1
1
1
fZ1 =
=
= 4.42 kHz
2p ´ R3 ´ C1 2p ´ 24 kW ´ 1.5 nF
(29)
fZ1 is close to the fC / 10 guideline of 5 kHz.
The second pole frequency fP2
1
1
fP2 =
=
= 201kHz
2p ´ R3 ´ C2 2p ´ 24 kW ´ 33 pF
(30)
fP2 is close to the fSW / 2 guideline of 200 kHz. Hence, the design satisfies all requirements for a good loop.
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8.2.1.2.20 Resistor Divider Selection for Setting VOUTA Voltage
b=
VREF
0.8 V
=
= 0.16
VOUTA
5V
(31)
Choose the divider current through R1 and R2 to be 50 µA. Then
R1 + R2 =
5V
50 mA
= 66 kW
(32)
and
R2
R1 + R2
= 0.16
(33)
Therefore, R2 = 16 kΩ and R1 = 84 kΩ.
8.2.1.2.21 BuckB Component Selection
Using the same method as for VBuckA produces the following parameters and components.
VOUTB
3.3 V
t ON min =
=
= 275 ns
VIN max ´ f SW 30 V ´ 400 kHz
(34)
This is higher than the minimum duty cycle specified (100 ns typical).
60 mV
RSENSE =
= 30 mW
2A
L = 200 ´
30 mW
= 15 mH
400 kHz
(35)
∆Iripple current ≈ 0.4 A (approximately 20% of IOUT max)
Select an output capacitance COUTB of 100 µF with low ESR in the range of 10 mΩ.
Assume fC = 50 kHz.
2 ´ DI OUTB
2 ´ 1.9 A
=
= 46 mF
COUTB »
fSW ´ DVOUTB 400 kHz ´ 0.12 V
VOUTB(Ripple) =
DVOUTB =
R3 =
=
I OUTB(Ripple)
8 ´ f SW ´ COUTB
DI OUTB
4 ´ f C ´ COUTB
+ I OUTB(Ripple) ´ ESR =
+ DI OUTB ´ ESR =
(36)
0.4 A
+ 0.4 A ´ 10 mW = 5.3 mV
8 ´ 400 kHz ´ 100 mF
1.9 A
+ 1.9 A ´ 10 mW = 114 mV
4 ´ 50 kHz ´ 100 mF
(37)
(38)
2p ´ f C ´ VOUTB ´ COUTB
GmBUCK ´ K CFB ´ VREF
2p ´ 50 kHz ´ 3.3 V ´ 100 mF
1mS ´ 4.16 S ´ 0.8 V
= 31kW
(39)
Use the standard value of R3 = 30 kΩ.
C1 =
10
2p ´ R3 ´ fC
34
10
=
= 1.1nF
2p ´ 30 kW ´ 50 kHz
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(40)
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C1
C2 =
æ fSW ö
÷ -1
è 2 ø
2p ´ R3 ´ C1´ ç
=
1.1nF
æ 400 kHz ö
2p ´ 30 kW ´ 1.1nF ´ ç
÷ -1
2
è
ø
GmBUCK ´ R3 ´ K CFB
fC =
´
2p ´ COUTB
=
= 27 pF
(41)
VREF
VOUTB
1mS ´ 30 kW ´ 4.16 S ´ 0.8 V
2p ´ 100 μF ´ 3.3 V
= 48 kHz
(42)
fC is close to the target bandwidth of 50 kHz.
The resulting zero frequency fZ1
fZ1 =
1
1
=
2p ´ R3 ´ C1
= 4.8 kHz
2p ´ 30 kW ´ 1.1nF
(43)
fZ1 is close to the fC guideline of 5 kHz.
The second pole frequency fP2
fP2 =
1
1
=
2p ´ R3 ´ C2
2p ´ 30 kW ´ 27 pF
= 196 kHz
(44)
fP2 is close to the fSW / 2 guideline of 200 kHz.
Hence, the design satisfies all requirements for a good loop.
8.2.1.2.22 Resistor Divider Selection for Setting VOUT Voltage
b=
VREF
VOUT
=
0.8 V
3.3 V
= 0.242
(45)
Choose the divider current through R1 and R2 to be 50 µA. Then
R1 + R2 =
3.3 V
50 mA
= 66 kW
(46)
and
R2
R1 + R2
= 0.242
(47)
Therefore, R2 = 16 kΩ and R1 = 50 kΩ.
8.2.1.2.23 BuckX High-Side and Low-Side N-Channel MOSFETs
An internal supply, which is 5.8 V typical under normal operating conditions, provides the gate-drive supply for
these MOSFETs. The output is a totem pole, allowing full-voltage drive of VREG to the gate with peak output
current of 0.7 A. The reference for the high-side MOSFET is a floating node at the phase terminal (PHx), and the
reference for the low-side MOSFET is the power-ground (PGx) terminal. For a particular application, select these
MOSFETs with consideration for the following parameters: rDS(on), gate charge Qg, drain-to-source breakdown
voltage BVDSS, maximum dc current IDC(max), and thermal resistance for the package.
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The times trand tf denote the rising and falling times of the switching node and have a relationship to the gatedriver strength of the TPS43335-Q1 and TPS43336-Q1 and to the gate Miller capacitance of the MOSFET. The
first term denotes the conduction losses, which are minimimal when the on-resistance of the MOSFET is low.
The second term denotes the transition losses, which arise due to the full application of the input voltage across
the drain-source of the MOSFET as it turns on or off. Transition losses are lower at low currents and when the
switching time is low.
æ V ´I
ö
PBuckTOPFET = (IOUT )2 ´ rDS(on) (1 + TC) ´ D + ç IN OUT ÷ ´ (tr + t f ) ´ f SW
2
è
ø
2
PBuckLOWERFET = (IOUT ) ´ rDS(on) (1 + TC) ´ (1 - D) + VF ´ IOUT ´ (2 ´ t d ) ´ fSW
(48)
(49)
In addition, during the dead time td when both the MOSFETs are off, the body diode of the low-side MOSFET
conducts, increasing the losses. The second term in the preceding equation denotes this. Using external
Schottky diodes in parallel with the low-side MOSFETs of the buck converters helps to reduce this loss.
Note: rDS(on) has a positive temperature coefficient, and TC term for rDS(on) accounts for that fact. TC = d × ΔT[°C].
The temperature coefficient d is available as a normalized value from MOSFET data sheets and can have an
assumed starting value of 0.005 / ºC.
8.2.1.3 Application Curves
Figure 29. Boost Cranking Pulse Response
with 2 A Load on Boost
Figure 30. Buck Load-Step Response:
BuckA 5 V, 200 mA to 2.4 A to 200 mA
Figure 31. Buck Load-Step Response:
BuckB 3.3 V, 400 mA to 1.8 A to 400 mA
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8.2.2 Automotive ADAS Supply
The following example shows an application with lower output voltage and reduced load on BuckB (2.5 V, 1 A)
5 to 30 V
D1
L1
VBAT
BOOST: 10 V, 20 W
3.9 µH
CIN
COUT1
10 µF
330 µF
470 µF
TOP-SW3
1k
VIN
VBAT
BOT-SW3
1.5 k
0.03
470 pF
TOP-SW1
VBuckA: 5 V, 15 W
EXTSUP
DS
0.015
L2
BOT-SW1
150 µF
DIV
GC2
VREG
CBA
CBB
GA1
GB1
PHA
PHB
GA2
GB2
0.1 µF
10 µH
COUTA
GC1
84 k
PGNDA
SA1
SA2
20 pF
1 nF 39 k
10 nF
5k
18 nF 8.2 k
VBuckB: 3.3 V, 16.5 W
22 µH
COUTB
100 µF
PGNDB
TPS43335-Q1
or
SB1
TPS43336-Q1
SB2
COMPA
34 k
FBB
COMPB
SSA
SSB
PGA
PGB
ENA
AGND
ENB
220 pF
TOP-SW2
L3
0.045
BOT-SW2
FBA
16 k
4.7 µF
0.1 µF
36 k
16 k
47 pF
1 nF
10 nF
5k
RT
COMPC
DLYAB
ENC
SYNC
1 nF
Figure 32. Simplified Automotive ADAS Supply Schematic
8.2.2.1 Design Requirements
Table 5 lists the design-goal parameters.
Table 5. Design-Goal Parameters
PARAMETER
VBuckA
VBuckB
BOOST
VIN = 5 V to 30 V
12 V - typical
VIN = 6 V to 30 V
12 V - typical
VBAT = 5 V (cranking pulse
input) to 30 V
Output voltage, VOUTx
5V
2.5 V
10 V
Maximum output current, IOUTx
3A
1A
2A
±0.2 V
±0.12 V
±0.5 V
0.1 A to 3 A
0.1 A to 1 A
0.1 A to 2 A
400 kHz
400 kHz
200 kHz
Input voltage
Load-step output tolerance, ∆VOUT + ∆VOUT(Ripple)
Current output load step, ∆IOUTx
Converter switching frequency, fSW
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8.2.2.2 Detailed Design Procedure
Table 6 illustrates the design process and component selection for the TPS43335-Q1 and TPS43336-Q1.
Table 6. Automotive ADAS Supply – Component Proposals
NAME
COMPONENT PROPOSAL
VALUE
L1
MSS1278T-392NL (Coilcraft)
3.9 µH
L2
MSS1278T-822ML (Coilcraft)
8.2 µH
L3
MSS1278T-223ML (Coilcraft)
22 µH
D1
SK103 (Micro Commercial Components)
TOP_SW3
IRF7416 (International Rectifier)
TOP_SW1, TOP_SW2
Si4840DY-T1-E3 (Vishay)
BOT_SW1, BOT_SW2
Si4840DY-T1-E3 (Vishay)
BOT_SW3
IRFR3504ZTRPBF (International Rectifier)
COUT1
EEVFK1V471Q (Panasonic)
470 µF
COUTA
ECASD91A157M010K00 (Murata)
150 µF
COUTB
ECASD40J107M015K00 (Murata)
100 µF
CIN
EEEFK1V331P (Panasonic)
330 µF
9
Power Supply Recommendations
The TPS43335-Q1 and TPS43336-Q1 devices are designed to operate from an input voltage up to 40 V. Ensure
that the input supply is well regulated. Furthermore, if the supply voltage in the application is likely to reach
negative voltage (for example, reverse battery) a forward diode must be placed at the input of the supply. For the
VIN pin, a good quality X7R ceramic capacitor is recommended. Capacitance derating for aging, temperature,
and DC bias must be taken into account while determining the capacitor value. Connect a local decoupling
capacitor close to the Vreg for proper filtering. The PowerPAD™ package, which offers an exposed thermal pad
to enhance thermal performance, must be soldered to the copper landing on the PCB for optimal performance.
10 Layout
10.1 Layout Guidelines
10.1.1 Grounding and PCB Circuit Layout Considerations
10.1.1.1 Boost converter
1. The path formed from the input capacitor to the inductor and BOT_SW3 with the low-side current-sense
resistor should have short leads and PC trace lengths. The same applies for the trace from the inductor to
Schottky diode D1 to the COUT1 capacitor. Connect the negative terminal of the input capacitor and the
negative terminal of the sense resistor together with short trace lengths.
2. The overcurrent-sensing shunt resistor may require noise filtering, and the filter capacitor should be close to
the IC pin.
10.1.1.2 Buck Converter
1. Connect the drain of TOP_SW1 and TOP_SW2 together with the positive terminal of input capacitor COUT1.
The trace length between these terminals should be short.
2. Connect a local decoupling capacitor between the drain of TOP_SWx and the source of BOT_SWx.
3. The Kelvin-current sensing for the shunt resistor should have traces with minimum spacing, routed in parallel
with each other. Place any filtering capacitors for noise near the IC pins.
4. The resistor divider for sensing the output voltage connects between the positive terminal of its respective
output capacitor and COUTA or COUTB and the IC signal ground. Do not locate these components and their
traces near any switching nodes or high-current traces.
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SLVSAV6E – JUNE 2011 – REVISED DECEMBER 2015
Layout Guidelines (continued)
10.1.2 Other Considerations
1. Short PGNDx and AGND to the thermal pad. Use a star ground configuration if connecting to a non-ground
plane system. Use tie-ins for the EXTSUP capacitor, compensation-network ground, and voltage-sense
feedback ground networks to this star ground.
2. Connect a compensation network between the compensation pins and IC signal ground. Connect the
oscillator resistor (frequency setting) between the RT pin and IC signal ground. Do not locate these sensitive
circuits near the dv/dt nodes; these include the gate-drive outputs, phase pins, and boost circuits (bootstrap).
3. Reduce the surface area of the high-current-carrying loops to a minimum by ensuring optimal component
placement. Locate the bypass capacitors as close as possible to their respective power and ground pins.
10.2 Layout Example
POWER
INPUT
Power Lines
Connection to GND Plane of PCB through vias
Connection to top/bottom of PCB through vias
Voltage Rail Outputs
VBOOST
VBUCKA
Microcontroller
Exposed Pad
connected to
GND Plane
VIN
EXTSUP
DIV
VREG
CBB
GB1
PHB
GB2
PGNDB
SB1
SB2
FBB
COMPB
SSB
PGB
AGND
RT
DLYAB
SYNC
Copyright © 2011–2015, Texas Instruments Incorporated
Product Folder Links: TPS43335-Q1 TPS43336-Q1
VBUCKB
VBAT
DS
GC1
GC2
CBA
GA1
PHA
GA2
PGNDA
SA1
SA2
FBA
COMPA
SSA
PGA
ENA
ENB
COMPC
ENC
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Layout Example (continued)
Supply Decoupling Capacitors
Place nearby
Boost Switching Components
Minimize this loop area to reduce ringing
Buck1 and Buck2 Switching Components
Minimize this loop area to reduce ringing
10.3 Power Dissipation Derating Profile, 38-Pin HTTSOP PowerPAD Package
Figure 33. Derating Profile for Power Dissipation Based on High-K JEDEC PCB
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TPS43335-Q1, TPS43336-Q1
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SLVSAV6E – JUNE 2011 – REVISED DECEMBER 2015
11 Device and Documentation Support
11.1 Device Support
11.1.1 Third-Party Products Disclaimer
TI'S PUBLICATION OF INFORMATION REGARDING THIRD-PARTY PRODUCTS OR SERVICES DOES NOT
CONSTITUTE AN ENDORSEMENT REGARDING THE SUITABILITY OF SUCH PRODUCTS OR SERVICES
OR A WARRANTY, REPRESENTATION OR ENDORSEMENT OF SUCH PRODUCTS OR SERVICES, EITHER
ALONE OR IN COMBINATION WITH ANY TI PRODUCT OR SERVICE.
11.2 Documentation Support
11.2.1 Related Documentation
For related documentation see the following:
TPS4333xEVM, SLVU457
11.3 Related Links
The table below lists quick access links. Categories include technical documents, support and community
resources, tools and software, and quick access to sample or buy.
Table 7. Related Links
PARTS
PRODUCT FOLDER
SAMPLE & BUY
TECHNICAL
DOCUMENTS
TOOLS &
SOFTWARE
SUPPORT &
COMMUNITY
TPS43335-Q1
Click here
Click here
Click here
Click here
Click here
TPS43336-Q1
Click here
Click here
Click here
Click here
Click here
11.4 Community Resources
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
11.5 Trademarks
PowerPAD, E2E are trademarks of Texas Instruments.
All other trademarks are the property of their respective owners.
11.6 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
11.7 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
Copyright © 2011–2015, Texas Instruments Incorporated
Product Folder Links: TPS43335-Q1 TPS43336-Q1
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12 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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Product Folder Links: TPS43335-Q1 TPS43336-Q1
PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
(3)
Device Marking
(4/5)
(6)
TPS43335QDAPRQ1
ACTIVE
HTSSOP
DAP
38
2000
RoHS & Green
NIPDAU
Level-3-260C-168 HR
-40 to 125
TPS43335Q1
TPS43336QDAPRQ1
ACTIVE
HTSSOP
DAP
38
2000
RoHS & Green
NIPDAU
Level-3-260C-168 HR
-40 to 125
TPS43336Q1
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of
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