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TPS43350-Q1, TPS43351-Q1
SLVSAR7E – JUNE 2011 – REVISED OCTOBER 2016
TPS4335x-Q1 Low IQ, Dual Synchronous Buck Controller
1 Features
2 Applications
•
•
•
1
•
•
•
•
•
•
•
•
•
•
•
•
•
Qualified for Automotive Applications
AEC-Q100 Test Guidance With the Following
Results:
– Device Temperature Grade 1: –40°C to 125°C
Ambient Operating Temperature
– Device HBM ESD Classification Level H2
– Device HBM CDM Classification Level C2
Two Synchronous Buck Controllers
Input Range up to 40 V (Transients up to 60 V)
Low-Power Mode IQ: 30 µA (One Buck On), 35 µA
(Two Bucks On)
Low Shutdown Current Ish < 4 µA
Buck Output Range 0.9 V to 11 V
Programmable Frequency and External
Synchronization Range 150 kHz to 600 kHz
Separate Enable Inputs (ENA, ENB)
Frequency Spread Spectrum (TPS43351-Q1)
Selectable Forced Continuous Mode or Automatic
Low-Power Mode at Light Loads
Sense Resistor or Inductor DCR Sensing
Out-of-Phase Switching Between Buck Channels
Peak Gate Drive Current 1.5 A
Thermally Enhanced, 38-Pin HTSSOP (DAP)
PowerPAD™ Package
•
Automotive Infotainment, Navigation, and
Instrument Cluster Systems
Industrial or Automotive Multi-Rail DC Power
Distribution Systems and Electronic Control Units
3 Description
The TPS43350-Q1 and TPS43351-Q1 include two
current-mode synchronous buck controllers designed
for the harsh environment in automotive applications.
The devices are ideal for use in a multi-rail system
with low quiescent requirements, as they
automatically operate in low-power mode (consuming
typically 30 µA) at light loads. The devices offer
protection features such as thermal, soft-start, and
overcurrent protection. During short-circuit conditions
of the regulator output, activation of the currentfoldback feature can limit the current through the
MOSFETs for control of power dissipation. The two
independent soft-start inputs allow ramp-up of the
output voltage independently during start-up.
The programmable range of the switching frequency
is from 150 kHz to 600 kHz, as is the frequency of an
external clock to which the devices can synchronize.
Additionally, the TPS43351-Q1 offers frequencyhopping spread-spectrum operation.
Device Information(1)
PART NUMBER
TPS43350-Q1
TPS43351-Q1
PACKAGE
BODY SIZE (NOM)
HTSSOP (38)
12.50 mm × 6.20 mm
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
Typical Application Diagram
VBAT
Reverse
Battery
MOSFET
Control
VBuckA
Internal
VREG
BuckA
SYNC
RCOSC
External
Sync
ENA
ENB
SSA
Buck
Enable
SSB
DLYAB
SoftStart
BuckB
(NOTE: Internal Components same as
BuckA above)
VBuckB
Copyright © 2016, Texas Instruments Incorporated
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
TPS43350-Q1, TPS43351-Q1
SLVSAR7E – JUNE 2011 – REVISED OCTOBER 2016
www.ti.com
Table of Contents
1
2
3
4
5
6
Features ..................................................................
Applications ...........................................................
Description .............................................................
Revision History.....................................................
Pin Configuration and Functions .........................
Specifications.........................................................
1
1
1
2
4
6
6.1
6.2
6.3
6.4
6.5
6.6
Absolute Maximum Ratings ...................................... 6
ESD Ratings ............................................................ 6
Recommended Operating Conditions....................... 7
Thermal Information .................................................. 7
DC Electrical Characteristics .................................... 7
Power Dissipation Derating Profile, 38-Pin HTTSOP
PowerPAD Package ................................................ 10
6.7 Typical Characteristics ............................................ 11
7
Detailed Description ............................................ 13
7.1 Overview ................................................................. 13
7.2 Functional Block Diagram ....................................... 13
7.3 Feature Description................................................. 14
7.4 Device Functional Modes........................................ 18
8
Application and Implementation ........................ 19
8.1 Application Information............................................ 19
8.2 Typical Application ................................................. 19
9 Power Supply Recommendations...................... 25
10 Layout................................................................... 26
10.1 Layout Guidelines ................................................. 26
10.2 Layout Example .................................................... 26
11 Device and Documentation Support ................. 27
11.1
11.2
11.3
11.4
11.5
11.6
11.7
Device Support ....................................................
Related Links ........................................................
Receiving Notification of Documentation Updates
Community Resources..........................................
Trademarks ...........................................................
Electrostatic Discharge Caution ............................
Glossary ................................................................
27
27
27
27
27
27
27
12 Mechanical, Packaging, and Orderable
Information ........................................................... 27
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision D (April 2013) to Revision E
Page
•
Added Pin Configuration and Functions section, ESD Ratings table, Feature Description section, Device Functional
Modes, Application and Implementation section, Power Supply Recommendations section, Layout section, Device
and Documentation Support section, and Mechanical, Packaging, and Orderable Information section and ....................... 1
•
Changed typically 30 µA in Description section .................................................................................................................... 1
•
Deleted the PACKAGE AND ORDERING INFORMATION section; see the POA at the end of the datasheet .................... 4
•
Changed I/O to TYPE in Pin Functions and clarified GND for pins AGND, PGNDA, and PGNDB and to PWR for
pins VBAT and VIN................................................................................................................................................................. 4
•
Changed description for PGA and PGB pins ......................................................................................................................... 5
•
Added description for Gate-driver supply in Absolute Maximum Ratings table ..................................................................... 6
•
Changed 1.7 and 1.8 TYP and MAX columns to span rows ................................................................................................. 7
•
Changed 1.9 Shutdown current TYP to 3 and MAX to 5 ....................................................................................................... 8
•
Added inductor ripple current equation................................................................................................................................. 21
•
Changed Layout Guidelines text ......................................................................................................................................... 26
Changes from Revision C (September 2012) to Revision D
Page
•
Changed pinout diagram ........................................................................................................................................................ 4
•
Revised Absolute Maximum Ratings table ............................................................................................................................. 6
2
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Copyright © 2011–2016, Texas Instruments Incorporated
Product Folder Links: TPS43350-Q1 TPS43351-Q1
TPS43350-Q1, TPS43351-Q1
www.ti.com
SLVSAR7E – JUNE 2011 – REVISED OCTOBER 2016
Changes from Revision B (June 2011) to Revision C
Page
•
Changed input-voltage value for pins ENA and ENB ............................................................................................................. 5
•
Added a sentence to EXTSUP pin description....................................................................................................................... 5
•
Corrected AEC specification in ESD ratings .......................................................................................................................... 6
•
Multiple changes throughout Electrical Characteristics table ................................................................................................. 7
•
Changed upper threshold voltage for ENx pins to 1.7 V ...................................................................................................... 14
•
Text deletion from second paragraph of Light-Load PFM Mode section ............................................................................. 16
•
Changed value of gate-driver decoupling capacitor ............................................................................................................. 17
•
Added upper voltage limit for EXTSUP pin .......................................................................................................................... 17
•
Replaced paragraphs following the figure at end of Gate-Driver Supply section................................................................. 18
•
Revised diagram of Simplified Application Schematic Example .......................................................................................... 19
•
Clarified parameter definition in Application Example table ................................................................................................. 20
•
Added equations for Output Capacitor COUTA section .......................................................................................................... 21
•
Added equations for BuckB Component Selection sectiion ................................................................................................. 23
•
Changed peak output current in BuckX High-Side and Low-Side N-Channel MOSFETs section ....................................... 24
Copyright © 2011–2016, Texas Instruments Incorporated
Product Folder Links: TPS43350-Q1 TPS43351-Q1
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TPS43350-Q1, TPS43351-Q1
SLVSAR7E – JUNE 2011 – REVISED OCTOBER 2016
www.ti.com
5 Pin Configuration and Functions
DAP Package
38-Pin HTSSOP With PowerPAD
Top View
VBAT
1
38
VIN
NC
2
37
EXTSUP
NC
3
36
NC
GC2
4
35
VREG
CBA
5
34
CBB
GA1
6
33
GB1
PHA
7
32
PHB
GA2
8
31
GB2
PGNDA
9
30
PGNDB
29
SB1
PowerPAD
SA1
10
SA2
11
28
SB2
FBA
12
27
FBB
COMPA
13
26
COMPB
SSA
14
25
SSB
PGA
15
24
PGB
ENA
16
23
AGND
ENB
17
22
RT
NC
18
21
DLYAB
AGND
19
20
SYNC
Not to scale
Pin Functions
NAME
NO.
TYPE
AGND
19, 23
GND
CBA
5
I
A capacitor on this pin acts as the voltage supply for the high-side N-channel MOSFET gate-drive circuitry in buck
controller BuckA. When the buck is in a dropout condition, the device automatically reduces the duty cycle of the high-side
MOSFET to approximately 95% on every fourth cycle to allow the capacitor to recharge.
CBB
34
I
A capacitor on this pin acts as the voltage supply for the high-side N-channel MOSFET gate-drive circuitry in buck
controller BuckB. When the buck is in a dropout condition, the device automatically reduces the duty cycle of the high-side
MOSFET to approximately 95% on every fourth cycle to allow the capacitor to recharge.
COMPA
13
O
Error amplifier output of BuckA and compensation node for voltage-loop stability. The voltage at this node sets the target
for the peak current through the inductor of BuckA. Clamping his voltage on the upper and lower ends provides currentlimit protection for the external MOSFETs.
COMPB
26
O
Error amplifier output of BuckB and compensation node for voltage-loop stability. The voltage at this node sets the target
for the peak current through the inductor of BuckB. Clamping his voltage on the upper and lower ends provides currentlimit protection for the external MOSFETs.
4
DESCRIPTION
Analog ground reference
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SLVSAR7E – JUNE 2011 – REVISED OCTOBER 2016
Pin Functions (continued)
NAME
NO.
TYPE
DESCRIPTION
DLYAB
21
O
The capacitor at the DLYAB pin sets the power-good delay interval used to de-glitch the outputs of the power-good
comparators. Leaving this pin open sets the power-good delay to an internal default value of 20 µs typical.
ENA
16
I
Enable input for BuckA (active-high with an internal pullup current source). An input voltage higher than 1.7 V enables the
controller, whereas an input voltage lower than 0.7 V disables the controller. When both ENA and ENB are low, the device
shuts down and consumes less than 4 µA of current.
ENB
17
I
Enable input for BuckB (active-high with an internal pullup current source). An input voltage higher than 1.7 V enables the
controller, whereas an input voltage lower than 0.7 V disables the controller. When both ENA and ENB are low, the device
shuts down and consumes less than 4 µA of current.
EXTSUP
37
I
One can use EXTSUP to supply the VREG regulator from one of the TPS43350-Q1 or TPS43351-Q1 buck regulator rails
to reduce power dissipation in cases where there is an expectation of high VIN. If EXTSUP is unused, leave the pin open
without a capacitor installed.
FBA
12
I
Feedback voltage pin for BuckA. The buck controller regulates the feedback voltage to the internal reference of 0.8 V. A
suitable resistor divider network between the buck output and the feedback pin sets the desired output voltage.
FBB
27
I
Feedback voltage pin for BuckB. The buck controller regulates the feedback voltage to the internal reference of 0.8 V. A
suitable resistor divider network between the buck output and the feedback pin sets the desired output voltage.
GA1
6
O
This output can drive the external high-side N-channel MOSFET for buck regulator BuckA. The output provides high peak
currents to drive capacitive loads. The gate-drive reference is to a floating ground provided by PHA that has a voltage
swing provided by CBA.
GA2
8
O
This output can drive the external low-side N-channel MOSFET for buck regulator BuckA. The output provides high peak
currents to drive capacitive loads. VREG provides the voltage swing on this pin.
GB1
33
O
This output can drive the external high-side N-channel MOSFET for buck regulator BuckB. The output provides high peak
currents to drive capacitive loads. The gate drive reference is to a floating ground provided by PHB that has a voltage
swing provided by CBB.
GB2
31
O
This output can drive the external low-side N-channel MOSFET for buck regulator BuckB. The output provides high peak
currents to drive capacitive loads. VREG provides the voltage swing on this pin.
GC2
4
O
This pin makes a floating output drive available to control the external P-channel MOSFET. This MOSFET can bypass the
boost rectifier diode or a reverse-protection diode when the boost is not switching or if boost is disabled, and thus reduce
power losses.
No connection
NC
2, 3, 18, 36
–
PGNDA
9
GND
Power ground connection to the source of the low-side N-channel MOSFETs of BuckA.
PGNDB
30
GND
Power ground connection to the source of the low-side N-channel MOSFETs of BuckB
PGA
15
O
Open-drain power-good indicator pin for BuckA. An internal power-good comparator monitors the voltage at the feedback
pin and pulls this output low when the output voltage falls below 93% of the set value or if either VIN or VBAT drops below
its respective undervoltage threshold.
PGB
24
O
Open-drain power-good indicator pin for BuckB. An internal power-good comparator monitors the voltage at the feedback
pin and pulls this output low when the output voltage falls below 93% of the set value or if either VIN or VBAT drops below
its respective undervoltage threshold..
PHA
7
O
Switching terminal of buck regulator BuckA, providing a floating ground reference for the high-side MOSFET gate-driver
circuitry and used to sense current reversal in the inductor when discontinuous-mode operation is desired.
PHB
32
O
Switching terminal of buck regulator BuckB, providing a floating ground reference for the high-side MOSFET gate-driver
circuitry and used to sense current reversal in the inductor when discontinuous-mode operation is desired.
RT
22
O
Connecting a resistor to ground on this pin sets the operational switching frequency of the buck and boost controllers. A
short circuit to ground on this pin defaults operation to 400 kHz for the buck controllers and 200 kHz for the boost
controller.
SA1
10
I
SA2
11
I
SB1
29
I
SB2
28
I
SSA
14
O
Soft-start or tracking input for buck controller BuckA. The buck controller regulates the FBA voltage to the lower of 0.8 V or
the SSA pin voltage. An internal pullup current source of 1 µA is present at the pin, and an appropriate capacitor
connected here sets the soft-start ramp interval. Alternatively, a resistor divider connected to another supply can provide a
tracking input to this pin.
SSB
25
O
Soft-start or tracking input for buck controller BuckB. The buck controller regulates the FBB voltage to the lower of 0.8 V or
the SSB pin voltage. An internal pullup current source of 1 µA is present at the pin, and an appropriate capacitor
connected here sets the soft-start ramp interval. Alternatively, a resistor divider connected to another supply can provide a
tracking input to this pin.
I
If an external clock is present on this pin, the device detects it, and the internal PLL locks on to the external clock. This
overrides the internal oscillator frequency. The device can synchronize to frequencies from 150 kHz to 600 kHz. A high
logic level on this pin ensures forced continuous-mode operation of the buck controllers and inhibits transition to low-power
mode. An open or low allows discontinuous-mode operation and entry into low-power mode at light loads. On the
TPS43351-Q1, a high level enables frequency-hopping spread spectrum, whereas an open or a low level disables it.
SYNC
20
High-impedance differential-voltage inputs from the current-sense element (sense resistor or inductor DCR) for each buck
controller. Choose the current-sense element to set the maximum current through the inductor based on the current-limit
threshold (subject to tolerances) and considering the typical characteristics across duty cycle and VIN. (SA1 positive node,
SA2 negative node).
High-impedance differential voltage inputs from the current-sense element (sense resistor or inductor DCR) for each buck
controller. Choose the current-sense element to set the maximum current through the inductor based on the current-limit
threshold (subject to tolerances) and considering the typical characteristics across duty cycle and VIN (SB1 positive node,
SB2 negative node).
Copyright © 2011–2016, Texas Instruments Incorporated
Product Folder Links: TPS43350-Q1 TPS43351-Q1
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TPS43350-Q1, TPS43351-Q1
SLVSAR7E – JUNE 2011 – REVISED OCTOBER 2016
www.ti.com
Pin Functions (continued)
NAME
NO.
TYPE
VBAT
1
PWR
Supply pin
VIN
38
PWR
Main input pin. This is the buck controller input pin. Additionally, it powers the internal control circuits of the device.
VREG
35
O
The device requires an external capacitor on this pin to provide a regulated supply for the gate drivers of the buck and
boost controllers. TI recommends capacitance on the order of 4.7 µF. The regulator obtain its power from either or
EXTSUP. This pin has current-limit protection; do not use it to drive any other loads.
Pad
GND
PowerPAD thermal pad is not directly connected to any leads of the package. However, it is electrically and thermally
connected to the substrate, which is the ground of the device.
PowerPAD
DESCRIPTION
6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted) (1)
Voltage
MIN
MAX
UNIT
Input voltage: VBAT
–0.3
60
V
Ground: PGNDA–AGND, PGNDB–AGND
–0.3
0.3
V
Enable inputs: ENA, ENB
–0.3
60
V
Bootstrap inputs: CBA, CBB
–0.3
68
V
Bootstrap inputs: CBA–PHA, CBB–PHB
–0.3
8.8
V
Phase inputs: PHA, PHB
–0.7
60
V
Phase inputs: PHA, PHB (for 150 ns)
–1
V
Feedback inputs: FBA, FBB
–0.3
13
V
Error amplifier outputs: COMPA, COMPB
–0.3
13
V
High-side MOSFET driver: GA1–PHA, GB1–PHB
–0.3
8.8
V
Low-side MOSFET drivers: GA2–PGNDA, GB2–PGNDB
–0.3
8.8
V
Current-sense voltage: SA1, SA2, SB1, SB2
–0.3
13
V
Soft start: SSA, SSB
–0.3
13
V
Power-good output: PGA, PGB
–0.3
13
V
Power-good delay: DLYAB
–0.3
13
V
Switching-frequency timing resistor: RT
–0.3
13
V
SYNC, EXTSUP
–0.3
13
V
Voltage
(PMOS driver)
P-channel MOSFET driver: GC2
–0.3
60
V
P-channel MOSFET driver: -GC2
–0.3
8.8
V
Voltage (Gate driver)
Gate-driver supply: VREG
–0.3
8.8
V
Junction temperature: TJ
–40
150
°C
Operating temperature: TA
–40
125
°C
Storage temperature: Tstg
–55
165
°C
Voltage
(Buck function:
BuckA and BuckB)
Temperature
(1)
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. All voltage
values are with respect to AGND, unless otherwise stated.
6.2 ESD Ratings
VALUE
Human-body model (HBM) AEC-Q100 Classification Level H2
V(ESD)
Electrostatic discharge
Charged-device model (CDM) AEC-Q100
Classification Level C2
Machine model (MM)
(1)
6
(1)
UNIT
±2000
Pins 12, 21, 22, and 27
±400
Pins 1 and 20
±750
All other pins
±500
Pins 15 and 24
±150
All other pins
±200
V
AEC Q100-002 indicates that HBM stressing shall be in accordance with the ANSI/ESDA/JEDEC JS-001 specification.
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SLVSAR7E – JUNE 2011 – REVISED OCTOBER 2016
6.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
Buck function:
BuckA and BuckB
voltage
Temperature
MIN
MAX
Input voltage: , VBAT
4
40
V
Enable inputs: ENA, ENB
0
40
V
Boot inputs: CBA, CBB
4
48
V
–0.6
40
V
Current-sense voltage: SA1, SA2, SB1, SB2
0
11
V
Power-good output: PGA, PGB
0
11
V
SYNC, EXTSUP
0
9
V
–40
125
°C
Phase inputs: PHA, PHB
Operating temperature: TA
UNIT
6.4 Thermal Information
TPS43333-Q1
THERMAL METRIC (1)
DAP (HTSSOP)
UNIT
38 PINS
RθJA
Junction-to-ambient thermal resistance
27.3
°C/W
RθJC(top)
Junction-to-case (top) thermal resistance
19.6
°C/W
RθJB
Junction-to-board thermal resistance
15.9
°C/W
ψJT
Junction-to-top characterization parameter
0.24
°C/W
ψJB
Junction-to-board characterization parameter
6.6
°C/W
RθJC(bot)
Junction-to-case (bottom) thermal resistance
1.2
°C/W
(1)
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
6.5 DC Electrical Characteristics
VIN = 8 V to 18 V, TJ = –40°C to 150°C (unless otherwise noted)
NO.
PARAMETER
1.0
Input Supply
1.1
VBat
1.2
1.3
1.5
1.6
Supply voltage
After initial start-up, condition is satisfied.
Iq_LPM_
Iq_LPM
Buck undervoltage lockout
LPM quiescent current:
TA = 25°C (2)
LPM quiescent current:
TA = 125°C (2)
UNIT
6.5
40
V
4
40
V
3.6
3.8
V
VIN rising. After a reset, initial start-up conditions
may apply. (1)
3.8
4
V
VIN = 13 V, BuckA: LPM, BuckB: off
30
40
VIN = 13 V, BuckB: LPM, BuckA: off
30
40
VIN = 13 V, BuckA, B: LPM
35
45
VIN = 13 V, BuckA: LPM, BuckB: off
40
50
VIN = 13 V, BuckB: LPM, BuckA: off
40
50
VIN falling. After a reset, initial start-up conditions
may apply. (1)
Normal operation, SYNC = High
Iq_NRM
MAX
V
VIN = 13 V, BuckA, B: LPM
1.7
TYP
40
Buck regulator operating range
after initial start-up
UV
MIN
4
Input voltage required for device
on initial start-up
VIN
VIN
TEST CONDITIONS
3.5
µA
µA
µA
45
55
µA
4.85
5.3
mA
7
7.6
mA
VIN = 13 V, BuckA: CCM, BuckB: off
Quiescent current:
TA = 25°C (2)
VIN = 13 V, BuckB: CCM, BuckA: off
VIN = 13 V, BuckA, B: CCM
(1)
(2)
If VBAT and VREG remain adequate, the buck can continue to operate if VIN is > 3.8 V.
Quiescent current specification is non-switching current consumption without including the current in the external feedback resistor
divider.
Copyright © 2011–2016, Texas Instruments Incorporated
Product Folder Links: TPS43350-Q1 TPS43351-Q1
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DC Electrical Characteristics (continued)
VIN = 8 V to 18 V, TJ = –40°C to 150°C (unless otherwise noted)
NO.
PARAMETER
TEST CONDITIONS
MIN
Normal operation, SYNC = High
1.8
Iq_NRM
TYP
MAX
5
5.5
UNIT
mA
7.5
8
mA
3
5
µA
VIN = 13 V, BuckA: CCM, BuckB: off
Quiescent current:
TA = 125°C (2)
VIN = 13 V, BuckB: CCM, BuckA: off
VIN = 13 V, BuckA, B: CCM
1.9
IBAT_sh
2.0
Input Voltage - Overvoltage Lockout
Shutdown current
2.1
VOVLO
Overvoltage shutdown
2.2
OVLOHys
Hysteresis
2.3
OVLOfilter
Filter time
BuckA, B: off, VBAT = 13 V
VIN rising
45
46
47
V
VIN falling
43
44
45
V
1
2
3
5
V
µs
Gate Driver for PMOS
3.1
rDS(on)
PMOS OFF
3.2
IPMOS_ON
Gate current
VIN = 13.5 V, VGS = –5 V
3.3
tdelay_ON
Turnon delay
C = 10 nF
4.0
Buck Controllers
4.1
VBuckA/B
Adjustable output voltage range
4.2
VREF, NRM
Internal reference voltage and
tolerance in normal mode
Measure FBX pin
4.3
VREF, LPM
Internal reference voltage and
tolerance in low-power mode
Measure FBX pin
4.4
VSENSE
4.5
10
0.792
5
10
µs
11
V
0.8
0.808
V
–1%
0.784
1%
0.8
–2%
FBx = 0.75 V (low duty cycles)
V sense for reverse current limit in
CCM
Ω
mA
0.9
V sense for forward current limit in
CCM
20
10
0.816
V
2%
60
75
90
mV
FBx = 1 V
–65
–37.5
–23
mV
FBx = 0 V
17
32.5
48
mV
4.6
VI-Foldback
V sense for output short
4.7
tdead
Shoot-through delay, blanking time
100
ns
High-side minimum on-time
100
ns
4.8
DCNRM
Maximum duty cycle (digitally
controlled)
4.9
DCLPM
Duty cycle LPM
ILPM_Entry
LPM entry threshold load current
as fraction of maximum set load
current
The exit threshold is specified to be always higher
than entry threshold
ILPM_Exit
LPM exit threshold load current as
fraction of maximum set load
current
The exit threshold is specified to be always higher
than entry threshold
4.10
98.75%
80%
1%
See (3)
. See (3)
10%
High-Side External NMOS Gate Drivers for Buck Controller
4.11
IGX1_peak
Gate driver peak current
4.12
rDS(on)
Source and sink driver
1.5
VREG = 5.8 V, IGX1 current = 200 mA
A
2
Ω
2
Ω
Low-Side NMOS Gate Drivers for Buck Controller
4.13
IGX2_peak
Gate-driver peak current
4.14
rDS(on)
Source and sink driver
1.5
VREG = 5.8 V, IGX2 current = 200 mA
A
Error Amplifier (OTA) for Buck Converters
(3)
8
4.15
GmBUCK
Transconductance
COMPA, COMPB = 0.8 V,
source/sink = 5 µA, test in feedback loop
4.16
IPULLUP_FBx
Pullup current at FBx pins
5.0
Digital Inputs: ENA, ENB, SYNC
5.1
VIH
5.2
VIL
5.3
5.5
0.72
1
1.35
mS
FBx = 0 V
50
100
200
nA
Higher threshold
VIN = 13 V
1.7
Lower threshold
VIN = 13 V
RIH_SYNC
Resistance
VSYNC = 5 V
500
IIL_ENx
Pullup current source on ENA,
ENB
VENx = 0 V
0.5
V
0.7
V
kΩ
2
µA
The exit threshold specification is to be always higher than the entry threshold.
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DC Electrical Characteristics (continued)
VIN = 8 V to 18 V, TJ = –40°C to 150°C (unless otherwise noted)
NO.
PARAMETER
6.0
Switching Parameters – Buck DC-DC Controllers
TEST CONDITIONS
MIN
TYP
MAX
UNIT
6.1
fSW_Buck
Buck switching frequency
6.2
fSW_Buck
Buck switching frequency
RT pin: GND
360
400
440
kHz
RT pin: 60-kΩ external resistor
360
400
440
kHz
fSW_adj
Buck adjustable range with
external resistor
6.3
RT pin: external resistor
150
600
kHz
6.4
fSYNC
Buck synchronization range
External clock input
150
600
kHz
6.5
fSS
Spread-spectrum spreading
TPS43351-Q1 only
7.0
Internal Gate-Driver Supply
5.8
6.1
V
7.1
VREG
0.2%
1%
7.5
7.8
7.2
VREG(EXTSUP)
0.2%
1%
7.3
4.6
4.8
V
5%
Internal regulated supply
VIN = 8 V to 18 V, EXTSUP = 0 V, SYNC = High
Load regulation
IVREG = 0 mA to 100 mA, EXTSUP = 0 V,
SYNC = High
Internal regulated supply
EXTSUP = 8.5 V
Load regulation
IEXTSUP = 0 mA to 125 mA, SYNC = High
EXTSUP = 8.5 V to 13 V
VEXTSUP_th
EXTSUP switch-over voltage
threshold
IVREG = 0 mA to 100 mA ,
EXTSUP ramping positive
7.4
VEXTSUP-Hys
EXTSUP switch-over hysteresis
150
250
mV
7.5
IREG-Limit
Current limit on VREG
EXTSUP = 0 V, normal mode as well as LPM
100
400
mA
7.6
IREG_EXTSUP-
Current limit on VREG when using
EXTSUP
IVREG = 0 mA to 100 mA,
EXTSUP = 8.5 V, SYNC = High
125
400
mA
Soft-start source current
SSA and SSB = 0 V
0.75
1.25
µA
Limit
8.0
Soft Start
8.1
ISSx
9.0
Oscillator (RT)
9.1
VRT
10.0
Power-Good / Delay
10.1
PGpullup
Pullup for A and B to Sx2
10.2
PGth1
Power-good threshold
10.3
PGhys
Hysteresis
10.4
PGdrop
Voltage drop
5.5
7.2
4.4
Oscillator reference voltage
1
1.2
V
50
FBx falling
–5%
–7%
V
kΩ
–9%
2%
10.5
10.6
PGleak
Leakage
10.7
tdeglitch
Power-good deglitch time
IPGA = 5 mA
450
mV
IPGA = 1 mA
100
mV
1
µA
16
µs
VSx2 = VPGx = 13 V
2
10.8
tdelay
Reset delay
External capacitor = 1 nF
VBuckX < PGth1
10.9
tdelay_fix
Fixed reset delay
No external capacitor, pin open
10.10
IOH
Activate current source (current to
charge external capacitor)
10.11
IIL
Activate current sink (current to
discharge external capacitor)
11.0
Overtemperature Protection
11.1
Tshutdown
Junction temperature shutdown
threshold
11.2
Thys
Junction temperature hysteresis
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1
ms
20
50
µs
30
40
50
µA
30
40
50
µA
150
165
°C
15
°C
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6.6 Power Dissipation Derating Profile, 38-Pin HTTSOP PowerPAD Package
Figure 1. Power Dissipation Derating Profile Based on High-K JEDEC PCB
10
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6.7 Typical Characteristics
90
10000
EFFICIENCY,
SYNC = LOW
FORCED CONTINUOUS MODE (SYNC = 1), 200-mA LOAD
1000
EFFICIENCY (%)
80
70
POWER LOSS,
SYNC = HIGH
60
100
50
40 POWER LOSS,
SYNC = LOW
30
10
1 A/DIV
POWER LOSS (mW)
100
1
20
DISCONTINUOUS MODE (SYNC = 0), 200-mA LOAD
1 A/DIV
1 A/DIV
EFFICIENCY,
SYNC = HIGH
10
0
0.0001
LOW-POWER MODE (SYNC = 0), 20-mA LOAD
0.1
0.001
0.01
0.1
OUTPUT CURRENT (A)
VIN = 12 V
VOUT = 5 V
L = 4.7 µH
RSENSE = 10 mΩ
2 µs/DIV
10
1
VIN = 12 V
L = 4.7 µH
fSW = 400 kHz
VOUT = 5 V
RSENSE = 10 mΩ
fSW = 400 kHz
Figure 3. Inductor Currents (Buck)
Figure 2. Efficiency Across Output Currents (Bucks)
60
Quiescent Current (µA)
VOUTA
VOUTB
1 V/DIV
50
40
BOTH BUCKS ON
30
ONE BUCK ON
20
10
NEITHER BUCK ON
0
-40
2 ms/DIV
Figure 4. Soft-Start Outputs (Buck)
50
Sense Current (µA)
Peak Current Sense Voltage (mV)
62.5
37.5
25
12.5 SYNC = LOW
0
–12.5
–25
SYNC = HIGH
0.8
0.95
1.1
1.25
1.4
10
85
35
60
Temperature (°C)
110
135
160
Figure 5. No-Load Quiescent Currentacross Temperature
75
–37.5
0.65
-15
1.55
0.9
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0
–0.1
–0.2
–0.3
150°C
25°C
0
1
2
COMPx Voltage (V)
Figure 6. BUCKx Peak Current Limit vs COMPx Voltage
3
4
5
6
7
8
9
10 11 12
Output Voltage (V)
Figure 7. Current-Sense Pins Input Current (Buck)
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80
805
70
804
Regulated FBx Voltage (mV)
Peak Current Sense Voltage (mV)
Typical Characteristics (continued)
60
50
40
30
20
10
803
802
801
800
799
798
797
796
0
795
0
0.2
0.4
0.8
0.6
–40
–15
10
FBx Voltage (V)
35
60
85
110
135
160
Temperature (°C)
Figure 8. Foldback Current Limit (Buck)
Figure 9. Regulated FBx Voltage vs Temperature (Buck)
Peak Current Sense Voltage (mV)
80
70
60
VIN = 8 V
50
40
VIN = 12 V
30
20
10
0
0
10
20
30
40
50
60
70
80
90 100
Duty Cycle (%)
Figure 10. Current Limit vs Duty Cycle (Buck)
12
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7 Detailed Description
7.1 Overview
The TPS43350-Q1 and TPS43351-Q1 devices feature two current-mode synchronous buck controllers. With light
loads, the buck controllers can be enabled to automatically operate in low-power mode, consuming just 30 µA of
quiescent current. The buck controllers have independent soft-start capability and power-good indicators. Current
foldback in the buck controllers provide external MOSFET protection. The switching frequency is programmable
over 150 kHz to 600 kHz or can be synchronized to an external clock in the same range. Additionally, the
TPS43351-Q1 offers frequency-hopping spread-spectrum operation.
7.2 Functional Block Diagram
VIN
38
VBAT
1
EXTSUP
37
VREG
35
RT
22
Gate Driver Supply
CBA
6
GA1
7
PHA
8
GA2
9
PGNDA
10
SA1
-
11
SA2
-
12
FBA
13
COMPA
15
PGA
34
CBB
33
GB1
32
PHB
31
GB2
30
PGNDB
29
SB1
28
SB2
27
FBB
26
COMPB
24
PGB
PWM logic
VREG
Internal Oscillator
Slope
Comp
180deg
SYNC
5
Internal ref (Band gap)
20
+
SYNC &LPM
+
+
Current
Sense Amp
-
GC2
Source/Sink
Logic
4
PWM comp
gm OTA
+
+
0.8 V
SSA
EN
1µA
-
SSA
FBA
SA2
14
ENA
VIN
VIN
500 nA
500 nA
ENA
16
ENB
17
SSB
25
+
1µA
ENB
VREF
40 µA
DLYAB
Second Buck Controller Channel
21
40 µA
AGND
23
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7.3 Feature Description
7.3.1 Buck Controllers: Normal Mode PWM Operation
7.3.1.1 Frequency Selection and External Synchronization
The buck controllers operate using constant-frequency peak-current mode control for optimal transient behavior
and ease of component choices. The switching frequency is programmable between 150 kHz and 600 kHz,
depending upon the resistor value at the RT pin. A short circuit to ground at this pin sets the default switching
frequency to 400 kHz. Using a resistor at RT, one can set another frequency according to Equation 1.
X
fSW =
(X = 24 kW ´ MHz)
RT
fSW = 24 ´
109
RT
(1)
For example:
• 600 kHz requires 40 kΩ
• 150 kHz requires 160 kΩ
It is also possible to synchronize to an external clock at the SYNC pin in the same frequency range of 150 kHz to
600 kHz. The device detects clock pulses at this pin, and an internal PLL locks on to the external clock within the
specified range. The device can also detect a loss of clock at this pin, and on detection of this condition, the
device sets the switching frequency to the internal oscillator. The two buck controllers operate at identical
switching frequencies, 180 degrees out of phase.
7.3.1.2 Enable Inputs
Independent enable inputs from the ENA and ENB pins enable the buck controllers. These are high-voltage pins,
with a threshold of 1.7 V for the high level, and with direct connection to the battery permissible for self-bias. The
low threshold is 0.7 V. Both these pins have internal pullup currents of 0.5 µA (typical). As a result, an open
circuit on these pins enables the respective buck controllers. But with both buck controllers disabled, the device
shuts down and consumes a current less than 4 µA.
7.3.1.3 Feedback Inputs
The right resistor feedback divider network connected to the FBx (feedback) pins sets the output voltage. Choose
this network such that the regulated voltage at the FBx pin equals 0.8 V. The FBx pins have a 100-nA pullup
current source as a protection feature in case the pins open up as a result of physical damage.
7.3.1.4 Soft-Start Inputs
In order to avoid large inrush currents, the buck controllers have independent programmable soft-start timers.
The voltage at the SSx pins acts as the soft-start reference voltage. The 1-µA pullup current available at the SSx
pins, in combination with a suitably chosen capacitor, generates a ramp of the desired soft-start speed. After
start-up, the pullup current ensures that this node is higher than the internal reference of 0.8 V, which then
becomes the reference for the buck controllers. Use Equation 2 to calculate the soft-start ramp time..
I SS ´ Dt
CSS =
(Farads)
DV
where
•
•
•
ISS = 1 µA (typical)
∆V = 0.8 V
CSS is the required capacitor for ∆t, the desired soft-start time.
(2)
An alternative use of the soft-start pins is as tracking inputs. In this case, connect them to the supply to be
tracked via a suitable resistor-divider network.
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Feature Description (continued)
7.3.1.5 Current-Mode Operation
Peak-current-mode control regulates the peak current through the inductor to maintain the output voltage at its
set value. The error between the feedback voltage at FBx and the internal reference produces a signal at the
output of the error amplifier (COMPx) which serves as a target for the peak inductor current. The device senses
the current through the inductor as a differential voltage at Sx1–Sx2 and compares voltage with this target during
each cycle. A fall or rise in load current produces a rise or fall in voltage at FBx, causing COMPx to fall or rise
respectively, thus increasing or decreasing the current through the inductor until the average current matches the
load. This process maintains the output voltage in regulation.
The top N-channel MOSFET turns on at the beginning of each clock cycle and stays on until the inductor current
reaches its peak value. Once this MOSFET turns off, and after a small delay (shoot-through delay) the lower Nchannel MOSFET turns on until the start of the next clock cycle. In dropout operation, the high-side MOSFET
stays on continuously. In every fourth clock cycle, there is a limit on the duty cycle of 95% in order to charge the
bootstrap capacitor at CBx. This allows a maximum duty cycle of 98.75% for the buck regulators. During dropout,
the buck regulator switches at one-fourth of its normal frequency.
7.3.1.6 Current Sensing and Current Limit With Foldback
Clamping of the maximum value of COMPx is such as to limit the maximum current through the inductor to a
specified value. When the output of the buck regulator (and hence the feedback value at FBx) falls to a low value
due to a short-circuit or overcurrent condition, the clamped voltage at COMPx successively decreases, thus
providing current foldback protection. This protects the high-side external MOSFET from excess current (forwarddirection current limit).
Similarly, if a fault condition shorts the output to a high voltage and the low-side MOSFET turns fully on, the
COMPx node drops low. A clamp is on its lower end as well, in order to limit the maximum current in the low-side
MOSFET (reverse-direction current limit).
An external resistor senses the current through the inductor. Choose the sense resistor such that the maximum
forward peak current in the inductor generates a voltage of 75 mV across the sense pins. This specified value is
for low duty cycles only. At typical duty-cycle conditions around 40% (assuming 5-V output and 12-V input), 50
mV is a more reasonable value, considering tolerances and mismatches. The typical characteristics provide a
guide for using the correct current-limit sense voltage.
The current-sense pins Sx1 and Sx2 are high-impedance pins with low leakage across the entire output range.
This allows DCR current sensing using the dc resistance of the inductor for higher efficiency. Figure 11 shows
DCR sensing. Here, the series resistance (DCR) of the inductor is the sense element. Place the filter
components close to the device for noise immunity. Remember that while the DCR sensing gives high efficiency,
it is inaccurate due to the temperature sensitivity and a wide variation of the parasitic inductor series resistance.
Hence, it may often be advantageous to use the more-accurate sense resistor for current sensing.
Inductor L
TPS43350-Q1
or
TPS43351-Q1
VBuckX
DCR
R1
1
C1
1
VC
2
Sx2
Sx1
1
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Figure 11. DCR Sensing Configuration
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Feature Description (continued)
7.3.1.7 Slope Compensation
Optimal slope compensation, which is adaptive to changes in input voltage and duty cycle, allows stable
operation at all conditions. For optimal performance of this circuit, choose the inductor and sense resistor
according to Equation 3.
L ´ f SW
= 200
RS
where
•
•
•
L is the buck regulator inductor in henries.
RS is the sense resistor in ohms.
fsw is the buck-regulator switching frequency in hertz.
(3)
7.3.1.8 Power-Good Outputs and Filter Delays
Each buck controller has an independent power-good comparator monitoring the feedback voltage at the FBx
pins and indicating whether the output voltage has fallen below a specified power-good threshold. This threshold
has a typical value of 93% of the regulated output voltage. The power-good indicator is available as an opendrain output at the PGx pins. An internal 50-kΩ pullup resistor to Sx2 is available, or use of an external resistor is
possible. Shutdown of a buck controller causes an internal pulldown of the power-good indicator. Connecting the
pullup resistor to a rail other than the output of that particular buck channel causes a constant current flow
through the resistor when the buck controller is in the powered-down state.
In order to avoid triggering the power-good indicators due to noise or fast transients on the output voltage, the
device uses an internal delay circuit for de-glitching. Similarly, when the output voltage returns to its set value
after a long negative transient, assertion of the power-good indicator (release of the open-drain pin) occurs after
the same delay. Use of this delay can pauses the delay of the reset. Program the duration of the delay of by
using a suitable capacitor at the DLYAB pin according to Equation 4.
tDELAY
1 ms
=
C DLYAB
1 nF
(4)
When the DLYAB pin is open, the delay setting is for a default value of 20 µs typical. The power-good delay
timing is common to both the buck rails, but the power-good comparators and indicators function independently.
7.3.1.9 Light-Load PFM Mode
An external clock or a high level on the SYNC pin results in forced continuous-mode operation of the bucks. An
open or low on the SYNC pin allows the buck controllers to operate in discontinuous mode at light loads by
turning off the low-side MOSFET on detection of a zero-crossing in the inductor current.
In discontinuous mode, as the load decreases, the duration when both the high-side and low-side MOSFETs turn
off increases (deep discontinuous mode). In case the duration exceeds 60% of the clock period and VBAT > 8 V,
the buck controller switches to a low-power operation mode. The design ensures that this typically occurs at 1%
of the set full-load current if the inductor and the sense resistor have been chosen appropriately as
recommended in the Slope Compensation section.
In low-power PFM mode, the buck monitors the FBx voltage and compares it with the 0.8-V internal reference.
Whenever the FBx value falls below the reference, the high-side MOSFET turns on for a pulse duration inversely
proportional to the difference – Sx2. At the end of this on-time, the high-side MOSFET turns off and the current in
the inductor decays until it becomes zero. The low-side MOSFET does not turn on. The next pulse occurs the
next time FBx falls below the reference value. This results in a constant volt-second ton hysteretic operation with
a total device quiescent current consumption of 30 µA when a single buck channel is active and 35 µA when
both channels are active.
As the load increases, the pulses become more and more frequent and move closer to each other until the
current in the inductor becomes continuous. At this point, the buck controller returns to normal fixed-frequency
current-mode control. Another criterion to exit the low-power mode is when VIN falls low enough to require higher
than 80% duty cycle of the high-side MOSFET.
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Feature Description (continued)
The TPS43350-Q1 and TPS43351-Q1 can support the full current load during low-power mode until the
transition to normal mode takes place. The design ensures that exit of the low-power mode occurs at 10%
(typical) of full-load current if the selection of inductor and sense resistor is as recommended. Moreover, there is
always a hysteresis between the entry and exit thresholds to avoid oscillating between the two modes.
In the event that both buck controllers are active, low-power mode is only possible when both buck controllers
have light loads that are low enough for low-power-mode entry.
7.3.2 Frequency-Hopping Spread Spectrum (TPS43351-Q1 Only)
The TPS43351-Q1 features a frequency-hopping pseudo-random spectrum spreading architecture. On this
device, whenever the SYNC pin is high, the internal oscillator frequency varies from one cycle to the next within
a band of ±5% around the value programmed by the resistor at the RT pin. The implementation uses a linear
feedback shift register that changes the frequency of the internal oscillator based on a digital code. The shift
register is long enough to make the hops pseudo-random in nature and is designed in such a way that the
frequency shifts only by one step at each cycle to avoid large jumps in the buck switching frequencies.
Table 1. Frequency Hopping Control
SYNC
TERMINAL
FREQUENCY SPREAD SPECTRUM (FSS)
COMMENTS
External clock
Not active
Device in forced continuous mode, internal PLL locks into external clock
between 150 kHz and 600 kHz.
Low or open
Not active
Device can enter discontinuous mode. Automatic LPM entry and exit,
depending on load conditions
High
TPS43350-Q1: FSS not active
Device in forced continuous mode
TPS43351-Q1: FSS active
7.3.3 Gate-Driver Supply (VREG, EXTSUP)
The gate-driver supplies of the buck and boost controllers are from an internal linear regulator whose output (5.8
V typical) is on the VREG pin and requires decoupling with a ceramic capacitor in the range of 3.3 µF to 10 µF.
This pin has internal current-limit protection; do not use it to power any other circuits.
VIN powers the VREG linear regulator by default when the EXTSUP voltage is lower than 4.6 V (typical). In case
VIN expected to go to high levels, there can be excessive power dissipation in this regulator, especially at high
switching frequencies and when using large external MOSFETs. In this case, it is advantageous to power this
regulator from the EXTSUP pin, which can be connected to a supply lower than VIN but high enough to provide
the gate drive. When the voltage on EXTSUP is greater than 4.6 V, the linear regulator automatically switches to
EXTSUP as its input, to provide this advantage. Efficiency improvements are possible when using one of the
switching regulator rails from the TPS4335x-Q1 or any other voltage available in the system to power EXTSUP.
The maximum voltage for application to EXTSUP is 9 V.
VIN
5.8 V
(typical)
LDO
VIN
EXTSUP
7.5 V
(typical)
LDO
EXTSUP
4.6 V (typical)
VREG
Figure 12. Internal Gate-Driver Supply
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Using a voltage above 5.8 V (sourced by VIN) for EXTSUP is advantageous, as it provides a large gate drive
and hence better on-resistance of the external MOSFETs. When using EXTSUP, always keep the buck rail
supplying EXTSUP enabled. Alternatively, if it is necessary to switch off the buck rail supplying EXTSUP, place a
diode between the buck rail and EXTSUP. During low-power mode, the EXTSUP functionality is not available.
The internal regulator operates as a shunt regulator powered from VIN and has a typical value of 7.5 V. Currentlimit protection for VREG is available in low-power mode as well. If EXTSUP is unused, leave the pin open
without a capacitor installed.
7.3.4 External P-Channel Drive (GC2) and Reverse-Battery Protection
The TPS4335x-Q1 includes a gate driver for an external P-channel MOSFET which can be connected across the
reverse-battery diode. This is useful to reduce power losses and the voltage drop over a typical diode. The gate
driver provides a swing of 6 V typical below the VIN voltage in order to drive a P-channel MOSFET.
GC2
VBAT
VIN
Fuse
TPS43350-Q1
or
TPS43351-Q1
VBAT
Copyright © 2016, Texas Instruments Incorporated
Figure 13. Reverse-Battery Protection Option
7.3.5 Undervoltage Lockout and Overvoltage Protection
The TPS4335x-Q1 starts up at a VIN voltage of 6.5 V (minimum), required for the internal supply (VREG). Once it
has started up, the device operates down to a VIN voltage of 3.6 V; below this voltage level, the undervoltage
lockout disables the device. Note: if VIN drops, VREG drops as well; hence, the gate-drive voltage decreases,
whereas the digital logic is fully functional. A voltage of 46 V at VIN triggers the overvoltage comparator, which
shuts down the device. In order to prevent transient spikes from shutting down the device, under- and
overvoltage protection have filter times of 5 µs (typical).
When the voltages return to the normal operating region, the enabled switching regulators startwith a new softstart ramp for the buck regulators.
7.3.6 Thermal Protection
The TPS4335x-Q1 protects itself from overheating using an internal thermal shutdown circuit. If the die
temperature exceeds the thermal shutdown threshold of 165ºC due to excessive power dissipation (for example,
due to fault conditions such as a short circuit at the gate drivers or VREG), the controllers turn off. Then restart
when the temperature has fallen by 15ºC.
7.4 Device Functional Modes
Table 2 lists the modes of operation for the device.
Table 2. Mode of Operation
ENABLE AND INHIBIT PINS
ENA
Low
Low
ENB
Low
High
High
Low
High
High
18
SYNC
X
Low
High
Low
High
Low
High
BUCK CONTROLLER STATUS
Shutdown
BuckB running
BuckA running
BuckA and BuckB running
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DEVICE STATUS
QUIESCENT CURRENT
Shutdown
Approximately 4 µA
BuckB: LPM enabled
Approximately 30 µA (light loads)
BuckB: LPM inhibited
mA range
BuckA: LPM enabled
Approximately 30 µA (light loads)
BuckA: LPM inhibited
mA range
BuckA and BuckB: LPM enabled
Approximately 35 µA (light loads)
BuckA and BuckB: LPM inhibited
mA range
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8 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
8.1 Application Information
The TPS4335x-Q1 devices are dual synchronous buck controllers used to convert a higher-input voltage to two
lower-output voltages. The following sections have the component values and calculations that are a good
starting point for use in the application. Some of the values in the equations are theoretical values, to improve the
performance of the device may require further optimization of these values.
8.2 Typical Application
4 V to 40 V
D1
VBAT
10 µF
CIN
220 µF
680 µF
CVIN
SWRB
1 kΩ
VBAT
SWAH
VBuckA — 5 V, 15 W
0.015 Ω
ENA
EXTSUP
ENB
RT
GC2
VREG
CBA
CBB
GA1
GB1
4.7 µF
SWBH
L2
0.1 µF
0.1 µF
L1
8.2 µH
100 µF
COUTA
VIN
PHA
0.03 Ω
VBuckB — 3.3 V, 6.6 W
15 µH
PHB
100 µF
COUTB
SWBL
SWAL
GA2
GB2
TPS43350-Q1
or
PGNDA
PGNDB
TPS43351-Q1
84 kΩ
SA1
Sb1
PGA
PGB
SA2
SB2
FBA
FBB
50kΩ
5kΩ
5 kΩ
16 kΩ
33 pF
1.5 nF 24 kΩ
10 nF
COMPA
SSA
SYNC
COMPB
SSB
16 kΩ
27 pF
30 kΩ 1.1 nF
10nF
AGND
DLYAB
1 nF
Copyright © 2016, Texas Instruments Incorporated
Figure 14. Simplified Application Schematic Example
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Typical Application (continued)
8.2.1 Design Requirements
Table 3 lists the design-goal parameters.
Table 3. Design Parameters
PARAMETER
Input voltage
Output voltage, VOUTx
Maximum output current, IOUTx
Load step output tolerance, ∆VOUT + ∆VOUT(Ripple)
Current output load step, ∆IOUTx
Converter switching frequency, fSW
VBuckA
VBuckB
VIN = 6 V to 30 V
12 V - typical
VIN = 6 V to 30 V
12 V - typical
5V
3.3 V
3A
2A
±0.2 V
±0.12 V
0.1 A to 3 A
0.1 A to 2 A
400 kHz
400 kHz
8.2.2 Detailed Design Procedure
The following example illustrates the design process and component selection for the TPS43350-Q1.
This is a starting point, and theoretical representation of the values to be used for the application; improving the
performance of the device may require further optimization of the derived components.
Table 4. Application Example – Component Proposals
NAME
COMPONENT PROPOSAL
VALUE
L1
MSS1278T-822ML (Coilcraft)
8.2 µH
L2
MSS1278T-153ML (Coilcraft)
15 µH
D1
SK103 (Micro Commercial Components)
SWRB
IRF7416 (International Rectifier)
SWAH, SWAL, SWBH,
SWBL
Si4840DY-T1-E3 (Vishay)
COUTA, COUTB
ECASD91A107M010K00 (Murata)
100 µF
CIN
EEEFK1V331P (Panasonic)
330 µF
8.2.2.1 BuckA Component Selection
8.2.2.1.1 Minimum ON Time, tON min
t ON min =
VOUTA
5V
=
= 416 ns
VIN max ´ f SW 30 V ´ 400 kHz
(5)
This is higher than the minimum on-time specified (100 ns typical). Hence, the minimum duty cycle is achievable
at this frequency.
8.2.2.1.2 Current-Sense Resistor RSENSE
Based on the typical characteristics for VSENSE limit with VIN versus duty cycle, the sense limit is approximately 65
mV (at VIN = 12 V and duty cycle of 5 V / 12 V = 0.416). Allowing for tolerances and ripple currents, choose
VSENSE with a maximum of 50 mV.
50 mV
RSENSE =
= 17 mW
3A
(6)
Select 15 mΩ.
20
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8.2.2.2 Inductor Selection L
As explained in the description of the buck controllers, for optimal slope compensation and loop response, the
inductor should be chosen such that:
R SENSE
15 mW
L = K FLR ´
= 200 ´
= 7.5 mH
f SW
400 kHz
(7)
KFLR = Coil selection constant = 200
Choose a standard value of 8.2 µH. For the buck converter, the inductor saturation currents and core should be
chosen to sustain the maximum currents.
8.2.2.3 Inductor Ripple Current IRIPPLE
At nominal input voltage of 12 V, this inductor value causes a ripple current of 30% of IO max ≈ 1 A.
VOUT
ሺVIN െ VOUTሻ ൈ ൬
൰൨
ሺVIN ൈ fSW ሻ
οIL ൌ
L
where
•
•
•
•
VIN = Input voltage
VOUT = Output voltage
fSW = Switching frequency
L = Inductor
(8)
8.2.2.4 Output Capacitor COUTA
Select an output capacitance COUTA of 100 µF with low ESR in the range of 10 mΩ. This gives ∆VO(Ripple) ≈ 15
mV and ∆V drop of ≈ 180 mV during a load step, which does not trigger the power-good comparator and is within
the required limits.
2 ´ DI OUTA
2 ´ 2.9 A
COUTA »
=
= 72.5 mF
f SW ´ DVOUTA 400 kHz ´ 0.2 V
(9)
VOUTA(Ripple) =
DVOUTA =
I OUTA(Ripple)
8 ´ f SW ´ COUTA
DI OUTA
4 ´ f C ´ COUTA
+ I OUTA(Ripple) ´ ESR =
+ DI OUTA ´ ESR =
1A
+ 1 A ´ 10 mW = 13.1mV
8 ´ 400 kHz ´ 100 mF
2.9 A
+ 2.9 A ´ 10 mW = 174 mV
4 ´ 50 kHz ´ 100 mF
(10)
(11)
8.2.2.5 Bandwidth of Buck Converter fC
Use the following guidelines to set frequency poles, zeroes and crossover values for a tradeoff between stability
and transient response.
• Crossover frequency fC between fSW / 6 and fSW / 10. Assume fC = 50 kHz.
• Select the zero fz ≈ fC / 10.
• Make the second pole fP2 ≈ fSW / 2.
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8.2.2.6 Selection of Components for Type II Compensation
VOUT
RESR
RL
R1
VSENSE
GmBUCK
COUT
R2
COMP
Type 2A
VREF
R3
R0
C2
C1
Copyright © 2016, Texas Instruments Incorporated
Figure 15. Buck Compensation Components
R3 =
2p ´ f C ´ VOUT ´ COUTx
=
2p ´ 50 kHz ´ 5 V ´ 100μF
GmBUCK ´ K CFB ´ VREF
GmBUCK ´ K CFB ´ VREF
= 23.57 kW
(12)
Use the standard value of R3 = 24 kΩ,
Where VOUT = 5 V, COUTx = 100 µF, GmBUCK = 1 mS, VREF = 0.8 V
KCFB = 0.125 / RSENSE = 8.33 S (0.125 is an internal constant)
C1 =
10
2p ´ R3 ´ fC
10
=
= 1.33 nF
2p ´ 24 kW ´ 50 kHz
(13)
Use the standard value of 1.5 nF.
C1
1.5 nF
=
= 33 pF
C2 =
æf
ö
æ 400 kHz ö
1
2p ´ R3 ´ C1ç SW ÷ - 1 2p ´ 24kW ´ 1.5 nF ç
÷
2
è
ø
è 2 ø
(14)
The resulting bandwidth of buck converter, fC:
fC =
GmBUCK ´ R3 ´ K CFB VREF
´
2p ´ COUTx
VOUT
fC =
1mS ´ 24 kW ´ 8.33 S ´ 0.8 V
= 50.9 kHz
2p ´ 100 μF ´ 5 V
(15)
This is close to the target bandwidth of 50 kHz.
The resulting zero frequency fZ1:
1
1
fZ1 =
=
= 4.42 kHz
2p ´ R3 ´ C1 2p ´ 24 kW ´ 1.5 nF
(16)
This is close to the fC / 10 guideline of 5 kHz.
The second pole frequency fP2:
1
1
fP2 =
=
= 201kHz
2p ´ R3 ´ C2 2p ´ 24 kW ´ 33 pF
(17)
This is close to the fSW / 2 guideline of 200 kHz. Hence, the design satisfies all requirements for a good loop.
8.2.2.7 Resistor Divider Selection for Setting VOUTA Voltage
V
0.8 V
b = REF =
= 0.16
VOUTA
5V
(18)
Choose the divider current through R1 and R2 to be 50 µA. Then
22
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R1 + R2 =
5V
50 mA
= 66 kW
(19)
and
R2
R1 + R2
= 0.16
(20)
Therefore, R2 = 16 kΩ and R1 = 84 kΩ.
8.2.2.8 BuckB Component Selection
Using the same method as for VBuckA produces the following parameters and components.
VOUTB
5V
t ON min =
=
= 416 ns
VIN max ´ f SW 30 V ´ 400 kHz
(21)
This is higher than the minimum duty cycle specified (100 ns typical).
60 mV
RSENSE =
= 30 mW
2A
L = 200 ´
30 mW
= 15 mH
400 kHz
(22)
∆Iripple current ≈ 0.4 A (approximately 20% of IOUT max)
Select an output capacitance CO of 100 µF with low ESR in the range of 10 mΩ. Assume fC = 50 kHz.
2 ´ DI OUTB
2 ´ 1.9 A
=
= 46 mF
COUTB »
fSW ´ DVOUTB 400 kHz ´ 0.12 V
VOUTB(Ripple) =
DVOUTB =
R3 =
=
I OUTB(Ripple)
8 ´ f SW ´ COUTB
DI OUTB
4 ´ f C ´ COUTB
+ I OUTB(Ripple) ´ ESR =
+ DI OUTB ´ ESR =
0.4 A
+ 0.4 A ´ 10 mW = 5.3 mV
8 ´ 400 kHz ´ 100 mF
1.9 A
+ 1.9 A ´ 10 mW = 114 mV
4 ´ 50 kHz ´ 100 mF
(23)
(24)
(25)
2p ´ f C ´ VOUTB ´ COUTB
GmBUCK ´ K CFB ´ VREF
2p ´ 50 kHz ´ 3.3 V ´ 100 mF
1mS ´ 4.16 S ´ 0.8 V
= 31kW
(26)
Use the standard value of R3 = 30 kΩ.
C1 =
10
2p ´ R3 ´ fC
C2 =
10
=
= 1.1nF
2p ´ 30 kW ´ 50 kHz
(27)
C1
æ fSW ö
÷ -1
è 2 ø
2p ´ R3 ´ C1´ ç
=
1.1nF
æ 400 kHz ö
2p ´ 30 kW ´ 1.1nF ´ ç
÷ -1
2
è
ø
= 27 pF
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(28)
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GmBUCK ´ R3 ´ K CFB
fC =
=
VREF
´
2p ´ COUTB
www.ti.com
VOUTB
1mS ´ 30 kW ´ 4.16 S ´ 0.8 V
2p ´ 100 μF ´ 3.3 V
= 48 kHz
(29)
This is close to the target bandwidth of 50 kHz.
The resulting zero frequency fZ1:
fZ1 =
1
1
=
2p ´ R3 ´ C1
= 4.8 kHz
2p ´ 30 kW ´ 1.1nF
(30)
This is close to the fC guideline of 5 kHz.
The second pole frequency fP2:
fP2 =
1
1
=
2p ´ R3 ´ C2
2p ´ 30 kW ´ 27 pF
= 196 kHz
(31)
This is close to the fSW / 2 guideline of 200 kHz.
Hence, the design satisfies all requirements for a good loop.
8.2.2.9 Resistor Divider Selection for Setting VOUT Voltage
b=
VREF
VOUT
=
0.8 V
3.3 V
= 0.242
(32)
Choose the divider current through R1 and R2 to be 50 µA. Then
R1 + R2 =
3.3 V
50 mA
= 66 kW
(33)
and
R2
R1 + R2
= 0.242
(34)
Therefore, R2 = 16 kΩ and R1 = 50 kΩ.
8.2.2.10 BUCKx High-Side and Low-Side N-Channel MOSFETs
An internal supply, which is 5.8 V typical under normal operating conditions, provides the gate-drive supply for
these MOSFETs. The output is a totem pole allowing full voltage drive of VREG to the gate with peak output
current of 1.5 A. The reference for the high-side MOSFET is a floating node at the phase terminal (PHx), and the
reference for the low-side MOSFET is the power-ground (PGx) terminal. For a particular application, select these
MOSFETs with consideration for the following parameters: rDS(on), gate charge Qg, drain-to-source breakdown
voltage BVDSS, maximum dc current IDC(max), and thermal resistance for the package.
The times tr and tf denote the rising and falling times of the switching node and have a relationship to the gatedriver strength of the TPS43350x-Q1 and gate Miller capacitance of the MOSFET. The first term denotes the
conduction losses, which are minimal when the on-resistance of the MOSFET is low. The second term denotes
the transition losses, which arise due to the full application of the input voltage across the drain-source of the
MOSFET as it turns on or off. They are lower at low currents and when the switching time is low.
æ V ´I
ö
PBuckTOPFET = (IOUT )2 ´ rDS(on) (1 + TC) ´ D + ç IN OUT ÷ ´ (tr + t f ) ´ f SW
2
è
ø
2
PBuckLOWERFET = (IOUT ) ´ rDS(on) (1 + TC) ´ (1 - D) + VF ´ IOUT ´ (2 ´ t d ) ´ fSW
24
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(35)
(36)
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In addition, during dead time td when both the MOSFETs are off, the body diode of the low-side MOSFET
conducts, increasing the losses. The second term in the foregoing equation denotes this. Using external Schottky
diodes in parallel to the low-side MOSFETs of the buck converters helps to reduce this loss.
NOTE
The rDS(on) has a positive temperature coefficient, and TC term for rDS(on) accounts for that
fact. TC = d × delta T[°C]. The temperature coefficient d is available as a normalized value
from MOSFET data sheets and can be assumed to be 0.005 / °C as a starting value.
8.2.3 Application Curves
VOUT AC-COUPLED
100 mV/DIV
100 mV/DIV
VOUT AC-COUPLED
2 A/DIV
2 A/DIV
IIND
IIND
VIN = 12 V
L = 4.7 µH
50 µs/DIV
VOUT = 5 V
RSENSE = 10 mΩ
fSW = 400 kHz
Figure 16. Buck Load Step: Forced Continuous Mode
(Moved Here)
(0 To 4 A at 2.5 A/µs)
VIN = 12 V
L = 4.7 µH
50 µs/DIV
VOUT = 5 V
RSENSE = 10 mΩ
fSW = 400 kHz
Figure 17. Buck Load Step: Low-Power-Mode Entry
4 A to 90 mA at 2.5 A/µs (Moved Here)
100 mV/DIV
VOUT AC-COUPLED
2 A/DIV
IIND
VIN = 12 V
LÄ = 4.7 µH
50 µs/DIV
VOUT = 5 V
RSENSE = 10 mΩ
fSW = 400 kHz
Figure 18. Buck Load Step: Low-Power-Mode Exit
90 mA to 4 A at 2.5 A/µs (Moved Here)
9 Power Supply Recommendations
The TPS4335x-Q1 devices operate over an input voltage supply range between 4 V and 40 V. This input must
be well regulated, and if the power source is located more than a few inches from the TPS4335x-Q1 devices,
bulk capacitance and bypass capacitors may be required at the power supply input.
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10 Layout
10.1 Layout Guidelines
This section lists the grounding and PCB circuit layout considerations.
10.1.1 Buck Converter
1. Connect the drain of SWAH and SWBH MOSFETs together with the positive terminal of the input capacitor
CIN. The trace length between these terminals should be short.
2. Connect a local decoupling capacitor between the drain of SWxH and source of SWxL.
3. The Kelvin-current sensing for the shunt resistor should have traces with minimum spacing, routed in parallel
with each other. Place any filtering capacitors for noise near the IC pins.
4. The resistor divider for sensing output voltage connects between the positive terminal of the respective
output capacitor and COUTA or COUTB and the IC signal ground. Do not locate these components and their
traces near any switching nodes or high-current traces.
10.1.2 Other Considerations
1. Short PGNDx and AGND to the thermal pad. Use a star ground configuration if there is no ground plane
present in the system. Use tie-ins for the EXTSUP capacitor, compensation-network ground, and voltagesense feedback-ground networks to this star ground.
2. Connect a compensation network between the compensation pins and IC signal ground. Connect the
oscillator resistor (frequency setting) between the RT pin and IC signal ground. Do not locate these sensitive
circuits near the dv/dt nodes; these include the gate-drive outputs and phase pins.
3. Reduce the surface area of the high-current-carrying loops to a minimum by ensuring optimal component
placement. Ensure the bypass capacitors are located as close as possible to their respective power and
ground pins.
10.2 Layout Example
POWER
INPUT
Power Lines
Connection to GND Plane of PCB through vias
Connection to top/bottom of PCB through vias
Voltage Rail Outputs
VIN
VBAT
EXTSUP
NC
NC
GC2
VREG
CBA
CBB
GA1
GB1
PHA
PHB
GB2
GA2
PGNDB
PGNDA
SA1
SB1
SA2
SB2
FBB
FBA
COMPB
COMPA
SSA
SSB
PGA
PGB
ENA
AGND
RT
ENB
NC
AGND
Microcontroller
VBUCKB
VBUCKA
NC
Exposed Pad
connected to GND
Plane
DLYAB
SYNC
Figure 19. TPS4335x-Q1 Layout Example
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11 Device and Documentation Support
11.1 Device Support
11.1.1 Third-Party Products Disclaimer
TI'S PUBLICATION OF INFORMATION REGARDING THIRD-PARTY PRODUCTS OR SERVICES DOES NOT
CONSTITUTE AN ENDORSEMENT REGARDING THE SUITABILITY OF SUCH PRODUCTS OR SERVICES
OR A WARRANTY, REPRESENTATION OR ENDORSEMENT OF SUCH PRODUCTS OR SERVICES, EITHER
ALONE OR IN COMBINATION WITH ANY TI PRODUCT OR SERVICE.
11.2 Related Links
The table below lists quick access links. Categories include technical documents, support and community
resources, tools and software, and quick access to sample or buy.
Table 5. Related Links
PARTS
PRODUCT FOLDER
SAMPLE & BUY
TECHNICAL
DOCUMENTS
TOOLS &
SOFTWARE
SUPPORT &
COMMUNITY
TPS43350-Q1
Click here
Click here
Click here
Click here
Click here
TPS43351-Q1
Click here
Click here
Click here
Click here
Click here
11.3 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper
right corner, click on Alert me to register and receive a weekly digest of any product information that has
changed. For change details, review the revision history included in any revised document.
11.4 Community Resources
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
11.5 Trademarks
PowerPAD, E2E are trademarks of Texas Instruments.
All other trademarks are the property of their respective owners.
11.6 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
11.7 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
12 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
(3)
Device Marking
(4/5)
(6)
TPS43350QDAPRQ1
ACTIVE
HTSSOP
DAP
38
2000
RoHS & Green
NIPDAU
Level-3-260C-168 HR
-40 to 125
TPS43350Q1
TPS43351QDAPRQ1
ACTIVE
HTSSOP
DAP
38
2000
RoHS & Green
NIPDAU
Level-3-260C-168 HR
-40 to 125
TPS43351Q1
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of
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