TPS562207
TPS562207
SLUSDR7B – JANUARY 2020 – REVISED
APRIL 2021
SLUSDR7B – JANUARY 2020 – REVISED APRIL 2021
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TPS562207 4.3-V to 17-V Input, 2-A Synchronous Buck Converter in SOT563
1 Features
3 Description
•
•
TPS562207 is a simple, easy-to-use, 2-A
synchronous buck converter in a SOT563 package.
•
•
•
•
•
•
•
•
•
•
•
2-A converter integrated 140-mΩ and 84-mΩ FETs
D-CAP2™ mode control with fast transient
response
Input voltage range: 4.3 V to 17 V
Output voltage range: 0.804 V to 7 V
Forced continuous conduction mode
580-kHz switching frequency
Low shutdown current less than 3 µA
2% feedback voltage accuracy (25 °C)
Support pre-bias function
Cycle-by-cycle over current limit
Hiccup-mode over current protection
Non-latch UVP and TSD protections
Fixed soft start: 1.2 ms
2 Applications
•
•
•
•
•
Digital TV power supply
Smart speaker
Wired networking
Digital set top box (STB)
Surveillance
The device is optimized to operate with minimum
external component counts and also optimized to
achieve low standby current.
This switch mode power supply (SMPS) device
employs D-CAP2 mode control providing a
fast transient response and supporting both lowequivalent series resistance (ESR) output capacitors
such as specialty polymer and ultra-low ESR
ceramic capacitors with no external compensation
components.
TPS562207 operates in Forced Continuous
Conduction Mode (FCCM), which maintains fixed
switching frequency and output voltage ripple is very
small. TPS562207 is available in a 6-pin 1.6-mm ×
1.6-mm SOT563 (DRL) package, and specified from a
–40°C to 125°C junction temperature.
Device Information
PART NUMBER
TPS562207
(1)
CIN
90%
FB 6
VIN
BODY SIZE (NOM)
1.60 mm × 1.60 mm
100%
VOUT
80%
70%
2
EN
SW
5
EN
Efficiency
VOUT
1
DRL (6)
For all available packages, see the orderable addendum at
the end of the data sheet.
TPS562207
VIN
PACKAGE(1)
60%
50%
40%
30%
COUT
Vout = 1.05 V
Vout = 3.3 V
Vout = 5 V
20%
3
GND
BST
4
10%
0
0.001
0.01
0.1
Iload (A)
1
2
Eff
TPS562207 Efficiency
Copyright © 2019, Texas Instruments Incorporated
Simplified Schematic
An©IMPORTANT
NOTICEIncorporated
at the end of this data sheet addresses availability, warranty, changes, use in
safety-critical
applications,
Copyright
2021 Texas Instruments
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intellectual property matters and other important disclaimers. PRODUCTION DATA.
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Table of Contents
1 Features............................................................................1
2 Applications..................................................................... 1
3 Description.......................................................................1
4 Revision History.............................................................. 2
5 Pin Configuration and Functions...................................3
6 Specifications.................................................................. 4
6.1 Absolute Maximum Ratings........................................ 4
6.2 ESD Ratings............................................................... 4
6.3 Recommended Operating Conditions.........................4
6.4 Thermal Information....................................................4
6.5 Electrical Characteristics.............................................6
6.6 Typical Characteristics................................................ 7
7 Detailed Description......................................................10
7.1 Overview................................................................... 10
7.2 Functional Block Diagram......................................... 10
7.3 Feature Description...................................................10
7.4 Device Functional Modes..........................................11
8 Application and Implementation.................................. 12
8.1 Application Information............................................. 12
8.2 Typical Application.................................................... 12
9 Layout.............................................................................17
9.1 Layout Guidelines..................................................... 17
9.2 Layout Example........................................................ 17
10 Device and Documentation Support..........................18
10.1 Receiving Notification of Documentation Updates..18
10.2 Support Resources................................................. 18
10.3 Trademarks............................................................. 18
10.4 Electrostatic Discharge Caution..............................18
10.5 Glossary..................................................................18
11 Mechanical, Packaging, and Orderable
Information.................................................................... 18
4 Revision History
Changes from Revision A (June 2020) to Revision B (April 2021)
Page
• Updated the numbering format for tables, figures, and cross-references throughout the document. ................1
Changes from Revision * (January 2020) to Revision A (June 2020)
Page
• Changed marketing status from Advance Information to initial release. ............................................................1
2
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5 Pin Configuration and Functions
VIN
1
6
FB
SW
2
5
EN
GND
3
4
BST
Figure 5-1. DRL Package 6-Pin SOT563 Top View
Table 5-1. Pin Functions
PIN
NAME
NO.
I/O
DESCRIPTION
VIN
1
I
Input voltage supply pin.
SW
2
O
Switch node connection between high-side NFET and low-side NFET.
GND
3
—
Ground pin Source terminal of low-side power NFET as well as the ground terminal for
controller circuit. Connect sensitive FB to this GND at a single point.
BST
4
O
Supply input for the high-side NFET gate drive circuit. Connect 0.1 uF capacitor between
BST and SW pin.
EN
5
I
Enable input control. Active high and must be pulled up to enable the device.
FB
6
I
Converter feedback input. Connect to output voltage with feedback resistor divider.
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6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)(1)
Input voltage
MIN
MAX
UNIT
VIN, EN
–0.3
19
V
BST
–0.3
25
V
BST (10 ns transient)
–0.3
27
V
BST (vs SW)
–0.3
6.5
V
FB
–0.3
6.5
V
–2
19
V
–3.5
21
V
SW
SW (10 ns transient)
Operating junction temperature, TJ
–40
150
°C
Storage temperature, Tstg
–55
150
°C
(1)
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress
ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under
Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device
reliability.
6.2 ESD Ratings
VALUE
Human-body model (HBM), per ANSI/ESDA/JEDEC
V(ESD)
(1)
(2)
Electrostatic discharge
JS-001(1)
UNIT
±2000
Charged-device model (CDM), per JEDEC specification JESD22C101(2)
V
±500
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
6.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MIN
VIN
Supply input voltage range
VI
Input voltage range
TJ
NOM
MAX
4.3
17
BST
–0.1
23
BST (10 ns transient)
–0.1
26
BST (vs SW)
–0.1
6
EN
–0.1
17
FB
–0.1
5.5
SW
–1.8
17
SW (10 ns transient)
–3.5
20
–40
125
Operating junction temperature
UNIT
V
V
°C
6.4 Thermal Information
TPS562207
THERMAL METRIC(1)
DRL
UNIT
6 PINS
RθJA
4
Junction-to-ambient thermal resistance
board(2)
141.0
°C/W
RθJA _effective
Junction-to-ambient thermal resistance with TI EVM
75
°C/W
RθJC(top)
Junction-to-case (top) thermal resistance
42.0
°C/W
RθJB
Junction-to-board thermal resistance
25.5
°C/W
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TPS562207
THERMAL METRIC(1)
DRL
UNIT
6 PINS
ψJT
Junction-to-top characterization parameter
1.0
°C/W
ψJB
Junction-to-board characterization parameter
25.3
°C/W
(1)
(2)
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
This RθJA_effective is tested on TPS562207EVM board(2 layer, copper thickness is 2 OZ) at VIN = 12V, VOUT = 5V, IOUT = 2A , TA =
25oC.
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6.5 Electrical Characteristics
TJ = –40°C to 125°C, VIN = 12 V (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
590
750
µA
1
3
µA
1.35
1.6
V
SUPPLY CURRENT
IVIN
Operating – non-switching
supply current
VIN current, EN = 5 V, VFB = 1 V
IVINSDN
Shutdown supply current
VIN current, EN = 0 V
LOGIC THRESHOLD
VENH
EN high-level input voltage
EN
VENL
EN low-level input voltage
EN
0.8
1.05
REN
EN pin resistance to GND
VEN = 12 V
225
400
788
V
900
kΩ
804
820
mV
0
±0.1
µA
VFB VOLTAGE AND DISCHARGE RESISTANCE
VFBTH
VFB threshold voltage
TA = 25°C
IFB
VFB input current
VFB = 1 V
RDS(on)h
High-side switch resistance
TA = 25°C, VBST – SW = 5.5 V
RDS(on)l
Low-side switch resistance
TA = 25°C
MOSFET
140
mΩ
84
mΩ
CURRENT LIMIT
Iocl_l_source
Low side FET source current
limit
INocl_l_sink
Low side FET sink current
limit
2.24
3.1
4
1.1
A
A
THERMAL SHUTDOWN
Thermal shutdown
threshold(1)
TSDN
Shutdown temperature
160
°C
Hysteresis
25
Minimum off time
VFB = 0.5 V
220
Soft-start time
Internal soft-start time, Test Vout from 10% to 90%
1.2
ms
Switching frequency
VO = 1.05 V
580
kHz
ON-TIME TIMER CONTROL
tOFF(MIN)
310
ns
SOFT START
Tss
FREQUENCY
Fsw
OUTPUT UNDERVOLTAGE
VUVP
Output UVP threshold
Hiccup detect (H > L)
65%
THICCUP_WAIT Hiccup on time
2.2
ms
THICCUP_RE
18
ms
Hiccup time before restart
UVLO
Wake up VIN voltage
UVLO
UVLO threshold
Shutdown VIN voltage
Hysteresis VIN voltage
(1)
6
4.0
3.3
3.6
4.3
V
0.4
Not production tested.
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6.6 Typical Characteristics
VIN = 12 V (unless otherwise noted)
811
0.7
809
Buck Quiescent Current (mA)
0.65
FB Voltage (mV)
807
0.6
0.55
0.5
805
803
801
799
0.45
797
0.4
-50
-20
10
40
70
Junction Temperature (oC)
100
795
-50
130
1.18
100
130
Vref
1.45
1.15
1.42
EN On Threshold (V)
EN Off Threshold (V)
10
40
70
Junction Temperature (oC)
Figure 6-2. FB Voltage vs Junction Temperature
Figure 6-1. Supply Current vs Junction
Temperature
1.12
1.09
1.06
1.39
1.36
1.33
1.03
1
-50
-20
10
40
70
Junction Temperature (oC)
100
1.3
-50
130
-20
ENLt
Figure 6-3. EN Off threshold Voltage vs Junction
Temperature
10
40
70
Junction Temperature (oC)
100
130
ENHt
Figure 6-4. EN On threshold Voltage vs Junction
Temperature
260
150
230
130
Low Side Rdson (m:)
High Side Rdson (m:)
-20
IQ
200
170
140
110
90
70
110
80
-50
-20
10
40
70
Junction Temperature (oC)
100
130
50
-50
HSR
Figure 6-5. High-Side Rds-On vs Junction
Temperature
-20
10
40
70
Junction Temperature (oC)
100
130
LSR
Figure 6-6. Low-Side Rds-On vs Junction
Temperature
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640
640
600
600
Switching Frequency (kHz)
Switching Frequency(kHz)
SLUSDR7B – JANUARY 2020 – REVISED APRIL 2021
560
520
Vout = 1.05 V
Vout = 3.3 V
Vout = 5 V
480
440
6
8
10
12
Vin (V)
14
16
18
0
100%
100%
90%
90%
80%
80%
70%
70%
60%
60%
50%
40%
30%
10%
0
0.001
0.01
0.1
Output Current (A)
1
0
0.001
2
70%
60%
60%
Efficiency
70%
50%
40%
0.1
Freq
1
2
EffV
50%
40%
30%
Vin = 5 V
Vin = 9 V
Vin = 12 V
Vin = 17 V
Vin = 5 V
Vin = 9 V
Vin = 12 V
Vin = 17 V
20%
10%
2
0
0.001
EffV
Figure 6-11. VOUT = 1.5 V Efficiency, L = 2.2µH
2
Figure 6-10. VOUT = 1.05 V Efficiency, L = 2.2 µH
80%
1
1.8
I_load (A)
80%
0.1
Output Current (A)
0.01
EffV
90%
0.01
1.6
Vin = 5 (V)
Vin = 9 (V)
Vin = 12 (V)
Vin = 17 (V)
10%
100%
0
0.001
1.4
40%
90%
10%
0.8
1
1.2
Iout_set (A)
50%
100%
20%
0.6
20%
Figure 6-9. VOUT = 0.95 V Efficiency, L = 2.2µH
30%
0.4
30%
Vin = 5 V
Vin = 9 V
Vin = 12 V
Vin = 17 V
20%
0.2
Figure 6-8. Switching Frequency vs Output Current
Efficiency
Efficiency
Vout = 1.05 V
Vout = 3.3 V
Vout = 5 V
480
Freq
Figure 6-7. Switching Frequency vs Input Voltage
Efficiency
520
440
4
8
560
0.01
0.1
Output Current (A)
1
2
EffV
Figure 6-12. VOUT =1.8 V Efficiency, L = 2.2µH
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100%
100%
90%
90%
80%
80%
70%
70%
60%
60%
Efficiency
Efficiency
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50%
40%
30%
10%
0
0.001
0.01
0.1
1
I_load (A)
40%
30%
Vin = 5 (V)
Vin = 9 (V)
Vin = 12 (V)
Vin = 17 (V)
20%
50%
10%
2
0
0.001
0.01
0.1
1
I_load (A)
EffV
Figure 6-13. VOUT = 3.3 V Efficiency, L = 3.3 µH
Vin = 9 (V)
Vin = 12 (V)
Vin = 17 (V)
20%
2
EffV
Figure 6-14. VOUT = 5 V Efficiency, L = 4.7 µH
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7 Detailed Description
7.1 Overview
TPS562207 is a 2-A synchronous buck converter. The proprietary D-CAP2 mode control supports low ESR
output capacitors such as specialty polymer capacitors and multi-layer ceramic capacitors without complex
external compensation circuits. The fast transient response of D-CAP2 mode control can reduce the output
capacitance required to meet a specific level of performance.
7.2 Functional Block Diagram
EN
5
VUVP
+
UVP
±
Hiccup
Control Logic
1
VIN
4
BST
2
SW
3
GND
VREG5
Regulator
UVLO
FB
6
Voltage
Reference
Ref
Soft Start
SS
±
+
+
PWM
HS
Turn-On
One Shot
XCON
VREG5
TSD
OCL
Threshold
NOCL
Threshold
LS
±
OCL
+
+
NOC
±
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7.3 Feature Description
7.3.1 Adaptive On-Time Control and PWM Operation
The main control loop of the TPS562207 is adaptive on-time pulse width modulation (PWM) controller that
supports a proprietary D-CAP2 mode control. The D-CAP2 mode control combines adaptive on-time control with
an internal compensation circuit for pseudo-fixed frequency and low external component count configuration with
both low-ESR and ceramic output capacitors. It is stable even with virtually no ripple at the output.
At the beginning of each cycle, the high-side MOSFET is turned on. This MOSFET is turned off after internal one
shot timer expires. This one shot duration is set proportional to the converter input voltage, VIN, and inversely
proportional to the output voltage, VO, to maintain a pseudo-fixed frequency over the input voltage range, hence
it is called adaptive on-time control. The one-shot timer is reset and the high-side MOSFET is turned on again
when the feedback voltage falls below the reference voltage. An internal ramp is added to reference voltage to
simulate output ripple, eliminating the need for ESR induced output ripple from D-CAP2 mode control.
10
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7.3.2 Soft Start and Pre-Biased Soft Start
TPS562207 have an internal 1.2-ms soft-start. When the EN pin becomes high, the internal soft-start function
begins ramping up the reference voltage to the PWM comparator.
If the output capacitor is pre-biased at startup, the devices initiate switching and start ramping up only after
the internal reference voltage becomes greater than the feedback voltage VFB. This scheme ensures that the
converters ramp up smoothly into regulation point.
7.3.3 Current Protection
The output over-current limit (OCL) is implemented using a cycle-by-cycle valley detect control circuit. The
switch current is monitored during the OFF state by measuring the low-side FET drain to source voltage.
This voltage is proportional to the switch current. To improve accuracy, the voltage sensing is temperature
compensated.
During the on time of the high-side FET switch, the switch current increases at a linear rate determined by Vin,
Vout, the on-time and the output inductor value. During the on time of the low-side FET switch, this current
decreases linearly. The average value of the switch current is the load current Iout. If the monitored current is
above the OCL level, the converter maintains low-side FET on and delays the creation of a new set pulse,
even the voltage feedback loop requires one, until the current level becomes OCL level or lower. In subsequent
switching cycles, the on-time is set to a fixed value and the current is monitored in the same manner.
There are some important considerations for this type of over-current protection. The load current is higher than
the over-current threshold by one half of the peak-to-peak inductor ripple current. Also, when the current is being
limited, the output voltage tends to fall as the demanded load current may be higher than the current available
from the converter. This may cause the output voltage to fall. When the FB voltage falls below the UVP threshold
voltage, the UVP comparator detects it. And then, the device will shut down after the UVP delay time (typically
24 µs) and re-start after the hiccup time (typically 18 ms).
When the over current condition is removed, the output voltage returns to the regulated value.
TPS562207 works in Forced Continuous Conduction Mode (FCCM). To support light load operation, the current
flowing through low-side FET is allowed to be negative, which means the current flow from drain to source of
low-side FET. This negative current is compared with low-side FET sink current limit to prevent device from
being over-current damaged. Once the sink current cross limit, the low-side FET will turn off and the high-side
FET will turn on to limit the negative current from overcurrent.
7.3.4 Undervoltage Lockout (UVLO) Protection
UVLO protection monitors the internal regulator voltage. When the voltage is lower than UVLO threshold voltage,
the device is shut off. This protection is non-latching.
7.3.5 Thermal Shutdown
The device monitors the temperature of itself. If the temperature exceeds the threshold value (typically 160°C),
the device is shut off. This is a non-latch protection. The device will resume normal working once the
temperature return below the recovery threshold value (typically 135°C).
7.4 Device Functional Modes
7.4.1 Normal Operation
When the input voltage is above the UVLO threshold and the EN voltage is above the enable threshold,
TPS562207 can operate in their normal switching modes. In continuous conduction mode (CCM), TPS562207
operates at a quasi-fixed frequency of 580 kHz.
7.4.2 Standby Operation
TPS562207 can be placed in standby mode by asserting the EN pin low.
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8 Application and Implementation
Note
Information in the following applications sections is not part of the TI component specification,
and TI does not warrant its accuracy or completeness. TI’s customers are responsible for
determining suitability of components for their purposes, as well as validating and testing their design
implementation to confirm system functionality.
8.1 Application Information
The devices are typical buck DC-DC converters. It typically uses to convert a higher dc voltage to a lower dc
voltage with a maximum available output current of 2 A. The following design procedure can be used to select
component values for TPS562207. Alternately, the WEBENCH® software may be used to generate a complete
design. The WEBENCH software uses an iterative design procedure and accesses a comprehensive database
of components when generating a design. This section presents a simplified discussion of the design process.
8.2 Typical Application
The application schematic in Figure 8-1 was developed to meet the previous requirements. This circuit is
available as the evaluation module (EVM). The sections provide the design procedure.
Figure 8-1 shows the TPS562207 4.3-V to 17-V input, 1.05-V output converter schematics.
VIN = 4.3 V to 17 V
VIN
C1
10 F
C2
10 F
VOUT
C3
0.1 F
R1 3 k
R2
10 k
1
L1
VOUT = 1.05 V/3A
VOUT
2
2.2 H
C9
22 F
C8
22 F
3
VIN
FB
SW
EN
GND
BST
1 C4
6
1
Not Installed
R3 10 k
5
VIN
4
C7 0.1 F
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Figure 8-1. 1.05-V/2-A Reference Design
12
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8.2.1 Design Requirements
Table 8-1 shows the design parameters for this application.
Table 8-1. Design Parameters
PARAMETER
EXAMPLE VALUE
Input voltage range
4.3 to 17 V
Output voltage
1.05 V
Transient response, load step: 10% ~
90% of full loading
ΔVout = ±5%
Input ripple voltage
200 mV
Output ripple voltage
20 mV
Output current rating
2A
Operating frequency
580 kHz
8.2.2 Detailed Design Procedure
8.2.2.1 Output Voltage Resistors Selection
The output voltage is set with a resistor divider from the output node to the FB pin. TI recommends to use 1%
tolerance or better divider resistors. Start by using Equation 1 to calculate VOUT.
To improve efficiency at very light loads consider using larger value resistors, too high of resistance will be more
susceptible to noise and voltage errors from the FB input current will be more noticeable.
Vout=0.804 x (1 + RFBT/RFBB)
(1)
8.2.2.2 Output Filter Selection
The LC filter used as the output filter has double pole at:
fP
1
2S LOUT u COUT
(2)
At low frequencies, the overall loop gain is set by the output set-point resistor divider network and the internal
gain of the device. The low frequency phase is 180°. At the output filter pole frequency, the gain rolls off at a
–40 dB per decade rate and the phase drops rapidly. D-CAP2 introduces a high frequency zero that reduces
the gain roll off to –20 dB per decade and increases the phase to 90° one decade above the zero frequency.
The inductor and capacitor for the output filter must be selected so that the double pole of Equation 2 is located
below the high frequency zero but close enough that the phase boost provided be the high frequency zero
provides adequate phase margin for a stable circuit. To meet this requirement use the values recommended in
Table 8-2.
Table 8-2. Recommended Component Values
C8 + C9 (µF)
OUTPUT
VOLTAGE (V)
R1 (kΩ)
R2 (kΩ)
TYP L1
(µH)
Min
Typ
Max
0.85
0.55
10.0
2.2
20
44
110
-
0.9
1.2
10.0
2.2
20
44
110
-
1
2.4
10.0
2.2
20
44
110
-
1.05
3
10.0
2.2
20
44
110
-
1.2
4.9
10.0
2.2
20
44
110
-
CFF (pF)
1.5
8.6
10.0
2.2
20
44
110
-
1.8
12.3
10.0
2.2
20
44
110
-
2.5
21
10.0
3.3
20
44
110
-
3.3
31
10.0
3.3
20
44
110
10-220
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Table 8-2. Recommended Component Values (continued)
OUTPUT
VOLTAGE (V)
C8 + C9 (µF)
R1 (kΩ)
R2 (kΩ)
TYP L1
(µH)
Min
Typ
Max
5
52
10.0
4.7
20
44
110
10-220
6.5
70.5
10.0
4.7
20
44
110
10-220
CFF (pF)
The inductor peak-to-peak ripple current, peak current and RMS current are calculated using Equation 3,
Equation 4, and Equation 5. The inductor saturation current rating must be greater than the calculated peak
current and the RMS or heating current rating must be greater than the calculated RMS current.
IlP
P
IlPEAK
ILO(RMS)
VIN(MAX) VOUT
VOUT
u
VIN(MAX)
LO u fSW
IO
(3)
IlP P
2
IO2
(4)
1
IlP
12
2
P
(5)
For this design example, the calculated peak current is 2.35 A and the calculated RMS current is 2.01 A. The
inductor used is a WE 74437349022 with an RMS current rating of 7.5 A.
The capacitor value and ESR determines the amount of output voltage ripple. TPS562207 is intended for use
with ceramic or other low ESR capacitors. Recommended values range from 20 µF to 110 µF. Use Equation 6 to
determine the required RMS current rating for the output capacitor.
ICO(RMS)
VOUT u VIN
VOUT
12 u VIN u LO u fSW
(6)
For this design two MuRata GRM21BR61A226ME44L 22-µF output capacitors are used. The typical ESR is 2
mΩ each. The calculated RMS current is 0.286 A and each output capacitor is rated for 4 A.
8.2.2.3 Input Capacitor Selection
The TPS562207 require an input decoupling capacitor and a bulk capacitor is needed depending on the
application. TI recommends a ceramic capacitor over 10 µF for the decoupling capacitor. An additional 0.1-µF
capacitor (C3) from pin 1 to ground is necessary to provide additional high frequency filtering. The capacitor
voltage rating needs to be greater than the maximum input voltage.
8.2.2.4 Bootstrap Capacitor Selection
A typical 0.1-µF ceramic capacitor must be connected between the BST to SW pin for proper operation. TI
recommends to use a ceramic capacitor.
14
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1.07
1.07
1.06
1.06
Output Voltage (V)
Output Voltage (V)
8.2.3 Application Curves
1.05
1.04
1.05
1.04
1.03
1.03
0
0.4
0.8
1.2
Output Current (A)
1.6
2
4
6
Load
Figure 8-2. Load Regulation with different loading
8
10
12
Input Voltage (V)
14
16
18
Load
Figure 8-3. Load Regulation with different input
voltage
Vin = 100 mV/div
Vout = 20 mV/div
SW = 5V/div
SW = 5V/div
Iout = 2A/div
Iout = 2A/div
1us/div
1us/div
Figure 8-4. Input Voltage Ripple
Figure 8-5. Output Voltage Ripple, Iout = 0.2 A
Vout = 20 mV/div
Vout = 500 mV/div
SW = 5V/div
Iout = 2A/div
SW = 5V/div
1us/div
10ms/div
Figure 8-6. Output Voltage Ripple, Iout = 2 A
Figure 8-7. Hiccup, Iout = 5 A
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Vout = 50 mV/div
Vout = 50 mV/div
Iout = 1A/div
Iout = 1A/div
400us/div
400us/div
Figure 8-8. Transient Response, 0.2 to 1.8 A
Figure 8-9. Transient Response, 1 to 2 A
Vin = 5 V/div
Vin = 5 V/div
EN = 2V/div
EN = 5V/div
Vout = 500 mV/div
Vout = 500 mV/div
2ms/div
2ms/div
Figure 8-10. Start Up Relative to VIN
Figure 8-11. Start Up Relative to EN
Vin = 5 V/div
Vin = 5 V/div
EN = 5V/div
EN = 2V/div
Vout = 500 mV/div
Vout = 500 mV/div
16
2ms/div
2ms/div
Figure 8-12. Shutdown Relative to VIN
Figure 8-13. Shutdown Relative to EN
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9 Layout
9.1 Layout Guidelines
1. VIN and GND traces should be as wide as possible to reduce trace impedance. The wide areas are also of
advantage from the view point of heat dissipation.
2. The input capacitor and output capacitor should be placed as close to the device as possible to minimize
trace impedance.
3. Provide sufficient vias for the input capacitor and output capacitor.
4. Keep the SW trace as physically short and wide as practical to minimize radiated emissions.
5. Do not allow switching current to flow under the device.
6. A separate VOUT path should be connected to the upper feedback resistor.
7. Make a Kelvin connection to the GND pin for the feedback path.
8. Voltage feedback loop should be placed away from the high-voltage switching trace, and preferably has
ground shield.
9. The trace of the FB node should be as small as possible to avoid noise coupling.
10. The GND trace between the output capacitor and the GND pin should be as wide as possible to minimize its
trace impedance.
9.2 Layout Example
VIN
GND
CIN
SW
RFBB
VIN
FB
SW
EN
GND
BST
RFBT
EN
Control
CBST
L
VOUT
GND
COUT
VIA (Connected to GND plane at bottom layer)
VIA (Connected to SW)
Figure 9-1. TPS562207 Layout
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10 Device and Documentation Support
10.1 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. Click on
Subscribe to updates to register and receive a weekly digest of any product information that has changed. For
change details, review the revision history included in any revised document.
10.2 Support Resources
TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight
from the experts. Search existing answers or ask your own question to get the quick design help you need.
Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do
not necessarily reflect TI's views; see TI's Terms of Use.
10.3 Trademarks
D-CAP2™ and TI E2E™ are trademarks of Texas Instruments.
WEBENCH® is a registered trademark of Texas Instruments.
All trademarks are the property of their respective owners.
10.4 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled
with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may
be more susceptible to damage because very small parametric changes could cause the device not to meet its published
specifications.
10.5 Glossary
TI Glossary
This glossary lists and explains terms, acronyms, and definitions.
11 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
18
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PACKAGE OPTION ADDENDUM
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PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
(4/5)
(6)
TPS562207DRLR
ACTIVE
SOT-5X3
DRL
6
4000
RoHS & Green
Call TI | SN
Level-1-260C-UNLIM
-40 to 125
2207
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of
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