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TPS56C215
SLVSD05C – MARCH 2016 – REVISED MARCH 2018
TPS56C215 3.8-V to 17-V Input , 12-A Synchronous Step-Down SWIFT™ Converter
1 Features
2 Applications
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1
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Integrated 13.5-mΩ and 4.5-mΩ MOSFETs
Support 12-A Continuous IOUT
4.5-V Start up without External 5.0-V Bias
0.6V +/-1% Reference Voltage across full
temperature range
0.6 V to 5.5 V Output Voltage Range
Supports Ceramic Output Capacitors
D-CAP3™ Control Mode for Fast Transient
Response
Selectable Forced Continuous Conduction Mode
(FCCM) for Tight Output Voltage Ripple or AutoSkipping Eco-mode™ for High Light-Load
Efficiency
Selectable FSW of 400 kHz, 800 kHz and 1.2 MHz
Monotonic Start Up into Pre-biased Outputs
Two Adjustable Current Limit Settings with Hiccup
Re-start
Optional External 5V bias for Enhanced Efficiency
Adjustable Soft Start with a Default 1-ms Soft
Start Time
–40°C to 150°C Operating Junction Temperature
Small 3.5-mm x 3.5-mm HotRod™ QFN Package
Supported at the WEBENCH™ Design Center
•
Server, Cloud-Computing, Storage
Telecom & Networking, Point-of-Load (POL)
IPCs, Factory Automation, PLC, Test
Measurement
High end DTV
3 Description
The TPS56C215 is TI's smallest monolithic 12-A
synchronous buck converter with an adaptive on-time
D-CAP3™ control mode. The device integrates low
RDS(on) power MOSFETs that enable high efficiency
and offers ease-of-use with minimum external
component count for space-conscious power
systems. Competitive features include a very
accurate reference voltage, fast load transient
response, auto-skip mode operation for light load
efficiency, adjustable current limit and no requirement
for external compensation. A forced continuous
conduction mode helps meet tight voltage regulation
accuracy requirements for performance DSPs and
FPGAs. The TPS56C215 is available in a thermally
enhanced 18-pin HotRod™ QFN package and is
designed to operate from –40°C to 150°C junction
temperature.
Device Information(1)
PART NUMBER
PACKAGE
TPS56C215
BODY SIZE (NOM)
VQFN (18)
3.5 mm x 3.5 mm
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
spacer
Typical Application
Efficiency vs Output Current
TPS56C215
VREG5
VIN
PGOOD
MODE
PGOOD
BOOT
LOUT
SW
EN
CSS
90
VREG5
RM_L
SS
COUT
VOUT
RUPPER
FB
AGND PGND
Efficiency(%)
VIN
CIN
95
RM_H
85
80
75
RLOWER
VIN=4.5V,VOUT =1.2V,400kHz
70
VIN =12V, VOUT=1.2V, 400kHz
Copyright © 2016, Texas Instruments Incorporated
VIN =17V, VOUT=1.2V, 400kHz
65
0
1
2
3
4
5
6
7
Output Current(A)
8
9
10
11
12
C001
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
TPS56C215
SLVSD05C – MARCH 2016 – REVISED MARCH 2018
www.ti.com
Table of Contents
1
2
3
4
5
6
7
Features ..................................................................
Applications ...........................................................
Description .............................................................
Revision History.....................................................
Pin Configuration and Functions .........................
Specifications.........................................................
1
1
1
2
3
4
6.1
6.2
6.3
6.4
6.5
6.6
6.7
4
4
4
4
6
7
8
Absolute Maximum Ratings ......................................
ESD Ratings ............................................................
Recommended Operating Conditions.......................
Thermal Information ..................................................
Electrical Characteristics...........................................
Timing Requirements ................................................
Typical Characteristics ..............................................
Detailed Description ............................................ 13
7.1 Overview ................................................................. 13
7.2 Functional Block Diagram ....................................... 14
7.3 Feature Description................................................. 14
7.4 Device Functional Modes........................................ 20
8
Application and Implementation ........................ 21
8.1 Application Information............................................ 21
8.2 Typical Application ................................................. 21
9 Power Supply Recommendations...................... 26
10 Layout................................................................... 27
10.1 Layout Guidelines ................................................. 27
10.2 Layout Example .................................................... 27
11 Device and Documentation Support ................. 30
11.1
11.2
11.3
11.4
11.5
11.6
Device Support ....................................................
Receiving Notification of Documentation Updates
Community Resources..........................................
Trademarks ...........................................................
Electrostatic Discharge Caution ............................
Glossary ................................................................
30
31
31
31
31
31
12 Mechanical, Packaging, and Orderable
Information ........................................................... 31
12.1 Package Marking .................................................. 31
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision B (July 2016) to Revision C
Page
•
Added feature item "4.5-V Start up without External 5.0-V Bias"........................................................................................... 1
•
Changed Ground symbol at pin VREG5 in Typical Application image. ................................................................................ 1
•
Changed from "5% resistors" to "1% resistors" in the MODE Selection description ........................................................... 17
•
Changed Power-Up Sequence image for Figure 27. ........................................................................................................... 17
•
Changed Adjustable VIN Undervoltage Lock Out image for Figure 28. .............................................................................. 18
•
Added Ih term to Equation 5 Definition List ......................................................................................................................... 18
•
Added Package Marking information.................................................................................................................................... 31
Changes from Revision A (March 2016) to Revision B
Page
•
Changed Features From: "Support 14-A Continuous IOUT" To: "Support 12-A Continuous IOUT"........................................... 1
•
Added compnent names to the Typical Application schematic .............................................................................................. 1
•
Deleted IOCL spec for "ILIM+1 option, Valley Current" condition ............................................................................................ 6
•
Changed From: "...up to 14 A" To: "...up to 12 A" in first sentence of Overview section. .................................................... 13
•
Deleted four rows in Mode Pin Resistor Settings table for IOUT of 14 A. .............................................................................. 17
Changes from Original (March 2016) to Revision A
•
2
Page
Added content for full Production data sheet ........................................................................................................................ 1
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SLVSD05C – MARCH 2016 – REVISED MARCH 2018
5 Pin Configuration and Functions
RNN Package
18-Pin VQFN
AGND 12
1 BOOT
VIN 11
2 VIN
13 FB
14 SS
15 EN
16 PGOOD
17 VREG5
18 MODE
18 MODE
TOP VIEW
17 VREG5
16 PGOOD
15 EN
14 SS
13 FB
BOTTOM VIEW
BOOT 1
12 AGND
VIN 2
11 VIN
PGND 10
3 PGND
PGND 3
10 PGND
PGND 9
4 PGND
PGND 4
9 PGND
PGND 8
5 PGND
PGND 5
8 PGND
7
6
6
SW
SW
7
Pin Functions
PIN
I/O
DESCRIPTION
NAME
NO.
BOOT
1
I
Supply input for the gate drive voltage of the high-side MOSFET. Connect the bootstrap capacitor between
BOOT and SW.
2,11
P
Input voltage supply pin for the control circuitry. Connect the input decoupling capacitors between VIN and
PGND.
3, 4, 5,
8, 9, 10
G
Power GND terminal for the controller circuit and the internal circuitry. Connect to AGND with a short trace.
VIN
PGND
SW
6, 7
O
Switch node terminal. Connect the output inductor to this pin.
AGND
12
G
Ground of internal analog circuitry. Connect AGND to PGND plane with a short trace.
FB
13
I
Converter feedback input. Connect to the center tap of the resistor divider between output voltage and
AGND.
SS
14
O
Soft-Start time selection pin. Connecting an external capacitor sets the soft-start time and if no external
capacitor is connected, the converter starts up in 1ms.
EN
15
I
Enable input control, leaving this pin floating enables the converter. It can also be used to adjust the input
UVLO by connecting to the center tap of the resistor divider between VIN and EN.
PGOOD
16
O
Open Drain Power Good Indicator, it is asserted low if output voltage is out of PGOOD threshold,
Overvoltage or if the device is under thermal shutdown, EN shutdown or during soft start.
VREG5
17
I/O
4.7-V internal LDO output which can also be driven externally with a 5V input. This pin supplies voltage to
the internal circuitry and gate driver. Bypass this pin with a 4.7-µF capacitor.
MODE
18
I
Switching Frequency, Current Limit selection and Light load operation mode selection pin. Connect this pin
to a resistor divider from VREG5 and AGND for different MODE options shown in Table 3.
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6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)
Input Voltage
(1)
MIN
MAX
UNIT
VIN
–0.3
20
V
SW
–2
19
V
SW(10 ns transient)
–3
20
V
EN
–0.3
6.5
V
BOOT –SW
–0.3
6.5
V
BOOT
–0.3
25.5
V
SS, MODE, FB
–0.3
6.5
V
VREG5
–0.3
6
V
Output Voltage
PGOOD
–0.3
6.5
V
Output
Current (2)
IOUT
14
A
TJ
Operating junction temperature
–40
150
°C
Tstg
Storage temperature
–55
150
°C
(1)
(2)
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
In order to be consistent with the TI reliability requirement of 100k Power-On-Hours at 105°C junction temperature, the output current
should not exceed 14A continuously under 100% duty operation as to prevent electromigration failure in the solder. Higher junction
temperature or longer power-on hours are achievable at lower than 14A continuos output current.
6.2 ESD Ratings
VALUE
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001
V(ESD)
(1)
(2)
Electrostatic discharge
(1)
UNIT
±2000
Charged-device model (CDM), per JEDEC specification JESD22C101 (2)
V
±500
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
6.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MIN
Input Voltage
NOM
MAX
UNIT
VIN
3.8
17
V
SW
–1.8
17
V
BOOT
–0.1
23.5
V
VREG5
–0.1
5.2
V
0
12
A
-40
150
°C
Output Current
ILOAD
Operating junction
temperature
TJ
6.4 Thermal Information
THERMAL METRIC (1)
RNN PACKAGE
18 PINS
UNIT
RθJA
Junction-to-ambient thermal resistance
29.5
°C/W
RθJC(top)
Junction-to-case (top) thermal resistance
17.0
°C/W
RθJB
Junction-to-board thermal resistance
8.6
°C/W
ψJT
Junction-to-top characterization parameter
0.4
°C/W
(1)
4
For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.
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Thermal Information (continued)
THERMAL METRIC (1)
RNN PACKAGE
18 PINS
UNIT
ψJB
Junction-to-board characterization parameter
8.6
°C/W
RθJC(bot)
Junction-to-case (bottom) thermal resistance
0.5
°C/W
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6.5 Electrical Characteristics
TJ = –40°C to 150°C, VIN=12V (unless otherwise noted)
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNIT
600
700
µA
SUPPLY CURRENT
IIN
VIN supply current
TJ = 25°C, VEN=5 V, non switching
IVINSDN
VIN shutdown current
TJ = 25°C, VEN=0 V
7
µA
LOGIC THRESHOLD
VENH
EN H-level threshold voltage
1.175
1.225
1.3
V
VENL
EN L-level threshold voltage
1.025
1.104
1.15
V
VENHYS
0.121
IENp1
EN pull-up current
IENp2
V
VEN = 1.0 V
0.35
1.91
2.95
µA
VEN = 1.3 V
3
4.197
5.5
µA
FEEDBACK VOLTAGE
TJ = 25°C
VFB
FB voltage
598
600
602
mV
597.5
600
602.5
mV
TJ = –40°C to 85°C
594
600
602.5
mV
TJ = –40°C to 150°C
594
600
606
mV
TJ = 0°C to 85°C
LDO VOLTAGE
VREG5
LDO Output voltage
TJ = –40°C to 150°C
4.58
4.7
4.83
V
ILIM5
LDO Output Current limit
TJ = –40°C to 150°C
100
150
200
mA
RDS(on)H
High side switch resistance
TJ = 25°C, VVREG5 = 4.7 V
13.5
mΩ
RDS(on)L
Low side switch resistance
TJ = 25°C, VVREG5 = 4.7 V
4.5
mΩ
Soft start charge current
TJ = -40°C to 150°C
MOSFET
SOFT START
Iss
4.9
6
7.1
µA
ILIM-1 option, Valley Current
9.775
11.5
13.225
A
ILIM option, Valley Current
11.73
13.8
15.87
A
CURRENT LIMIT
IOCL
Current Limit (Low side sourcing)
Current Limit (Low side negative)
Valley Current
4
A
POWER GOOD
VFB falling (fault)
VPGOODTH
PGOOD threshold
84%
VFB rising (good)
93%
VFB rising (fault)
116%
VFB falling (good)
107%
OUTPUT UNDERVOLTAGE AND OVERVOLTAGE PROTECTION
VOVP
Output OVP threshold
OVP detect
VUVP
Output UVP threshold
Hiccup detect
121% x
VFB
68% x
VFB
THERMAL SHUTDOWN
TSDN
Thermal shutdown threshold
TSDN
VREG5 thermal shutdown threshold
VREG5
Shutdown temperature
160
°C
15
°C
171
°C
18
°C
VREG5 rising voltage
4.3
V
VREG5 falling voltage
3.57
V
VREG5 hysteresis
730
mV
Hysteresis
Shutdown temperature
Hysteresis
UVLO
UVLO
6
UVLO threshold
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Electrical Characteristics (continued)
TJ = –40°C to 150°C, VIN=12V (unless otherwise noted)
PARAMETER
UVLO,
UVLO threshold, VREG5=4.7V
VREG5=4.7V
CONDITIONS
MIN
TYP
VIN rising voltage, VREG5=4.7V
3.32
VIN falling voltage, VREG5=4.7V
3.26
VIN hysteresis, VREG5=4.7V
MAX
UNIT
V
V
60
mV
6.6 Timing Requirements
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNIT
310
340
380
ns
ON-TIME TIMER CONTROL
tON
SW On Time
VIN = 12 V, VOUT=3.3 V, FSW = 800 kHz
tON min
SW Minimum on time
VIN = 17 V, VOUT=0.6 V, FSW= 1200 kHz
tOFF
SW Minimum off time
25°C, VFB=0.5 V
54
ns
310
ns
SOFT START
tSS
Soft start time
Internal soft-start time
1.045
ms
OUTPUT UNDERVOLTAGE AND OVERVOLTAGE PROTECTION
tUVPDEL
Output Hiccup delay relative to SS time
UVP detect
1
cycle
tUVPEN
Output Hiccup enable delay relative to
SS time
UVP detect
7
cycle
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1000
20
900
18
Shutdown Current(µA)
Non-Switching Operating Quiscent Current - µA
6.7 Typical Characteristics
800
700
600
500
400
16
14
12
10
8
6
4
300
0
-50
0
50
100
150
TJ - Junction Temperature(ƒC)
±50
0
50
100
150
TJ - Junction Temperature(ƒC)
C002
Figure 1. Quiescent Current vs Temperature
C003
Figure 2. Shutdown Current vs Temperature
30
0.606
0.604
RDS(on) - On Resistance - m
VFB - Feedback Voltage(V)
VIN =12V
2
VIN =12V
200
0.602
0.6
0.598
0.596
VIN =12V
0.594
25
20
15
VIN =12V
10
-50
0
50
100
TJ - Junction Temperature(ƒC)
150
±50
0
50
100
150
TJ - Junction Temperature(ƒC)
C004
Figure 3. Feedback Voltage vs Temperature
C005
Figure 4. High-side RDS(on) vs Temperature
8
10
Soft-Start Charge Current(µA)
RDS(ON) - On Resistance - m
9
8
7
6
5
4
3
2
6
5
VIN =12V
1
VIN =12V
0
4
-50
0
50
100
TJ - Junction Temperature(ƒC)
150
±50
0
50
100
TJ - Junction Temperature(ƒC)
C006
Figure 5. Low-side RDS(on) vs Temperature
8
7
150
C008
Figure 6. Soft-Start Charge Current vs Temperature
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Typical Characteristics (continued)
6
Enable Pin Pull-Up Current(µA)
Enable Pin Pull-Up Current(uA)
3
2.5
2
1.5
5.5
5
4.5
4
3.5
VIN =12V
1
0
±50
50
100
150
TJ - Junction Temperature(ƒC)
VIN =12V
3
0
±50
50
100
150
TJ - Junction Temperature(ƒC)
C009
Figure 7. Enable Pull-Up Current, VEN =1.0V
C010
Figure 8. Enable Pull-Up Current, VEN =1.3V
120
18
Low Side Valley Current Limit(A)
ILIM option
PGOOD Threshold(%)
115
110
105
VFB
VFB
VFB
VFB
100
95
rising
falling
rising
falling
90
85
80
17
ILIM-1 option
16
15
14
13
12
11
10
1
2
3
4
5
6
7
8
9
10
TJ - Junction Temperature(ƒC)
50
100
150
TJ - Junction Temperature(ƒC)
Figure 9. PGOOD Threshold vs Temperature
C012
Figure 10. Current Limit vs Temperature
100
100
90
90
80
80
70
70
Efficiency(%)
Efficiency(%)
0
±50
C011
60
50
40
30
60
50
40
30
20
VOUT =1.2V,FSW = 400kHz
20
10
VOUT =1.2V,FSW = 800kHz
10
VOUT =1.2V,FSW = 1200kHz
0
0
0
0
Output Current(A)
1
10
0
0.001
0.01
0.1
1
Output Current(A)
C013
Figure 11. Efficiency with Internal VREG5 = 4.7V, VIN = 12V
VOUT=1.2V,FSW= 400kHz
VOUT =1.2V,FSW= 800kHz
VOUT=1.2V,FSW = 1200kHz
10
C014
Figure 12. Efficiency with External VREG5 = 5V, VIN=12V
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Typical Characteristics (continued)
90
80
80
70
70
Efficiency(%)
Efficiency(%)
100
90
60
50
40
30
50
40
30
20
VIN =12V,VOUT=1.2V
20
VIN =12V,VOUT=1.2V
10
VIN =12V,VOUT=3.3V
10
VIN =12V,VOUT=3.3V
VIN =12V,VOUT =5.5V
0
0.001
0.01
0.1
1
VIN =12V,VOUT=5.5V
0
0
10
Output Current(A)
1
2
3
4
90
90
80
80
70
70
Efficiency(%)
100
50
40
6
7
8
9
10
11
12
C016
Figure 14. Efficiency, Mode = FCCM, FSW = 400kHz
100
60
5
Output Current(A)
C015
Figure 13. Efficiency, Mode = DCM, FSW = 400kHz
Efficiency(%)
60
30
60
50
40
30
VIN =12V,VOUT =1.2V
VIN =12V,VOUT =3.3V
VIN =12V,VOUT=5.5V
20
10
0
0.001
0.01
0.1
1
VIN =12V,VOUT =3.3V
10
VIN =12V,VOUT =5.5V
0
10
Output Current(A)
VIN =12V,VOUT =1.2V
20
0
1
2
3
4
5
6
7
8
9
10
11
Output Current(A)
C017
Figure 15. Efficiency, Mode = DCM, FSW = 1200kHz
12
C018
Figure 16. Efficiency, Mode = FCCM, FSW = 1200kHz
1.206
500
VIN =4.5V,VOUT =1.2V
450
Output Voltage(V)
1.203
Switching Frequency(kHz)
VIN =12V,VOUT=1.2V
VIN =17V, VOUT =1.2V
1.2
1.197
400
350
300
250
200
VIN =4.5V,VOUT =1.2V
VIN =7V,VOUT=1.2V
150
1.194
1
2
3
4
5
6
7
8
9
10
11
Output Current(A)
12
0
1
2
3
4
5
6
7
Output Current(A)
C019
Figure 17. Load Regulation, FSW = 800kHz
10
VIN =17V,VOUT =1.2V
100
0
8
9
10
11
12
C021
Figure 18. FSW Load Regulation, Mode = DCM, FSW = 400kHz
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Typical Characteristics (continued)
1400
1300
800
Switching Frequency(kHz)
Switching Frequency(kHz)
900
700
600
500
VIN =4.5V,VOUT=1.2V
VIN =7V,VOUT =1.2V
VIN =17V,VOUT =1.2V
400
300
0
1
2
3
4
5
6
7
8
9
10
11
Output Current(A)
1200
1100
1000
900
800
600
12
0
2
3
4
5
6
7
8
9
10
11
Output Current
12
C023
Figure 20. FSW Load Regulation, Mode = DCM, FSW =
1200kHz
600
1000
500
400
300
VIN =4.5V, VOUT =1.2V
VIN =12V, VOUT =1.2V
VIN =17V,VOUT=1.2V
200
0
1
2
3
4
5
6
7
8
9
10
11
Output Current(A)
Switching Frequency(kHz)
Switching Frequency(kHz)
1
C022
Figure 19. FSW Load Regulation, Mode = DCM, FSW = 800kHz
900
800
700
600
VIN =4.5V,VOUT =1.2V
VIN =12V,VOUT =1.2V
VIN =17V,VOUT =1.2V
500
400
12
0
1
2
3
4
5
6
7
8
9
10
11
Output Current(A)
C024
Figure 21. FSW Load Regulation, Mode = FCCM, FSW =
400kHz
12
C025
Figure 22. FSW Load Regulation, Mode = FCCM, FSW =
800kHz
600
1300
1200
1100
1000
VIN =4.5V,VOUT=1.2V
VIN =12V,VOUT=1.2V
900
VIN =17V,VOUT=1.2V
800
0
1
2
3
4
5
6
7
8
Output Current(A)
9
10
11
12
Switching Frequency(kHz)
1400
Switching Frequency(kHz)
VIN =4.5V, VOUT =1.2V
VIN =7V,VOUT =1.2V
VIN =17V, VOUT=1.2V
700
500
400
300
VIN =12V, VOUT =1.2V
VIN =12V, VOUT =3.3V
VIN =12V,VOUT=5.5V
200
0
Figure 23. FSW Load Regulation, Mode = FCCM, FSW =
1200kHz
1
2
3
4
5
6
7
8
9
10
11
Output Current(A)
C026
12
C027
Figure 24. FSW Load Regulation, Mode = FCCM, FSW =
400kHz
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Typical Characteristics (continued)
Switching Frequency(kHz)
1400
1300
1200
1100
1000
VIN =12V,VOUT=1.2V
VIN =12V,VOUT=3.3V
900
VIN =12V,VOUT =5.5V
800
0
1
2
3
4
5
6
7
8
9
Output Current(A)
10
11
12
C028
Figure 25. FSW Load Regulation, Mode = FCCM, FSW = 1200kHz
12
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7 Detailed Description
7.1 Overview
The TPS56C215 is a high density synchronous step down buck converter which can operate from 3.8-V to 17-V
input voltage (VIN). It has 13.5-mΩ and 4.5-mΩ integrated MOSFETs that enable high efficiency up to 12 A. The
device employs D-CAP3™ mode control that provides fast transient response with no external compensation
components and an accurate feedback voltage. The control topology provides seamless transition between
FCCM operating mode at higher load condition and DCM/Eco-mode™ operation at lighter load condition.
DCM/Eco-mode™ allows the TPS56C215 to maintain high efficiency at light load. The TPS56C215 is able to
adapt to both low equivalent series resistance (ESR) output capacitors such as POSCAP or SP-CAP, and ultralow ESR ceramic capacitors.
The TPS56C215 has three selectable switching frequencies (FSW) 400kHz, 800kHz and 1200kHz which gives
the flexibility to optimize the design for higher efficiency or smaller size. There are two selectable current limits.
All these options are configured by choosing the right voltage on the MODE pin.
The TPS56C215 has a 4.7 V internal LDO that creates bias for all internal circuitry. There is a feature to
overdrive this internal LDO with an external voltage on the VREG5 pin which improves the converter’s efficiency.
The undervoltage lockout (UVLO) circuit monitors the VREG5 pin voltage to protect the internal circuitry from low
input voltages. The device has an internal pull-up current source on the EN pin which can enable the device
even with the pin floating.
Soft-start time can be selected by connecting a capacitor to the SS pin. The device is protected from output
short, undervoltage and over temperature conditions.
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7.2 Functional Block Diagram
PG rising threshold
TPS56C215
+
PGOOD Logic
UV
UV threshold
PGOOD
+
+
Delay
UVP / OVP
Logic
+
VREG5
PG falling threshold
OV threshold
OV
Internal Ramp
VREF
VIN
UVLO
+
-
-
Error Amp
LDO
+
+
+
FB
BOOT
BOOT
Control Logic
-
x
x
x
x
x
x
x
Internal SS
One shot
SS
On Time
Min On Time/Off Time
FCCM/SKIP
Soft-Start
Power Good
Internal/External VREG5
UVP/TSD
SW
SW
XCON
VREG5
PGND
Light Load Operation/
Current Limit/
Switching Frequency
MODE
TSD 160C/171C
SW
OCL
+
Ip1
Ip2
+
EN
ZC
+
Enable Threshold
NOCL
+
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7.3 Feature Description
7.3.1 PWM Operation and D-CAP3™ Control
The TPS56C215 operates using the adaptive on-time PWM control with a proprietary D-CAP3™ control which
enables low external component count with a fast load transient response while maintaining a good output
voltage accuracy. At the beginning of each switching cycle the high side MOSFET is turned on for an on-time set
by an internal one shot timer. This on-time is set based on the converter’s input voltage, output voltage and the
pseudo-fixed frequency hence this type of control topology is called an adaptive on-time control. The one shot
timer resets and turns on again once the feedback voltage (VFB) falls below the internal reference voltage (VREF).
An internal ramp is generated which is fed to the FB pin to simulate the output voltage ripple. This enables the
use of very low-ESR output capacitors such as multi-layered ceramic caps (MLCC). No external current sense
network or loop compensation is required for DCAP3™ control topology.
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Feature Description (continued)
The TPS56C215 includes an error amplifier that makes the output voltage very accurate. This error amplifier is
absent in other flavors of DCAP3™. For any control topology that is compensated internally, there is a range of
the output filter it can support. The output filter used with the TPS56C215 is a low pass L-C circuit. This L-C filter
has double pole that is described in
1
¦P =
2 ´ p ´ LOUT ´ COUT
(1)
At low frequencies, the overall loop gain is set by the output set-point resistor divider network and the internal
gain of the TPS56C215. The low frequency L-C double pole has a 180 degree in phase. At the output filter
frequency, the gain rolls off at a –40dB per decade rate and the phase drops rapidly. The internal ripple
generation network introduces a high-frequency zero that reduces the gain roll off from –40dB to –20dB per
decade and increases the phase to 90 degree one decade above the zero frequency. The internal ripple injection
high frequency zero is changed according to the switching frequency selected as shown in table below. The
inductor and capacitor selected for the output filter must be such that the double pole is located close enough to
the high-frequency zero so that the phase boost provided by this high-frequency zero provides adequate phase
margin for the stability requirement. The crossover frequency of the overall system should usually be targeted to
be less than one-fifth of the switching frequency (FSW).
Table 1. Ripple Injection Zero
Switching Frequency (kHz)
Zero Location (kHz)
400
7.1
800
14.3
1200
21.4
Table 2 lists the inductor values and part numbers that are used to plot the efficiency curves in the Typical
Characteristics section.
Table 2. Inductor Values
VOUT(V)
1.2
3.3
5.5
(1)
LOUT(uH)
Würth Part
Number (1)
400
1.2
744325120
800
0.68
744311068
1200
0.47
744314047
400
2.4
744325240
FSW(kHz)
800
1.5
7443552150
1200
1.2
744325120
400
3.3
744325330
800
2.4
744325240
1200
1.5
7443552150
See Third-Party Products disclaimer
7.3.2 Eco-mode™ Control
The TPS56C215 is designed with Eco-mode™ control to increase efficiency at light loads. This option can be
chosen using the MODE pin as shown in Table 3. As the output current decreases from heavy load condition, the
inductor current is also reduced. If the output current is reduced enough, the valley of the inductor current
reaches the zero level, which is the boundary between continuous conduction and discontinuous conduction
modes. The low-side MOSFET is turned off when a zero inductor current is detected. As the load current further
decreases the converter runs into discontinuous conduction mode. The on-time is kept approximately the same
as it is in continuous conduction mode. The off-time increases as it takes more time to discharge the output with
a smaller load current. The light load current where the transition to Eco-mode™ operation happens ( IOUT(LL) )
can be calculated from Equation 2.
(V -V
) × VOUT
1
IOUT(LL) =
× IN OUT
2 × LOUT × FSW
VIN
(2)
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After identifying the application requirements, design the output inductance (LOUT) so that the inductor peak-topeak ripple current is approximately between 20% and 30% of the IOUT(ma×) (peak current in the application). It is
also important to size the inductor properly so that the valley current doesn't hit the negative low side current
limit.
7.3.3 4.7 V LDO
The VREG5 pin is the output of the internal 4.7-V linear regulator that creates the bias for all the internal circuitry
and MOSFET gate drivers. The VREG5 pin needs to be bypassed with a 4.7-µF capacitor. An external voltage
that is above the LDO's internal output voltage can override the internal LDO, switching it to the external rail once
a higher voltage is detected. This enhances the efficiency of the converter because the quiescent current now
runs off this external rail instead of the input power supply. The UVLO circuit monitors the VREG5 pin voltage
and disables the output when VREG5 falls below the UVLO threshold. When using an external bias on the
VREG5 rail, any power-up and power-down sequencing can be applied but it is important to understand that if
there is a discharge path on the VREG5 rail that can pull a current higher than the internal LDO's current limit
(ILIM5) from the VREG5, then the VREG5 LDO turns off thereby shutting down the output of TPS56C215. If such
condition does not exist and if the external VREG5 rail is turned off, the VREG5 voltage switches over to the
internal LDO voltage which is 4.7 V typically in a few nanoseconds. Figure 26 below shows this transition of the
VREG5 voltage from an external bias of 5.5 V to the internal LDO output of 4.7 V when the external bias to
VREG5 is disabled while the output of TPS56C215 remains unchanged.
VREG5
VOUT
Figure 26. VREG5 Transition
7.3.4 MODE Selection
TPS56C215 has a MODE pin that can offer 12 different states of operation as a combination of Current Limit,
Switching Frequency and Light Load operation. The device can operate at two different current limits ILIM-1 and
ILIM to support an output continuous current of 10 A and 12 A respectively. The TPS56C215 is designed to
compare the valley current of the inductor against the current limit thresholds so it is important to understand that
the output current will be half the ripple current higher than the valley current. For example with the ILIM current
limit selection, the OCL threshold is 11.73A minimum which means that a pk-pk inductor ripple current of 0.54 A
minimum is needed to be able to draw 12 A out of the converter without entering an overcurrent condition.
TPS56C215 can operate at three different frequencies of 400 kHz, 800 kHz and 1200 kHz and also can choose
between Eco-mode™ and FCCM mode. The device reads the voltage on the MODE pin during start-up and
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latches onto one of the MODE options listed below in Table 3. The voltage on the MODE pin can be set by
connecting this pin to the center tap of a resistor divider connected between VREG5 and AGND. A guideline for
the top resistor (RM_H) and the bottom resistor (RM_L) in 1% resistors is shown in Table 3. It is important that the
voltage for the MODE pin is derived from the VREG5 rail only since internally this voltage is referenced to detect
the MODE option. The MODE pin setting can be reset only by a VIN power cycling.
Table 3. MODE Pin Resistor Settings
RM_L (kΩ)
RM_H (kΩ)
Light Load
Operation
Current Limit
Frequency (kHz)
5.1
300
FCCM
ILIM-1
400
10
200
FCCM
ILIM
400
20
160
FCCM
ILIM-1
800
20
120
FCCM
ILIM
800
51
200
FCCM
ILIM-1
1200
51
180
FCCM
ILIM
1200
51
150
DCM
ILIM-1
400
51
120
DCM
ILIM
400
51
91
DCM
ILIM-1
800
51
82
DCM
ILIM
800
51
62
DCM
ILIM-1
1200
51
51
DCM
ILIM
1200
Figure 27 below shows the typical start-up sequence of the device once the EN pin voltage crosses the EN turnon threshold. After the voltage on VREG5 pin crosses the rising UVLO threshold it takes 100us to read the first
MODE setting and approximately 100us from there to finish the last MODE setting. The output voltage starts
ramping after the MODE setting reading is completed.
EN threshold
1.2 V
EN
VREG5 UVLO
4.3 V
VREG5
MODE16
MODE1
MODE
200 µs
100 µs
tss(1ms)
SS
Figure 27. Power-Up Sequence
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7.3.5 Soft Start and Pre-biased Soft Start
The TPS56C215 has an adjustable soft-start time that can be set by connecting a capacitor on SS pin. When the
EN pin becomes high, the soft-start charge current (ISS) begins charging the external capacitor (CSS) connected
between SS and AGND. The devices tracks the lower of the internal soft-start voltage or the external soft-start
voltage as the reference. The equation for the soft-start time (TSS) is shown in Equation 3:
C × VREF
TSS(S) = SS
ISS
where
•
VREF is 0.6 V and ISS is 6 µA
(3)
If the output capacitor is pre-biased at startup, the device initiates switching and starts ramping up only after the
internal reference voltage becomes greater than the feedback voltage VFB. This scheme ensures that the
converters ramp up smoothly into regulation point.
7.3.6 Enable and Adjustable UVLO
The EN pin controls the turn-on and turn-off of the device. When EN pin voltage is above the turn-on threshold
which is around 1.2 V, the device starts switching and when the EN pin voltage falls below the turn-off threshold
which is around 1.1V it stops switching. If the user application requires a different turn-on (VSTART) and turn-off
thresholds (VSTOP) respectively, the EN pin can be configured as shown in Figure 28 by connecting a resistor
divider between VIN and EN. The EN pin has a pull-up current Ip1 that sets the default state of the pin when it is
floating. This current increases to Ip2 when the EN pin voltage crosses the turn-on threshold. The UVLO
thresholds can be set by using Equation 4 and Equation 5.
TPS56C215
VIN
Ip1
Ih
R1
EN
R2
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Figure 28. Adjustable VIN Undervoltage Lock Out
æV
ö
VSTART ç ENFALLING ÷ - VSTOP
V
è ENRISING ø
R1 =
æ VENFALLING ö
Ip1 ç1 ÷ + Ih
VENRISING ø
è
(4)
R1´ VENFALLING
R2 =
VSTOP - VENFALLING + R1 Ip2
where
•
•
•
•
•
18
Ip2 = 4.197 μA
Ip1 = 1.91 μA
Ih = 2.287 μA
VENRISING = 1.225 V
VENFALLING = 1.104 V
(5)
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7.3.7 Power Good
The Power Good (PGOOD) pin is an open drain output. Once the FB pin voltage is between 93% and 107% of
the internal reference voltage (VREF) the PGOOD is de-asserted and floats after a 200 µs de-glitch time. A pull-up
resistor of 10 kΩ is recommended to pull it up to VREG5. The PGOOD pin is pulled low when the FB pin voltage
is lower than VUVP or greater than VOVP threshold; or, in an event of thermal shutdown or during the soft-start
period
7.3.8 Overcurrent Protection and Undervoltage Protection
The output overcurrent limit (OCL) is implemented using a cycle-by-cycle valley detect control circuit. The switch
current is monitored during the OFF state by measuring the low-side FET drain to source voltage. This voltage is
proportional to the switch current. During the on time of the high-side FET switch, the switch current increases at
a linear rate determined by input voltage , output voltage, the on-time and the output inductor value. During the
on time of the low-side FET switch, this current decreases linearly. The average value of the switch current is the
load current IOUT. If the measured drain to source voltage of the low-side FET is above the voltage proportional to
current limit, the low side FET stays on until the current level becomes lower than the OCL level which reduces
the output current available. When the current is limited the output voltage tends to drop because the load
demand is higher than what the converter can support. When the output voltage falls below 68% of the target
voltage, the UVP comparator detects it and shuts down the device after a wait time of 1ms, the device re-starts
after a hiccup time of 7ms. In this type of valley detect control the load current is higher than the OCL threshold
by one half of the peak to peak inductor ripple current. When the overcurrent condition is removed, the output
voltage returns to the regulated value. If an OCL condition happens during start-up then the device enters
hiccup-mode immediately without a wait time of 1ms.
7.3.9 Out-of-Bounds Operation
The device has an out-of-bounds (OOB) overvoltage protection that protects the output load at a much lower
overvoltage threshold of 8% above the target voltage. OOB protection does not trigger an overvoltage fault, OOB
protection operates as an early no-fault overvoltage protection mechanism. During the OOB operation, the
controller operates in forced PWM mode only by turning on the low-side FET. Turning on the low-side FET
beyond the zero inductor current quickly discharges the output capacitor thus causing the output voltage to fall
quickly toward the setpoint. During the operation, the cycle-by cycle negative current limit is also activated to
ensure the safe operation of the internal FETs.
7.3.10 UVLO Protection
Undervoltage Lock Out protection (UVLO) monitors the internal VREG5 regulator voltage. When the VREG5
voltage is lower than UVLO threshold voltage, the device is shut off. This protection is non-latching.
7.3.11 Thermal Shutdown
The device monitors the internal die temperature. If this temperature exceeds the thermal shutdown threshold
value (TSDN typically 160°C) the device shuts off. This is a non-latch protection. During start up, if the device
temperature is higher than 160°C the device does not start switching and does not load the MODE settings. If the
device temp goes higher than TSDN threshold after startup, it stops switching with SS reset to ground and an
internal discharge switch turns on to quickly discharge the output voltage. The device re-starts switching when
the temperature goes below the thermal shutdown threshold but the MODE settings are not re-loaded again.
There is a second higher thermal protection on the device TSDN VREG5 which protects it from over temperature
conditions not caused by the switching of the device itself. This threshold is at typically 170°C. Even under nonswitching condition of the device after exceeding TSDN threshold, if it still continues to heat up the VREG5 output
shuts off once temperature goes beyond TSDN VREG5, thereby shutting down the device completely.
7.3.12 Output Voltage Discharge
The device has a 500ohm discharge switch that discharges the output VOUT through SW node during any event
of fault like output overvoltage, output undervoltage , TSD , if VREG5 voltage below the UVLO and when the EN
pin voltage (VEN) is below the turn-on threshold.
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7.4 Device Functional Modes
7.4.1 Light Load Operation
When the MODE pin is selected to operate in FCCM mode, the converter operates in continuous conduction
mode (FCCM) during light-load conditions. During FCCM, the switching frequency (FSW) is maintained at an
almost constant level over the entire load range which is suitable for applications requiring tight control of the
switching frequency and output voltage ripple at the cost of lower efficiency under light load. If the MODE pin is
selected to operate in DCM/Eco-mode™, the device enters pulse skip mode after the valley of the inductor ripple
current crosses zero. The Eco-mode™ maintains higher efficiency at light load with a lower switching frequency.
7.4.2
Standby Operation
The TPS56C215 can be placed in standby mode by pulling the EN pin low. The device operates with a shutdown current of 7uA when in standby condition.
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8 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
8.1 Application Information
The schematic of Figure 29 shows a typical application for TPS56C215. This design converts an input voltage
range of 4.5 V to 17 V down to 1.2 V with a maximum output current of 12 A.
8.2 Typical Application
VIN
VIN = 4.5 V - 17 V
U1
TPS56C215
C1
0.1µF
C2
0.1µF
C3
22µF
C4
22µF
C5
22µF
C6
22µF
14
C7
0.047µF
15
EN
R1
PGOOD
10.0k
R2
52.3k
16
17
18
C8
4.7µF
LOUT
C9
2
11
R3
49.9k
VIN
VIN
BOOT
SW
SW
FB
SS
EN
PGOOD
VREG5
PGND
PGND
PGND
PGND
PGND
PGND
MODE
AGND
VOUT = 1.2 V, 12 A
1
0.1µF
6
7
13
C11
47µF
R4 10.0k
3
4
5
8
9
10
VOUT
470nH
C12
47µF
C13
47µF
C14
47µF
C10
56pF
R5
10.0k
12
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Figure 29. Application Schematic
8.2.1 Design Requirements
Table 4. Design Parameters
PARAMETER
VOUT
Output voltage
IOUT
Output current
ΔVOUT
Transient response
VIN
Input voltage
VOUT(ripple)
Output voltage ripple
FSW
CONDITIONS
TYP
MAX
UNIT
1.2
9-A load step
4.5
A
40
mV
12
20
Start input voltage
Input voltage rising
Stop input voltage
Input voltage falling
Internal
UVLO
Switching frequency
V
12
Internal
UVLO
17
V
mV(P-P)
1.2
Operating Mode
TA
MIN
V
V
MHz
DCM
Ambient temperature
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8.2.2 Detailed Design Procedure
8.2.2.1 External Component Selection
8.2.2.1.1 Output Voltage Set Point
To change the output voltage of the application, it is necessary to change the value of the upper feedback
resistor. By changing this resistor the user can change the output voltage above 0.6 V. See Equation 6
æ
ö
R
VOUT = 0.6 ´ ç 1 + UPPER ÷
è RLOWER ø
(6)
8.2.2.1.2 Switching Frequency and MODE Selection
Switching Frequency, current limit and switching mode (DCM or FCCM) are set by a voltage divider from VREG5
to GND connected to the MODE pin. See Table 3 for possible MODE pin configurations. Switching frequency
selection is a tradeoff between higher efficiency and smaller system solution size. Lower switching frequency
yields higher overall efficiency but relatively bigger external components. Higher switching frequencies cause
additional switching losses which impact efficiency and thermal performance. For this design 1.2 MHz is chosen
as the switching frequency, the switching mode is DCM and the output current is 12 A.
8.2.2.1.3 Inductor Selection
The inductor ripple current is filtered by the output capacitor. A higher inductor ripple current means the output
capacitor should have a ripple current rating higher than the inductor ripple current. See Table 5 for
recommended inductor values.
The RMS and peak currents through the inductor can be calculated using Equation 7 and Equation 8. It is
important that the inductor is rated to handle these currents.
2ö
æ
1 æ VOUT × (VIN(max) - VOUT )ö ÷
ç
2
÷
IL(rms)= ç I OUT + × ç
12 ç VIN(max) × LOUT × FSW ÷ ÷÷
ç
è
ø
è
ø
IOUT(ripple)
IL(peak) = IOUT +
2
(7)
(8)
During transient/short circuit conditions the inductor current can increase up to the current limit of the device so it
is safe to choose an inductor with a saturation current higher than the peak current under current limit condition.
8.2.2.1.4 Output Capacitor Selection
After selecting the inductor the output capacitor needs to be optimized. In DCAP3, the regulator reacts within one
cycle to the change in the duty cycle so the good transient performance can be achieved without needing large
amounts of output capacitance. The recommended output capacitance range is given in Table 5
Ceramic capacitors have very low ESR, otherwise the maximum ESR of the capacitor should be less than
VOUT(ripple)/IOUT(ripple)
Table 5. Recommended Component Values
VOUT (V)
0.6
RLOWER (kΩ)
10
1.2
3.3
22
RUPPER (kΩ)
0
10
45.3
FSW (kHz)
LOUT (µH)
COUT(min) (µF)
COUT(max) (µF)
CFF (pF)
400
0.68
300
500
–
800
0.47
100
500
–
1200
0.33
88
500
–
400
1.2
100
500
–
–
800
0.68
88
500
1200
0.47
88
500
–
400
2.4
88
500
100–220
800
1.5
88
500
100–220
1200
1.2
88
500
100–220
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Table 5. Recommended Component Values (continued)
VOUT (V)
RLOWER (kΩ)
RUPPER (kΩ)
5.5
FSW (kHz)
LOUT (µH)
COUT(min) (µF)
COUT(max) (µF)
CFF (pF)
400
3.3
88
500
100–220
800
2.4
88
500
100–220
1200
1.5
88
700
100–220
82.5
8.2.2.1.5 Input Capacitor Selection
The minimum input capacitance required is given in Equation 9.
IOUT ×VOUT
CIN(min) =
VINripple ×VIN ×FSW
(9)
TI recommends using a high quality X5R or X7R input decoupling capacitors of 40 µF on the input voltage pin.
The voltage rating on the input capacitor must be greater than the maximum input voltage. The capacitor must
also have a ripple current rating greater than the maximum input current ripple of the application. The input ripple
current is calculated by Equation 10 below:
ICIN(rms) = IOUT ×
(VIN(min)-VOUT )
VOUT
×
VIN(min)
VIN(min)
(10)
8.2.3 Application Curves
100
100
90
90
80
80
70
70
Efficiency (%)
Efficiency (%)
Figure 30 through Figure 46 apply to the circuit of Figure 29. VIN = 12 V. Ta = 25 °C unless otherwise specified.
60
50
40
60
50
40
30
30
20
20
VIN = 5V
VIN = 12V
10
0
1
2
3
4
5
6
7
8
Output Current (A)
9
10
11
VIN = 5V
VIN = 12V
10
0
12
0
0.001
D101
Figure 30. Efficiency
0.010.02 0.05 0.1 0.2 0.5
Output Current (A)
1
2 3 45 7 1015
D102
Figure 31. Light Load Efficiency
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1
1
0.8
0.8
0.6
0.6
Load Regulation (%)
0.4
0.2
0
-0.2
-0.4
0.4
0.2
0
-0.2
-0.4
-0.6
-0.6
-0.8
-0.8
-1
-1
0
1
2
3
4
5
6
7
8
Output Current (A)
9
10
11
12
0
1
2
Figure 32. Load Regulation, VIN = 5 V
5
6
7
8
Output Current (A)
9
10
11
12
D104
0.25
60
180
0.20
50
150
40
120
30
90
20
60
0.10
0.05
Gain (dB)
Line Regulation (%)
4
Figure 33. Load Regulation, VIN = 12 V
0.15
0.00
-0.05
-0.10
-0.15
10
30
0
0
-10
-30
-20
-60
-30
-90
-40
-0.20
-50
-0.25
4
5
6
7
8
9 10 11 12 13 14 15 16 17 18
Input Voltage (V)
D105
-60
100 200
500 1000
Figure 34. Line Regulation, IOUT = 6 A
10000
Frequency (Hz)
-120
Gain (dB)
Phase (Deg) -150
-180
100000
500000
D106
Figure 35. Loop Response, IOUT = 6 A
VIN = 100 mV / div (ac coupled)
VIN = 100 mV / div (ac coupled)
SW = 5 V / div
SW = 5 V / div
Time = 50 µsec / div
Time = 500 nsec / div
Figure 36. Input Voltage Ripple, IOUT = 10 mA
24
3
D103
Phase (Degree)
Load Regulation (%)
SLVSD05C – MARCH 2016 – REVISED MARCH 2018
Figure 37. Input Voltage Ripple, IOUT = 800 mA
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VIN = 100 mV / div (ac coupled)
VOUT = 20 mV / div (ac coupled)
SW = 5 V / div
SW = 5 V / div
Time = 50 µsec / div
Time = 500 nsec / div
Figure 38. Input Voltage Ripple, IOUT = 12 A
Figure 39. Output Voltage Ripple, IOUT = 10 mA
VOUT = 20 mV / div (ac coupled)
VOUT = 20 mV / div (ac coupled)
SW = 5 V / div
SW = 5 V / div
Time = 500 nsec / div
Time = 500 nsec / div
Figure 40. Output Voltage Ripple, IOUT = 800 mA
Figure 41. Output Voltage Ripple, IOUT = 12 A
VIN = 10 V / div
VIN = 10 V / div
EN = 5 V / div
EN = 5 V / div
VOUT = 500 mV / div
VOUT = 500 mV / div
PGOOD = 5 V / div
PGOOD = 5 V / div
Time = 2 msec / div
Time = 2 msec / div
Figure 42. Start Up Relative to VIN Rising
Figure 43. Start Up Relative to EN Rising
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VIN = 10 V / div
VIN = 10 V / div
EN = 5 V / div
EN = 5 V / div
VOUT = 500 mV / div
VOUT = 500 mV / div
PGOOD = 5 V / div
PGOOD = 5 V / div
Time = 2 msec / div
Time = 2 msec / div
Figure 44. Shut Down Relative to VIN Falling
Figure 45. Shut Down Relative to EN Falling
VOUT = 50 mV / div (ac coupled)
IOUT = 2 A / div
Load step = 3 A - 9 A, slew rate = 1 A / µsec
Time = 200 µsec / div
Figure 46. Transient Response
9 Power Supply Recommendations
The TPS56C215 is intended to be powered by a well regulated dc voltage. The input voltage range is 3.8 to 17
V. TPS56C215 is a buck converter. The input supply voltage must be greater than the desired output voltage for
proper operation. Input supply current must be appropriate for the desired output current. If the input voltage
supply is located far from the TPS56215 circuit, some additional input bulk capacitance is recommended. Typical
values are 100 µF to 470 µF.
26
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10 Layout
10.1 Layout Guidelines
•
•
•
•
•
•
•
Recommend a four-layer or six-layer PCB for good thermal performance and with maximum ground plane. 3"
x 3", four-layer PCB with 2-oz. copper used as example.
Recommend having equal caps on each side of the IC. Place them right across VIN as close as possible.
Inner layer 1 will be ground with the PGND to AGND net tie
Inner layer2 has VIN copper pour that has vias to the top layer VIN. Place multiple vias under the device
near VIN and PGND and near input capacitors to reduce parasitic inductance and improve thermal
performance
Bottom later is GND with the BOOT trace routing.
Feedback should be referenced to the quite AGND and routed away from the switch node.
VIN trace must be wide to reduce the trace impedance.
10.2 Layout Example
Figure 47 shows the recommended top side layout. Component reference designators are the same as the
circuit shown in Figure 29. Resistor divider for EN is not used in the circuit of Figure 29, but are shown in the
layout for reference.
R5
R4
C10
REN1
C7
FB
SS
EN
AGND
VIN
PGND
PGND
SW
VIN
SW
C1
VREG5
C4
PGOOD
MODE
C9
C8
R3
R2
R1
BOOT
C3
REN2
PGOOD
OUTPUT
PGND
PGND
PGND
PGND
C2
C5
C6
L1
C11
C13
C12
C14
Figure 47. Top Side Layout
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Layout Example (continued)
Figure 48 shows the recommended layout for the first internal layer. It is comprised of a large PGND plane and a
smaller ANGD island. AGND and PGND are connected at a single point to reduce circulating currents.
AGND
SINGLE POINT
AGND TO PGND
CONNECTION
PGND PLANE
Figure 48. Mid Layer 1 Layout
Figure 49 shows the recommended layout for the second internal layer. It is comprised of a large PGND plane, a
smaller copper fill area to connect the two top side VIN copper areas and a second VOUT copper fill area.
VIN
PGND PLANE
VOUT
Figure 49. Mid Layer 2 Layout
28
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Layout Example (continued)
Figure 50 shows the recommended layout for the bottom layer. It is comprised of a large PGND plane and a
trace to connect the BOOT capacitor to the SW node.
PGND PLANE
Figure 50. Bottom Layer Layout
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11 Device and Documentation Support
11.1 Device Support
11.1.1 Third-Party Products Disclaimer
TI'S PUBLICATION OF INFORMATION REGARDING THIRD-PARTY PRODUCTS OR SERVICES DOES NOT
CONSTITUTE AN ENDORSEMENT REGARDING THE SUITABILITY OF SUCH PRODUCTS OR SERVICES
OR A WARRANTY, REPRESENTATION OR ENDORSEMENT OF SUCH PRODUCTS OR SERVICES, EITHER
ALONE OR IN COMBINATION WITH ANY TI PRODUCT OR SERVICE.
11.1.2 Development Support
The evaluation module for system validation in shown in Figure 51.
Figure 51. System Validation EVM Board
30
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11.2 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper
right corner, click on Alert me to register and receive a weekly digest of any product information that has
changed. For change details, review the revision history included in any revised document.
11.3 Community Resources
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
11.4 Trademarks
D-CAP3, Eco-mode, HotRod, DCAP3, -mode, E2E are trademarks of Texas Instruments.
All other trademarks are the property of their respective owners.
11.5 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
11.6 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
12 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
12.1 Package Marking
56C215
TI YMS
LLLL
TI
YM
S
LLLL
=
=
=
=
TI Letters
Year Month Date Code
Assembly Site Code
Assembly Lot Code
Y : Year Code (1, 2, 3, 4, 5, 6, 7, 8, 9, 0)
M : Month Code (1, 2, 3, 4, 5, 6, 7, 8, 9, 0, A, B, C)
Figure 52. Symbolization
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PACKAGE OPTION ADDENDUM
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15-Nov-2017
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
Lead/Ball Finish
MSL Peak Temp
(2)
(6)
(3)
Op Temp (°C)
Device Marking
(4/5)
TPS56C215RNNR
ACTIVE
VQFN-HR
RNN
18
3000
Green (RoHS
& no Sb/Br)
CU | CU NIPDAU
Level-2-260C-1 YEAR
-40 to 125
56C215
TPS56C215RNNT
ACTIVE
VQFN-HR
RNN
18
250
Green (RoHS
& no Sb/Br)
CU | CU NIPDAU
Level-2-260C-1 YEAR
-40 to 125
56C215
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of
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