TPS56C231
SLVSGB5 – AUGUST 2022
TPS56C231 3.8-V to 17-V Input , 12-A Synchronous Step-Down Converter
1 Features
2 Applications
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Data center and enterprise computing POLs
Wireless infrastructure
IPCs, factory automation, PLC, test measurement
High-end DTV
3 Description
The TPS56C231 is a small, high-efficiency,
synchronous buck converter with an adaptive ontime D-CAP3 control mode. Because external
compensation is not required, the device is easy
to use and requires few external components. The
device is well-suited for space-constrained data
center applications.
The TPS56C231 has competitive features including
a very accurate reference voltage, fast load
transient response, and no requirement for external
compensation, adjustable current limit, and both Ecomode and FCCM operation modes for selection at
light-load condition through the configuration of the
MODE pin. To attain high efficiency at light load,
Eco-mode can be selected. To support tight output
voltage ripple requirement, FCCM can be selected.
The TPS56C231 operates from a –40°C to 125°C
junction temperature range.
Package Information
Package(1)
Part Number
TPS56C231
(1)
Body Size (NOM)
RNN (VQFN-HR, 18) 3.50 mm × 3.50 mm
For all available packages, see the orderable addendum at
the end of the data sheet.
100
VIN
VIN
BOOT
VREG5
SW
95
90
VOUT
85
EN
PGOOD
VREG5
MODE
FB
Efficiency (%)
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4.5-V to 17-V input range without external bias
3.8-V to 17-V input range with external bias
Supports 12-A continuous output current
TPS56C231 supports 15-A peak current
Integrated 7.8-mΩ and 3.2-mΩ MOSFETs
0.6-V ±1% reference voltage across a –40°C to
125°C junction temperature range
0.6-V to 5.5-V output voltage range
146-μA low quiescent current
D-CAP3™ control mode for fast transient response
Supports ceramic output capacitors
Selectable fSW of 400 kHz, 800 kHz, and 1200 kHz
Selectable FCCM (forced continuous conduction
mode) for tight output voltage ripple
Selectable Eco-mode (auto skip mode) for high
light-load efficiency
Optional external 5-V bias for enhanced efficiency
Prebiased start-up capability
Adjustable soft start with a default 1.2-ms soft-start
time
Power-good indicator to monitor output voltage
Two adjustable current limit settings with hiccup
restart: TPS56C231 (14.7 A, 17 A) and
TPS56C231L (11.5 A, 13.8 A)
Non-latched protections for UV, OV, OT, and UVLO
Pin-to-pin compatible with 12-A TPS56C215, and
8-A TPS568231 and TPS568215
–40°C to 125°C operating junction temperature
3.5-mm × 3.5-mm, 18-pin HotRod™ QFN package
80
75
70
65
SS
60
AGND
PGND
VIN=12V, V OUT=1.2V, 400kHz
VIN=12V, V OUT=3.3V, 400kHz
VIN=12V, V OUT=5V, 400kHz
55
50
0
Simplified Schematic
1
2
3
4
5
6
7
8
Output Current (A)
9
10
11
12
Efficiency, FCCM Mode
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
TPS56C231
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SLVSGB5 – AUGUST 2022
Table of Contents
1 Features............................................................................1
2 Applications..................................................................... 1
3 Description.......................................................................1
4 Revision History.............................................................. 2
5 Pin Configuration and Functions...................................3
6 Specifications.................................................................. 4
6.1 Absolute Maximum Ratings........................................ 4
6.2 ESD Ratings............................................................... 4
6.3 Recommended Operating Conditions.........................4
6.4 Thermal Information....................................................5
6.5 Electrical Characteristics.............................................5
6.6 Typical Characteristics................................................ 7
7 Detailed Description......................................................13
7.1 Overview................................................................... 13
7.2 Functional Block Diagram......................................... 14
7.3 Feature Description...................................................15
7.4 Device Functional Modes..........................................19
8 Application and Implementation.................................. 20
8.1 Application Information............................................. 20
8.2 Typical Application.................................................... 20
8.3 Power Supply Recommendations.............................24
8.4 Layout....................................................................... 24
9 Device and Documentation Support............................26
9.1 Device Support......................................................... 26
9.2 Receiving Notification of Documentation Updates....26
9.3 Support Resources................................................... 26
9.4 Trademarks............................................................... 26
9.5 Electrostatic Discharge Caution................................26
9.6 Glossary....................................................................26
10 Mechanical, Packaging, and Orderable
Information.................................................................... 26
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
2
DATE
REVISION
NOTES
August 2022
*
Initial release
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5 Pin Configuration and Functions
AGND 12
1 BOOT
VIN 11
2 VIN
BOOT 1
13 FB
14 SS
15 EN
16 PGOOD
17 VREG5
18 MODE
18 MODE
TOP VIEW
17 VREG5
16 PGOOD
15 EN
14 SS
13 FB
BOTTOM VIEW
12 AGND
VIN 2
11 VIN
PGND 10
3 PGND
PGND 3
10 PGND
PGND 9
4 PGND
PGND 4
9 PGND
PGND 8
5 PGND
PGND 5
8 PGND
7
6
6
7
SW
SW
Figure 5-1. 18-Pin VQFN RNN Package (Bottom View and Top View)
Table 5-1. Pin Functions
Pin
Name
Type
No.
Description
(1)
1
I
Supply input for the gate drive voltage of the high-side MOSFET. Connect the bootstrap capacitor between
BOOT and SW.
2,11
P
Input voltage supply pin for the control circuitry. Connect the input decoupling capacitors between VIN and
PGND.
3, 4, 5,
8, 9, 10
G
Power GND pin for the controller circuit and the internal circuitry. Connect to AGND with a short trace.
SW
6, 7
O
Switch node pin. Connect the output inductor to this pin.
AGND
12
G
Ground of internal analog circuitry. Connect AGND to the PGND plane with a short trace.
FB
13
I
Converter feedback input. Connect to the center tap of the resistor divider between output voltage and AGND.
SS
14
O
Soft-start time selection pin. Connecting an external capacitor sets the soft-start time and if no external
capacitor is connected, the converter starts up in 1.2 ms.
EN
15
I
Enable input control, leaving this pin floating enables the converter. This pin can also be used to adjust the
input UVLO by connecting to the center tap of the resistor divider between VIN and EN.
PGOOD
16
O
Open-drain power-good indicator. The pin is asserted low if output voltage is out of the PGOOD threshold,
overvoltage, or if the device is under thermal shutdown, EN shutdown, or during soft start.
VREG5
17
I/O
4.7-V internal LDO output that can also be driven externally with a 5-V input. This pin supplies voltage to the
internal circuitry and gate driver. Bypass this pin with a 4.7-µF capacitor.
MODE
18
I
Switching frequency, current limit selection, and light load operation mode selection pin. Connect this pin to a
resistor divider from VREG5 and AGND for different MODE options shown in Table 7-2.
BOOT
VIN
PGND
(1)
I = input, P = power, G = ground, O = output
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6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted) (1)
MIN
MAX
VIN
–0.3
20
SW
–2
19
SW (10-ns transient)
–5
25
VIN-SW
22
VIN-SW (10-ns transient)
25
UNIT
EN
–0.3
6.5
BOOT-SW
–0.3
6.5
BOOT-SW (10-ns transient)
–0.3
7.5
BOOT
–0.3
25.5
SS, MODE, FB
–0.3
6.5
VREG5
–0.3
6
PGOOD
–0.3
6.5
TJ
Operating junction temperature
–40
150
°C
Tstg
Storage temperature
–55
150
°C
Pin voltage
(1)
V
Operation outside the Absolute Maximum Ratings may cause permanent device damage. Absolute Maximum Ratings do not imply
functional operation of the device at these or any other conditions beyond those listed under Recommended Operating Conditions. If
used outside the Recommended Operating Conditions but within theAbsolute Maximum Ratings, the device may not be fully functional,
and this may affect device reliability, functionality, performance, and shorten the device lifetime.
6.2 ESD Ratings
VALUE
V(ESD)
(1)
(2)
Electrostatic discharge
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1)
±2000
Charged-device model (CDM), per ANSI/ESDA/JEDEC JS-002(2)
±500
UNIT
V
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
6.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MIN
Pin voltage
4
NOM
MAX
UNIT
VIN
3.8
17
V
SW
–1.8
17
V
BOOT
–0.1
23.5
V
VREG5, MODE, FB, PGOOD, EN
–0.1
5.5
V
0
12
A
–40
125
°C
Output current
ILOAD
Operating junction
temperature
TJ
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6.4 Thermal Information
RNN (JEDEC)
THERMAL METRIC(1)
RθJA
RNN (TI EVM)
UNIT
18 PINS
Junction-to-ambient thermal resistance
49.9
27
°C/W
applicable(2)
°C/W
RθJC(top)
Junction-to-case (top) thermal resistance
24.9
Not
RθJB
Junction-to-board thermal resistance
11.3
Not applicable(2)
°C/W
ψJT
Junction-to-top characterization parameter
0.5
0.4
°C/W
ψJB
Junction-to-board characterization parameter
11
10
°C/W
(1)
(2)
For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report.
Not applicable to an EVM layout
6.5 Electrical Characteristics
TJ = –40°C to +125°C, VIN = 12 V (unless otherwise noted)
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNIT
SUPPLY CURRENT
IIN
VIN supply current
TJ = 25°C, VEN = 5 V, non-switching
146
µA
IVINSDN
VIN shutdown current
VEN = 0 V
9.3
µA
LOGIC THRESHOLD
VENH
EN H-level threshold voltage
1.175
1.225
1.3
V
VENL
EN L-level threshold voltage
1.025
1.104
1.15
V
VENHYS
IENp1
IENp2
0.121
EN pullup current
V
VEN = 1.0 V
0.35
1.91
2.95
µA
VEN = 1.3 V
3
4.197
5.5
µA
598
600
602
mV
FEEDBACK VOLTAGE
TJ = 25°C
VFB
FB voltage
TJ = 0°C to 85°C
597.5
600
602.5
mV
TJ = –40°C to 85°C
594
600
602.5
mV
TJ = –40°C to 125°C
594
600
606
mV
LDO VOLTAGE
VREG5
LDO output voltage
TJ = –40°C to 125°C
4.58
4.7
4.83
V
ILIM5
LDO output current limit
TJ = –40°C to 125°C
100
150
200
mA
UVLO
UVLO
UVLO,
VREG5 = 4.7
V
UVLO threshold
UVLO threshold, VREG5 = 4.7 V
VREG5 rising voltage
4.25
V
VREG5 falling voltage
3.52
V
VREG5 hysteresis
730
mV
VIN rising voltage, VREG5 = 4.7 V
3.32
V
VIN falling voltage, VREG5 = 4.7 V
3.24
V
VIN hysteresis, VREG5 = 4.7 V
80
mV
MOSFET
RDS(on)H
High-side switch resistance
TJ = 25°C, VVREG5 = 4.7 V
7.8
mΩ
RDS(on)L
Low-side switch resistance
TJ = 25°C, VVREG5 = 4.7 V
3.2
mΩ
60
ns
ON-TIME TIMER CONTROL
tON min
SW minimum on time(1)
VIN = 17 V, VOUT = 0.6 V, fSW =
1200 kHz
tOFF
SW minimum off time
VFB = 0.5 V
310
ns
SOFT START AND OUTPUT DISCHARGE
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6.5 Electrical Characteristics (continued)
TJ = –40°C to +125°C, VIN = 12 V (unless otherwise noted)
PARAMETER
CONDITIONS
tSS
Soft-start time
Internal soft start time, TJ = –
40°C to 125°C
Iss
Soft-start charge current
TJ = –40°C to 125°C
RDIS
Discharge resistance
TJ = 25°C, VOUT = 0.5 V, VEN = 0 V
MIN
TYP
MAX
1.2
4.9
6
UNIT
ms
7.1
370
µA
Ω
CURRENT LIMIT
IOCL
INOCL
TPS56C231 current limit (low-side
sourcing)
ILIM-1 option, valley current
12
14.7
16.8
A
ILIM option, valley current
14
17
19.2
A
TPS56C231L current limit (low-side
sourcing)
ILIM-1 option, valley current
9.775
11.5
13.225
A
ILIM option, valley current
11.73
13.8
15.87
A
TPS56C231 current limit (low-side
negative)
Valley current
4.9
A
TPS56C231L current limit (low-side
negative)
Valley current
4
A
POWER GOOD
VPGOODTH
PGOOD threshold
VFB falling (fault)
84%
VFB rising (good)
93%
VFB rising (fault)
116%
VFB falling (good)
108%
Delay from low to high
128
µs
Delay form high to low
14
µs
tPGOODLY
PGOOD delay time
VPG_L
PGOOD sink current
IOL = 4 mA
IPGLK
PGOOD leak current
VPGOOD = 5.5 V
0.4
V
1
uA
OUTPUT UNDERVOLTAGE AND OVERVOLTAGE PROTECTION
VOVP
Output OVP threshold
OVP detect
121%
TOVPDEL
Output OVP response delay
VUVP
Output UVP threshold
tUVPDGL
UVP prop deglitch
1
ms
tUVPDEL
Output hiccup delay relative to SS time
UVP detect
1
cycle
tUVPEN
Output hiccup enable delay relative to SS
time
UVP detect
7
cycle
52
Hiccup detect
µs
70%
THERMAL SHUTDOWN
TSDN
(1)
6
Thermal shutdown threshold(1)
Shutdown temperature
Hysteresis
160
°C
15
°C
Not production tested
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6.6 Typical Characteristics
154
11.5
152
11
150
10.5
IVINSDN (uA)
Non-switching Current (uA)
TJ = –40°C to 125°C, VIN = 12 V(unless otherwise noted)
148
146
10
9.5
144
9
142
8.5
140
-40
-20
0
20
40
60
80
100
Junction Temperature (°C)
120
8
-40
140
Figure 6-1. Quiescent Current vs Temperature
0
20
40
60
80
100
Junction Temperature (°C)
120
140
Figure 6-2. Shutdown Current vs Temperature
10.5
0.602
10
High-side RDS(ON) (mohm)
0.601
Reference Voltage (V)
-20
0.6
0.599
0.598
0.597
0.596
0.595
9.5
9
8.5
8
7.5
7
6.5
0.594
-40
-20
0
20
40
60
80
100
Junction Temperature (°C)
120
6
-40
140
Figure 6-3. Reference Voltage vs Temperature
-20
0
20
40
60
80
100
Junction Temperature (°C)
120
140
Figure 6-4. High-Side RDS(on) vs Temperature
4.5
6.1
6
4.1
3.9
3.7
ISS (uA)
Low-side RDS(ON) (mohm)
4.3
3.5
3.3
5.9
5.8
3.1
5.7
2.9
2.7
2.5
-40
-20
0
20
40
60
80
100
Junction Temperature (°C)
120
Figure 6-5. Low-Side RDS(on) vs Temperature
140
5.6
-40
-20
0
20
40
60
80
100
Junction Temperature (°C)
120
140
Figure 6-6. Soft-Start Charge Current vs Temperature
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6.6 Typical Characteristics (continued)
3.1
5.1
2.8
4.8
2.5
4.5
IENp2 (uA)
IENp1 (uA)
TJ = –40°C to 125°C, VIN = 12 V(unless otherwise noted)
2.2
1.9
4.2
3.9
1.6
3.6
1.3
3.3
1
-40
-20
0
20
40
60
80
100
Junction Temperature (°C)
120
3
-40
140
Figure 6-7. Enable Pullup Current, VEN = 1 V
20
40
60
80
100
Junction Temperature (°C)
120
140
16
ILIM
ILIM-1
18
17
16
15
14
13
-20
0
20
40
60
80
100
Junction Temperature (°C)
120
Low-side Valley Current Limit (A)
Low-side Valley Current Limit (A)
0
Figure 6-8. Enable Pullup Current, VEN = 1.3 V
19
12
-40
-20
14
13
12
11
10
9
-40
140
Figure 6-9. TPS56C231 Current Limit vs Temperature
ILIM
ILIM-1
15
-20
0
20
40
60
80
100
Junction Temperature (°C)
120
140
Figure 6-10. TPS56C231L Current Limit vs Temperature
100
100
90
95
90
80
Efficiency (%)
Efficiency (%)
85
70
60
50
80
75
70
65
40
60
30
20
0.001
VIN=5V, V OUT=1.2V, 400kHz
VIN=12V, V OUT=1.2V, 400kHz
50
0.01
0.1
1
Output Current (A)
10 20
Figure 6-11. Efficiency, DCM Mode, fSW = 400 kHz
8
VIN=5V, V OUT=1.2V, 400kHz
VIN=12V, V OUT=1.2V, 400kHz
55
0
1
2
3
4
5
6
7
8
Output Current (A)
9
10
11
12
Figure 6-12. Efficiency, FCCM Mode, fSW = 400 kHz
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6.6 Typical Characteristics (continued)
TJ = –40°C to 125°C, VIN = 12 V(unless otherwise noted)
100
100
90
95
90
80
Efficiency (%)
Efficiency (%)
85
70
60
50
80
75
70
65
40
60
30
20
0.001
VIN=5V, V OUT=1.2V, 800kHz
VIN=12V, V OUT=1.2V, 800kHz
VIN=5V, V OUT=1.2V, 800kHz
VIN=12V, V OUT=1.2V, 800kHz
55
50
0.01
0.1
1
Output Current (A)
10 20
0
Figure 6-13. Efficiency, DCM Mode, fSW = 800 kHz
1
2
3
4
5
6
7
8
Output Current (A)
9
10
11
12
Figure 6-14. Efficiency, FCCM Mode, fSW = 800 kHz
100
100
90
95
90
80
Efficiency (%)
Efficiency (%)
85
70
60
50
80
75
70
65
40
60
30
20
0.001
VIN=5V, V OUT=1.2V, 1200kHz
VIN=12V, V OUT=1.2V, 1200kHz
VIN=5V, V OUT=1.2V, 1200kHz
VIN=12V, V OUT=1.2V, 1200kHz
55
50
0.01
0.1
1
Output Current (A)
10 20
0
Figure 6-15. Efficiency, DCM Mode, fSW = 1200 kHz
1
2
3
4
5
6
7
8
Output Current (A)
9
10
11
12
Figure 6-16. Efficiency, FCCM Mode, fSW = 1200 kHz
100
100
90
95
90
80
Efficiency (%)
Efficiency (%)
85
70
60
50
80
75
70
65
40
VIN=12V, V OUT=1.2V, 400kHz
VIN=12V, V OUT=3.3V, 400kHz
VIN=12V, V OUT=5V, 400kHz
30
20
0.001
60
VIN=12V, V OUT=1.2V, 400kHz
VIN=12V, V OUT=3.3V, 400kHz
VIN=12V, V OUT=5V, 400kHz
55
50
0.01
0.1
1
Output Current (A)
10 20
Figure 6-17. Efficiency, DCM Mode, fSW = 400 kHz
0
1
2
3
4
5
6
7
8
Output Current (A)
9
10
11
12
Figure 6-18. Efficiency, FCCM Mode, fSW = 400 kHz
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6.6 Typical Characteristics (continued)
TJ = –40°C to 125°C, VIN = 12 V(unless otherwise noted)
100
100
90
95
90
80
Efficiency (%)
Efficiency (%)
85
70
60
50
75
70
65
40
60
VIN=12V, V OUT=1.2V, 800kHz
VIN=12V, V OUT=3.3V, 800kHz
VIN=12V, V OUT=5V, 800kHz
30
20
0.001
80
VIN=12V, V OUT=1.2V, 800kHz
VIN=12V, V OUT=3.3V, 800kHz
VIN=12V, V OUT=5V, 800kHz
55
50
0.01
0.1
Output Current (A)
1
10 20
0
Figure 6-19. Efficiency, DCM Mode, fSW = 800 kHz
1
2
3
4
5
6
7
8
Output Current (A)
9
10
11
12
Figure 6-20. Efficiency, FCCM Mode, fSW = 800 kHz
100
100
90
95
90
80
Efficiency (%)
Efficiency (%)
85
70
60
50
80
75
70
65
40
20
0.001
60
VIN=12V, V OUT=1.2V, 1200kHz
VIN=12V, V OUT=3.3V, 1200kHz
VIN=12V, V OUT=5V, 1200kHz
30
VIN=12V, V OUT=1.2V, 1200kHz
VIN=12V, V OUT=3.3V, 1200kHz
VIN=12V, V OUT=5V, 1200kHz
55
50
0.01
0.1
1
Output Current (A)
10 20
0
Figure 6-21. Efficiency, DCM Mode, fSW = 1200 kHz
1
2
3
4
5
6
7
8
Output Current (A)
9
10
11
12
Figure 6-22. Efficiency, FCCM Mode, fSW = 1200 kHz
1.208
100
90
1.206
Output Voltage (V)
Efficiency (%)
80
70
60
50
40
30
20
10
0.001
Ext-5VCC, VIN=5V, V OUT=1.2V, 800kHz
Ext-5VCC, VIN=12V, V OUT=1.2V, 800kHz
Internal 5VCC, VIN=5V, V OUT=1.2V, 800kHz
Internal 5VCC, VIN=12V, V OUT=1.2V, 800kHz
0.01
0.1
1
Output Current (A)
10 20
Figure 6-23. Efficiency, Ext-VCC vs Internal-VCC, DCM Mode,
fSW = 800 kHz
10
1.204
1.202
1.2
1.198
VIN=5V, V OUT=1.2V
VIN=12V, V OUT=1.2V
1.196
0
1
2
3
4
5
6
7
8
Output Current (A)
9
10
11
12
Figure 6-24. Load Regulation, fSW = 800 kHz
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6.6 Typical Characteristics (continued)
TJ = –40°C to 125°C, VIN = 12 V(unless otherwise noted)
450
900
VIN=5V, V OUT=1.2V
VIN=12V, V OUT=1.2V
400
700
Frequency (kHz)
Frequency (kHz)
350
300
250
200
150
600
500
400
300
100
200
50
100
0
0.001
0.01
0.1
1
Output Current (A)
0
0.001
10 20
Figure 6-25. fSW Load Regulation, DCM Mode, fSW = 400 kHz
0.01
0.1
1
Output Current (A)
10 20
Figure 6-26. fSW Load Regulation, DCM Mode, fSW = 800 kHz
1200
600
VIN=5V, V OUT=1.2V
VIN=12V, V OUT=1.2V
550
Frequency (kHz)
1000
Frequency (kHz)
VIN=5V, V OUT=1.2V
VIN=12V, V OUT=1.2V
800
800
600
400
200
500
450
400
350
0
0.001
VIN=5V, V OUT=1.2V
VIN=12V, V OUT=1.2V
300
0.01
0.1
1
Output Current (A)
10 20
Figure 6-27. fSW Load Regulation, DCM Mode, fSW = 1200 kHz
0
1
2
3
4
5
6
7
8
Output Current (A)
9
10
11
12
Figure 6-28. fSW Load Regulation, FCCM Mode, fSW = 400 kHz
900
1200
850
1150
1100
Frequency (kHz)
Frequency (kHz)
800
750
700
650
1050
1000
950
900
850
600
800
550
VIN=5V, V OUT=1.2V
VIN=12V, V OUT=1.2V
500
VIN=5V, V OUT=1.2V
VIN=12V, V OUT=1.2V
750
700
0
1
2
3
4
5
6
7
8
Output Current (A)
9
10
11
12
Figure 6-29. fSW Load Regulation, FCCM Mode, fSW = 800 kHz
0
1
2
3
4
5
6
7
8
Output Current (A)
9
10
11
12
Figure 6-30. fSW Load Regulation, FCCM Mode, fSW = 1200 kHz
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6.6 Typical Characteristics (continued)
600
900
550
850
500
800
Frequency (kHz)
Frequency (kHz)
TJ = –40°C to 125°C, VIN = 12 V(unless otherwise noted)
450
400
350
300
650
VIN=12V, V OUT=1.2V
VIN=12V, V OUT=3.3V
VIN=12V, V OUT=5V
550
200
500
0
1
2
3
4
5
6
7
8
Output Current (A)
9
10
11
12
Figure 6-31. fSW Load Regulation, FCCM Mode, fSW = 400 kHz
0
1
2
3
4
5
6
7
8
Output Current (A)
9
10
11
12
Figure 6-32. fSW Load Regulation, FCCM Mode, fSW = 800 kHz
1300
500
1200
400
Frequency (kHz)
Frequency (kHz)
700
600
VIN=12V, V OUT=1.2V
VIN=12V, V OUT=3.3V
VIN=12V, V OUT=5V
250
1100
1000
900
700
0
1
2
3
4
5
6
7
8
Output Current (A)
9
10
11
200
0.01
0.1
1
Output Current (A)
10 20
Figure 6-34. fSW Load Regulation, DCM Mode, fSW = 400 kHz
1000
1400
VIN=12V, V OUT=1.2V
VIN=12V, V OUT=3.3V
VIN=12V, V OUT=5V
1200
Frequency (kHz)
800
300
0
0.001
12
Figure 6-33. fSW Load Regulation, FCCM Mode, fSW = 1200 kHz
VIN=12V, V OUT=1.2V
VIN=12V, V OUT=3.3V
VIN=12V, V OUT=5V
100
VIN=12V, V OUT=1.2V
VIN=12V, V OUT=3.3V
VIN=12V, V OUT=5V
800
Frequency (kHz)
750
600
400
VIN=12V, V OUT=1.2V
VIN=12V, V OUT=3.3V
VIN=12V, V OUT=5V
1000
800
600
400
200
200
0
0.001
0.01
0.1
1
Output Current (A)
10 20
Figure 6-35. fSW Load Regulation, DCM Mode, fSW = 800 kHz
12
0
0.001
0.01
0.1
1
Output Current (A)
10 20
Figure 6-36. fSW Load Regulation, DCM Mode, fSW = 1200 kHz
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7 Detailed Description
7.1 Overview
The TPS56C231x is a high-density, synchronous step-down buck converter that can operate from 3.8-V to 17-V
input voltage (VIN). The device has 7.8-mΩ and 3.2-mΩ integrated MOSFETs that enable high efficiency up
to 12 A. The device employs D-CAP3 control mode that provides fast transient response with no external
compensation components and an accurate feedback voltage. The control topology provides a seamless
transition between FCCM operating mode at higher load condition and Eco-mode operation at lighter load
condition. Eco-mode allows the TPS56C231x to maintain high efficiency at light load. The TPS56C231x can
adapt to both low equivalent series resistance (ESR) output capacitors such as POSCAP or SP-CAP, and
ultra-low ESR ceramic capacitors.
The TPS56C231x has three selectable switching frequencies (fSW): 400 kHz, 800 kHz, and 1200 kHz. These
frequencies give the flexibility to optimize the design for higher efficiency or smaller size. There are two
selectable current limits. All these options are configured by choosing the right voltage on the MODE pin. The
TPS56C231 has higher OCP to support higher peak current requirement.
The TPS56C231x has a 4.7-V internal LDO that creates bias for all internal circuitry. There is a feature to
overdrive this internal LDO with an external voltage on the VREG5 pin, which improves the efficiency of the
converter. The undervoltage lockout (UVLO) circuit monitors the VREG5 pin voltage to protect the internal
circuitry from low input voltages. The device has an internal pullup current source on the EN pin, which can
enable the device even with the pin floating.
Soft-start time can be selected by connecting a capacitor to the SS pin. The device is protected from output
short, undervoltage, and overtemperature conditions.
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7.2 Functional Block Diagram
PG high
threshold
UV threshold
+
PGOOD
+
UV
PG Logic
+
OV
+
PG low
threshold
VIN
OV threshold
+
Vref
+
VREGOK
LDO
VREG5
UVLO
+
+PWM
FB
SS
BOOT
Internal SS
+
Control Logic
VIN
SS
On/Off time
Minimum On/Off
Internal/External VREG5
OVP/UVP/TSD
FCCM/SKIP
Soft-Start
PGOOD
Ripple injection
SW
One Shot
SW
XCON
PGND
Ip1
Ih
+
+
EN
OCL
+
Mode
ZC
Light Load Operation/
Current Limit/
Switching Frequency
+
NOCL
OT threshold
+
THOK
Discharge Control
14
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7.3 Feature Description
7.3.1 PWM Operation and D-CAP3 Control Mode
The TPS56C231x operates using the adaptive on-time PWM control with a proprietary D-CAP3 control mode,
which enables low external component count with a fast load transient response while maintaining a good output
voltage accuracy. At the beginning of each switching cycle, the high-side MOSFET is turned on for an on time
set by an internal one-shot timer. This on time is set based on the input voltage of the converter, output voltage
of the converter, and the pseudo-fixed frequency, hence this type of control topology is called an adaptive
on-time control. The one-shot timer resets and turns on again once the feedback voltage (VFB) falls below the
internal reference voltage (VREF). An internal ramp is generated, which is fed to the FB pin to simulate the output
voltage ripple, enabling the use of very low-ESR output capacitors such as multi-layered ceramic caps (MLCC).
No external current sense network or loop compensation is required for D-CAP3 control mode topology.
The TPS56C231x includes an error amplifier that makes the output voltage very accurate. This error amplifier is
absent in other flavors of D-CAP3 control mode. For any control topology that is compensated internally, there is
a range of the output filter it can support. The output filter used with the TPS56C231x is a low-pass L-C circuit.
This L-C filter has double pole that is described in Equation 1.
¦P =
1
2 ´ p ´ LOUT ´ COUT
(1)
At low frequencies, the overall loop gain is set by the output set-point resistor divider network and the internal
gain of the TPS56C231x. The low frequency L-C double pole has a 180 degree in-phase. At the output filter
frequency, the gain rolls off at a –40 dB per decade rate and the phase drops rapidly. The internal ripple
generation network introduces a high-frequency zero that reduces the gain roll off from –40 dB to –20 dB per
decade and increases the phase to 90 degree one decade above the zero frequency. The internal ripple injection
high frequency zero is changed according to the switching frequency selected as shown in Table 7-1. The
inductor and capacitor selected for the output filter must be such that the double pole is located close enough to
the high-frequency zero so that the phase boost provided by this high-frequency zero provides adequate phase
margin for the stability requirement. The crossover frequency of the overall system usually must be targeted to
be less than one-fifth of the switching frequency (fSW).
Table 7-1. Ripple Injection Zero
Switching Frequency (kHz)
Zero Location (kHz)
400
17.8
800
27.1
1200
29.8
7.3.2 Eco-mode Control
The TPS56C231x is designed with Eco-mode control to increase efficiency at light loads. This option can be
chosen using the MODE pin as shown in Table 7-2. As the output current decreases from heavy load condition,
the inductor current is also reduced. If the output current is reduced enough, the valley of the inductor current
reaches the zero level, which is the boundary between continuous conduction and discontinuous conduction
modes. The low-side MOSFET is turned off when a zero inductor current is detected. As the load current further
decreases, the converter runs into discontinuous conduction mode. The on time is kept approximately the same
as it is in continuous conduction mode. The off time increases as it takes more time to discharge the output
with a smaller load current. Use Equation 2 to calculate the light load current where the transition to Eco-mode
operation happens (IOUT(LL)).
IOUT(LL) =
1
2 × LOUT × FSW
×
(VIN -VOUT ) × VOUT
VIN
(2)
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After identifying the application requirements, design the output inductance (LOUT) so that the inductor peak-topeak ripple current is approximately between 20% and 30% of the IOUT(ma×) (peak current in the application).
Size the inductor properly so that the valley current does not hit the negative low-side current limit.
7.3.3 4.7-V LDO
The VREG5 pin is the output of the internal 4.7-V linear regulator that creates the bias for all the internal circuitry
and MOSFET gate drivers. The VREG5 pin must be bypassed with a 4.7-µF capacitor. An external voltage that
is above the internal output voltage of the LDO can override the internal LDO, switching it to the external rail
after a higher voltage is detected. This action enhances the efficiency of the converter because the quiescent
current now runs off this external rail instead of the input power supply. The UVLO circuit monitors the VREG5
pin voltage and disables the output when VREG5 falls below the UVLO threshold. When using an external bias
on the VREG5 rail, any power-up and power-down sequencing can be applied but it is important to understand
that if there is a discharge path on the VREG5 rail that can pull a current higher than the internal current
limit of the LDO (ILIM5) from the VREG5, then the VREG5 LDO turns off thereby, shutting down the output of
TPS56C231x. If such condition does not exist and if the external VREG5 rail is turned off, the VREG5 voltage
switches over to the internal LDO voltage, which is 4.7 V typically in a few nanoseconds.
7.3.4 MODE Selection
The TPS56C231x has a MODE pin that can offer 12 different states of operation as a combination of current
limit, switching frequency, and light load operation. The device can operate at two different current limits (ILIM-1
and ILIM) to support an output continuous current of 12 A, respectively.
The TPS56C231x is designed to compare the valley current of the inductor against the current limit thresholds,
so make sure to understand that the output current is half the ripple current higher than the valley current. Take
the TPS56C231 as an example, with the ILIM current limit selection, the OCL threshold is 14 A minimum, which
means that a pk-pk inductor ripple current of 2 A minimum is needed to draw 15 A out of the converter without
entering an overcurrent condition.
The TPS56C231x can operate at three different frequencies of 400 kHz, 800 kHz, and 1200 kHz and also
can choose between Eco-mode and FCCM mode. In Eco-mode, TPS56C231x works in DCM (discontinuous
conduction mode) with high efficiency in light loading. In FCCM mode, TPS56C231x works in forced PWM
(forced continuous conduction mode) with tight output voltage ripple. The device reads the voltage on the MODE
pin during start-up and latches onto one of the MODE options listed in Table 7-2. The voltage on the MODE pin
can be set by connecting this pin to the center tap of a resistor divider connected between VREG5 and AGND.
A guideline for the top resistor (RM_H) and the bottom resistor (RM_L) in 1% resistors is shown in Table 7-2.
Ensure that the voltage for the MODE pin is derived from the VREG5 rail only because, internally, this voltage is
referenced to detect the MODE option. The MODE pin setting can be reset only by a VIN power cycling.
Table 7-2. MODE Pin Resistor Settings
16
RM_L (kΩ)
RM_H (kΩ)
Light Load
Operation
Current Limit
Frequency (kHz)
5.1
300
FCCM
ILIM-1
400
10
200
FCCM
ILIM
400
20
160
FCCM
ILIM-1
800
20
120
FCCM
ILIM
800
51
200
FCCM
ILIM-1
1200
51
180
FCCM
ILIM
1200
51
150
DCM
ILIM-1
400
51
120
DCM
ILIM
400
51
91
DCM
ILIM-1
800
51
82
DCM
ILIM
800
51
62
DCM
ILIM-1
1200
51
51
DCM
ILIM
1200
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Figure 7-1 shows the typical start-up sequence of the device after the EN pin voltage crosses the EN turn-on
threshold. After the voltage on VREG5 pin crosses the rising UVLO threshold, it takes 144 μs to read the first
MODE setting and a maximum of approximately 180 μs from accomplishing MODE to soft start. The output
voltage starts ramping after the MODE setting reading is completed.
VIN
EN Threshold
1.225 V for Buck
EN
EN Threshold
0.8 V for VREG5
UVLO
VREG5
tss (1.2ms)
MODE
144us
180us
1ms
VOUT
PGOOD
Figure 7-1. Power-Up Sequence
7.3.5 Soft Start and Prebiased Soft Start
The TPS56C231x has an internal 1.2-ms soft-start time and an external adjustable soft-start time that can be
set by connecting a capacitor on the SS pin. When the EN pin becomes high, the soft-start charge current (ISS)
begins charging the external capacitor (CSS) connected between SS and AGND. The device tracks the lower of
the internal soft-start voltage or the external soft-start voltage as the reference. Equation 3 is the equation for the
soft-start time (tSS):
TSS(S) =
CSS × VREF
ISS
(3)
where
•
VREF is 0.6 V and ISS is 6 µA.
If the output capacitor is prebiased at start-up, the device initiates switching and starts ramping up only after
the internal reference voltage becomes greater than the feedback voltage, VFB. This scheme ensures that the
converters ramp up smoothly into the regulation point.
7.3.6 Enable and Adjustable UVLO
The EN pin controls the turn-on and turn-off of the device. When EN pin voltage is above the turn-on threshold,
which is approximately 1.2 V, the device starts switching and when the EN pin voltage falls below the turn-off
threshold, which is approximately 1.1 V, it stops switching. If the user application requires a different turn-on
(VSTART) and turn-off thresholds (VSTOP), respectively, the EN pin can be configured as shown in Figure 7-2 by
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connecting a resistor divider between VIN and EN. The EN pin has a pullup current, Ip1, that sets the default
state of the pin when it is floating. This current increases to Ip2 when the EN pin voltage crosses the turn-on
threshold. Use Equation 4 and Equation 5 to set the UVLO thresholds.
IC
VIN
R1
R2
Ip1
Ih
EN
Figure 7-2. Adjustable VIN Undervoltage Lockout
æV
ö
VSTART ç ENFALLING ÷ - VSTOP
V
è ENRISING ø
R1 =
æ VENFALLING ö
Ip1 ç1 ÷ + Ih
VENRISING ø
è
R2 =
(4)
R1´ VENFALLING
VSTOP - VENFALLING + R1 Ip2
(5)
where
•
•
•
•
•
Ip2 is 4.197 μA.
Ip1 is 1.91 μA.
Ih is 2.287 μA.
VENRISING is 1.225 V.
VENFALLING is 1.104 V.
7.3.7 Power Good
The power-good (PGOOD) pin is an open-drain output. After the FB pin voltage is between 93% and 108%
of the internal reference voltage (VREF), PGOOD is de-asserted and floats after a 14-µs de-glitch time. TI
recommends a 10-kΩ pullup resistor to pull it up to VREG5. The PGOOD pin is pulled low when the FB pin
voltage is lower than VUVP or greater than VOVP threshold, in an event of thermal shutdown, or during the
soft-start period.
7.3.8 Overcurrent Protection and Undervoltage Protection
The output overcurrent limit (OCL) is implemented using a cycle-by-cycle valley detect control circuit. The switch
current is monitored during the off state by measuring the low-side FET drain-to-source voltage. This voltage is
proportional to the switch current. During the on time of the high-side FET switch, the switch current increases at
a linear rate determined by:
•
•
•
18
Input voltage
Output voltage
On time
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Output inductor value
During the on time of the low-side FET switch, this current decreases linearly. The average value of the switch
current is the load current IOUT. If the measured drain-to-source voltage of the low-side FET is above the voltage
proportional to current limit, the low-side FET stays on until the current level becomes lower than the OCL level,
which reduces the output current available. When the current is limited, the output voltage tends to drop because
the load demand is higher than what the converter can support. When the output voltage falls below 70% of the
target voltage, the UVP comparator detects it and shuts down the device after a wait time of 1 ms, the device
restarts after a 7-ms hiccup time. In this type of valley detect control, the load current is higher than the OCL
threshold by one half of the peak-to-peak inductor ripple current. When the overcurrent condition is removed,
the output voltage returns to the regulated value. If an OCL condition happens during start-up, then the device
enters hiccup-mode immediately without a 1-ms wait time.
7.3.9 UVLO Protection
Undervoltage lockout protection (UVLO) monitors the internal VREG5 regulator voltage. When the VREG5
voltage is lower than UVLO threshold voltage, the device is shut off. This protection is non-latching.
7.3.10 Thermal Shutdown
The device monitors the internal die temperature. If this temperature exceeds the thermal shutdown threshold
value (TSDN typically 160°C), the device shuts off. This protection is a non-latch protection. During start-up, if
the device temperature is higher than 160°C, the device does not start switching and does not load the MODE
settings. If the device temperature goes higher than TSDN threshold after start-up, it stops switching with SS
reset to ground and an internal discharge switch turns on to quickly discharge the output voltage. The device
re-starts switching when the temperature goes below the thermal shutdown threshold but the MODE settings are
not re-loaded again.
7.3.11 Output Voltage Discharge
The device has a 370-Ω discharge switch that discharges the output VOUT through the SW node during any
event of fault like output overvoltage, output undervoltage, TSD, and if VREG5 voltage below the UVLO, and
when the EN pin voltage (VEN) is below the turn-on threshold.
7.4 Device Functional Modes
7.4.1 Light Load Operation
When the MODE pin is selected to operate in FCCM mode, the converter operates in continuous conduction
mode (FCCM) during light-load conditions. During FCCM, the switching frequency (fSW) is maintained at an
almost constant level over the entire load range, which is suitable for applications requiring tight control of the
switching frequency and output voltage ripple at the cost of lower efficiency under light load. If the MODE pin is
selected to operate in Eco-mode, the device enters pulse skip mode after the valley of the inductor ripple current
crosses zero. The Eco-mode maintains higher efficiency at light load with a lower switching frequency.
7.4.2 Standby Operation
The TPS56C231x can be placed in standby mode by pulling the EN pin low. The device operates with a
shutdown current of approximately 9 μA when in standby condition.
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8 Application and Implementation
Note
Information in the following applications sections is not part of the TI component specification,
and TI does not warrant its accuracy or completeness. TI’s customers are responsible for
determining suitability of components for their purposes, as well as validating and testing their design
implementation to confirm system functionality.
8.1 Application Information
The schematic of Figure 8-1 shows a typical application for the TPS56C231x. This design converts an input
voltage range of 4.5 V to 17 V down to 1.2 V with a maximum output current of 12 A.
8.2 Typical Application
U1
VIN = 4.5 V - 17 V
VIN
VIN
C1
0.1µF
C2
0.1µF
C3
22µF
C4
22µF
2
11
C5
22µF
C6
22µF
EN
15
VIN
VIN
EN
BOOT
SW
SW
1
R10
6
7
C9
0
0.1µF
L1
VOUT
SW
R3
PG
16
PGOOD
10.0k
R4
82.0k
C8
4.7uF
R5
51.0k
FB
VREG5
17
MODE
18
SS
14
0.047µF
C7
VREG5
MODE
PGND
PGND
PGND
PGND
PGND
PGND
SS
AGND
13
FB
3
4
5
8
9
10
R6
0
R7
10.0k
R8
0
VOUT = 1.2 V
VOUT
680nH
C11
47µF
C12
47µF
C13
47µF
C14
47µF
C10
56pF
R9
10.0k
12
Figure 8-1. Application Schematic
8.2.1 Design Requirements
Table 8-1. Design Parameters
Parameter
Conditions
Min
Typ
Max
Unit
VOUT
Output voltage
1.2
IOUT
Output current
12
A
ΔVOUT
Transient response
40
mV
VIN
Input voltage
VOUT(ripple)
Output voltage ripple
fSW
4.5
20
17
V
mV(P-P)
Start input voltage
Input voltage rising
Internal
UVLO
V
Stop input voltage
Input voltage falling
Internal
UVLO
V
Switching frequency
800
Operating mode
TA
12
V
kHz
DCM
Ambient temperature
25
°C
8.2.2 Detailed Design Procedure
8.2.2.1 External Component Selection
8.2.2.1.1 Output Voltage Set Point
To change the output voltage of the application, change the value of the upper feedback resistor. By changing
this resistor, the user can change the output voltage above 0.6 V. See Equation 6.
20
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æ
ö
R
VOUT = 0.6 ´ ç 1 + UPPER ÷
è RLOWER ø
(6)
8.2.2.1.2 Switching Frequency and MODE Selection
Switching frequency, current limit, and switching mode (DCM or FCCM) are set by a voltage divider from VREG5
to GND connected to the MODE pin. See Table 7-2 for possible MODE pin configurations. Switching frequency
selection is a trade-off between higher efficiency and smaller system solution size. Lower switching frequency
yields higher overall efficiency but relatively bigger external components. Higher switching frequencies cause
additional switching losses, which impact efficiency and thermal performance. For this design, 800 kHz is chosen
as the switching frequency. The switching mode is DCM and the output current is 12 A.
8.2.2.1.3 Inductor Selection
The inductor ripple current is filtered by the output capacitor. A higher inductor ripple current means the
output capacitor must have a ripple current rating higher than the inductor ripple current. See Table 8-2 for
recommended inductor values.
Use Equation 7 and Equation 8 to calculate the RMS and peak currents through the inductor. Make sure that the
inductor is rated to handle these currents.
2ö
æ
1 æ VOUT × (VIN(max) - VOUT )ö ÷
ç
2
÷
IL(rms)= ç I OUT + × ç
12 ç VIN(max) × LOUT × FSW ÷ ÷÷
ç
è
ø ø
è
IL(peak) = IOUT +
(7)
IOUT(ripple)
(8)
2
During transient, short-circuit conditions, the inductor current can increase up to the current limit of the device,
so it is safe to choose an inductor with a saturation current higher than the peak current under current limit
condition.
8.2.2.1.4 Output Capacitor Selection
After selecting the inductor, the output capacitor must be optimized. In D-CAP3 control mode, the regulator
reacts within one cycle to the change in the duty cycle so the good transient performance can be achieved
without needing large amounts of output capacitance. Table 8-2 gives the recommended output capacitance
range.
Ceramic capacitors have very low ESR, otherwise the maximum ESR of the capacitor must be less than
VOUT(ripple) / IOUT(ripple).
Table 8-2. Recommended Component Values
VOUT (V)
0.6
1.2
3.3
RLOWER (kΩ)
RUPPER (kΩ)
10
10
10
0
10
45.3
fSW (kHz)
LOUT (µH)
COUT(min) (µF)
COUT(max) (µF)
CFF (pF)
400
0.68
300
500
—
800
0.47
100
500
—
1200
0.33
88
500
—
400
1.2
100
500
—
800
0.68
88
500
—
1200
0.47
88
500
—
400
2.4
88
500
100 – 220
800
1.5
88
500
100 – 220
1200
1.2
88
500
100 – 220
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Table 8-2. Recommended Component Values (continued)
VOUT (V)
5.5
RLOWER (kΩ)
RUPPER (kΩ)
10
82.5
fSW (kHz)
LOUT (µH)
COUT(min) (µF)
COUT(max) (µF)
CFF (pF)
400
3.3
88
500
100 – 220
800
2.4
88
500
100 – 220
1200
1.5
88
700
100 – 220
8.2.2.1.5 Input Capacitor Selection
Equation 9 gives the minimum input capacitance required.
CIN(min) =
IOUT ×VOUT
VINripple ×VIN ×FSW
(9)
TI recommends using a high quality X5R or X7R input decoupling capacitors of 40 µF on the input voltage pin.
The voltage rating on the input capacitor must be greater than the maximum input voltage. The capacitor must
also have a ripple current rating greater than the maximum input current ripple of the application. Use Equation
10 to calculate the input ripple current:
ICIN(rms) = IOUT ×
22
(VIN(min)-VOUT )
VOUT
×
VIN(min)
VIN(min)
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8.2.3 Application Curves
VIN = 12 V. Ta = 25°C (unless otherwise specified).
100
1.206
90
1.205
1.204
Output Voltage (V)
Efficiency (%)
80
70
60
50
1.203
1.202
1.201
1.2
1.199
40
1.198
30
1.197
20
0.001
1.196
0.01
0.1
Output Current (A)
1
10 20
0
1
2
3
4
5
6
7
8
Output Current (A)
9
10
11
12
Figure 8-2. Efficiency
Figure 8-3. Load Regulation
Figure 8-4. Output Voltage Ripple, IOUT = 10 mA,
Time = 80 μS/div
Figure 8-5. Output Voltage Ripple, IOUT = 12 A,
Time = 1 μS/div
Figure 8-6. Start-Up Relative to EN Rising, Time = 2
ms/div
Figure 8-7. Shutdown Relative to EN Falling, Time
= 200 μS/div
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Figure 8-8. Transient Response, Load Step = 3 A – Figure 8-9. Transient Response, Load Step = 1.2 A
9 A – 3 A, Slew Rate Setting = 2.5 A/μS, Time = 100 – 10.8 A – 1.2 A, Slew Rate Setting = 2.5 A/μS, Time
uS/div
= 100 μS/div
8.3 Power Supply Recommendations
The TPS56C231x is intended to be powered by a well regulated DC voltage. The input voltage range is 3.8
V to 17 V. The TPS56C231x is a buck converter. The input supply voltage must be greater than the desired
output voltage for proper operation. Input supply current must be appropriate for the desired output current. If
the input voltage supply is located far from the TPS56C231x circuit, TI recommends some additional input bulk
capacitance. Typical values are 100 µF to 470 µF.
8.4 Layout
8.4.1 Layout Guidelines
•
•
•
•
•
•
•
•
•
24
Use a four-layer or six-layer PCB for good thermal performance and with maximum ground plane. 3-inch ×
3-inch, four-layer PCB with 2-oz. copper is used as an example.
VIN, PGND, and SW traces must be as wide as possible to reduce trace impedance and improve heat
dissipation.
Place equal capacitors on each side of the IC. Place them right from each VIN to PGND pin as close as
possible to the device on the same side of the PCB.
Use vias near both VIN pins and provide a low impedance connection between them through an internal
layer.
Use multiple vias near both PGND pins and use the layer directly below the device to connect them together,
which helps to minimize noise and can help heat dissipation.
Inner layer 1 is ground with the PGND to AGND net tie.
Inner layer 2 has VIN copper pour that has vias to the top layer VIN.
Bottom layer is GND with the BOOT trace routing.
Reference feedback to the quiet AGND and route away from the switch node. Also keep feedback resistors
and the feedforward capacitor near the IC.
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CFF
Rupper
8.4.2 Layout Example
PGND
PGND
PGND
PGND
PGND
Css
FB
VIN
AGND
Rlower
SS
SW
EN
SW
PG
RM_H
MO
DE
BOOT
PGND
VRE
G5
VIN
CVREG5
CB
T
RM_L
OOT
Top Line
VIN Plane
Bottom Line
SW Plane
GND Plane
VOUT Plane
Figure 8-10. Layout Example
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9 Device and Documentation Support
9.1 Device Support
9.1.1 Third-Party Products Disclaimer
TI'S PUBLICATION OF INFORMATION REGARDING THIRD-PARTY PRODUCTS OR SERVICES DOES NOT
CONSTITUTE AN ENDORSEMENT REGARDING THE SUITABILITY OF SUCH PRODUCTS OR SERVICES
OR A WARRANTY, REPRESENTATION OR ENDORSEMENT OF SUCH PRODUCTS OR SERVICES, EITHER
ALONE OR IN COMBINATION WITH ANY TI PRODUCT OR SERVICE.
9.2 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. Click on
Subscribe to updates to register and receive a weekly digest of any product information that has changed. For
change details, review the revision history included in any revised document.
9.3 Support Resources
TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight
from the experts. Search existing answers or ask your own question to get the quick design help you need.
Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do
not necessarily reflect TI's views; see TI's Terms of Use.
9.4 Trademarks
D-CAP3™, HotRod™, and TI E2E™ are trademarks of Texas Instruments.
All trademarks are the property of their respective owners.
9.5 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled
with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may
be more susceptible to damage because very small parametric changes could cause the device not to meet its published
specifications.
9.6 Glossary
TI Glossary
This glossary lists and explains terms, acronyms, and definitions.
10 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
26
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PACKAGE OPTION ADDENDUM
www.ti.com
12-Dec-2023
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
Samples
(4/5)
(6)
TPS56C231LRNNR
ACTIVE
VQFN-HR
RNN
18
3000
RoHS & Green
SN
Level-2-260C-1 YEAR
-40 to 125
C231L
Samples
TPS56C231RNNR
ACTIVE
VQFN-HR
RNN
18
3000
RoHS & Green
SN
Level-2-260C-1 YEAR
-40 to 125
56C231
Samples
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of
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