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TPS61251
SLVSAF7C – SEPTEMBER 2010 – REVISED APRIL 2019
TPS61251 Boost Converter for Battery Backup Charging With Adjustable Constant
Current and Snooze Mode
1 Features
2 Applications
•
•
1
•
•
•
•
•
•
•
•
•
•
•
•
Resistor Programmable Input Current Limit
– ±10% Current accuracy at 500 mA over full
temperature range
– Programmable from 100 mA up to 1500 mA
Snooze mode draws only 2 μA (typical) quiescent
current
Designed to charge large capacitor values in the
Farad range
Up to 92% Efficiency
Power good indicates appropriate output voltage
level even in shutdown
VIN range from 2.3 V to 6 V
Adjustable output voltage up to 6.5 V
100% Duty-cycle mode when VIN > VOUT
Load disconnect and reverse current protection
Short-circuit protection
Typical operating frequency 3.5 MHz
Available in a 2 × 2-mm WSON-8 package
Create a custom design using the TPS61251 with
the WEBENCH® Power Designer
Current limited applications with high peak power
loads (SSD, PCMCIA Tx bursts, memory,
GPRS/GSM Tx)
Li-Ion applications
Battery backup applications
Audio applications
RF-PA buffer
•
•
•
•
3 Description
The TPS61251 device provides a power supply
solution for products powered by either a three-cell,
NiCd or NiMH battery, or a one-cell Li-Ion or Lipolymer battery. The wide input voltage range is ideal
to power portable applications like mobile phones,
solid state drives (SSD) and wireless modems. The
converter is designed to charge large capacitors in
the Farad range to support battery back up
applications. During capacitor charging, the
TPS61251 device is working as a constant current
source until VOUT has reached its programmed value.
The charge current can be programmed by an
external resistor RILIM and provides a ±10% accuracy
for the 500-mA average input current limit.
Device Information(1)
PART NUMBER
TPS61251
PACKAGE
BODY SIZE (NOM)
WSON (8)
2.00 mm × 2.00 mm
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
Simplified Schematic
VOUT
L1
1 μH
VOUT
L
5.5 V
VIN
2.3 V to
6.0 V
R1
1 MΩ
VIN
C1
10 µF
EN
FB
CFF
1 nF
COUT
4.7 µF
CBULK
>150 µF
R4
1 MΩ
R2
280 kΩ
ILIM
RILIM
20 kΩ
GND
PG
Power Good
Output
TPS61251
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
TPS61251
SLVSAF7C – SEPTEMBER 2010 – REVISED APRIL 2019
www.ti.com
Table of Contents
1
2
3
4
5
6
7
8
9
Features ..................................................................
Applications ...........................................................
Description .............................................................
Revision History.....................................................
Description (Continued) ........................................
Device Options.......................................................
Pin Configuration and Functions .........................
Specifications.........................................................
1
1
1
2
3
3
4
5
8.1
8.2
8.3
8.4
8.5
8.6
5
5
5
5
6
6
Absolute Maximum Ratings ......................................
ESD Ratings..............................................................
Recommended Operating Conditions.......................
Thermal Information ..................................................
Electrical Characteristics...........................................
Typical Characteristics ..............................................
Detailed Description .............................................. 8
9.1 Overview ................................................................... 8
9.2 Functional Block Diagram ......................................... 9
9.3 Feature Description................................................... 9
9.4 Device Functional Modes........................................ 11
10 Application and Implementation........................ 12
10.1 Application Information.......................................... 12
10.2 Typical Application ............................................... 12
11 Power Supply Recommendations ..................... 18
12 Layout................................................................... 18
12.1 Layout Guidelines ................................................. 18
12.2 Layout Example .................................................... 18
12.3 Thermal Consideration.......................................... 19
13 Device and Documentation Support ................. 20
13.1
13.2
13.3
13.4
13.5
13.6
13.7
Device Support......................................................
Development Support ...........................................
Receiving Notification of Documentation Updates
Community Resource............................................
Trademarks ...........................................................
Electrostatic Discharge Caution ............................
Glossary ................................................................
20
20
20
20
20
20
21
14 Mechanical, Packaging, and Orderable
Information ........................................................... 21
4 Revision History
Changes from Revision B (July 2015) to Revision C
Page
•
Added "±10% accuracy for the 500-mA average input current limit" to Features and Description ........................................ 1
•
Added links for Webench ....................................................................................................................................................... 1
•
Added Receiving Notification of Documentation Updates ................................................................................................... 20
Changes from Revision A (May 2015) to Revision B
•
Deleted package suffix from device number in the Device Options table. ............................................................................ 3
Changes from Original (September 2010) to Revision A
•
2
Page
Page
Added ESD Ratings table, Feature Description section, Device Functional Modes, Application and Implementation
section, Power Supply Recommendations section, Layout section, Device and Documentation Support section, and
Mechanical, Packaging, and Orderable Information section ................................................................................................. 1
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5 Description (Continued)
The TPS61251 device in combination with a reservoir capacitor allows the converter to provide high current
pules that would exceed the capability of the suppling circuit (PC slot, USB) and keeps the slot power safely
within its capabilities. During light loads the device automatically enters an enhanced power save mode (snooze
mode), which allows the converter to maintain the required output voltage, while only drawing 2 μA from the
battery. This allows maximum efficiency at lowest quiescent currents.
TPS61251 device allows the use of small inductors and input capacitors to achieve a small solution size. During
shutdown, the load is completely disconnected from the battery and will not discharge either the battery nor the
charged bulk capacitor. The TPS61251 device is available in a 8-pin QFN package measuring 2 × 2 mm (DSG).
6 Device Options
(1)
(2)
OUTPUT VOLTAGE (1)
PART NUMBER (2)
Adjustable
TPS61251
Contact TI for other fixed output voltage options
For detailed ordering information check the Mechanical, Packaging,
and Orderable Information section at the end of this data sheet.
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7 Pin Configuration and Functions
DSG Package
8-Pin WSON
Top View
8 VIN
GND 1
FB 3
ILIM 4
d
ose d
Exp al Pa
rm
The
VOUT 2
7 SW
6 EN
5 PG
Pin Functions
PIN
NAME
NO.
I/O
DESCRIPTION
EN
6
I
Enable input (1 enabled, 0 disabled)
FB
3
I
Voltage feedback pin
GND
1
ILIM
4
I
Adjustable average input current limit. Can be connected to VIN for maximum current limit or to GND
for minimum current limit.
PG
5
O
Output power good (1 good, 0 failure; open drain)
SW
7
I
Connection for Inductor
VIN
8
I
Supply voltage for power stage
VOUT
2
O
Boost converter output
Exposed
Thermal Pad
4
Ground
Must be soldered to achieve appropriate power dissipation and for mechanical reasons. Must be
connected to GND.
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8 Specifications
8.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted) (1)
Voltage (2)
Temperature
(1)
(2)
MIN
MAX
UNIT
VIN, VOUT, SW, EN, PG, FB, ILIM
–0.3
7
V
Operating junction, TJ
–40
150
°C
Storage, Tstg
–65
150
°C
Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating
conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods my affect device reliability.
All voltages are with respect to network ground terminal.
8.2 ESD Ratings
VALUE
V(ESD)
(1)
(2)
Electrostatic discharge
Human body model (HBM), per ANSI/ESDA/JEDEC JS-001, all pins (1)
±2000
Charged device model (CDM), per JEDEC specification JESD22-C101, all
pins (2)
±500
UNIT
V
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
8.3 Recommended Operating Conditions
MIN
Supply voltage at VIN
NOM
MAX
UNIT
2.3
6
3
6.5
Programable input current limit set by RILIM
100
1500
mA
Operating free air temperature, TA
–40
85
°C
Operating junction temperature, TJ
–40
125
°C
Output voltage at VOUT
V
V
8.4 Thermal Information
TPS61251
THERMAL METRIC (1)
DSG (WSON)
UNIT
8 PINS
RθJA
Junction-to-ambient thermal resistance
80.2
°C/W
RθJCtop
Junction-to-case (top) thermal resistance
93.5
°C/W
RθJB
Junction-to-board thermal resistance
54.2
°C/W
ψJT
Junction-to-top characterization parameter
0.9
°C/W
ψJB
Junction-to-board characterization parameter
59.3
°C/W
RθJCbot
Junction-to-case (bottom) thermal resistance
20
°C/W
(1)
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
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8.5 Electrical Characteristics
Over recommended free air temperature range, typical values are at TA = 25°C. Unless otherwise noted, specifications apply
for condition VIN = EN = 3.6 V, VOUT = 5.5 V.
PARAMETER
VFB
TEST CONDITIONS
Feedback voltage
rDS(on)
TYP
MAX
UNIT
1.2
1.218
V
2.3 V ≤ VIN ≤ 6 V
Maximum line regulation
f
MIN
1.182
0.5%
Maximum load regulation
0.5%
Oscillator frequency
3500
kHz
200
mΩ
High side switch ON resistance
Low side switch ON resistance
130
Reverse leakage current into VOUT
EN = GND
ILIM pin set to VIN
IIN(DC)
Programmable input average switch current limit
mΩ
3.5
1500
ILIM pin set to GND
100
RILIM = 20 kΩ (500 mA)
–10%
Quiescent current
SNOOZE mode, IOUT = 0 mA, current into
VIN pin
ISD
Shutdown current (1)
VIN turned on when EN is connected to
GND and no voltage is present at VOUT
OVP
Input over voltage protection threshold
mA
10%
PFM enabled, device is not switching
IQ
µA
mA
30
µA
2
0.85
Falling
6.4
Rising
6.5
3.5
μA
V
CONTROL STAGE
Falling
VUVLO
Under voltage lockout threshold
VIL
EN input low voltage
2.3 V ≤ VIN ≤ 6 V
VIH
EN input high voltage
2.3 V ≤ VIN ≤ 6 V
EN, PG input leakage current
Clamped on GND or VIN
Power Good threshold voltage
2
Hysteresis
Rising referred to VFB
1
V
V
0.5
92.5%
V
V
0.4
µA
95% 97.5%
Falling referred to VOUT
2.3
Power good delay
(1)
2.1
0.1
V
50
µs
Overtemperature protection
140
°C
Overtemperature hysteresis
20
°C
When the power good threshold is triggered the first time a comparator is turned on to observe the output voltage increasing the
shutdown current.
8.6 Typical Characteristics
Table 1. Table Of Graphs
DESCRIPTION
Efficiency
FIGURE
vs Output current (VOUT = 5.5 V, ILIM = 1.5 A, R1 = 2320 kΩ and R2 = 649 kΩ)
Figure 1
vs Output current in 100% Duty-Cycle Mode (VOUT = 5.5V, ILIM = 1.5 A, R1 = 2320 kΩ
and R2 = 649 kΩ)
Figure 2
vs Input voltage (VOUT = 5.5 V, ILOAD = {0.01;0.1; 1.0; 10; 100; 500 mA}, R1 = 2320 kΩ
and R2 = 649 kΩ)
Figure 3
Maximum output current
vs Input voltage (VOUT = 5.5 V, ILIM = {100; 200; 500; 1000; 1500 mA}, R1 = 1000 kΩ
and R2 = 280 kΩ)
Figure 4
Output voltage
vs Output current (VOUT = 5.5 V, ILIM = 1.5 A, R1 = 1000 kΩ and R2 = 280 kΩ)
Figure 5
6
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100
100
VI = 3.6 V
VI = 4.2 V
90
90
80
80
VI = 5.5 V
VI = 3.3 V
VI = 6 V
VI = 2.3 V
70
VI = 2.7 V
60
Efficiency - %
Efficiency - %
70
50
40
30
60
50
40
30
20
20
VO = 5 V,
ILIM = max
10
0
0.00001
0.0001
0.001
0.01
0.1
IO - Output Current - A
0
0.00001
1
Figure 1. Efficiency vs Output Current
1.6
1.5
1.4
IO = 500 mA
90
80
1.3
1.2
IO - Output Current - A
IO = 0.1 mA
Efficiency - %
70
IO = 10 mA
50
IO = 100 mA
IO = 0.01 mA
IO = 1 mA
40
30
20
0
2.3
2.7
3.1
3.5 3.9 4.3 4.7 5.1
VI - Input Voltage - V
5.5
0.001
0.01
0.1
IO - Output Current - A
1
1.1
1
IO (I_Lim = 1.5 A)
IO (I_Lim = 1 A)
IO (I_Lim = 0.5 A)
0.9
0.8
IO (I_Lim = 0.2 A)
0.7
0.6
0.5
0.4
0.3
0.2
VO = 5 V,
ILIM = max
10
0.0001
Figure 2. Efficiency vs Output Current In 100% Duty-Cycle
Mode
100
60
VO = 5 V,
ILIM = max
10
IO (I_Lim = 0.1 A)
0.1
0
2.3
5.9
2.8
3.3
3.8
4.3
4.8
5.3
VI - Input Voltage - V
5.8
Figure 4. Maximum Output Current vs Input Voltage
Figure 3. Efficiency vs Input Voltage
5.6
5.575
VO - Output Voltage - V
5.55
5.525
VI = 2.3 V
VI = 2.7 V
VI = 3.3 V
5.5
5.475
VI = 3.6 V
VI = 4.2 V
5.45
5.425
5.4
0.000001 0.00001 0.0001 0.001
0.01
IO - Output Current - A
0.1
1
Figure 5. Output Voltage vs Output Current
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9 Detailed Description
9.1 Overview
The TPS61251 boost converter operates as a quasi-constant frequency adaptive on-time controller. In a typical
application the frequency is 3.5 MHz and is defined by the input to output voltage ratio and does not vary from
moderate to heavy load currents. At light load the converter automatically enters power-save mode and operates
in pulse frequency modulation (PFM) mode. During PWM operation the converter uses a unique fast response
quasi-constant on-time valley current mode controller scheme which offers excellent line and load regulation and
the use of small ceramic input capacitors.
Based on the VIN/VOUT ratio, a simple circuit predicts the required on-time. At the beginning of the switching
cycle, the low-side N-MOS switch is turned on and the inductor current ramps up to a peak current that is defined
by the on-time and the inductance. In the second phase, once the on-timer has expired, the rectifier is turned on
and the inductor current decays to a preset valley current threshold. Finally, the switching cycle repeats by
setting the on timer again and activating the low-side N-MOS switch.
The TPS61251 device directly and accurately controls the average input current through intelligent adjustment of
the valley current limit, allowing an accuracy of ±10% at 500-mA average input current. Together with an external
bulk capacitor the TPS61251 device allows an application to be interfaced directly to its load, without overloading
the input source due to appropriate set average input current limit.
High values of output capacitance are mainly achieved by putting capacitors in parallel. This reduces the overall
series resistance (ESR) to very low values. This results in almost no voltage ripple at the output and therefore
the regulation circuit has no voltage drop to react on. Nevertheless to ensure accurate output voltage regulation
even with very low ESR the regulation loop can switch to a pure comparator regulation scheme. During this
operation the output voltage is regulated between two thresholds. The upper threshold is defined by the
programmed output voltage and the lower value is about 10 mV lower. If the upper threshold is reached the offtime is increased to reduce the current in the inductor. Therefore the output voltage will slightly drop until the
lower threshold is tripped. Now the off-time is reduced to increase the current in the inductor to charge up the
output voltage to the steady-state value. The current swing during this operation mode is strongly depending on
the current drawn by the load but will not exceed the programmed current limit. The output voltage during
comparator operation stays within the specified accuracy with minimum voltage ripple.
This architecture with adaptive slope compensation provides excellent transient load response and requiring
minimal output filtering. Internal softstart and loop compensation simplifies the design process while minimizing
the number of external components.
8
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9.2 Functional Block Diagram
SW
VIN
Gate Drive
VOUT
PMOS
NMOS
Valley
Current
Sense
Pulse
PWM Modulator
FB
Softstart
VREF
EN
Control
Logic
Thermal
Shutdown
Undervoltage
Lockout
Snooze Mode
Detection
Input
Current
Sense
Averaging
Circuit
gm
VREF2
1V
VOUT
IAVE
Error Amp.
PG
ILIM
GND
9.3 Feature Description
9.3.1 Current Limit Operation
The current limit circuit employs a valley current sensing scheme. Current limit detection occurs during the offtime through sensing of the voltage drop across the synchronous rectifier. The output voltage is reduced as the
power stage of the device operates in a constant current mode. The maximum continuous output current
(IOUT(CL)), before entering current limit (CL) operation, can be defined by Equation 1 as shown below:
IOUT(CL) = (1 - D) g IIN(DC)
(1)
The duty cycle (D) can be estimated by following Equation 2
V gh
D = 1 - IN
VOUT
(2)
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Feature Description (continued)
9.3.2 Soft Start
The TPS61251 device has an internal charging circuit that controls the current during the output capacitor
charging and prevents the converter from inrush current that exceeds the set current limit. For typical 100 µs the
current is ramped to the set current limit. After reaching the current limit threshold the output capacitor is charged
with a constant current until the programmed output voltage is reached. During the phase where VIN > VOUT the
rectifying switch is controlled by the current limit circuit and works as a linear regulator in constant current mode.
If then VIN = VOUT, the converter starts switching and boosting up the voltage to its nominal output voltage by still
charging the capacitor with a constant current set by resistor RILIM. During constant current charging power
dissipation in the TPS61251 device is increased resulting in a thermal rise or heating of the device. If the output
capacitor is very large charging time can be long and thermal rise high. To prevent overheating of the device
during the charge phase the current will be limited to a lower value when device temperature is high. Please refer
to Thermal Regulation.
9.3.3 Enable
The device is enabled by setting EN pin to a voltage above 1 V. At first, the internal reference is activated and
the internal analog circuits are settled. Afterwards, the softstart is activated and the output voltage ramps up. The
output voltage reaches its nominal value as fast as the current limit settings and the load condition allows it.
The EN input can be used to control power sequencing in a system with several DC-DC converters. The EN pin
can be connected to the output of another converter, to drive the EN pin high and getting a sequencing of supply
rails. With EN = GND, the device enters shutdown mode.
9.3.4 Undervoltage Lockout (UVLO)
The UVLO prevents the device from malfunctioning at low input voltages and the battery from excessive
discharge. It disables the output stage of the converter once the falling VIN trips the undervoltage lockout
threshold VUVLO which is typically 2 V. The device starts operation once the rising VIN trips VUVLO threshold plus
its hysteresis of 100 mV at typical 2.1 V.
9.3.5 Power Good
The device has a built-in power good function to indicate whether the output voltage has reached the
programmed value and therefore the capacitor is fully charged. The power good output (PG) is set high if the
feedback voltage reaches 95% of its nominal value. The power good comparator operates even in shut down
mode when EN is set to low and/or VIN is turned off. This guaranties power good functionality until the capacitor
is discharged. The PG output goes low when VOUT drops below 2.3 V and indicates the discharge of the
capacitor. If the output voltage decreases further and goes below 2 V the converter disables all internal circuitry.
Therefore the PG open drain output becomes high resistive and follows the voltage the pullup resistor is
connected to.
Because power good functionality is active as long as the output capacitors are charged the converter can be
disconnected from its supply but is still supplying the following circuitry with energy. A connected buck converter
or buck-boost converter can use this energy to support a follow-on circuit that needs additional energy for a
secured shut down.
9.3.6 Input Overvoltage Protection
This converter has a input overvoltage protection that protects the device from damage due to a voltage higher
than the absolute maximum rating of the input allows. If 6.5 V (typical) at the input is exceeded, the converter
completely shuts down to protect its inner circuitry as well as the circuit connected to VOUT. If the input voltage
drops below 6.4 V (typical), the device turns on again and enters normal start-up again.
9.3.7 Load Disconnect and Reverse Current Protection
The TPS61251 device has an intelligent load disconnect circuit that prevents current flow in any direction during
shutdown. In case of a connected battery and VIN > VOUT the converter will not discharge the battery during
shutdown of the converter. In the opposite case when a bulk capacitor is connected to VOUT and charged to a
higher voltage than VIN the converter prevents the capacitor from being discharged through the input load
(battery).
10
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Feature Description (continued)
9.3.8 Thermal Regulation
The TPS61251 device contains a thermal regulation loop that monitors the die temperature. If the die
temperature rises to values above 110°C, the device automatically reduces the current to prevent the die
temperature from further increasing. Once the die temperature drops about 10°C below the threshold, the device
will automatically increase the current to the target value. This function also reduces the current during a shortcircuit-condition.
9.3.9 Thermal Shutdown
As soon as the junction temperature, TJ, exceeds 140°C (typical) the device enters thermal shutdown. In this
mode, the High Side and Low Side MOSFETs are turned off. When the junction temperature falls about 20°C
below the thermal shutdown, the device continues the operation.
9.4 Device Functional Modes
9.4.1 Power-Save Mode
The TPS61251 device integrates a power save mode to improve efficiency at light load. In power save mode the
converter only operates when the output voltage trips below a set threshold voltage. It ramps up the output
voltage with several pulses and goes into power save mode once the output voltage exceeds the set threshold
voltage. During the power save operation when the output voltage is above the set threshold the converter turns
off some of the inner circuits to save energy.
The PFM mode is left and PWM mode entered in case the output current can not longer be supported in PFM
mode.
9.4.2 Snooze Mode
During this enhanced power save mode, the converter still maintains the output voltage with a tolerance of ±2%.
The operating current in snooze mode is, however, drastically reduced to a typical value of 2 μA. This will be
achieved by turning off as much as possible of the inner regulation circuits. Load current in snooze mode is
limited to 2 mA. If the load current increases above 2 mA, the controller recognizes a further drop of the output
voltage and the device turns on again to charge the output capacitor to the programmed output voltage again.
9.4.3 100% Duty-Cycle Mode
If VIN > VOUT the TPS61251 device offers the lowest possible input-to-output voltage difference while still
maintaining current limit operation with the use of the 100% duty-cycle mode. In this mode, the PMOS switch is
constantly turned on. During this operation the output voltage follows the input voltage and will not fall below the
programmed value if the input voltage decreases below VOUT. The output voltage drop during 100% mode
depends on the load current and input voltage, and the resulting output voltage is calculated using Equation 3.
VOUT = VIN - (DCR + rDS(on) ) g IOUT
where
•
•
DCR is the DC resistance of the inductor
rDS(on) is the typical on-resistance of the PMOS switch
(3)
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10 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
10.1 Application Information
The TPS61251 device provides a power supply solution for products powered by either a three-cell, NiCd or
NiMH battery, or a one-cell Li-Ion or Li-polymer battery. The wide input voltage range is ideal to power portable
applications like mobile phones, solid state drives (SSD) and wireless modems. The converter is designed to
charge large capacitors in the Farad range to support battery back up applications.
10.2 Typical Application
Figure 6 shows a typical application for 5.5-V output voltage with input current limit.
VOUT
L1
1 μH
VOUT
L
5.5 V
VIN
2.3 V to
6.0 V
VIN
C1
10 µF
EN
CFF
1 nF
R1
1 MΩ
FB
COUT
4.7 µF
CBULK
>150 µF
R4
1 MΩ
R2
280 kΩ
ILIM
RILIM
20 kΩ
GND
Power Good
Output
PG
TPS61251
Figure 6. Typical Application Schematic
10.2.1 Design Requirements
Table 2 lists the design requirements.
Table 2. Design Parameters
PARAMETER
SYMBOL
VALUE
UNIT
Input voltage
VIN
3.6
V
VIN(min)
2.9
V
Minimum input voltage
Output voltage
VOUT
5.5
V
Input current limit set by
RILIM
ILIM
500
mA
Feedback voltage
VFB
1.2
V
MHz
Switching frequency
f
3.5
Estimated efficiency
η
90%
L1
1
Inductor value of choice
12
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µH
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10.2.2 Detailed Design Procedure
10.2.2.1 Custom Design With WEBENCH® Tools
Click here to create a custom design using the TPS61251 device with the WEBENCH® Power Designer.
1. Start by entering the input voltage (VIN), output voltage (VOUT), and output current (IOUT) requirements.
2. Optimize the design for key parameters such as efficiency, footprint, and cost using the optimizer dial.
3. Compare the generated design with other possible solutions from Texas Instruments.
The WEBENCH Power Designer provides a customized schematic along with a list of materials with real-time
pricing and component availability.
In most cases, these actions are available:
• Run electrical simulations to see important waveforms and circuit performance
• Run thermal simulations to understand board thermal performance
• Export customized schematic and layout into popular CAD formats
• Print PDF reports for the design, and share the design with colleagues
Get more information about WEBENCH tools at www.ti.com/WEBENCH.
10.2.2.2 Output Voltage Setting
The output voltage can be calculated using Equation 4.
æ
R ö
VOUT = VFB g ç 1 + 1 ÷
è R2 ø
(4)
To minimize the current through the feedback divider network and therefore increase efficiency during snooze
mode operation, R2 must be > 240 k. To keep the network robust against noise the resistor divider can also be
in the lower 100-k values. In this case, R1 is 1000 kΩ and R2 is 280 kΩ.
An external feed forward capacitor C1 is required for optimum load transient response. The value of C1 must be
1000 pF. The connection from FB pin to the resistor divider should be kept short and away from noise sources,
such as the inductor or the SW line.
10.2.2.3 Average Input Current Limit
The average input current is set by selecting the correct external resistor value correlating to the required current
limit. Equation 5 is a guideline for selecting the correct resistor value.
1.0V
RILIM =
g 10,000
ILIM
(5)
For a current limit of 500 mA the resistor value is 20 kΩ
To allow maximum current limit (1500 mA) the ILIM pin can be directly connected to VIN. If ILIM is connected to
GND the minimum current (100 mA) limit is set.
10.2.2.4 Maximum Output Current
The maximum output current is set by RILIM and the input to output voltage ratio and can be calculated using
Equation 6.
V gh
IOUT(max) » ILIM g IN
VOUT
(6)
Following the example, IOUT(max) will be 295 mA at 3.6 V input voltage and will decrease with lower input voltage
values due to the energy conservation.
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10.2.2.5 Inductor Selection
As for all switch mode power supplies two main passive components are required for storing the energy during
operation. This is done by an inductor and an output capacitor. The inductor must be connected between VIN
and SW pin to make sure that the TPS61251 device operates. To select the right inductor current rating the
programmed input current limit as well as the current ripple through the inductor is necessary. Estimation of the
maximum peak inductor current can be done using Equation 7.
VIN(min) g D
VIN(min) g h
IL(max) = ILIM + DIL = ILIM +
with D = 1 Lg f
VOUT
(7)
Regarding the example from above the current ripple (ΔIL) will be 290 mA and therefore an inductor with a rated
current of about 800 mA should be used.
The TPS61251 device is designed to work with inductor values between 1 µH and 2.2 µH. TI recommends a 1.5
µH inductor for typical applications. In space constrained applications, it might be possible to consider smaller
inductor values depending on the targeted inductor ripple current. Therefore, the inductor value can be reduced
down to 1 µH without degrading the stability.
In regular boost converter designs the current through the inductor is defined by the switch current limit of the
converters switches and therefore bigger inductors have to be chosen. The TPS61251 device allows the design
engineer to reduce the current limit to the needs of the application regardless the maximum switch current limit of
the converter. Programming a lower current value allows the use of smaller inductors without the danger to get
into saturation.
10.2.2.6 Output Capacitor
The second energy storing device is the output capacitor. When selecting output capacitors for large pulsed
loads, the magnitude and duration of the pulsing current, together with the ripple voltage specification, determine
the choice of the output capacitor. Both the ESR of the capacitor and the charge stored in the capacitor each
cycle contribute to the output voltage ripple. The ripple due to the charge is approximately what results from
Equation 8.
I
-I
gt
VRIPPLE(mV) = PULSE STANDBY on
COUT
where
•
•
IPULSE and tON are the peak current and on time during transmission burst.
ISTANDBY is the current in standby mode.
(8)
The above is a worst-case approximation assuming all the pulsing energy comes from the output capacitor.
The ripple due to the capacitor ESR is defined by Equation 9.
DVESR = (IPULSE - ISTANDBY ) g ESR
(9)
High capacitance values and low ESR can lead to instability in some internally compensated boost converters.
The internal loop compensation of the TPS61251 device is optimized to be stable with output capacitor values
greater than 150 μF with very low ESR.
Because big bulk capacitors can not be placed very close to the IC, it is required to put a small ceramic capacitor
of about 4.7 µF as close as possible to the output terminals. This will reduce parasitic effects that can influence
the functionality of the converter.
Table 3. List Of Bulk Capacitors
VENDOR (alphabetical order)
CAPACITANCE
PART NUMBER
Kemet
470 µF, 6.3 V, 55 mΩ
T520W477M006ATE055
Sanyo
470 µF, 6.3 V, 35 mΩ
6TPE470MAZU
14
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10.2.2.7 Input Capacitor
Multilayer ceramic capacitors are an excellent choice for input decoupling of the step-up converter as they have
extremely low ESR and are available in small form factors. Input capacitors should be located as close as
possible to the device. While a 10-μF input capacitor is sufficient for most applications, larger values may be
used to reduce input current ripple on the supply rail without limitations. Although low ESR tantalum capacitors
may be used.
NOTE
DC Bias effect: High capacitance ceramic capacitors have a DC Bias effect, which has a
strong influence on the final effective capacitance. Therefore, the right capacitor value has
to be chosen very carefully. Package size and voltage rating in combination with material
are responsible for differences between the rated capacitor value and the effective
capacitance. A 10-V rated 0805 capacitor with 10 µF can have an effective capacitance of
less 5 µF at an output voltage of 5 V.
10.2.2.8 Checking Loop Stability
The first step of circuit and stability evaluation is to look from a steady-state perspective at the following signals:
• Switching node, SW
• Inductor current, IL
• Output ripple voltage, VOUT(AC)
These are the basic signals that need to be measured when evaluating a switching converter. When the
switching waveform shows large duty cycle jitter or the output voltage or inductor current shows oscillations, the
regulation loop may be unstable. This is often a result of board layout and/or L-C combination.
As a next step in the evaluation of the regulation loop, the load transient response is tested. The time between
the load transient takes place and the turn on of the PMOS switch, the output capacitor must supply all of the
current required by the load. VOUT immediately shifts by an amount equal to ΔI(LOAD) × ESR, where ESR is the
effective series resistance of COUT. ΔI(LOAD) begins to charge or discharge COUT generating a feedback error
signal used by the regulator to return VOUT to its steady-state value. The results are most easily interpreted when
the device operates in PWM mode.
During this recovery time, VOUT can be monitored for settling time, overshoot or ringing that helps judge the
converter’s stability. Without any ringing, the loop has usually more than 45°C of phase margin. Because the
damping factor of the circuitry is directly related to several resistive parameters (for example, MOSFET rDS(on))
that are temperature dependant, the loop stability analysis has to be done over the input voltage range, load
current range, and temperature range.
10.2.3 Application Curves
Table 4. Table Of Graphs
DESCRIPTION
Waveforms
FIGURE
Load transient response (Tantal Capacitor 2.3 mF with >60 mΩ ESR, VOUT =
5.5 V, VIN = 3.6 V, ILIM = 1000 mA, Load change from 50 mA to 550 mA)
Figure 7
Load transient response (6 × 330-uF Polymer Tantal
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