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TPS74701-Q1
SBVS141B – APRIL 2010 – REVISED SEPTEMBER 2016
TPS74701-Q1 500-mA Low-Dropout Linear Regulator With Programmable Soft Start
1 Features
3 Description
•
•
The TPS74701-Q1 low-dropout (LDO) linear regulator
provides an easy-to-use, robust power management
solution for a wide variety of applications. Userprogrammable soft start minimizes stress on the input
power source by reducing capacitive inrush current
on start-up. The soft start is monotonic and wellsuited for powering many different types of
processors and ASICs. The enable input and power
good output allow easy sequencing with external
regulators. This complete flexibility permits the user to
configure a solution that meets the sequencing
requirements of FPGAs, DSPs, and other
applications with special start-up requirements.
1
•
•
•
•
•
•
•
•
•
•
Qualified for Automotive Applications
AEC-Q100 Test Guidance With the Following:
– Device Temperature Grade 1: –40°C to 125°C
– Device HBM ESD Classification Level 2
– Device CDM ESD Classification C4A
VOUT Range: 0.8 V to 3.6 V
Ultra-Low VIN Range: 0.8 V to 5.5 V
VBIAS Range: 2.7 V to 5.5 V
Low Dropout: 50 mV Typical at 500 mA,
VBIAS = 5 V
Power Good (PG) Output Allows Supply
Monitoring or Provides a Sequencing Signal for
Other Supplies
2% Accuracy Over Line, Load, and Temperature
Programmable Soft Start Provides Linear Voltage
Start-Up
VBIAS Permits Low VIN Operation With Good
Transient Response
Stable With Any Output Capacitor ≥ 2.2 µF
Available in a Small 3-mm × 3-mm × 1-mm 10-Pin
VSON Package
A precision reference and error amplifier deliver 2%
accuracy over load, line, temperature, and process.
The device is stable with any type of capacitor
greater than or equal to 2.2 µF, and is fully specified
from –40°C to 125°C. The TPS74701-Q1 is offered in
a small 3-mm × 3-mm 10-pin VSON package for
compatibility with the TPS74801-Q1.
Device Information(1)
PART NUMBER
PACKAGE
TPS74701-Q1
VSON (10)
BODY SIZE (NOM)
3.00 mm × 3.00 mm
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
2 Applications
•
•
•
•
FPGA Applications
DSP Core and I/O Voltages
Post-Regulation Applications
Applications With Special Start-Up Time or
Sequencing Requirements
Hot-Swap and Inrush Controls
•
Turnon Response
Typical Application Circuit (Adjustable)
VIN
IN
CIN
CSS = 0nF
PG
CSS = 560pF
R3
BIAS
VOUT
OUT
EN TPS74701-Q1
VBIAS
R1
SS
GND
CBIAS
CSS
FB
CSS = 5600pF
0.5V/div
VOUT
COUT
R2
3.8V
Copyright © 2016, Texas Instruments Incorporated
1V/div
VEN
1.8V
Time (2ms/div)
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
TPS74701-Q1
SBVS141B – APRIL 2010 – REVISED SEPTEMBER 2016
www.ti.com
Table of Contents
1
2
3
4
5
6
7
Features ..................................................................
Applications ...........................................................
Description .............................................................
Revision History.....................................................
Pin Configuration and Functions .........................
Specifications.........................................................
1
1
1
2
3
4
6.1
6.2
6.3
6.4
6.5
6.6
4
4
4
5
5
7
Absolute Maximum Ratings ......................................
ESD Ratings..............................................................
Recommended Operating Conditions.......................
Thermal Information ..................................................
Electrical Characteristics...........................................
Typical Characteristics ..............................................
Detailed Description ............................................ 11
7.1
7.2
7.3
7.4
Overview .................................................................
Functional Block Diagram .......................................
Feature Description.................................................
Device Functional Modes........................................
11
11
11
14
8
Application and Implementation ........................ 15
8.1 Application Information............................................ 15
8.2 Typical Application .................................................. 15
9 Power Supply Recommendations...................... 19
10 Layout................................................................... 19
10.1 Layout Guidelines ................................................. 19
10.2 Layout Example .................................................... 19
10.3 Power Dissipation ................................................. 19
11 Device and Documentation Support ................. 23
11.1
11.2
11.3
11.4
11.5
11.6
Device Support......................................................
Receiving Notification of Documentation Updates
Community Resources..........................................
Trademarks ...........................................................
Electrostatic Discharge Caution ............................
Glossary ................................................................
23
23
23
23
23
23
12 Mechanical, Packaging, and Orderable
Information ........................................................... 23
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision A (September 2010) to Revision B
Page
•
Added ESD Ratings table, Recommended Operating Conditions table, Feature Description section, Device
Functional Modes, Application and Implementation section, Power Supply Recommendations section, Layout
section, Device and Documentation Support section, and Mechanical, Packaging, and Orderable Information section. ..... 1
•
Deleted Ordering Information table; see POA at the end of the data sheet........................................................................... 1
2
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SBVS141B – APRIL 2010 – REVISED SEPTEMBER 2016
5 Pin Configuration and Functions
DRC Package
10-Pin VSON
Top View
IN
1
10
OUT
IN
2
9
OUT
PG
3
8
FB
BIAS
4
7
SS
EN
5
6
GND
Thermal
Pad
Not to scale
Pin Functions
PIN
NAME
NO.
I/O
DESCRIPTION
BIAS
4
I
Bias input voltage for error amplifier, reference, and internal control circuits.
EN
5
I
Enable pin. Driving this pin high enables the regulator. Driving this pin low puts the regulator
into shutdown mode. This pin must not be left unconnected.
FB
8
I
Feedback pin. The feedback connection to the center tap of an external resistor divider
network that sets the output voltage. This pin must not be left floating.
GND
6
—
IN
1, 2
I
Ground
Input to the device.
OUT
9, 10
O
Regulated output voltage. A small capacitor (total typical capacitance ≥ 2.2 µF, ceramic) is
needed from this pin to ground to assure stability.
PG
3
O
Power Good pin. An open-drain, active-high output that indicates the status of VOUT. When
VOUT exceeds the PG trip threshold, the PG pin goes into a high-impedance state. When
VOUT is below this threshold the pin is driven to a low-impedance state. A pullup resistor from
10 kΩ to 1 MΩ must be connected from this pin to a supply of up to 5.5 V. The supply can be
higher than the input voltage. Alternatively, the PG pin can be left unconnected if output
monitoring is not necessary.
SS
7
—
Soft-Start pin. A capacitor connected on this pin to ground sets the start-up time. If this pin is
left unconnected, the regulator output soft-start ramp time is typically 200 µs.
Thermal Pad
—
—
Must be soldered to the ground plane for increased thermal performance.
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SBVS141B – APRIL 2010 – REVISED SEPTEMBER 2016
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6 Specifications
6.1 Absolute Maximum Ratings
At TJ = –40°C to 125°C, unless otherwise noted. All voltages are with respect to GND. (1)
MIN
MAX
UNIT
VIN, VBIAS
Input voltage
–0.3
6
V
VEN
Enable voltage
–0.3
6
V
VPG
Power good voltage
–0.3
6
V
VSS
Soft-start voltage
–0.3
6
V
VFB
Feedback voltage
–0.3
6
V
VOUT
Output voltage
–0.3
VIN + 0.3
V
IPG
PG sink current
0
1.5
mA
IOUT
Maximum output current
Internally limited
Output short-circuit duration
Indefinite
PDISS
Continuous total power dissipation
TJ
Operating junction temperature
–40
125
°C
Tstg
Storage temperature
–55
150
°C
(1)
See Thermal Information
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only and functional operation of the device at these conditions is not implied. Exposure to absolute-maximum-rated conditions for
extended periods may affect device reliability.
6.2 ESD Ratings
VALUE
V(ESD)
(1)
Electrostatic discharge
Human-body model (HBM), per AEC Q100-002
(1)
±2000
Charged-device model (CDM), per AEC Q100-011
±500
UNIT
V
AEC Q100-002 indicates that HBM stressing shall be in accordance with the ANSI/ESDA/JEDEC JS-001 specification.
6.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
VIN
Input supply voltage
VEN
Enable supply voltage
VBIAS
(1)
BIAS supply voltage
MIN
MAX
VOUT + VDO (VIN)
5.5
V
0
VIN
V
(2)
5.5
V
VOUT + VDO (VBIAS)
UNIT
VOUT
Output voltage
0.8
3.3
V
IOUT
Output current
0
500
mA
COUT
Output capacitor
2.2
µF
CIN (3)
Input capacitor
1
µF
CBIAS
BIAS capacitor
0.1
µF
TJ
Operating junction temperature
–40
(1)
(2)
(3)
4
125
°C
BIAS supply is required when VIN is below VOUT + 1.62 V.
VBIAS has a minimum voltage of 2.7 V or VOUT + VDO (VBIAS), whichever is higher.
If VIN and VBIAS are connected to the same supply, the recommended minimum capacitor for the supply is 4.7 µF.
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6.4 Thermal Information
TPS74701-Q1
THERMAL METRIC (1) (2)
DRC (VSON)
UNIT
10 PINS
RθJA
Junction-to-ambient thermal resistance
RθJC(top)
Junction-to-case (top) thermal resistance
RθJB
Junction-to-board thermal resistance
ψJT
Junction-to-top characterization parameter
0.7
°C/W
ψJB
Junction-to-board characterization parameter
16.9
°C/W
RθJC(bot)
Junction-to-case (bottom) thermal resistance
5.9
°C/W
(1)
(2)
50.4
°C/W
70
°C/W
17.7
°C/W
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
For thermal estimates of this device based on PCB copper area, see the TI PCB Thermal Calculator.
6.5 Electrical Characteristics
At VEN = 1.1 V, VIN = VOUT + 0.3 V, CBIAS = 0.1 µF, CIN = COUT = 10 µF, CNR = 1 nF, IOUT = 50 mA, VBIAS = 5 V, and TJ = –40°C
to 125°C, unless otherwise noted. Typical values are at TJ = 25°C.
PARAMETER
TEST CONDITIONS
MIN
TYP
UNIT
Input voltage range
VBIAS
Bias pin voltage range
VREF
Internal reference (Adj.)
TJ = 25°C
Output voltage range
VIN = 5 V, IOUT = 500 mA
VREF
Accuracy (1)
2.97 V ≤ VBIAS ≤ 5.5 V,
50 mA ≤ IOUT ≤ 500 mA
–2%
Line regulation
VOUT (NOM) + 0.3 ≤ VIN ≤ 5.5 V
0.03
%/V
50 mA ≤ IOUT ≤ 500 mA
0.09
%/A
VOUT
VOUT/VIN
VOUT + VDO
MAX
VIN
VOUT/IOUT Load regulation
IOUT = 500 mA,
VBIAS – VOUT (NOM) ≥ 1.62 V (3)
VIN dropout voltage (2)
VDO
VBIAS dropout voltage
2.7
0.796
(2)
IOUT = 500 mA, VIN = VBIAS
±0.5%
V
5.5
V
0.804
V
3.6
V
2%
50
120
mV
1.31
1.39
V
ICL
Current limit
1350
mA
IBIAS
Bias pin current
1
2
mA
ISHDN
Shutdown supply current (IGND) VEN ≤ 0.4 V
1
50
µA
IFB
Feedback pin current
0.15
1
µA
Power-supply rejection
(VIN to VOUT)
PSRR
Power-supply rejection
(VBIAS to VOUT)
VOUT = 80% × VOUT (NOM)
0.8
5.5
–1
1 kHz, IOUT = 500 mA,
VIN = 1.8 V, VOUT = 1.5 V
60
300 kHz, IOUT = 500 mA,
VIN = 1.8 V, VOUT = 1.5 V
30
1 kHz, IOUT = 500 mA,
VIN = 1.8 V, VOUT = 1.5 V
50
300 kHz, IOUT = 500 mA,
VIN = 1.8 V, VOUT = 1.5 V
30
Noise
Output noise voltage
100 Hz to 100 kHz,
IOUT = 500 mA, CSS = 0.001 µF
tSTR
Minimum start-up time
RLOAD for IOUT = 1 A, CSS = open
Soft-start charging current
VSS = 0.4 V
ISS
VEN,
800
dB
dB
25 × VOUT
200
Enable input high level
VEN,
LO
Enable input low level
VEN,
HYS
Enable pin hysteresis
50
VEN,
DG
Enable pin deglitch time
20
(1)
(2)
(3)
Enable pin current
VEN = 5 V
µs
440
HI
IEN
µVRMS
nA
1.1
5.5
V
0
0.4
V
0.1
mV
µs
1
µA
Adjustable devices tested at 0.8 V; resistor tolerance is not taken into account.
Dropout is defined as the voltage from VIN to VOUT when VOUT is 3% below nominal.
1.62 V is a test condition of this device and can be adjusted by referring to Figure 6.
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Electrical Characteristics (continued)
At VEN = 1.1 V, VIN = VOUT + 0.3 V, CBIAS = 0.1 µF, CIN = COUT = 10 µF, CNR = 1 nF, IOUT = 50 mA, VBIAS = 5 V, and TJ = –40°C
to 125°C, unless otherwise noted. Typical values are at TJ = 25°C.
PARAMETER
TEST CONDITIONS
VIT
PG trip threshold
VHYS
PG trip hysteresis
VPG, LO
PG output low voltage
IPG = 1 mA (sinking), VOUT < VIT
IPG, LKG
PG leakage current
VPG = 5.25 V, VOUT > VIT
TJ
Operating junction temperature
TSD
6
Thermal shutdown temperature
VOUT decreasing
MIN
TYP
MAX
85
90
94
3
0.1
–40
Shutdown, temperature increasing
165
Reset, temperature decreasing
140
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UNIT
%VOUT
%VOUT
0.3
V
1
µA
125
°C
°C
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SBVS141B – APRIL 2010 – REVISED SEPTEMBER 2016
6.6 Typical Characteristics
0.20
0.5
0.15
0.4
0.3
0.10
Change in VOUT (%)
Change in VOUT (%)
At TJ = 25°C, VIN = VOUT(TYP) + 0.3 V, VBIAS = 5 V, IOUT = 50 mA, VEN = VIN, CIN = 1 µF, CBIAS = 4.7 µF, and COUT = 10 µF,
unless otherwise noted.
-40°C
0.05
0
+25°C
-0.05
+125°C
-0.01
0.2
-40°C
0.1
0
-0.1
+125°C
-0.2
+25°C
-0.3
-0.15
-0.4
-0.20
-0.5
0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
0.5
5.0
1.0
1.5
2.0
VIN - VOUT (V)
2.5
3.0
3.5
4.0
VBIAS - VOUT (V)
Figure 1. VIN Line Regulation
Figure 2. VBIAS Line Regulation
1.2
0.5
0.4
0.3
Change in VOUT (%)
Change in VOUT (%)
1.0
0.8
0.6
0.4
0.2
+125°C
0.1
0
-0.1
-40°C
+25°C
-0.2
-0.3
0.2
-0.4
0
-0.5
0
10
20
30
40
0
50
100
500
Figure 4. Load Regulation
200
90
180
80
160
VDO (VIN - VOUT) (mV)
VDO (VIN - VOUT) (mV)
Figure 3. Load Regulation
70
60
50
40
+125°C
+25°C
20
400
IOUT (mA)
100
30
300
200
IOUT (mA)
IOUT = 0.5A
140
120
100
+25°C
80
+125°C
60
40
10
-40°C
20
-40°C
0
0
100
200
300
400
0
500
0
0.5
IOUT (mA)
1.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
VBIAS - VOUT (V)
Figure 5. Dropout Voltage vs IOUT and Temperature (TJ)
Figure 6. Dropout Voltage vs (VBIAS – VOUT) and
Temperature (TJ)
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Typical Characteristics (continued)
2200
Power-Supply Rejection Ratio (dB)
90
VDO (VBIAS - VOUT) (mV)
2000
1800
1600
1400
+125°C
1200
1000
+25°C
-40°C
800
600
80
IOUT = 0.1A
70
60
50
40
IOUT = 0.5A
30
VIN = 1.8V
VOUT = 1.2V
VBIAS = 5V
CSS = 1nF
20
10
0
0
100
300
200
400
500
10
100
1k
IOUT (mA)
Figure 7. VBIAS Dropout Voltage vs IOUT and Temperature
(TJ)
60
IOUT = 100mA
50
40
30
VIN = 1.8V
VOUT = 1.2V
COUT = 10mF
CSS = 1nF
20
10
100
IOUT = 500mA
Power-Supply Rejection Ratio (dB)
Power-Supply Rejection Ratio (dB)
70
10
10M
80
1kHz
70
60
10kHz
50
40
100kHz
30
500kHz
20
VOUT = 1.2V
IOUT = 500mA
CSS = 1nF
10
0
1k
10k
100k
1M
0
10M
0.25
0.50
0.75
1.00
1.25
1.50
1.75
2.00 2.25
VIN - VOUT (V)
Frequency (Hz)
Figure 9. VIN PSRR vs Frequency
Figure 10. VIN PSRR vs (VIN – VOUT)
2.0
IOUT = 100mA
VOUT = 1.2V
1.8
+125°C
1.6
1.4
IBIAS (mA)
Output Spectral Noise Density (mV/ÖHz)
1M
90
80
0
CSS = 0nF
0.1
CSS = 10nF
1.2
1.0
0.8
+25°C
0.6
CSS = 1nF
-40°C
0.4
0.2
0
0.01
100
1k
10k
100k
0
100
200
300
400
500
IOUT (mA)
Frequency (Hz)
Figure 11. Noise Spectral Density
8
100k
Figure 8. VBIAS PSRR vs Frequency
90
1
10k
Frequency (Hz)
Figure 12. Bias Pin Current vs IOUT and Temperature (TJ)
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Typical Characteristics (continued)
2.0
500
1.8
475
+125°C
1.6
450
1.2
ISS (nA)
IBIAS (mA)
1.4
+25°C
1.0
0.8
425
400
375
0.6
-40°C
0.4
350
325
0.2
300
0
2.0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
-50
0
-25
VBIAS (V)
Figure 13. Bias Pin Current vs VBIAS and Temperature (TJ)
50
75
100
125
Figure 14. Soft-Start Charging Current (ISS) vs Temperature
(TJ)
1.0
1.5
0.9
1.4
0.8
1.3
0.7
1.2
Current Limit (A)
VOL Low-Level PG Voltage (V)
25
Junction Temperature (°C)
0.6
0.5
0.4
0.3
+125°C
1.1
1.0
-40°C
0.9
+25°C
0.8
0.2
0.7
0.1
0.6
0
VOUT = 0.8V
0.5
0
2
6
4
8
10
12
1.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
5.0
VBIAS - VOUT (V)
PG Current (mA)
Figure 16. Current Limit vs (VBIAS – VOUT)
Figure 15. Low-Level PG Voltage vs Current
CSS = 1nF
COUT = 2.2mF (Ceramic)
50mV/div
COUT = 2.2mF (Ceramic)
50mV/div
CSS = 1nF
3.8V
5.0V
1V/div
1V/div
1V/ms
3.3V
1V/ms
1.8V
Time (50ms/div)
Time (50ms/div)
IOUT = 1 A, VEN = VIN = 1.8 V, VOUT = 1.5 V
IOUT = 1 A, VEN = VIN = 1.8 V, VOUT = 1.5 V
Figure 17. VBIAS Line Transient
Figure 18. VIN Line Transient
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Typical Characteristics (continued)
CSS = 0nF
COUT = 470mF (OSCON)
100mV/div
CSS = 560pF
CSS = 1nF
CSS = 5600pF
0.5V/div
VOUT
100mV/div
COUT = 10mF (Ceramic)
100mV/div
3.8V
COUT = 2.2mF (Ceramic)
1V/div
500mA/div
VEN
1.8V
1A/ms
50mA
Time (50ms/div)
Time (2ms/div)
IOUT = 1 A, VEN = VIN = 1.8 V, VOUT = 1.5 V
IOUT = 1 A, VEN = VIN = 1.8 V, VOUT = 1.5 V
Figure 19. Output Load Transient Response
Figure 20. Turnon Response
1V/div
VIN = VBIAS = VEN
VOUT
VPG
Time (20ms/div)
IOUT = 1 A, VEN = VIN = 1.8 V, VOUT = 1.5 V
Figure 21. Power Up and Power Down
10
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7 Detailed Description
7.1 Overview
The TPS74701-Q1 is a low-dropout regulator that features soft-start capability. This regulator use a low current
bias input to power all internal control circuitry, allowing the NMOS pass transistor to regulate very low input and
output voltages.
The use of an NMOS-pass FET offers several critical advantages for many applications. Unlike a PMOS topology
device, the output capacitor has little effect on loop stability. This architecture allows the TPS74701 to be stable
with any capacitor type of value 2.2 µF or greater. Transient response is also superior to PMOS topologies,
particularly for low VIN applications.
The TPS74701-Q1 features a programmable voltage-controlled soft-start circuit that provides a smooth,
monotonic start-up and limits start-up inrush currents that may be caused by large capacitive loads. A power
good (PG) output is available to allow supply monitoring and sequencing of other supplies. An enable (EN) pin
with hysteresis and deglitch allows slow-ramping signals to be used for sequencing the device. The low VIN and
VOUT capability allows for inexpensive, easy-to-design, and efficient linear regulation between the multiple
supply voltages often present in processor-intensive systems.
7.2 Functional Block Diagram
IN
Current
Limit
BIAS
UVLO
OUT
Thermal
Limit
0.44µA
VOUT
R1
SS
CSS
Soft-Start
Discharge
0.8V
Reference
FB
PG
EN
Hysteresis
and Deglitch
R2
0.9 × VREF
GND
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7.3 Feature Description
7.3.1 Transient Response
The TPS74701-Q1 was designed to have excellent transient response for most applications with a small amount
of output capacitance. In some cases, the transient response may be limited by the transient response of the
input supply. This limitation is especially true in applications where the difference between the input and output is
less than 300 mV. In this case, adding additional input capacitance improves the transient response much more
than just adding additional output capacitance would do. With a solid input supply, adding additional output
capacitance reduces undershoot and overshoot during a transient event; see Figure 19. Because the TPS74701Q1 is stable with output capacitors as low as 2.2 µF, many applications may then need very little capacitance at
the LDO output. For these applications, local bypass capacitance for the powered device may be sufficient to
meet the transient requirements of the application. This design reduces the total solution cost by avoiding the
need to use expensive, high-value capacitors at the LDO output.
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Feature Description (continued)
7.3.2 Dropout Voltage
The TPS74701-Q1 offers very low dropout performance, making it well-suited for high-current, low VIN/low VOUT
applications. The low dropout of the TPS74701-Q1 allows the device to be used in place of a DC-DC converter
and still achieve good efficiency. This feature provides designers with the power architecture for their applications
to achieve the smallest, simplest, and lowest cost solution.
There are two different specifications for dropout voltage with the TPS74701-Q1. The first specification (shown in
Figure 22) is referred to as VIN Dropout and is used when an external bias voltage is applied to achieve low
dropout. This specification assumes that VBIAS is at least 1.62 V (1) above VOUT, which is the case for VBIAS when
powered by a 3.3-V rail with 5% tolerance and with VOUT = 1.5 V. If VBIAS is higher than VOUT + 1.62 V (1), VIN
dropout is less than specified.
BIAS
IN
VBIAS = 5V ±5%
VIN = 1.8V
VOUT = 1.5V
IOUT = 500 mA
Efficiency = 83%
OUT
Reference
VOUT
COUT
FB
Simplified Block Diagram
Figure 22. Typical Application of the TPS74701-Q1 Using an Auxiliary Bias Rail
The second specification (shown in Figure 23) is referred to as VBIAS Dropout and applies to applications where
IN and BIAS are tied together. This option allows the device to be used in applications where an auxiliary bias
voltage is not available or low dropout is not required. Dropout is limited by BIAS in these applications because
VBIAS provides the gate drive to the pass FET; therefore, VBIAS must be 1.39 V above VOUT. Because of this
usage, IN and BIAS tied together easily consume huge power. Pay attention not to exceed the power rating of
the IC package.
VIN
BIAS
IN
VBIAS = 3.3V ±5%
VIN = 3.3V ± 5V
VOUT = 1.5V
Reference
IOUT = 500 mA
Efficiency = 45%
OUT
VOUT
COUT
FB
Simplified Block Diagram
Figure 23. Typical Application of the TPS74701-Q1 Without an Auxiliary Bias Rail
(1)
12
1.62 V is a test condition of this device and can be adjusted by referring to Figure 6.
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Feature Description (continued)
7.3.3 Output Noise
The TPS74701-Q1 provides low output noise when a soft-start capacitor is used. When the device reaches the
end of the soft-start cycle, the soft-start capacitor serves as a filter for the internal reference. By using a 0.001-µF
soft-start capacitor, the output noise is reduced by half and is typically 30 µVRMS for a 1.2-V output (10 Hz to
100 kHz). Further increasing CSS has little effect on noise. Because most of the output noise is generated by the
internal reference, the noise is a function of the set output voltage. The RMS noise with a 0.001-µF soft-start
capacitor is given in Equation 1:
(
VN(mVRMS) = 25
mVRMS
V
)x V
OUT(V)
(1)
The low output noise of the TPS74701-Q1 makes it a good choice for powering transceivers, PLLs, or other
noise-sensitive circuitry.
7.3.4 Enable and Shutdown
The enable (EN) pin is active high and is compatible with standard digital signaling levels. VEN below 0.4 V turns
the regulator off, while VEN above 1.1 V turns the regulator on. Unlike many regulators, the enable circuitry has
hysteresis and deglitching for use with relatively slowly ramping analog signals. This configuration allows the
TPS74701-Q1 to be enabled by connecting the output of another supply to the EN pin. The enable circuitry
typically has 50 mV of hysteresis and a deglitch circuit to help avoid ON and OFF cycling as a result of small
glitches in the VEN signal.
The enable threshold is typically 0.8 V and varies with temperature and process variations. Temperature
variation is approximately –1 mV/°C; process variation accounts for most of the rest of the variation to the 0.4-V
and 1.1-V limits. If precise turnon timing is required, a fast rise-time signal must be used to enable the
TPS74701-Q1.
If not used, EN can be connected to either IN or BIAS. If EN is connected to IN, it must be connected as close as
possible to the largest capacitance on the input to prevent voltage droops on that line from triggering the enable
circuit.
7.3.5 Power Good
The power good (PG) pin is an open-drain output and can be connected to any 5.5 V or lower rail through an
external pullup resistor. This pin requires at least 1.1 V on VBIAS to have a valid output. The PG output is highimpedance when VOUT is greater than VIT + VHYS. If VOUT drops below VIT or if VBIAS drops below 1.9 V, the opendrain output turns on and pulls the PG output low. The PG pin also asserts when the device is disabled. The
recommended operating condition of the PG pin sink current is up to 1 mA, so the pullup resistor for PG must be
in the range of 10 kΩ to 1 MΩ. If output voltage monitoring is not needed, the PG pin can be left floating.
7.3.6 Internal Current Limit
The TPS74701-Q1 features a factory-trimmed, accurate current limit that is flat over temperature and supply
voltage. The current limit allows the device to supply surges of up to 1 A and maintain regulation. The current
limit responds in about 10 µs to reduce the current during a short-circuit fault.
The internal current limit protection circuitry of the TPS74701-Q1 is designed to protect against overload
conditions. It is not intended to allow operation above the rated current of the device. Continuously running the
TPS74701-Q1 above the rated current degrades device reliability.
7.3.7 Thermal Protection
Thermal protection disables the output when the junction temperature rises to approximately 160°C, allowing the
device to cool. When the junction temperature cools to approximately 140°C, the output circuitry is enabled.
Depending on power dissipation, thermal resistance, and ambient temperature the thermal protection circuit may
cycle ON and OFF. This cycling limits the dissipation of the regulator, protecting it from damage as a result of
overheating.
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Feature Description (continued)
Activation of the thermal protection circuit indicates excessive power dissipation or inadequate heat sinking. For
reliable operation, junction temperature should be limited to 125°C maximum. To estimate the margin of safety in
a complete design (including heat sink), increase the ambient temperature until thermal protection is triggered;
use worst-case loads and signal conditions. For good reliability, thermal protection should trigger at least 40°C
above the maximum expected ambient condition of the application. This condition produces a worst-case junction
temperature of 125°C at the highest expected ambient temperature and worst-case load.
The internal protection circuitry of the TPS74701-Q1 is designed to protect against overload conditions. It is not
intended to replace proper heat sinking. Continuously running the TPS74701-Q1 into thermal shutdown degrades
device reliability.
7.4 Device Functional Modes
7.4.1 Normal Operation
The device regulates to the nominal output voltage under the following conditions:
• The input voltage and bias voltage are both at least at the respective minimum specifications.
• The enable voltage has previously exceeded the enable rising threshold voltage and has not decreased
below the enable falling threshold.
• The output current is less than the current limit.
• The device junction temperature is less than the maximum specified junction temperature.
7.4.2 Dropout Operation
If the input voltage is lower than the nominal output voltage plus the specified dropout voltage, but all other
conditions are met for normal operation, the device operates in dropout mode. In this condition, the output
voltage is the same as the input voltage minus the dropout voltage. The transient performance of the device is
significantly degraded because the pass device is in a triode state and no longer controls the current through the
LDO. Line or load transients in dropout can result in large output voltage deviations.
7.4.3 Disabled
The device is disabled under the following conditions:
• The input or bias voltages are below the respective minimum specifications.
• The enable voltage is less than the enable falling threshold voltage or has not yet exceeded the enable rising
threshold.
• The device junction temperature is greater than the thermal shutdown temperature.
Table 1 shows the conditions that lead to the different modes of operation.
Table 1. Device Functional Mode Comparison
OPERATING MODE
PARAMETER
VIN
VEN
VBIAS
IOUT
TJ
Normal mode
VIN > VOUT(nom) + VDO
(VIN)
VEN > VEN, HI
VBIAS ≥ VOUT + 1.39 V
IOUT < ICL
TJ < 125°C
Dropout mode
VIN < VOUT(nom) + VDO
(VIN)
VEN > VEN, HI
VBIAS < VOUT + 1.39 V
—
TJ < 125°C
VIN < VIN(min)
VEN < VEN, LO
VBIAS < VBIAS(min)
—
TJ > 165°C
Disabled mode (any
true condition the
device)
14
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8 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
8.1 Application Information
The TPS74701-Q1 device is a 500-mA low-dropout regulator with soft-start function integrated. Based on the
end-application, different output voltage could be achieved with different values of external components.
8.2 Typical Application
Figure 24 illustrates the typical application circuit for the TPS74701-Q1 adjustable output device.
VIN
IN
CIN
1µF
PG
R3
BIAS
EN
VBIAS
R1
SS
CBIAS
1µF
VOUT
TPS74701-Q1 OUT
COUT
10µF
FB
GND
CSS
R2
(
VOUT = 0.8 × 1 +
R1
R2
)
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Figure 24. Typical Application Circuit for the TPS74701-Q1
R1 and R2 can be calculated for any output voltage using the formula shown in Figure 24. See Table 3 for
sample resistor values of common output voltages. To achieve the maximum accuracy specifications, R2 must be
less than or equal to 4.99 kΩ.
8.2.1 Design Requirements
For this design example, use the parameters in Table 2.
Table 2. Design Parameters
PARAMETER
EXAMPLE VALUE
Input voltage
1.8 V ± 10%
Output voltage
1.5 V ± 3%
Enable voltage
1.8 V ± 10%
BIAS voltage
3.3 V ± 10%
Output current
500 mA
Output capacitor
10 µF
Start-up time
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