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TPS7A7002
SBVS209D – MAY 2013 – REVISED APRIL 2017
TPS7A7002 Very Low Input, Very Low Dropout 3-A Regulator With Enable
1 Features
3 Description
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•
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•
•
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The TPS7A7002 is a high-performance, positivevoltage, low-dropout (LDO) regulator designed for
use in applications requiring very-low input voltage
and very-low dropout voltage at up to 3 A. The device
operates with a single input voltage as low as
1.425 V, and with an output voltage programmable to
as low as 0.5 V. The output voltage can be set using
an external divider.
1
Input Voltage as Low as 1.425 V
380-mV Maximum Dropout at 2 A
600-mV Maximum Dropout at 3 A
Adjustable Output from 0.5 V
Protections: Current Limit and Thermal Shutdown
Enable Pin
1-µA Ground Current in Shutdown Mode
Full Industrial Temperature Range
Available in an SOIC-8, Fully RoHS-Compliant
Package
2 Applications
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The TPS7A7002 features ultra-low dropout, ideal for
applications where VOUT is very close to VIN.
Additionally, the TPS7A7002 has an enable pin for
further reduced power dissipation while in Shutdown
mode. The TPS7A7002 provides excellent regulation
over variations in line, load, and temperature.
The TPS7A7002 is available in an 8-pin SO
PowerPAD™ package.
Telecom and Networking Cards
Motherboards and Peripheral Cards
Industrial
Wireless Infrastructure
Set-Top Boxes
Medical Equipment
Notebook Computers
Battery-Powered Systems
Device Information(1)
PART NUMBER
TPS7A7002
Dropout Voltage vs Output Current
(VOUT = 3.3 V)
400
NC
TPS7A7002
Input Voltage
OUT
R1
Enable
EN
FB
R2
NC
VOUT = 0.5 ´ 1 +
GND
R1
R2
COUT
Dropout Voltage (mV)
IN
−40°C
25°C
125°C
350
Output Voltage
CIN
BODY SIZE (NOM)
3.90 mm × 4.89 mm
(1) For all available packages, see the package option addendum
at the end of the data sheet.
Typical Application
NC
PACKAGE
SO PowerPAD (8)
300
250
200
150
100
50
0
0
500m
1
Output Current (A)
1.5
2
G003
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
TPS7A7002
SBVS209D – MAY 2013 – REVISED APRIL 2017
www.ti.com
Table of Contents
1
2
3
4
5
6
7
Features ..................................................................
Applications ...........................................................
Description .............................................................
Revision History.....................................................
Pin Configuration and Functions .........................
Specifications.........................................................
1
1
1
2
3
4
6.1
6.2
6.3
6.4
6.5
6.6
4
4
4
4
5
6
Detailed Description .............................................. 7
7.1
7.2
7.3
7.4
8
Absolute Maximum Ratings .....................................
ESD Ratings..............................................................
Recommended Operating Conditions.......................
Thermal Information ..................................................
Electrical Characteristics...........................................
Typical Characteristics ..............................................
Overview ...................................................................
Functional Block Diagram .........................................
Feature Description...................................................
Device Functional Modes..........................................
7
7
7
8
Application and Implementation .......................... 9
8.1 Application Information.............................................. 9
8.2 Typical Application .................................................. 10
9 Power Supply Recommendations...................... 11
10 Layout................................................................... 11
10.1
10.2
10.3
10.4
Layout Guidelines .................................................
Layout Example ....................................................
Thermal Consideration..........................................
Power Dissipation .................................................
11
12
12
12
11 Device and Documentation Support ................. 13
11.1
11.2
11.3
11.4
11.5
11.6
11.7
Device Support......................................................
Documentation Support ........................................
Receiving Notification of Documentation Updates
Community Resources..........................................
Trademarks ...........................................................
Electrostatic Discharge Caution ............................
Glossary ................................................................
13
13
13
13
13
13
13
12 Mechanical, Packaging, and Orderable
Information ........................................................... 13
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision C (July 2015) to Revision D
Page
•
Changed OUT pin description text from "TI recommends using at least a 4.7-μF ceramic capacitor, and up to 10 μF
for a good transient response." to " A 4.7-μF or larger capacitor of any type is required for stability." for clarity.................. 3
•
Changed "operating free-air" to "junction" in Absolute Maximum Ratings table condition line ............................................. 4
•
Added rows for enable pin voltage, input capacitor, output capacitor, and feedforward capacitance to
Recommended Operating Conditions table............................................................................................................................ 4
•
Added min value of 0 to output current in Recommended Operating Conditions table ......................................................... 4
•
Changed note (1) in Electrical Characteristics table; deleted initial reference to R1 and updated R2 resistor range............. 5
•
Changed Output Capacitor (OUT) section; reworded for clarity............................................................................................. 9
Changes from Revision B (November 2013) to Revision C
•
Page
Added ESD Ratings table, Feature Description section, Device Functional Modes, Application and Implementation
section, Power Supply Recommendations section, Layout section, Device and Documentation Support section, and
Mechanical, Packaging, and Orderable Information section. ................................................................................................ 1
Changes from Revision A (September 2013) to Revision B
Page
•
Changed data sheet status from product preview to production data.................................................................................... 1
•
Added pin 1 identifier (black bar) to pinout diagram............................................................................................................... 3
Changes from Original (May 2013) to Revision A
•
2
Page
Changed product preview data sheet..................................................................................................................................... 7
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SBVS209D – MAY 2013 – REVISED APRIL 2017
5 Pin Configuration and Functions
DDA Package
8-Pin SO PowerPAD
Top View
NC
1
8
GND
EN
2
7
FB
PowerPAD
IN
3
6
OUT
NC
4
5
NC
Pin Functions
PIN
NAME
NO.
I/O
DESCRIPTION
EN
2
I
Enable input. Pulling this pin to less than 0.5 V turns the regulator off. Connect to VIN if not
being used.
FB
7
I
This pin is the output voltage feedback input through voltage dividers. See Table 2 for more
details.
GND
8
—
IN
3
I
NC
1, 4, 5
—
Not internally connected. The NC pins are not connected to any electrical node. TI
recommends connecting the NC pins to large-area planes.
OUT
6
O
Regulated output pin. A 4.7-μF or larger capacitor of any type is required for stability.
PowerPAD
—
—
TI strongly recommends connecting the thermal pad to a large-area ground plane. If an
electrically floating, dedicated thermal plane is available, the thermal pad can also be
connected to it.
Ground pin
Input pin. Although it is not required for stability, TI recommends connecting a 1-μF to 10-μF
capacitor with low equivalent series resistance (ESR) across this pin and GND.
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6 Specifications
6.1 Absolute Maximum Ratings
over junction temperature range (unless otherwise noted) (1)
Voltage
Current
(2)
MAX
–0.3
7
EN, FB, OUT
–0.3
VIN + 0.3 (2)
OUT
Temperature
(1)
MIN
IN
UNIT
Internally limited
V
A
Operating virtual junction, TJ
–55
150
Storage temperature, Tstg
–55
150
°C
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
The absolute maximum rating is VIN + 0.3 V or 7 V, whichever is smaller.
6.2 ESD Ratings
VALUE
V(ESD)
(1)
(2)
Electrostatic discharge
Human body model (HBM), per ANSI/ESDA/JEDEC JS-001 (1)
±2000
Charged-device model (CDM), per JEDEC specification JESD22-C101 (2)
±500
UNIT
V
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
6.3 Recommended Operating Conditions
MIN
VIN
Input voltage
VEN
Enable pin voltage
CIN
Input capacitor
COUT
Output capacitor (1) (2)
CFB
Feedforward capacitance
IOUT
Output current
TJ
Junction temperature
(1)
(2)
NOM
MAX
UNIT
1.425
6.5
V
0
VIN
V
1
10
µF
200
µF
0
100
nF
0
3
A
–40
125
°C
4.7
10
See Figure 1 and Figure 2 for additional output capacitor ESR requirements.
For output capacitors larger than 47 µF, a feedforward capacitor of at least 220 pF must be used.
6.4 Thermal Information
TPS7A7002
THERMAL METRIC (1)
DDA (SO
PowerPAD)
UNIT
8 PINS
RθJA
Junction-to-ambient thermal resistance
46.4
°C/W
RθJC(top)
Junction-to-case (top) thermal resistance
54.2
°C/W
RθJB
Junction-to-board thermal resistance
29.9
°C/W
ψJT
Junction-to-top characterization parameter
10.2
°C/W
ψJB
Junction-to-board characterization parameter
29.8
°C/W
RθJC(bot)
Junction-to-case (bottom) thermal resistance
6.8
°C/W
(1)
4
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
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6.5 Electrical Characteristics
Over the full operating temperature range (see Recommended Operating Conditions), VEN = 1.1 V, VFB = VOUT (1), 1.425 V ≤
VIN ≤ 6.5 V, 10 µA ≤ IOUT ≤ 3 A, COUT = 10 μF (unless otherwise noted). Typical values are at TJ = 25°C.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
INPUT VOLTAGE
GND pin current
VIN = 3.3 V,
50-Ω load resistor between OUT and GND
3
mA
Shutdown GND pin current
VIN = 6.5 V, VEN = 0 V
5
µA
IGND
OUTPUT VOLTAGE
Output voltage accuracy (2) (3)
VOUT
VIN = VOUT + 0.5 V (4), IOUT = 10 mA
–2%
2%
VIN = 1.8 V, IOUT = 0.8 A, 0°C ≤ TJ = TA ≤ 85°C
–2%
2%
IOUT = 10 mA
–3%
ΔVO(ΔVI)
Line regulation
IOUT = 10 mA
ΔVO(ΔIO)
Load regulation (3)
10 mA ≤ IOUT ≤ 3 A
VDO
Dropout voltage
ICL
(5)
3%
0.2
0.4
%/V
0.25
0.75
%/A
IOUT = 1 A, 0.5 V ≤ VOUT ≤ 5 V
200
IOUT = 2 A, 0.5 V ≤ VOUT ≤ 5 V
380
IOUT = 3 A, 0.5 V ≤ VOUT ≤ 4.8 V
600
Output current limit
VIN = 1.425 V, VOUT = 0.9 × VOUT(NOM)
3.36
VREF
Reference voltage accuracy
VIN = 3.3 V, IOUT = 10 mA
0.49
IFB
FB pin current
VFB = 0.5 V
IEN
EN pin current
VEN = 0 V, VIN = 3.3 V
VEN(LO)
EN pin input low (disable)
VIN = 3.3 V
0
VEN(HI)
EN pin input high (enable)
VIN = 3.3 V
1.1
mV
A
FEEDBACK
0.5
0.51
V
1
µA
0.2
µA
0.5
V
VIN
V
ENABLE
TEMPERATURE
TSD
(1)
(2)
(3)
(4)
(5)
Shutdown, temperature increasing
160
Reset, temperature decreasing
140
Thermal shutdown temperature
°C
When setting VOUT to a value other than 0.5 V, connect R2 to the FB pin using 27-kΩ ≤ R2 ≤ 33-kΩ resistors. See Figure 7 for details of
R1 and R2.
Accuracy does not include error on feedback resistors R1 and R2.
TPS7A7002 is not tested at VOUT = 0.5 V, 2.3 V ≤ VIN ≤ 6.5 V, and 500 mA ≤ IOUT ≤ 3 A because the power dissipation is higher than
the maximum rating of the package. Also, this accuracy specification does not apply to any application condition that exceeds the power
dissipation limit of the package.
VIN = VOUT + 0.5 V or 1.425 V, whichever is greater.
VDO = VIN – VOUT with VFB = GND configuration.
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6.6 Typical Characteristics
for all fixed voltage versions and an adjustable version at TJ = 25°C, VEN = VIN, CIN = 10 μF, COUT = 10 μF, and using the
component values in Table 2 (unless otherwise noted)
10
10
Region of Instability
ESR of Output Capacitor (W)
ESR of Output Capacitor (W)
Region of Instability
1
100m
Stable Region
10m
1m
1
100m
Stable Region
10m
1m
Region of Instability
100u
0
500m
1
Output Current (A)
Region of Instability
1.5
100u
2
0
500m
G000
COUT = 10 µF
Figure 1. Stability Curve
IOUT = 0.1 A
IOUT = 1 A
Dropout Voltage (mV)
PSRR (dB)
−40°C
25°C
125°C
350
40
30
20
10
300
250
200
150
100
50
10
100
1k
10k
100k
Frequency (Hz)
1M
0
10M
0
500m
G002
VIN = 5 V, VOUT = 3.3 V
1
Output Current (A)
1.5
2
G003
VOUT = 3.3 V
Figure 3. Power-Supply Ripple Rejection vs Frequency
Figure 4. Dropout Voltage vs Output Current
400
400
−40°C
25°C
125°C
300
−40°C
25°C
125°C
350
Dropout Voltage (mV)
350
Dropout Voltage (mV)
G001
Figure 2. Stability Curve
50
250
200
150
100
50
300
250
200
150
100
50
0
500m
1
Output Current (A)
1.5
2
0
0
G004
VOUT = 1.6 V
500m
1
Output Current (A)
1.5
2
G005
VOUT = 1.4 V
Figure 5. Dropout Voltage vs Output Current
6
2
400
60
0
1.5
COUT = 100 µF
70
0
1
Output Current (A)
Figure 6. Dropout Voltage vs Output Current
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7 Detailed Description
7.1 Overview
The TPS7A7002 offers a high current supply with very-low dropout voltage. The TPS7A7002 is designed to
minimize the required component count for a simple, small-size, and low-cost solution.
7.2 Functional Block Diagram
OUT
Current
Limit
IN
VOUT
VOUT = 0.5 x (1 +
UVLO
Thermal
Protection
Charge
Pump
0.5V Reference
R1
)
R2
R1
FB
R2
EN
Hysteresis
GND
Figure 7. Adjustable Output Voltage Version
7.3 Feature Description
7.3.1 Internal Current Limit
The TPS7A7002 internal current limit helps protect the regulator during fault conditions. During a current limit
condition, the output sources a fixed amount of current largely independent of output voltage. For reliable
operation, do not operate the device in a current limit state for an extended period of time.
Powering on the device with the enable pin, or increasing the input voltage above the minimum operating voltage
while a low-impedance short exists on the output of the device, may result in a sequence of high-current pulses
from the input to the output of the device. The energy consumed by the device is minimal during these events;
therefore, there is no failure risk. Additional input capacitance helps to mitigate the load transient requirement of
the upstream supply during these events.
7.3.2 Enable (EN)
The enable pin (EN) is an active-high logic input. When it is logic low, the device turns off, and the consumption
current is less than 1 µA. When it is logic high, the device turns on. The EN pin must be connected to a logic
high or logic low level.
When the enable function is not required, connect EN to IN.
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7.4 Device Functional Modes
Table 1 provides a quick comparison between the normal, dropout, and disabled modes of operation.
Table 1. Device Functional Mode Comparison
PARAMETER
OPERATING MODE
VIN
EN
IOUT
TJ
Normal
VIN > VOUT(nom) + VDO
VEN > VEN(HI)
IOUT < ICL
TJ < TSD
Dropout
VIN < VOUT(nom) + VDO
VEN > VEN(HI)
IOUT < ICL
TJ < TSD
Disabled
—
VEN < VEN(LO)
—
TJ > TSD
7.4.1 Normal Operation
The device regulates to the nominal output voltage under the following conditions:
• The input voltage is greater than the nominal output voltage plus the dropout voltage (VOUT(nom) + VDO).
• The enable voltage has previously exceeded the enable rising threshold voltage and not yet decreased below
the enable falling threshold.
• The output current is less than the current limit (IOUT < ICL).
• The device junction temperature is less than the thermal shutdown temperature (TJ < TSD).
7.4.2 Dropout Operation
If the input voltage is lower than the nominal output voltage plus the specified dropout voltage, but all other
conditions are met for normal operation, the device operates in dropout mode. In this mode, the output voltage
tracks the input voltage. During this mode, the transient performance of the device becomes significantly
degraded because the pass device is in a triode state and no longer controls the current through the LDO. Line
or load transients in dropout can result in large output-voltage deviations.
8
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8 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
8.1 Application Information
The TPS7A7002 offers a high current supply with very-low dropout voltage, and it is designed to minimize the
required component count for a simple, small-size, and low-cost solution. This section discusses the
implementation of the TPS7A7002 LDO.
8.1.1 Input Capacitor (IN)
An input capacitor is not required for stability; however, TI recommends connecting a 1-µF to 10-µF low
equivalent series resistance (ESR) capacitor across IN and GND as close as possible to the device.
8.1.2 Output Capacitor (OUT)
The TPS7A7002 is stable with standard ceramic capacitors with capacitance values from 4.7 μF to 47 μF without
a feedforward capacitor. For output capacitors from 47 μF to 200 μF, a feedforward capacitor of at least 220 pF
must be used. The TPS7A7002 is evaluated using an X5R-type, 10-μF ceramic capacitor. X5R- and X7R-type
capacitors are recommended because of minimal variation in value and ESR over temperature. Maximum ESR
must be less than 1 Ω.
As with any regulator, increasing the size of the output capacitor reduces overshoot and undershoot magnitude,
but increases duration of the transient response.
8.1.3 Feedback Resistors (FB)
The voltage on the FB pin sets the output voltage and is determined by the values of R1 and R2. Use Equation 1
to calculate the values of R1 and R2 for any voltage.
æ
R ö
VOUT = VREF ´ ç 1 + 1 ÷
R
è
2ø
(1)
Table 2 shows the recommended resistor values for the best performance of the TPS7A7002. If the values in
Table 2 are not used, keep the value of R2 from 27 kΩ to 33 kΩ. In Table 2, E96 series resistors are used. For
the actual design, pay attention to any resistor error factors.
Table 2. Sample Resistor Values for Common Output Voltages
VOUT
R1 (kΩ)
R2 (kΩ)
1
30.1
30.1
1.2
42.2
30.1
1.5
60.4
30.1
1.8
78.7
30.1
2.5
121
30.1
3
150
30.1
3.3
169
30.1
5
274
30.1
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8.2 Typical Application
This section describes the implementation of the TPS7A7002, using the feedback pin to configure the output
voltage and regulate a 2-A load at 1.4 V using a 1.6-V input voltage, operating in a temperature range of 25°C to
85°C. Figure 8 shows the schematic for this typical application circuit.
NC
NC
TPS7A7002
Input Voltage
Output Voltage
IN
OUT
CIN
COUT
R1
Enable
EN
FB
NC
GND
R2
VOUT = 0.5 ´ 1 +
R1
R2
Figure 8. Typical Application Schematic
8.2.1 Design Requirements
For this design example, use the parameters listed in Table 3 as the input parameters.
Table 3. Design Parameters
PARAMETER
DESIGN REQUIREMENT
Input voltage
1.6 V ±3%
Output voltage
1.4 V ±3%
Maximum output current
2A
Ambient temperature
25°C ≤ TA ≤ 75°C
8.2.2 Detailed Design Procedure
At IOUT = 2 A, the TPS7A7002 has a maximum dropout of less than 150 mV over temperature, as seen in
Figure 9; thus, a 200-mV headroom is sufficient for operation over both input and output voltage accuracy.
To achieve 1.2 V on the output, choose the correct feedback resistors. The Feedback Resistors (FB) section
suggests keeping the value of R2 in the range of 27 kΩ to 33 kΩ, so select R2 to be 30.1 kΩ, a standard resistor
in the E96 series. Using Equation 1 to achieve a 1.4-V output, determine the size for R1 using Equation 2.
R1 = ((2 × VOUT) – 1) × R2
(2)
Given that R2 = 30.1 kΩ and VOUT = 1.4 V, R1 = 54.2 kΩ. The closest resistor in the E96 series is 53.6 kΩ, giving
an output voltage within the output design requirements.
With a headroom voltage of 200 mV and a 2-A maximum load, the internal power dissipation is 400 mW, and
corresponds to a 18.56°C junction temperature rise for the DDA package.
With a 75°C maximum ambient temperature as per design constraints, the junction temperature is at 93.56°C,
and satisfies the recommended operating junction temperature range.
10
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8.2.3 Application Curve
400
−40°C
25°C
125°C
Dropout Voltage (mV)
350
300
250
200
150
100
50
0
0
500m
1
Output Current (A)
1.5
2
G005
VOUT = 1.4 V
Figure 9. Dropout Voltage vs Output Current
9 Power Supply Recommendations
These devices are designed to operate from an input voltage supply range from 1.425 V to 6.5 V. The input
voltage range provides adequate headroom for the device to have a regulated output. This input supply is well
regulated and stable. If the input supply is noisy, additional input capacitors with low ESR can help improve the
output noise performance.
10 Layout
10.1 Layout Guidelines
For best performance, place all circuit components on the same side of the circuit board, and place the external
components as close to the device as practically possible. The use of vias and long traces is strongly
discouraged because of parasitics that might affect performance; follow these guidelines to minimize parasitics.
Also, embed a ground reference plane to maintain accuracy of the output voltage and shield noise. Make sure
that this plane is connected to the PowerPAD in order to help spread (or sink) heat from the device; be aware
that NC pins might be connected to this plane. The recommended layout is shown in Figure 10.
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10.2 Layout Example
R2
TPS7A7002
VEN
NC
1
8
GND
EN
2
7
FB
IN
3
6
OUT
NC
4
5
CIN
R1
VIN
VOUT
NC
COUT
GND PLANE
Figure 10. Layout Recommendation
10.3 Thermal Consideration
Thermal protection disables the output when the junction temperature rises to approximately 160°C, allowing the
device to cool. When the junction temperature cools to approximately 140°C, the output circuitry is re-enabled.
The internal protection circuitry of the TPS7A7002 is designed to protect against overload conditions. The
protection circuitry is not intended to replace proper heat sinking. Continuously running the TPS7A7002 into
thermal shutdown degrades device reliability.
10.4 Power Dissipation
Power dissipation (PD) of the device depends on the input voltage and load conditions, and is calculated using
Equation 3.
PD
VIN VOUT u IOUT
(3)
In order to minimize power dissipation and achieve greater efficiency, use the lowest possible input voltage
necessary to achieve the required output voltage regulation
On the SOIC (DDA) package, the primary conduction path for heat is through the exposed pad to the PCB. The
pad can either be connected to ground or left floating; however, attach the pad to an appropriate amount of
copper PCB area to prevent the device from overheating. The maximum junction-to-ambient thermal resistance
depends on the maximum ambient temperature, maximum device junction temperature, and power dissipation of
the device, and is calculated using Equation 4:
RqJA =
12
+125°C - TA
PD
(4)
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Copyright © 2013–2017, Texas Instruments Incorporated
Product Folder Links: TPS7A7002
TPS7A7002
www.ti.com
SBVS209D – MAY 2013 – REVISED APRIL 2017
11 Device and Documentation Support
11.1 Device Support
11.1.1 Device Nomenclature
PRODUCT (1)
DESCRIPTION
YYY is package designator.
Z is package quantity.
TPS7A7002yyyz
(1)
For the most current package and ordering information see the Package Option Addendum at the end of this document, or visit the
device product folder at www.ti.com.
11.2 Documentation Support
11.2.1 Related Documentation
For related documentation, see the following:
• A Topical Index of TI LDO Application Notes
• Semiconductor and IC Package Thermal Metrics
11.3 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper
right corner, click on Alert me to register and receive a weekly digest of any product information that has
changed. For change details, review the revision history included in any revised document.
11.4 Community Resources
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
11.5 Trademarks
PowerPAD, E2E are trademarks of Texas Instruments.
All other trademarks are the property of their respective owners.
11.6 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
11.7 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
12 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
Submit Documentation Feedback
Copyright © 2013–2017, Texas Instruments Incorporated
Product Folder Links: TPS7A7002
13
PACKAGE OPTION ADDENDUM
www.ti.com
9-Jan-2017
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
Lead/Ball Finish
MSL Peak Temp
(2)
(6)
(3)
Op Temp (°C)
Device Marking
(4/5)
TPS7A7002DDA
ACTIVE SO PowerPAD
DDA
8
75
Green (RoHS
& no Sb/Br)
CU NIPDAUAG
Level-2-260C-1 YEAR
-40 to 125
SJA
TPS7A7002DDAR
ACTIVE SO PowerPAD
DDA
8
2500
Green (RoHS
& no Sb/Br)
CU NIPDAUAG
Level-2-260C-1 YEAR
-40 to 125
SJA
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
Addendum-Page 1
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
9-Jan-2017
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
9-Jan-2017
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
TPS7A7002DDAR
Package Package Pins
Type Drawing
SO
Power
PAD
DDA
8
SPQ
Reel
Reel
A0
Diameter Width (mm)
(mm) W1 (mm)
2500
330.0
12.8
Pack Materials-Page 1
6.4
B0
(mm)
K0
(mm)
P1
(mm)
5.2
2.1
8.0
W
Pin1
(mm) Quadrant
12.0
Q1
PACKAGE MATERIALS INFORMATION
www.ti.com
9-Jan-2017
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
TPS7A7002DDAR
SO PowerPAD
DDA
8
2500
366.0
364.0
50.0
Pack Materials-Page 2
GENERIC PACKAGE VIEW
DDA 8
PowerPAD TM SOIC - 1.7 mm max height
PLASTIC SMALL OUTLINE
Images above are just a representation of the package family, actual package may vary.
Refer to the product data sheet for package details.
4202561/G
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IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT OF THIRD
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