UCC27284-Q1
SLUSE23A – MARCH 2020 – REVISEDUCC27284-Q1
NOVEMBER 2020
SLUSE23A – MARCH 2020 – REVISED NOVEMBER 2020
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UCC27284-Q1 Automotive 120-V Half-Bridge Driver
with Negative Voltage Handling and Low Switching Losses
1 Features
3 Description
•
The UCC27284-Q1 is a robust N-channel MOSFET
driver with a maximum switch node (HS) voltage
rating of 100 V. It allows for two N-channel MOSFETs
to be controlled in half-bridge or synchronous buck
configuration based topologies. Its 3.5-A peak sink
current and 2.5-A peak source current along with low
pull-up and pull-down resistance allows the
UCC27284-Q1 to drive large power MOSFETs with
minimum switching losses during the transition of the
MOSFET Miller plateau. Since the inputs are
independent of the supply voltage, UCC27284-Q1 can
be used in conjunction with both analog and digital
controllers. Two inputs, and therefore outputs, can be
overlapped, if needed, in applications such as
secondary side full-bridge synchronous rectification.
•
•
•
•
•
•
•
•
•
•
AEC-Q100 qualified with following results
– Temperature grade 1 (Tj = –40°C to 150°C)
– Device HBM ESD classification level 1B
– Device CDM ESD classification level C3
Drives two N-channel MOSFETs in high-side lowside configuration
5-V typical under voltage lockout
16-ns typical propagation delay
12-ns rise, 10-ns fall time with 1.8-nF load
1-ns typical delay matching
5-V negative voltage handling on inputs
14-V negative voltage handling on HS
3.5-A sink, 2.5-A Source output currents
Absolute maximum boot voltage 120 V
Integrated bootstrap diode
2 Applications
•
•
•
•
•
Automotive DC/DC converters
Electric power steering
On-board charger (OBC)
Integrated belt starter generator (iBSG)
Automotive HVAC compressor modules
7V
75V
VDD
HO
HI
HB
LI
HS
VSS
LO
To Load
The input pins as well as the HS pin are able to
tolerate significant negative voltage, which improves
system robustness. 5-V UVLO allows systems to
operate at lower bias voltages, which is necessary in
many high frequency applications and improves
system efficiency in certain operating modes. Small
propagation delay and delay matching specifications
minimize the dead-time requirement which further
improves efficiency.
Under voltage lockout (UVLO) is provided for both the
high-side and low-side driver stages forcing the
outputs low if the VDD voltage is below the specified
threshold. An integrated bootstrap diode eliminates
the need for an external discrete diode in many
applications, which saves board space and reduces
system cost. UCC27284-Q1 is offered in SOIC
package for harsh system environments.
Device Information (1)
PART NUMBER
UCC27284-Q1
Simplified Application Diagram
(1)
PACKAGE (DESIGNATOR) (SIZE)
SOIC8 (D) (6 mm x 5mm)
SOIC8-PowerPAD (DDA) (6 mm x 5mm)
For all available packages, see the orderable addendum at
the end of the data sheet.
An©IMPORTANT
NOTICEIncorporated
at the end of this data sheet addresses availability, warranty, changes, use in
safety-critical
applications,
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2020 Texas Instruments
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intellectual property matters and other important disclaimers. PRODUCTION DATA.
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Table of Contents
1 Features............................................................................1
2 Applications..................................................................... 1
3 Description.......................................................................1
4 Revision History.............................................................. 2
5 Pin Configuration and Functions...................................3
Pin Functions.................................................................... 3
6 Specifications.................................................................. 4
6.1 Absolute Maximum Ratings........................................ 4
6.2 ESD Ratings............................................................... 4
6.3 Recommended Operating Conditions.........................4
6.4 Thermal Information....................................................5
6.5 Electrical Characteristics.............................................5
6.6 Switching Characteristics............................................6
6.7 Timing Diagrams......................................................... 6
6.8 Typical Characteristics................................................ 7
7 Detailed Description......................................................12
7.1 Overview................................................................... 12
7.2 Functional Block Diagram......................................... 12
7.3 Feature Description...................................................12
7.4 Device Functional Modes..........................................14
8 Application and Implementation.................................. 15
8.1 Application Information............................................. 15
8.2 Typical Application.................................................... 16
9 Power Supply Recommendations................................24
10 Layout...........................................................................25
10.1 Layout Guidelines................................................... 25
10.2 Layout Example...................................................... 25
11 Device and Documentation Support..........................26
11.1 Receiving Notification of Documentation Updates.. 26
11.2 Support Resources................................................. 26
11.3 Trademarks............................................................. 26
11.4 Glossary.................................................................. 26
12 Mechanical, Packaging, and Orderable
Information.................................................................... 26
4 Revision History
Changes from Revision * (March 2020) to Revision A (October 2020)
Page
• Changed marketing status from Advance Information to initial release..............................................................1
2
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5 Pin Configuration and Functions
VDD
1
8
LO
HB
2
7
VSS
HO
3
6
LI
HS
4
5
HI
Not to scale
Figure 5-1. D Package 8-Pin SOIC Top View
VDD
1
HB
2
8
LO
7
VSS
6
LI
5
HI
Thermal
HO
3
HS
4
Pad
Not to scale
Figure 5-2. DDA Package 8-Pin SOIC with PowerPAD Top View
Pin Functions
PIN
Name
D
DDA
I/O(1)
DESCRIPTION
HB
2
2
P
High-side bootstrap supply. The bootstrap diode is on-chip but the external bootstrap
capacitor is required. Connect positive side of the bootstrap capacitor to this pin. Typical
recommended value of HB bypass capacitor is 0.1 μF, This value primarily depends on the
gate charge of the high-side MOSFET. When using external boot diode, connect cathode of
the diode to this pin.
HI
5
5
I
High-side input.
HO
3
3
O
High-side output. Connect to the gate of the high-side power MOSFET or one end of
external gate resistor, when used.
HS
4
4
P
High-side source connection. Connect to source of high-side power MOSFET. Connect
negative side of bootstrap capacitor to this pin.
LI
6
6
I
Low-side input
LO
8
8
O
Low-side output. Connect to the gate of the low-side power MOSFET or one end of external
gate resistor, when used.
VDD
1
1
P
Positive supply to the low-side gate driver. Decouple this pin to VSS. Typical decoupling
capacitor value is 1 μF. When using an external boot diode, connect the anode to this pin.
Thermal
Pad
n/a
Pad
-
Connect to a large thermal mass trace (generally IC ground plane, VSS) to improve thermal
performance. This can only be electrically connected to VSS.
(1)
P = Power, G = Ground, I = Input, O = Output, I/O = Input/Output
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6 Specifications
6.1 Absolute Maximum Ratings
All voltages are with respect to Vss (1) (2)
VDD
Supply voltage
VHI, VLI
Input voltages on HI and LI
VLO
Output voltage on LO
VHO
Output voltage on HO
VHS
Voltage on HS
DC
Pulses < 100 ns(3)
DC
Pulses < 100
ns(3)
DC
Pulses < 100
ns(3)
MIN
MAX
UNIT
–0.3
20
V
V
–5
20
–0.3
VDD + 0.3
–2
VDD + 0.3
VHS – 0.3
VHB + 0.3
VHS – 2
VHB + 0.3
–10
100
–14
100
V
V
V
VHB
Voltage on HB
–0.3
120
V
VHB-HS
Voltage on HB with respect to HS
–0.3
20
V
TJ
Operating junction temperature
–40
150
°C
300
°C
150
°C
Lead temperature (soldering, 10 sec.)
Tstg
(1)
(2)
(3)
Storage temperature
–65
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under
Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device
reliability.
All voltages are with respect to Vss. Currents are positive into, negative out of the specified terminal.
Values are verified by characterization only.
6.2 ESD Ratings
VALUE
V(ESD)
(1)
(2)
Electrostatic discharge
Human-body model (HBM), per AEC Q100-002
(1) (2)
±2000
Charged-device model (CDM), per AEC Q100-011
±1500
UNIT
V
AEC Q100-002 indicates that HBM stressing shall be in accordance with the ANSI/ESDA/JEDEC JS-001 specification..
Pins HS, HB and HO are rated at 500V HBM
6.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
VDD
Supply voltage
VHI, VLI
Input Voltage
VLO
VHO
VHS
VHB
4
NOM
5.5
12
MAX
UNIT
16
V
0
VDD
Low side output voltage
0
VDD
High side output voltage
VHS
VHB
Voltage on
HS(1)
Voltage on HS (Pulses < 100 ns)(1)
Voltage on HB
Vsr
Voltage slew rate on HS
TJ
Operating junction temperature
(1)
MIN
–8
100
–12
100
VHS + 5.5
VHS+16
V
50
V/ns
–40
150
°C
V
VHB-HS < 16V (Voltage on HB with respect to HS must be less than 16V)
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6.4 Thermal Information
UCC27284-Q1
THERMAL
METRIC(1)
UNIT
D
DDA
8 PINS
8 PINS
RθJA
Junction-to-ambient thermal resistance
118.3
40.8
°C/W
RθJC(top)
Junction-to-case (top) thermal resistance
53.6
54.4
°C/W
RθJB
Junction-to-board thermal resistance
63.1
16.4
°C/W
ψJT
Junction-to-top characterization parameter
10.7
4.1
°C/W
ψJB
Junction-to-board characterization parameter
62.1
16.4
°C/W
RθJC(bot)
Junction-to-case (bottom) thermal resistance
n/a
4.9
°C/W
(1)
For more information about thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report, SPRA953
6.5 Electrical Characteristics
VDD = VHB = 12 V, VHS = VSS = 0 V, No load on LO or HO, TJ = –40°C to +150°C, (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX UNIT
SUPPLY CURRENTS
IDD
VDD quiescent current
VLI = VHI = 0
0.3
0.4
mA
IDDO
VDD operating current
f = 500 kHz, CLOAD = 0
2.2
4.5
mA
IHB
HB quiescent current
VLI = VHI = 0 V
0.2
0.4
mA
IHBO
HB operating current
f = 500 kHz, CLOAD = 0
2.5
4
mA
IHBS
HB to VSS quiescent current
VHS = VHB = 110 V
5.0
50
μA
f = 500 kHz, CLOAD = 0
0.1
IHBSO
HB to VSS operating
current(1)
mA
INPUT
VHIT
Input rising threshold
1.9
2.1
2.4
V
VLIT
Input falling threshold
0.9
1.1
1.3
V
100
250
350
kΩ
5.0
5.4
V
4.5
4.9
V
VIHYS
Input voltage Hysteresis
RIN
Input pulldown resistance
1.0
V
UNDERVOLTAGE LOCKOUT PROTECTION (UVLO)
VDDR
VDD rising threshold
4.7
VDDF
VDD falling threshold
4.2
VDDHYS
VDD threshold hysteresis
VHBR
HB rising threshold with respect to HS pin
3.3
3.7
4.7
V
VHBF
HB falling threshold with respect to HS pin
3.0
3.3
4.4
V
VHBHYS
HB threshold hysteresis
0.5
V
0.3
V
BOOTSTRAP DIODE
VF
Low-current forward voltage
IVDD-HB = 100 μA
0.65
0.85
V
VFI
High-current forward voltage
IVDD-HB = 80 mA
0.85
1.0
V
RD
Dynamic resistance, ΔVF/ΔI
IVDD-HB = 100 mA and 80 mA
1.5
2.5
Ω
LO GATE DRIVER
VLOL
Low level output voltage
ILO = 100 mA
0.085
0.4
V
VLOH
High level output voltage
ILO = -100 mA, VLOH = VDD – VLO
0.13
0.42
V
VLO = 0 V
2.5
A
VLO = 12 V
3.5
A
Peak pullup current
(1)
Peak pulldown current (1)
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VDD = VHB = 12 V, VHS = VSS = 0 V, No load on LO or HO, TJ = –40°C to +150°C, (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX UNIT
HO GATE DRIVER
VHOL
Low level output voltage
IHO = 100 mA
0.1
0.4
V
VHOH
High level output voltage
IHO = –100 mA, VHOH = VHB- VHO
0.12
0.42
V
Peak pullup current (1)
VHO = 0 V
2.5
A
Peak pulldown current (1)
VHO = 12 V
3.5
A
(1)
Parameter not tested in production
6.6 Switching Characteristics
VDD = VHB = 12 V, VHS = VSS = 0 V, No load on LO or HO, TJ = –40°C to +150°C, (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
PROPAGATION DELAYS
tDLFF
VLI falling to VLO falling
See Section 6.7
16
30
ns
tDHFF
VHI falling to VHO falling
See Section 6.7
16
30
ns
tDLRR
VLI rising to VLO rising
See Section 6.7
16
30
ns
tDHRR
VHI rising to VHO rising
See Section 6.7
16
30
ns
DELAY MATCHING
tMON
From LO being ON to HO being OFF
See Section 6.7
1
7
ns
tMOFF
From LO being OFF to HO being ON
See Section 6.7
1
7
ns
12
OUTPUT RISE AND FALL TIME
tR
LO, HO rise time
CLOAD = 1800 pF, 10% to 90%
ns
tF
LO, HO fall time
CLOAD = 1800 pF, 90% to 10%
tR
LO, HO (3 V to 9 V) rise time
CLOAD = 0.1 μF, 30% to 70%
0.33
10
0.6
μs
ns
tF
LO, HO (3 V to 9 V) fall time
CLOAD = 0.1 μF, 70% to 30%
0.23
0.6
μs
MISCELLANEOUS
TPW,min
Minimum input pulse width that changes the output
Bootstrap diode turnoff
(1)
time(1)
IF = 20 mA, IREV = 0.5 A
20
ns
50
ns
Parameter not tested in production
6.7 Timing Diagrams
LI
Voltage (V)
Voltage (V)
HI
Input
(HI, LI)
LO
TDLRR, TDHRR
Output
(HO, LO)
HO
Time (s)
TDLFF,
TDHFF
Time (s)
TMON
6
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6.8 Typical Characteristics
Unless otherwise specified VVDD=VHB = 12 V, VHS=VVSS = 0 V, No load on outputs
0.22
0.3
VDD Quiescent Current (mA)
0.28
HB Quiescent Current (mA)
0.26
0.24
0.22
0.2
0.18
0.16
0.14
5.5V
12V
16V
0.12
0.1
-40
-15
10
A.
35
60
85
Temperature (°C)
110
0.18
0.14
0.1
0.06
5.5V
12V
16V
0.02
-40
135 150
10
A.
VHI = VLI = 0 V
35
60
85
Temperature (°C)
110
135 150
IHBQ
VHI = VLI = 0 V
Figure 6-2. HB Quiescent Current
Figure 6-1. VDD Quiescent Current
6
4.5
-40°C
25°°C
150°°C
5
-40°C
25°C
150°C
4
3.5
3
IHBO (mA)
4
IDDO (mA)
-15
IDDQ
3
2.5
2
1.5
2
1
1
0.5
0
0
1
2
3 4 5 67 10
20 30 50 70100
Frequency (kHz)
200
1
500 1000
2
2.22
18
2.21
Input Rising Threshold (V)
21
IHBS (PA)
15
12
9
6
200
500 1000
IHBO
2.2
2.19
2.18
5.5V
12V
16V
2.17
3
A.
20 30 50 70100
Frequency (kHz)
Figure 6-4. HB Operating Current
Figure 6-3. VDD Operating Current
0
-40
3 4 5 67 10
IDDO
-15
10
35
60
85
Temperature (°C)
110
135 150
VHB=VHS=100V
2.16
-40
-15
10
35
60
85
Temperature (°C)
110
IHBS
135 150
IN_R
Figure 6-6. Input Rising Threshold
Figure 6-5. HB to VSS Quiescent Current
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280
1.145
270
1.135
Input Resistance (k:)
Input Falling Threshold (V)
1.14
1.13
1.125
1.12
1.115
1.105
-40
-15
10
35
60
85
Temperature (°C)
110
250
240
5.5V
12V
16V
1.11
260
230
-40
135 150
5.2
4
5
3.8
4.8
4.6
135 150
R_IN
3.4
Rise
Fall
-15
10
35
60
85
Temperature (°C)
110
3
-40
135 150
-15
10
VDDU
35
60
85
Temperature (°C)
110
135 150
HBUV
Figure 6-10. HB UVLO Threshold
Figure 6-9. VDD UVLO Threshold
1
1.8
Diode Dynamic Resistance (:)
100uA
80mA
Diode Forward Voltage (V)
110
3.6
Rise
Fall
0.8
0.6
0.4
-15
10
35
60
85
Temperature (°C)
110
135 150
Vfq1
Figure 6-11. Boot Diode Forward Voltage Drop
8
35
60
85
Temperature (°C)
3.2
4.4
0.2
-40
10
Figure 6-8. Input Pull-down Resistor
HB UVLO (V)
VDD UVLO (V)
Figure 6-7. Input Falling Threshold
4.2
-40
-15
IN_F
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1.7
1.6
1.5
1.4
1.3
1.2
-40
-15
10
35
60
85
Temperature (°C)
110
135 150
R_Dy
Figure 6-12. Boot Diode Dynamic Resistance
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0.22
0.14
0.2
Output Voltage (V)
Output Voltage (V)
0.12
0.1
0.18
0.16
0.14
0.08
5.5V
12V
16V
0.06
-40
A.
-15
10
35
60
85
Temperature (°C)
110
5.5V
12V
16V
0.12
0.1
-40
135 150
-15
10
V_LO
A.
IO=100mA
35
60
85
Temperature (°C)
110
135 150
V_LO
IO=-100mA
Figure 6-13. LO Low Output Voltage (VLOL)
Figure 6-14. LO High Output Voltage (VLOH)
0.2
0.16
0.18
Output Voltage (V)
Output Voltage (V)
0.14
0.12
0.16
0.14
0.12
0.1
5.5V
12V
16V
0.08
-40
A.
-15
10
35
60
85
Temperature (°C)
110
0.08
-40
135 150
-15
10
UCC2
V_HO
A.
IO=100mA
35
60
85
Temperature (°C)
110
135 150
V_HO
IO=-100mA
Figure 6-15. HO Low Output Voltage (VHOL)
Figure 6-16. HO High Output Voltage (VHOH)
15
10.5
5.5V
12V
16V
10
LO Fall Time (ns)
14
LO Rise Time (ns)
5.5V
12V
16V
0.1
13
12
11
5.5V
12V
16V
9.5
9
8.5
10
9
-40
A.
-15
10
35
60
85
Temperature (°C)
110
CL=1800pF
Figure 6-17. LO Rise Time
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8
-40
135 150
-15
10
35
60
85
Temperature (°C)
110
LO_R
A.
135 150
LO_F
CL=1800pF
Figure 6-18. LO Fall Time
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18
9
5.5V
12V
16V
5.5V
12V
16V
8.7
HO Fall Time (ns)
HO Rise Time (ns)
15
12
8.4
8.1
7.8
9
7.5
6
-40
A.
-15
10
35
60
85
Temperature (°C)
110
7.2
-40
135 150
A.
CL=1800pF
35
60
85
Temperature (°C)
110
135 150
HO_F
Figure 6-20. HO Fall Time
0.41
0.47
0.38
0.43
0.39
Time (Ps)
0.35
Time (Ps)
10
CL=1800pF
Figure 6-19. HO Rise Time
0.32
0.29
0.26
0.35
0.31
0.27
0.23
0.23
0.19
Rise
Fall
0.2
-40
A.
-15
HO_R
-15
10
35
60
85
Temperature (°C)
110
Rise
Fall
0.15
-40
135 150
-15
10
LO_R
A.
CL=100nF
35
60
85
Temperature (°C)
110
135 150
HO_R
CL=100nF
Figure 6-21. LO Rise & Fall Time
Figure 6-22. HO Rise & Fall Time
20
19
18.5
19
18
17.5
Time (ns)
Time (ns)
18
17
17
16.5
16
16
15.5
5.5V
12V
16V
15
14
-40
-15
10
35
60
85
Temperature (°C)
110
135 150
TDHR
5.5V
12V
16V
15
14.5
-40
-15
10
35
60
85
Temperature (°C)
110
135 150
TDLF
Figure 6-23. HO Rising Propagation Delay (TDHRR) Figure 6-24. HO Falling Propagation Delay (TDHFF)
10
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20
19
19.5
18.5
19
18
17.5
18
Time (ns)
Time (ns)
18.5
17.5
17
16.5
16
16.5
16
15.5
5.5V
12V
16V
15.5
15
-40
17
-15
10
35
60
85
Temperature (°C)
110
5.5V
12V
16V
15
135 150
TDLR
14.5
-40
-15
10
35
60
85
Temperature (°C)
110
135 150
TDLF
Figure 6-25. LO Rising Propagation Delay (TDLRR) Figure 6-26. LO Falling Propagation Delay (TDLFF)
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7 Detailed Description
7.1 Overview
The UCC27284-Q1 is a high-voltage gate driver designed to drive both the high-side and the low-side N-channel
FETs in a synchronous buck or a half-bridge configurations. The two outputs are independently controlled with
two TTL-compatible input signals. The device can also work with CMOS type control signals at its inputs as long
as signals meet turn-on and turn-off threshold specifications of the UCC27284-Q1. The floating high-side driver
is capable of working with HS voltage up to 100 V with respect to VSS. A 100 V bootstrap diode is integrated in
the UCC27284-Q1 device to charge high-side gate drive bootstrap capacitor. A robust level shifter operates at
high speed while consuming low power and provides clean level transitions from the control logic to the high-side
gate driver. Undervoltage lockout (UVLO) is provided on both the low-side and the high-side power rails.
7.2 Functional Block Diagram
HB
UVLO
LEVEL
SHIFT
DRIVER
STAGE
HO
HS
HI
VDD
UVLO
DRIVER
STAGE
LO
VSS
LI
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7.3 Feature Description
7.3.1 Start-up and UVLO
Both the high-side and the low-side driver stages include UVLO protection circuitry which monitors the supply
voltage (V DD) and the bootstrap capacitor voltage (V HB–HS). The UVLO circuit inhibits each output until sufficient
supply voltage is available to turn on the external MOSFETs. The built-in UVLO hysteresis prevents chattering
during supply voltage variations. When the supply voltage is applied to the VDD pin of the device, both the
outputs are held low until VDD exceeds the UVLO threshold, typically 5 V. Any UVLO condition on the bootstrap
capacitor (VHB–HS) disables only the high- side output (HO).
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Table 7-1. VDD UVLO Logic Operation
Condition (VHB-HS > VHBR
VDD-VSS < VDDR during device start-up
VDD-VSS < VDDR – VDDH after device start-up
HI
LI
HO
LO
H
L
L
L
L
H
L
L
H
H
L
L
L
L
L
L
H
L
L
L
L
H
L
L
H
H
L
L
L
L
L
L
HI
LI
HO
LO
H
L
L
L
Table 7-2. HB UVLO Logic Operation
Condition (VDD > VDDR
VHB-HS < VHBR during device start-up
VHB-HS < VHBR – VHBH after device start-up
L
H
L
H
H
H
L
H
L
L
L
L
H
L
L
L
L
H
L
H
H
H
L
H
L
L
L
L
7.3.2 Input Stage
The two inputs operate independent of each other and also independent of VDD. The independence allows for
full control of two outputs compared to the gate drivers that have a single input. The overlap of inputs and
therefore respective outputs allow the use in applications such as secondary side synchronous rectification.
Whenever both the inputs are high, both the outputs shall be high as well. In other words, the outputs follow the
input logic in all operating conditions except when the driver is in UVLO mode. There is no fixed time de-glitch
filter implemented in the device and therefore propagation delay and delay matching are not sacrificed. In other
words, there is no built-in dead-time feature. Because the inputs are independent of supply voltage, they can be
connected to outputs of either digital controller or analog controller. Inputs can accept wide slew rate signals and
input can withstand negative voltage to increase the robustness. Small filter at the inputs of the driver further
improves system robustness in noise prone applications. The inputs have internal pull down resistors with typical
value of 250 kΩ. Thus, when the inputs are floating, the outputs are held low.
7.3.3 Level Shifter
The level shift circuit is the interface from the high-side input, which is a VSS referenced signal, to the high-side
driver stage which is referenced to the switch node (HS pin). The level shift allows control of the HO output
which is referenced to the HS pin. The delay introduced by the level shifter is kept as low as possible and
therefore the device provides excellent propagation delay characteristic and delay matching with the low-side
driver output. Low delay matching allows power stages to operate with less dead time. The reduction in deadtime is very important in applications where high efficiency is required.
7.3.4 Output Stage
The output stages are the interface from level shifter output to the power MOSFETs in the power train. High slew
rate, low resistance, and high peak current capability of both outputs allow for efficient switching of the power
MOSFETs. The low-side output stage is referenced to VSS and the high-side is referenced to HS. The device
output stages are robust to handle harsh environment, such as –2 V transient for 100 ns. The device can also
sustain positive transients on the outputs. The device output stages feature a pull-up structure which delivers the
highest peak source current when it is most needed, during the Miller plateau region of the power switch turn on
transition. The output pull-up and pull-down structure of the device is totem pole NMOS-PMOS structure.
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7.3.5 Negative Voltage Transients
In most applications, the body diode of the external low-side power MOSFET clamps the HS node to ground. In
some situations, board capacitances and inductances can cause the HS node to transiently swing several volts
below ground, before the body diode of the external low-side MOSFET clamps this swing. When used in
conjunction with the UCC27284-Q1, the HS node can swing below ground as long as specifications are not
violated and conditions mentioned in this section are followed.
HS must always be at a lower potential than HO. Pulling HO more negative than specified conditions can
activate parasitic transistors which may result in excessive current flow from the HB supply. This may result in
damage to the device. The same relationship is true with LO and VSS. If necessary, a Schottky diode can be
placed externally between HO and HS or LO and VSS to protect the device from this type of transient. The diode
must be placed as close to the device pins as possible in order to be effective.
Ensure that the HB to HS operating voltage is 16 V or less. Hence, if the HS pin transient voltage is –5 V, then
VDD (and thus HB) is ideally limited to 11 V to keep the HB to HS voltage below 16 V. Generally when HS
swings negative, HB follows HS instantaneously and therefore the HB to HS voltage does not significantly
overshoot.
Low ESR bypass capacitors from HB to HS and from VDD to VSS are essential for proper operation of the gate
driver device. The capacitor should be located at the leads of the device to minimize series inductance. The
peak currents from LO and HO can be quite large. Any series inductances with the bypass capacitor causes
voltage ringing at the leads of the device which must be avoided for reliable operation.
Based on application board design and other operating parameters, along with HS pin, other pins such as
inputs, HI and LI, might also transiently swing below ground. To accommodate such operating conditions
UCC27284-Q1 input pins are capable of handling absolute maximum of -5V. As explained earlier, based on the
layout and other design constraints, some times the outputs, HO and LO, might also see transient voltages for
short durations. Therefore, UCC27284-Q1 gate drivers can also handle -2 V 100 ns transients on output pins,
HO and LO.
7.4 Device Functional Modes
The device operates in normal mode and UVLO mode. See Section 7.3.1 for more information on UVLO
operation mode. In normal mode when the V DD and V HB–HS are above UVLO threshold, the output stage is
dependent on the states of the HI and LI pins. The output HO and LO will be low if input state is floating.
Table 7-3. Input/Output Logic in Normal Mode of Operation
(1)
(2)
14
HI
LI
HO (1)
LO (2)
H
H
H
H
L
H
L
H
H
L
H
L
L
L
L
L
Floating
L
L
L
Floating
H
L
H
L
Floating
L
L
H
Floating
H
L
Floating
Floating
L
L
HO is measured with respect to HS
LO is measured with respect to VSS
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8 Application and Implementation
Note
Information in the following applications sections is not part of the TI component specification, and TI
does not warrant its accuracy or completeness. TI’s customers are responsible for determining
suitability of components for their purposes. Customers should validate and test their design
implementation to confirm system functionality.
8.1 Application Information
Most electronic devices and applications are becoming more and more power hungry. These applications are
also reducing in overall size. One way to achieve both high power and low size is to improve the efficiency and
distribute the power loss optimally. Most of these applications employ power MOSFETs and they are being
switched at higher and higher frequencies. To operate power MOSFETs at high switching frequencies and to
reduce associated switching losses, a powerful gate driver is employed between the PWM output of controller
and the gates of the power semiconductor devices, such as power MOSFETs, IGBTs, SiC FETs, and GaN FETs.
Many of these applications require proper UVLO protection so that power semiconductor devices are turned ON
and OFF optimally. Also, gate drivers are indispensable when it is impossible for the PWM controller to directly
drive the gates of the switching devices. With the advent of digital power, this situation is often encountered
because the PWM signal from the digital controller is often a 3.3-V logic signal which cannot effectively turn on a
power switch. A level-shift circuit is needed to boost the 3.3-V signal to the gate-drive voltage (such as 12 V or 5
V) in order to fully turn-on the power device, minimize conduction losses, and minimize the switching losses.
Traditional buffer drive circuits based on NPN/PNP bipolar transistors in totem-pole arrangement prove
inadequate with digital power because they lack level-shifting capability and under voltage lockout protection.
Gate drivers effectively combine both the level-shifting and buffer-drive functions. Gate drivers also solve other
problems such as minimizing the effect of high-frequency switching noise (by placing the high-current driver
device physically close to the power switch), driving gate-drive transformers and controlling floating power device
gates. This helps reduce power dissipation and thermal stress in controllers by moving gate charge power losses
from the controller IC to the gate driver.
UCC27284-Q1 gate drivers offer high voltage (100 V), small delays (16 ns), and good driving capability (2.5
A/3.5 A) in a single device. The floating high-side driver is capable of operating with switch node voltages up to
100 V. This allows for N-channel MOSFETs control in half-bridge, full-bridge, synchronous buck, synchronous
boost, and active clamp topologies. UCC27284-Q1 gate driver IC also has built-in bootstrap diode to help power
supply designers optimize PWB area and to help reduce bill of material cost in most applications. Each channel
is controlled by its respective input pins (HI and LI), allowing flexibility to control ON and OFF state of the output.
Switching power devices such as MOSFETs have two main loss components; switching losses and conduction
losses. Conduction loss is dominated by current through the device and ON resistance of the device. Switching
losses are dominated by gate charge of the switching device, gate voltage of the switching device, and switching
frequency. Applications where operating switching frequency is very high, the switching losses start to
significantly impact overall system efficiency. In such applications, to reduce the switching losses it becomes
essential to reduce the gate voltage. The gate voltage is determined by the supply voltage the gate driver ICs,
therefore, the gate driver IC needs to operate at lower supply voltage in such applications. UCC27284-Q1 gate
driver has typical UVLO level of 5V and therefore, they are perfectly suitable for such applications. There is
enough UVLO hysteresis provided to avoid any chattering or nuisance tripping which improves system
robustness.
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8.2 Typical Application
7V
75 V
VDD
SECONDARY
SIDE
CIRCUIT
HB
HI
LI
CONTROL
PWM
CONTROLLER
DRIVE
HI
HO
HS
DRIVE
LO
LO
UCC27284-Q1
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Figure 8-1. Typical Application
8.2.1 Design Requirements
Table below lists the system parameters. UCC27284-Q1 needs to operate satisfactorily in conjunction with them.
Table 8-1. Design Requirements
Parameter
Value
MOSFET
CSD19535KTT
Maximum Bus/Input Voltage, Vin
75V
Operating Bias Voltage, VDD
7V
Switching Frequency, Fsw
300kHz
Total Gate Charge of FET at given VDD, QG
52nC
MOSFET Internal Gate Resistance, RGFET_Int
1.4
Maximum Duty Cycle, DMax
0.5
Gate Driver
UCC27284-Q1
8.2.2 Detailed Design Procedure
8.2.2.1 Select Bootstrap and VDD Capacitor
The bootstrap capacitor must maintain the V HB-HS voltage above the UVLO threshold for normal operation.
Calculate the maximum allowable drop across the bootstrap capacitor, ΔVHB, with Equation 1.
¿VHB = VDD F VDH F VHBL
= :7 V 1 V (4.4 V 0.37 V); = 1.97 V
(1)
where
•
•
•
VDD is the supply voltage of gate driver device
VDH is the bootstrap diode forward voltage drop
VHBL is the HB falling threshold ( VHBR(max) – VHBH)
In this example the allowed voltage drop across bootstrap capacitor is 1.97 V.
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It is generally recommended that ripple voltage on both the bootstrap capacitor and VDD capacitor should be
minimized as much as possible. Many of commercial, industrial, and automotive applications use ripple value of
0.5 V.
Use Equation 2 to estimate the total charge needed per switching cycle from bootstrap capacitor.
DMAX
IHB
Q TOTAL = Q G + IHBS × l
p+l
p
fSW
fSW
= 52 nC + 0.083 nC + 1.33 nC = 53.41 nC
(2)
where
•
•
•
•
QG is the total MOSFET gate charge
IHBS is the HB to VSS leakage current from datasheet
DMax is the converter maximum duty cycle
IHB is the HB quiescent current from the datasheet
The caculated total charge is 53.41 nC.
Next, use Equation 3 to estimate the minimum bootstrap capacitor value.
CBOOT :min ; =
QTOTAL
53.41 nC
=
= 27.11 nF
¿VHB
1.97 V
(3)
The calculated value of minimum bootstrap capacitor is 27.11 nF. It should be noted that, this value of
capacitance is needed at full bias voltage. In practice, the value of the bootstrap capacitor must be greater than
calculated value to allow for situations where the power stage may skip pulse due to various transient conditions.
It is recommended to use a 100-nF bootstrap capacitor in this example. It is also recommenced to include
enough margin and place the bootstrap capacitor as close to the HB and HS pins as possible. Also place a small
size, 0402, low value, 1000 pF, capacitor to filter high frequency noise, in parallel with main bypass capacitor.
For this application, choose a CBOOT capacitor that has the following specifications: 0.1 µF, 25 V, X7R
As a general rule the local VDD bypass capacitor must be greater than the value of bootstrap capacitor value
(generally 10 times the bootstrap capacitor value). For this application choose a C VDD capacitor with the
following specifications: 1 µF , 25 V, X7R
C VDD capacitor is placed across VDD and VSS pin of the gate driver. Similar to bootstrap capacitors, place a
small size and low value capacitor in parallel with the main bypass capacitor. For this application, choose 0402,
1000 pF, capacitance in parallel with main bypass capacitor to filter high frequency noise.
The bootstrap and bias capacitors must be ceramic types with X7R dielectric or better. Choose a capacitor with a
voltage rating at least twice the maximum voltage that it will be exposed to. Choose this value because most
ceramic capacitors lose significant capacitance when biased. This value also improves the long term reliability of
the system.
8.2.2.2 Estimate Driver Power Losses
The total power loss in gate driver device such as the UCC27284-Q1 is the summation of the power loss in
different functional blocks of the gate driver device. These power loss components are explained in this section.
1. Equation 4 describes how quiescent currents (IDD and IHB) affect the static power losses, PQC.
PQC = :VDD × IDD ; + :VDD F VDH ; × IHB
= 7 V × 0.4 mA + 6 V × 0.4 mA = 5.2 mW
(4)
it is not shown here, but for better approximation, add no load operating current, IDDO and IHBO in above
equation.
2. Equation 5 shows how high-side to low-side leakage current (IHBS) affects level-shifter losses (PIHBS).
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PIHBS = VHB × IHBS × D = 82 V × 50 µA × 0.5 = 2.05 mW
(5)
where
• D is the high-side MOSFET duty cycle
• VHB is the sum of input voltage and voltage across bootstrap capacitor.
3. Equation 6 shows how MOSFETs gate charge (QG) affects the dynamic losses, PQG.
R GD _R
R GD _R + R GATE + R GFET :int ;
= 2 × 7 V × 52 nC × 300 kHz × 0.74 = 0.16 W
PQG = 2 × VDD × Q G × fSW ×
(6)
where
•
•
•
•
•
QG is the total MOSFET gate charge
fSW is the switching frequency
RGD_R is the average value of pullup and pulldown resistor
RGATE is the external gate drive resistor
RGFET(int) is the power MOSFETs internal gate resistor
Assume there is no external gate resistor in this example. The average value of maximum pull-up and pull
down resistance of the driver output section is approximately 4 Ω. Substitute the application values to
calculate the dynamic loss due to gate charge, which is 160 mW here.
4. Equation 7 shows how parasitic level-shifter charge (QP) on each switching cycle affects dynamic losses, (P
LS) during high-side switching.
PLS = VHB × QP × fSW
(7)
For this example and simplicity, it is assumed that value of parasitic charge QP is 1 nC. Substituting values
results in 24.6 mW as level shifter dynamic loss. This estimate is very high for level shifter dynamic losses.
The sum of all the losses is 191.85 mW as a total gate driver loss. As shown in this example, in most
applications the dynamic loss due to gate charge dominates the total power loss in gate driver device. For gate
drivers that include bootstrap diode, one should also estimate losses in bootstrap diode. Diode forward
conduction loss is computed as product of average forward voltage drop and average forward current.
Equation 8 estimates the maximum allowable power loss of the device for a given ambient temperature.
PMAX =
kTJ F TA o
REJA
(8)
where
•
•
•
•
PMAX is the maximum allowed power dissipation in the gate driver device
TJ is the recommended maximum operating junction temperature
TA is hte ambient temperature of the gate driver device
RθJA is the junction-to-ambient thermal resistance
To better estimate the junction temperature of the gate driver device in the application, it is recommended to first
accurately measure the case temperature and then determine the power dissipation in a given application. Then
use ψ JT to calculate junction temperature. After estimating junction temperature and measuring ambient
temperature in the application, calculate θJA(effective). Then, if design parameters (such as the value of an external
gate resistor or power MOSFET) change during the development of the project, use θ JA(effective) to estimate how
these changes affect junction temperature of the gate driver device.
For detailed information regarding the thermal information table, please refer to the Semiconductor and Device
Package Thermal Metrics application report.
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8.2.2.3 Selecting External Gate Resistor
In high-frequency switching power supply applications where high-current gate drivers such as the UCC27284Q1 are used, parasitic inductances, parasitic capacitances and high-current loops can cause noise and ringing
on the gate of power MOSFETs. Often external gate resistors are used to damp this ringing and noise. In some
applications the gate charge, which is load on gate driver device, is significantly larger than gate driver peak
output current capability. In such applications external gate resistors can limit the peak output current of the gate
driver. it is recommended that there should be provision of external gate resistor whenever the layout or
application permits.
Use Equation 9 to calculate the driver high-side pull-up current.
IOHH =
VDD F VDH
R HOH + RGATE + RGFET:int;
(9)
where
•
•
•
•
•
IOHH is the high-side, peak pull-up current
VDH is the bootstrap diode forward voltage drop
RHOH is the gate driver internal high-side pull-up resistor. Value either directly provided in datasheet or can be
calculated from test conditions (RHOH = VHOH/IHO)
RGATE is the external gate resistance connected between driver output and power MOSFET gate
RGFET(int) is the MOSFET internal gate resistance provided by MOSFET datasheet
Use Equation 10 to calculate the driver high-side sink current.
IOLH =
VDD F VDH
R HOL + RGATE + RGFET:int;
(10)
where
•
RHOL is the gate driver internal high-side pull-down resistance
Use Equation 11 to calculate the driver low-side source current.
IOHL =
VDD
R LOH + RGATE + RGFET:int;
(11)
where
•
RLOH is the gate driver internal low-side pull-up resistance
Use Equation 12 to calculate the driver low-side sink current.
IOLL =
VDD
R LOL + RGATE + RGFET:int;
(12)
where
•
RLOL is the gate driver internal low-side pull-down resistance
Typical peak pull up and pull down current of the device is 2.5 A and 3.5 A respectively. These equations help
reduce the peak current if needed. To establish different rise time value compared to fall time value, external
gate resistor can be anti-paralleled with diode-resistor combination as shown in Section 8.2. Generally selecting
an optimal value or configuration of external gate resistor is an iterative process. For additional information on
selecting external gate resistor please refer to External Gate Resistor Design Guide for Gate Drivers
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8.2.2.4 Delays and Pulse Width
The total delay encountered in the PWM, driver and power stage need to be considered for a number of
reasons, primarily delay in current limit response. Also to be considered are differences in delays between the
drivers which can lead to various concerns depending on the topology. The synchronous buck topology
switching requires careful selection of dead-time between the high-side and low-side switches to avoid cross
conduction as well as excessive body diode conduction.
Bridge topologies can be affected by a volt-second imbalance on the transformer if there is imbalance in the
high-side and low-side pulse widths in any operating condition. The UCC27284-Q1 device has maximum
propagation delay, across process, and temperature variation, of 30 ns and delay matching of 7 ns, which is one
of the best in the industry.
Narrow input pulse width performance is an important consideration in gate driver devices, because output may
not follow input signals satisfactorily when input pulse widths are very narrow. Although there may be relatively
wide steady state PWM output signals from controller, very narrow pulses may be encountered under following
operating conditions.
•
•
•
soft-start period
large load transients
short circuit conditions
These narrow pulses appear as an input signal to the gate driver device and the gate driver device need to
respond properly to these narrow signals.
Figure 8-2 shows that the UCC27284-Q1 device produces reliable output pulse even when the input pulses are
very narrow and bias voltages are very low. The propagation delay and delay matching do not get affected when
the input pulse width is very narrow.
HI (2V/div)
BW=1GHz
LI (2V/div)
BW=1GHz
HO (5V/div)
LO (5V/div)
BW=1GHz
BW=1GHz
Figure 8-2. Input and Output Pulse Width
8.2.2.5 External Bootstrap Diode
The UCC27284-Q1 incorporates the bootstrap diode necessary to generate the high-side bias for HO to work
satisfactorily. The characteristics of this diode are important to achieve efficient, reliable operation. The
characteristics to consider are forward voltage drop and dynamic resistance. Generally, low forward voltage drop
diodes are preferred for low power loss during charging of the bootstrap capacitor. The device has a boot diode
forward voltage drop rated at 0.85 V and dynamic resistance of 1.5 Ω for reliable charge transfer to the bootstrap
capacitor. The dynamic characteristics to consider are diode recovery time and stored charge. Diode recovery
times that are specified without operating conditions, can be misleading. Diode recovery times at no forward
current (I F) can be noticeably less than with forward current applied. The UCC27284-Q1 boot diode recovery is
specified as 50 ns at I F = 20 mA, I REV = 0.5 A. Dynamic impedance of UCC27284-Q1 bootstrap diode naturally
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limits the peak forward current and prevents any damage if repetitive peak forward current pulses exist in the
system for most applications.
In applications where switching frequencies are very high, for example in excess of 1 MHz, and the low-side
minimum pulse widths are very small, the diode peak forward current could be very high and peak reverse
current could also be very high, specifically if high bootstrap capacitor value has been chosen. In such
applications it might be advisable to use external Schottkey diode as bootstrap diode. It is safe to at least make
a provision for such diode on the board if possible.
8.2.2.6 VDD and Input Filter
Some switching power supply applications are extremely noisy. Noise may come from ground bouncing and
ringing at the inputs, (which are the HI and LI pins of the gate driver device). To mitigate such situations, the
UCC27284-Q1 offers both negative input voltage handling capability and wide input threshold hysteresis. If these
features are not enough, then the application might need an input filter. Small filter such as 10-Ω resistor and 47pF capacitor might be sufficient to filter noise at the inputs of the gate driver device. This RC filter would
introduce delay and therefore need to be considered carefully. High frequency noise on bias supply can cause
problems in performance of the gate driver device. To filter this noise it is recommended to use 1-Ω resistor in
series with bias supply as shown in Typical Application diagram. This resistor also acts as a current limiting
element. In the event of short circuit on the bias rail, this resistor opens up and prevents further damage. This
resistor can also be helpful in debugging the design during development phase.
8.2.2.7 Transient Protection
As mentioned in previous sections, high power high switching frequency power supplies are inherently noisy.
High dV/dt and dI/dt in the circuit can cause negative voltage on different pins such as HO, LO, and HS. The
device tolerates negative voltage on all of these pins as mentioned in specification tables. If parasitic elements of
the circuit cause very large negative swings, circuit might require additional protection. In such cases fast acting
and low leakage type Schottky diode should be used. This diode must be placed as close to the gate driver
device pin as possible for it to be effective in clamping excessive negative voltage on the gate driver device pin.
To avoid the possibility of driver device damage due to over-voltage on its output pins or supply pins, low
leakage Zener diode can be used. A 15-V Zener diode is often sufficient to clamp the voltage below the
maximum recommended value of 16 V.
8.2.3 Application Curves
To minimize the switching losses in power supplies, turn-ON and turn-OFF of the power MOSFETs need to be as
fast as possible. Higher the drive current capability of the driver, faster the switching. Therefore, the UCC27284Q1 is designed with high drive current capability and low resistance of the output stages. One of the common
way to test the drive capability of the gate driver device , is to test it under heavy load. Rise time and fall time of
the outputs would provide idea of drive capability of the gate driver device. There must not be any resistance in
this test circuit. Figure 8-3 and Figure 8-4 shows rise time and fall time of HO respectively of UCC27284-Q1.
Figure 8-5 and Figure 8-6 shows rise time and fall time of LO respectively of UCC27284-Q1. For accuracy
purpose, the VDD and HB pin of the gate driver device were connected together. HS and VSS pins are also
connected together for this test.
Peak current capability can be estimated using the fastest dV/dt along the rise and fall curve of the plot. This
method is also useful in comparing performance of two or more gate driver devices.
As explained in Section 8.2.2.4, propagation delay plays an important role in reliable operation of many
applications. Figure 8-7 and Figure 8-8
Figure 8-8 shows propagation delay and delay matching of UCC27284-Q1. Figure 8-9 shows input negative
voltage handling capability of UCC27284-Q1.
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VDD = VHB = 6 V, HS =
VSS
CLOAD = 10 nF
Ch4 = HO
Figure 8-3. HO Rise Time
A.
VDD = VHB = 6 V, HS = VSS
CLOAD = 10 nF Ch4 = LO
Figure 8-5. LO Rise Time
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VDD = VHB=6 V, HS = VSS
CLOAD = 10
nF
Ch4 = HO
Figure 8-4. HO Fall Time
A.
VDD = VHB = 6 V, HS = VSS
CLOAD = 10 nF
Ch4 = LO
Figure 8-6. LO Fall Time
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UCC27284-Q1
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A.
VDD = 6 V
SLUSE23A – MARCH 2020 – REVISED NOVEMBER 2020
CLOAD = 2 nF Ch1 = HI Ch2 = LI Ch3 = HO Ch4
= LO
A.
VDD = 6 V
Figure 8-7. Propagation Delay and Delay Matching
A.
VDD = 10 V Vin = 100 V
CL = 1 nF
CLOAD = 2 nF
Ch1 = HI Ch2 = LI Ch3 = HO Ch4
= LO
Figure 8-8. Propagation Delay and Delay Matching
Ch1 = HI Ch2 = LI Ch3 = HO Ch4 = LO
Figure 8-9. Input Negative Voltage
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9 Power Supply Recommendations
The recommended bias supply voltage range for UCC27284-Q1 is from 5.5 V to 16 V. The lower end of this
range is governed by the internal under voltage-lockout (UVLO) protection feature, 5 V typical, of the VDD supply
circuit block. The upper end of this range is driven by the 16-V recomended maximum voltage rating of the V DD.
It is recommended that voltage on VDD pin should be lower than maximum recommended voltage. In some
transient condition it is not possible to keep this voltage below recommended maximum level and therefore
absolute maximum voltage rating of the UCC27284-Q1 is 20 V.
The UVLO protection feature also involves a hysteresis function. This means that once the device is operating in
normal mode, if the V DD voltage drops, the device continues to operate in normal mode as far as the voltage
drop do not exceeds the hysteresis specification, V DDHYS. If the voltage drop is more than hysteresis
specification, the device shuts down. Therefore, while operating at or near the 5.5-V range, the voltage ripple on
the auxiliary power supply output should be smaller than the hysteresis specification of UCC27284-Q1 to avoid
triggering device shutdown.
A local bypass capacitor should be placed between the VDD and GND pins. This capacitor should be located as
close to the device as possible. A low ESR, ceramic surface mount capacitor is recommended. It is
recommended to use two capacitors across VDD and GND: a low capacitance ceramic surface-mount capacitor
for high frequency filtering placed very close to VDD and GND pin, and another high capacitance value surfacemount capacitor for device bias requirements. In a similar manner, the current pulses delivered by the HO pin
are sourced from the HB pin. Therefore, two capacitors across the HB to HS are recommended. One low value
small size capacitor for high frequency filtering and another one high capacitance value capacitor to deliver HO
pulses.
In power supplies where noise is very dominant and there is space on the PWB (Printed Wiring Board), it is
recommended to place a small RC filter at the inputs. This allows for improving the overall performance of the
design. In such applications. it is also recommended to have a place holder for power MOSFET external gate
resistor. This resistor allows the control of not only the drive capability but also the slew rate on HS, which
impacts the performance of the high-side circuit. If diode is used across the external gate resistor, it is
recommended to use a resistor in series with the diode, which provides further control of fall time.
In power supply applications such as motor drives, there exist lot of transients through-out the system. This
sometime causes over voltage and under voltage spikes on almost all pins of the gate driver device. To increase
the robustness of the design, it is recommended that the clamp diode should be used on HO and LO pins. If user
does not wish to use power MOSFET parasitic diode, external clamp diode on HS pin is recommended, which
needs to be high voltage high current type (same rating as MOSFET) and very fast acting. The leakage of these
diodes across the temperature needs to be minimal.
In power supply applications where it is almost certain that there is excessive negative HS voltage, it is
recommended to place a small resistor between the HS pin and the switch node. This resistance helps limit
current into the driver device up to some extent. This resistor will impact the high side drive capability and
therefore needs to be considered carefully.
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10 Layout
10.1 Layout Guidelines
To achieve optimum performance of high-side and low-side gate drivers, one must consider following printed
wiring board (PWB) layout guidelines.
•
•
•
•
•
•
Low ESR/ESL capacitors must be connected close to the device between VDD and VSS pins and between
HB and HS pins to support high peak currents drawn from VDD and HB pins during the turn-on of the
external MOSFETs.
To prevent large voltage transients at the drain of the top MOSFET, a low ESR electrolytic capacitor and a
good quality ceramic capacitor must be connected between the high side MOSFET drain and ground (VSS).
In order to avoid large negative transients on the switch node (HS) pin, the parasitic inductances between the
source of the high-side MOSFET and the source of the low-side MOSFET (synchronous rectifier) must be
minimized.
Overlapping of HS plane and ground (VSS) plane should be minimized as much as possible so that coupling
of switching noise into the ground plane is minimized.
Thermal pad should be connected to large heavy copper plane to improve the thermal performance of the
device. Generally it is connected to the ground plane which is the same as VSS of the device. It is
recommended to connect this pad to the VSS pin only.
Grounding considerations:
– The first priority in designing grounding connections is to confine the high peak currents that charge and
discharge the MOSFET gates to a minimal physical area. This confinement decreases the loop inductance
and minimize noise issues on the gate terminals of the MOSFETs. Place the gate driver as close to the
MOSFETs as possible.
– The second consideration is the high current path that includes the bootstrap capacitor, the bootstrap
diode, the local ground referenced bypass capacitor, and the low-side MOSFET body diode. The
bootstrap capacitor is recharged on a cycle-by-cycle basis through the bootstrap diode from the ground
referenced VDD bypass capacitor. The recharging occurs in a short time interval and involves high peak
current. Minimizing this loop length and area on the circuit board is important to ensure reliable operation.
10.2 Layout Example
HB Bypass
Gate Driver
Capacitor (Top)
(Top)
Input Filters
(Top)
External Gate
Resistor (Top)
Boot Diode
VDD Bypass
External Gate
Capacitors (Top) (Bottom) Resistor (Bottom)
Figure 10-1. Layout Example
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11 Device and Documentation Support
11.1 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper
right corner, click on Alert me to register and receive a weekly digest of any product information that has
changed. For change details, review the revision history included in any revised document.
11.2 Support Resources
TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight
from the experts. Search existing answers or ask your own question to get the quick design help you need.
Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do
not necessarily reflect TI's views; see TI's Terms of Use.
11.3 Trademarks
TI E2E™ is a trademark of Texas Instruments.
All trademarks are the property of their respective owners.
11.4 Glossary
TI Glossary
This glossary lists and explains terms, acronyms, and definitions.
12 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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PACKAGE OPTION ADDENDUM
www.ti.com
12-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
(4/5)
(6)
UCC27284QDQ1
ACTIVE
SOIC
D
8
75
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 125
U284Q
UCC27284QDRQ1
ACTIVE
SOIC
D
8
2500
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 125
U284Q
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of
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