CY24713SXCT

CY24713 Set-top Box Clock Generator with VCXO Features • Integrated phase-locked loop (PLL) • Low-jitter, high-accuracy outputs • VCXO with analog adjust • 3.3V Operation • 8-pin SOIC Benefits • High-performance PLL tailored for Set Top Box applications • Meets critical timing requirements in complex system designs • Large ±150-ppm range, better linearity • Meet industry standard voltage platforms • Industry standard packaging saves on board space Part Number CY24713 Outputs 3 Input Frequency Range 27-MHz pullable crystal input per Cypress specification Output Frequencies 4.9152 MHz, 13.5 MHz, 27 MHz Logic Block Diagram Pin Configuration Cypress Semiconductor Corporation Document #: 38-07396 Rev. ** • 3901 North First Street • San Jose, CA 95134 • 408-943-2600 Revised March 11, 2005 CY24713 Pin Description Name XIN VDD VCXO VSS CLK_B CLK_A CLK_C XOUT [1] Number 1 2 3 4 5 6 7 8 Description Reference Crystal Input 3.3V Voltage Supply Input Analog Control for VCXO Ground 13.5-MHz Clock Output 4.9152-MHz Clock Output 27-MHz Clock Output Reference Crystal Output Absolute Maximum Conditions Parameter VDD TS TJ Storage Description Supply Voltage Temperature[2] Junction Temperature Digital Inputs Digital Outputs referred to VDD Electrostatic Discharge Analog Input Min. –0.5 –65 – VSS – 0.3 VSS – 0.3 – –0.5 Max. 7.0 125 125 VDD + 0.3 VDD + 0.3 2000 7.0 Unit V °C °C V V V V Pullable Crystal Specifications Parameter FNOM CLNOM R1 R3/R1 DL F3SEPHI F3SEPLO C0 C0/C1 C1 Description Nominal crystal frequency Nominal load capacitance Equivalent series resistance (ESR) Fundamental mode Ratio of third overtone mode ESR to fundamen- Ratio used because typical tal mode ESR R1 values are much less than the maximum spec. Crystal drive level Third overtone separation from 3*FNOM Third overtone separation from 3*FNOM Crystal shunt capacitance Ratio of shunt to motional capacitance Crystal motional capacitance No external series resistor assumed High side Low side Condition Parallel resonance, fundamental mode, AT cut Min. – – – 3 Typ. 27 14 – – Max. – – 25 – Unit MHz pF Ω – 300 – – 180 14.4 0.5 – – – – 18 2.0 – –150 7 250 21.6 mW ppm ppm pF pF Notes: 1. Float XOUT if XIN is externally driven. 2. Rated for 10 years Document #: 38-07396 Rev. ** Page 2 of 6 CY24713 Recommended Operating Conditions Parameter VDD TA CLOAD tPU Description Operating Voltage Ambient Temperature Max. Load Capacitance Power-up time for all VDDs to reach minimum specified voltage (power ramps must be monotonic) Min. 3.135 0 – 0.05 Typ. 3.3 – – – Max. 3.465 70 15 500 Unit V °C pF ms DC Electrical Characteristics Parameter IOH IOL CIN IIZ f∆XO VVCXO IVDD Description Output High Current Output Low Current Input Capacitance Input Leakage Current VCXO pullability range VCXO input range Supply Current Conditions VOH = VDD – 0.5, VDD = 3.3V VOL = 0.5, VDD = 3.3V Min. 12 12 – – ±150 0 – Typ. 24 24 – 5 – – 25 Max. – – 7 – – VDD 30 Unit mA mA pF µA ppm V mA AC Electrical Characteristics (VDD = 3.3V) Parameter[3] DC ER0 EF1 t9 t10 Description Output Duty Cycle Rising Edge Rate Falling Edge Rate Clock Jitter PLL Lock Time Conditions Duty Cycle is defined in Figure 1 50% of VDD Output Clock Edge Rate, Measured from 20% to 80% of VDD, CLOAD = 15 pF Figure 2. Output Clock Edge Rate, Measured from 80% to 20% of VDD, CLOAD = 15 pF Figure 2. Peak-Peak period jitter maximum absolute jitter Min. 45 0.8 0.8 – – Typ. 50 1.4 1.4 200 – Max. 55 – – 250 3 Unit % V/ns V/ns ps ms Notes: 3. Not 100% tested Document #: 38-07396 Rev. ** Page 3 of 6 CY24713 Test Circuit V DD 0.1 µ F OUTPUTS CLK out C LOAD GND t1 t2 t3 80% 50% t4 CLK 50% CLK 20% Figure 1. Duty Cycle Definition; DC = t2/t1 Figure 2. Rise and Fall Time Definitions: ER = 0.6 x VDD/t3, EF = 0.6 x VDD/t4 Ordering Information Ordering Code CY24713SC CY24713SCT Lead-free CY24713SXC CY24713SXCT 8-pin SOIC 8-pin SOIC Commercial Commercial 3.3V 3.3V Package Type 8-pin SOIC 8-pin SOIC Operating Range Commercial Commercial Operating Voltage 3.3V 3.3V Document #: 38-07396 Rev. ** Page 4 of 6 CY24713 Package Diagram 8-lead (150-Mil) SOIC S8 8 Lead (150 Mil) SOIC - S08 PIN 1 ID 4 1 1. DIMENSIONS IN INCHES[MM] MIN. MAX. 2. PIN 1 ID IS OPTIONAL, ROUND ON SINGLE LEADFRAME RECTANGULAR ON MATRIX LEADFRAME 3. REFERENCE JEDEC MS-012 0.230[5.842] 0.244[6.197] 0.150[3.810] 0.157[3.987] 4. PACKAGE WEIGHT 0.07gms PART # S08.15 STANDARD PKG. SZ08.15 LEAD FREE PKG. 5 8 0.189[4.800] 0.196[4.978] SEATING PLANE 0.010[0.254] 0.016[0.406] X 45° 0.061[1.549] 0.068[1.727] 0.004[0.102] 0.050[1.270] BSC 0.004[0.102] 0.0098[0.249] 0°~8° 0.016[0.406] 0.035[0.889] 0.0075[0.190] 0.0098[0.249] 0.0138[0.350] 0.0192[0.487] 51-85066-*C All product and company names mentioned in this document may be trademarks of their respective holders. Document #: 38-07396 Rev. ** Page 5 of 6 CY24713 Document History Page Document Title: CY24713 Set-top Box Clock Generator with VCXO Document Number: 38-07396 REV. ** ECN No. 333175 Issue Date See ECN Orig. of Change RGL New Data Sheet Description of Change Document #: 38-07396 Rev. ** Page 6 of 6