CY62136ESL MoBL®
2-Mbit (128 K × 16) Static RAM
2-Mbit (128 K × 16) Static RAM
Features
■
Very high speed: 45 ns
■
Wide voltage range: 2.2 V to 3.6 V and 4.5 V to 5.5 V
■
Ultra low standby power
❐ Typical standby current: 1 A
❐ Maximum standby current: 7 A
not toggling. Placing the device into standby mode reduces
power consumption by more than 99% when deselected (CE
HIGH). The input and output pins (I/O0 through I/O15) are placed
in a high impedance state when the device is deselected (CE
HIGH), the outputs are disabled (OE HIGH), both Byte High
Enable and Byte Low Enable are disabled (BHE, BLE HIGH) or
during a write operation (CE LOW and WE LOW).
To write to the device, take Chip Enable (CE) and Write Enable
(WE) inputs LOW. If Byte Low Enable (BLE) is LOW, then data
from I/O pins (I/O0 through I/O7) is written into the location
specified on the address pins (A0 through A16). If Byte High
Enable (BHE) is LOW, then data from I/O pins (I/O8 through
I/O15) is written into the location specified on the address pins
(A0 through A16).
■
Ultra low active power
❐ Typical active current: 2 mA at f = 1 MHz
■
Easy memory expansion with CE and OE features
■
Automatic power-down when deselected
■
Complementary metal oxide semiconductor (CMOS) for
optimum speed and power
■
Available in Pb-free 44-pin thin small outline package (TSOP) II
package
Functional Description
The CY62136ESL is a high performance CMOS static RAM
organized as 128K words by 16 bits. This device features
advanced circuit design to provide ultra low active current. This
is ideal for providing More Battery Life (MoBL®) in portable
applications. The device also has an automatic power down
feature that reduces power consumption when addresses are
To read from the device, take Chip Enable (CE) and Output
Enable (OE) LOW while forcing the Write Enable (WE) HIGH. If
Byte Low Enable (BLE) is LOW, then data from the memory
location specified by the address pins appears on I/O0 to I/O7. If
Byte High Enable (BHE) is LOW, then data from memory
appears on I/O8 to I/O15. See the Truth Table on page 11 for a
complete description of read and write modes.
The device is suitable for interfacing with processors that have
TTL I/P levels. It is not suitable for processors that require CMOS
I/P levels. Please see Electrical Characteristics on page 4 for
more details and suggested alternatives.
For a complete list of related documentation, click here.
Logic Block Diagram
128 K x 16
RAM Array
SENSE AMPS
ROW DECODER
DATA IN DRIVERS
A10
A9
A8
A7
A6
A5
A4
A3
A2
A1
A0
I/O0–I/O7
I/O8–I/O15
Cypress Semiconductor Corporation
Document Number: 001-48147 Rev. *L
•
BHE
WE
CE
OE
BLE
A13
A14
A15
A16
A11
A12
COLUMN DECODER
198 Champion Court
•
San Jose, CA 95134-1709
•
408-943-2600
Revised November 29, 2017
CY62136ESL MoBL®
Contents
Pin Configuration ............................................................. 3
Product Portfolio .............................................................. 3
Maximum Ratings ............................................................. 4
Operating Range ............................................................... 4
Electrical Characteristics ................................................. 4
Capacitance ...................................................................... 5
Thermal Resistance .......................................................... 5
AC Test Loads and Waveforms ....................................... 5
Data Retention Characteristics ....................................... 6
Data Retention Waveform ................................................ 6
Switching Characteristics ................................................ 7
Switching Waveforms ...................................................... 8
Truth Table ...................................................................... 11
Document Number: 001-48147 Rev. *L
Ordering Information ...................................................... 12
Ordering Code Definitions ......................................... 12
Package Diagram ............................................................ 13
Acronyms ........................................................................ 14
Document Conventions ................................................. 14
Units of Measure ....................................................... 14
Document History Page ................................................. 15
Sales, Solutions, and Legal Information ...................... 17
Worldwide Sales and Design Support ....................... 17
Products .................................................................... 17
PSoC® Solutions ...................................................... 17
Cypress Developer Community ................................. 17
Technical Support ..................................................... 17
Page 2 of 17
CY62136ESL MoBL®
Pin Configuration
Figure 1. 44-pin TSOP II pinout (Top View) [1]
A4
A3
A2
A1
A0
CE
I/O0
I/O1
I/O2
I/O3
VCC
VSS
I/O4
I/O5
I/O6
I/O7
WE
A16
A15
A14
A13
A12
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
A5
A6
A7
OE
BHE
BLE
I/O15
I/O14
I/O13
I/O12
VSS
VCC
I/O11
I/O10
I/O9
I/O8
NC
A8
A9
A10
A11
NC
Product Portfolio
Power Dissipation
Product
CY62136ESL
Range
VCC Range (V) [2]
Industrial 2.2 V to 3.6 V and 4.5 V to 5.5 V
Speed
(ns)
45
Operating ICC, (mA)
f = 1MHz
f = fmax =1/TRC
Standby, ISB2
(A)
Typ [3]
Max
Typ [3]
Max
Typ [3]
Max
2
2.5
15
20
1
7
Notes
1. NC pins are not connected on the die.
2. Datasheet specifications are not guaranteed for VCC in the range of 3.6 V to 4.5 V.
3. Typical values are included for reference only and are not guaranteed or tested. Typical values are measured at VCC = 3 V, and VCC = 5 V, TA = 25 °C.
Document Number: 001-48147 Rev. *L
Page 3 of 17
CY62136ESL MoBL®
DC input voltage [4, 5] .....................................–0.5 V to 6.0 V
Maximum Ratings
Exceeding the maximum ratings may impair the useful life of the
device. These user guidelines are not tested.
Storage temperature ................................ –65 °C to +150 °C
Ambient temperature
with power applied ................................... –55 °C to +125 °C
Supply voltage
to ground potential [4, 5] .................................–0.5 V to 6.0 V
DC voltage applied to outputs
in High Z State [4, 5] ........................................–0.5 V to 6.0 V
Output current into outputs (LOW) ............................. 20 mA
Static discharge voltage
(MIL-STD-883, Method 3015) .................................. >2001 V
Latch up current ..................................................... > 200 mA
Operating Range
Device
CY62136ESL
Range
Ambient
Temperature
VCC[6]
Industrial –40 °C to +85 °C 2.2 V–3.6 V, and
4.5 V–5.5 V
Electrical Characteristics
Over the Operating Range
Parameter
VOH
VOL
VIH
VIL
Description
Output HIGH voltage
Output LOW voltage
Input HIGH voltage
Input LOW voltage
Test Conditions
45 ns
Min
Typ [7]
Max
2.2 < VCC < 2.7
IOH = –0.1 mA
2.0
–
–
2.7 < VCC < 3.6
IOH = –1.0 mA
2.4
–
–
4.5 < VCC < 5.5
IOH = –1.0 mA
2.4
–
–
4.5 < VCC < 5.5
IOH = –0.1 mA
–
–
3.4 [8]
2.2 < VCC < 2.7
IOL = 0.1 mA
–
–
0.4
2.7 < VCC < 3.6
IOL = 2.1 mA
–
–
0.4
4.5 < VCC < 5.5
IOL = 2.1 mA
–
–
0.4
2.2 < VCC < 2.7
1.8
–
VCC + 0.3
2.7 < VCC < 3.6
2.2
–
VCC + 0.3
4.5 < VCC < 5.5
2.2
–
VCC + 0.5
2.2 < VCC < 2.7
–0.3
–
0.6
2.7 < VCC < 3.6
–0.3
–
0.8
Unit
V
V
V
V
4.5 < VCC < 5.5
–0.5
–
0.8
IIX
Input leakage current
GND < Vin < VCC
–1
–
+1
IOZ
Output leakage current
GND < VO < VCC, Output disabled
–1
–
+1
A
ICC
VCC Operating supply current
f = fmax = 1/tRC
–
15
20
mA
–
2
2.5
f = 1 MHz
VCC = VCCmax
IOUT = 0 mA,
CMOS levels
A
ISB1[9]
Automatic CE power-down
current — CMOS inputs
CE > VCC 0.2 V,
VIN > VCC – 0.2 V or VIN < 0.2 V,
f = fmax (Address and data only),
f = 0 (OE, BHE, BLE and WE),
VCC = VCC(max)
–
1
7
A
ISB2[9]
Automatic CE power-down
current — CMOS inputs
CE > VCC – 0.2 V,
VIN > VCC – 0.2 V or VIN < 0.2 V,
f = 0, VCC = VCC(max)
–
1
7
A
Notes
4. VIL(min) = –2.0 V for pulse durations less than 20 ns.
5. VIH(max) = VCC + 0.75 V for pulse durations less than 20 ns.
6. Full Device AC operation assumes a 100 s ramp time from 0 to VCC (min) and 200 s wait time after VCC stabilization.
7. Typical values are included for reference only and are not guaranteed or tested. Typical values are measured at VCC = 3 V, and VCC = 5 V, TA = 25 °C.
8. Please note that, the maximum VOH limit for this device may not exceed minimum CMOS VIH of 3.5 V. If you are interfacing this SRAM with 5 V legacy processors
that require a minimum VIH of 3.5 V, please refer to Application Note AN6081 for technical details and options you may consider. This maximum limit is not 100% tested.
9. Chip enable (CE) and byte enables (BHE and BLE) need to be tied to CMOS levels to meet the ISB1 / ISB2 / ICCDR spec. Other inputs can be left floating.
Document Number: 001-48147 Rev. *L
Page 4 of 17
CY62136ESL MoBL®
Capacitance
Parameter [10]
Description
CIN
Input capacitance
COUT
Output capacitance
Test Conditions
Max
TA = 25 °C, f = 1 MHz, VCC = VCC(typ)
Unit
10
pF
10
pF
Thermal Resistance
Parameter [10]
Description
JA
Thermal resistance
(junction to ambient)
JC
Thermal resistance
(junction to case)
Test Conditions
44-pin TSOP II Unit
Still Air, soldered on a 3 × 4.5 inch, four-layer printed circuit
board
57
C/W
17
C/W
AC Test Loads and Waveforms
Figure 2. AC Test Loads and Waveforms
R1
VCC
OUTPUT
VCC
R2
30 pF
INCLUDING
JIG AND
SCOPE
10%
GND
Rise Time = 1 V/ns
ALL INPUT PULSES
90%
90%
10%
Fall Time = 1 V/ns
Equivalent to:
THÉVENIN EQUIVALENT
RTH
OUTPUT
V TH
Parameters
2.5 V
3.0 V
5.0 V
Unit
R1
16667
1103
1800
R2
15385
1554
990
RTH
8000
645
639
VTH
1.20
1.75
1.77
V
Note
10. Tested initially and after any design or process changes that may affect these parameters.
Document Number: 001-48147 Rev. *L
Page 5 of 17
CY62136ESL MoBL®
Data Retention Characteristics
Over the Operating Range
Parameter
Description
Conditions
Min
Typ [11]
Max
Unit
1.0
–
–
V
–
0.8
3
A
VDR
VCC for data retention
ICCDR[12]
Data retention current
tCDR [13]
Chip deselect to data
retention time
0
–
–
ns
tR [14]
Operation recovery time
45
–
–
ns
CE > VCC – 0.2 V,
VCC = 1.0 V
VIN > VCC – 0.2 V or VIN < 0.2 V
Data Retention Waveform
Figure 3. Data Retention Waveform
DATA RETENTION MODE
VCC
VCC(min)
tCDR
VDR > 1.0 V
VCC(min)
tR
CE
Notes
11. Typical values are included for reference only and are not guaranteed or tested. Typical values are measured at VCC = VCC(typ), TA = 25 °C.
12. Chip enable (CE) and byte enables (BHE and BLE) need to be tied to CMOS levels to meet the ISB1 / ISB2 / ICCDR specification. Other inputs can be left floating.
13. Tested initially and after any design or process changes that may affect these parameters.
14. Full device operation requires linear VCC ramp from VDR to VCC(min) > 100 s or stable at VCC(min) > 100 s.
Document Number: 001-48147 Rev. *L
Page 6 of 17
CY62136ESL MoBL®
Switching Characteristics
Over the Operating Range
Parameter [15, 16]
Description
45 ns
Min
Max
Unit
Read Cycle
tRC
Read cycle time
45
–
ns
tAA
Address to data valid
–
45
ns
tOHA
Data hold from address change
10
–
ns
tACE
CE LOW to data valid
–
45
ns
tDOE
OE LOW to data valid
–
22
ns
tLZOE
OE LOW to Low Z [17]
5
–
ns
–
18
ns
10
–
ns
–
tHZOE
tLZCE
OE HIGH to High Z
CE LOW to Low Z
[17, 18]
[17]
[17, 18]
tHZCE
CE HIGH to High Z
18
ns
tPU
CE LOW to power-up
0
–
ns
tPD
CE HIGH to ower-down
–
45
ns
tDBE
BLE/BHE LOW to data valid
–
22
ns
5
–
ns
–
18
ns
45
–
ns
ns
[17]
tLZBE
BLE/BHE LOW to Low Z
tHZBE
BLE/BHE HIGH to High Z [17, 18]
Write Cycle
tWC
[19, 20]
Write cycle time
tSCE
CE LOW to write end
35
–
tAW
Address setup to write end
35
–
ns
tHA
Address hold from write end
0
–
ns
tSA
Address setup to write start
0
–
ns
ns
tPWE
WE pulse width
35
–
tBW
BLE/BHE LOW to write end
35
–
ns
tSD
Data setup to write end
25
–
ns
tHD
Data hold from write end
0
–
ns
–
18
ns
10
–
ns
[17, 18]
tHZWE
WE LOW to High Z
tLZWE
WE HIGH to Low Z [17]
Notes
15. In an earlier revision of this device, under a specific application condition, READ and WRITE operations were limited to switching of the byte enable and/or chip
enable signals as described in the Application Notes AN13842 and AN66311. However, the issue has been fixed and in production now, and hence, these Application
Notes are no longer applicable. They are available for download on our website as they contain information on the date code of the parts, beyond which the fix has
been in production.
16. Test conditions for all parameters other than tri-state parameters assume signal transition time of 3 ns or less, timing reference levels of 1.5 V, input pulse levels of
0 to 3 V, and output loading of the specified IOL/IOH as shown in the Figure 2 on page 5.
17. At any temperature and voltage condition, tHZCE is less than tLZCE, tHZBE is less than tLZBE, tHZOE is less than tLZOE, and tHZWE is less than tLZWE for any device.
18. tHZOE, tHZCE, tHZBE, and tHZWE transitions are measured when the outputs enter a high-impedance state.
19. The internal write time of the memory is defined by the overlap of WE, CE = VIL, BHE, BLE or both = VIL. All signals must be active to initiate a write and any of these
signals can terminate a write by going inactive. The data input setup and hold timing must be referenced to the edge of the signal that terminates the write.
20. The minimum write cycle pulse width for Write Cycle No. 3 (WE Controlled, OE Controlled) should be equal to sum of tSD and tHZWE.
Document Number: 001-48147 Rev. *L
Page 7 of 17
CY62136ESL MoBL®
Switching Waveforms
Figure 4. Read Cycle No.1 (Address Transition Controlled) [21, 22]
tRC
RC
ADDRESS
tOHA
DATA OUT
tAA
PREVIOUS DATA VALID
DATA VALID
Figure 5. Read Cycle No. 2 (OE Controlled) [22, 23]
ADDRESS
tRC
CE
tPD
tHZCE
tACE
OE
tHZOE
tDOE
tLZOE
BHE/BLE
tHZBE
tDBE
tLZBE
DATA OUT
HIGH IMPEDANCE
HIGH
IMPEDANCE
DATA VALID
tLZCE
tPU
VCC
SUPPLY
CURRENT
50%
50%
ICC
ISB
Notes
21. The device is continuously selected. OE, CE = VIL, BHE, BLE, or both = VIL.
22. WE is HIGH for read cycle.
23. Address valid before or similar to CE, BHE, BLE transition LOW.
Document Number: 001-48147 Rev. *L
Page 8 of 17
CY62136ESL MoBL®
Switching Waveforms (continued)
Figure 6. Write Cycle No. 1 (WE Controlled) [24, 25, 26]
tWC
ADDRESS
tSCE
CE
tAW
tHA
tSA
WE
tPWE
tBW
BHE/BLE
OE
tSD
DATA I/O
NOTE 27
tHD
DATAIN
tHZOE
Figure 7. Write Cycle No. 2 (CE Controlled) [24, 25, 26]
tWC
ADDRESS
tSCE
CE
tSA
tAW
tHA
tPWE
WE
tBW
BHE/BLE
OE
tSD
DATA I/O
t HD
DATAIN
NOTE 27
tHZOE
Notes
24. The internal write time of the memory is defined by the overlap of WE, CE = VIL, BHE and/or BLE = VIL. All signals are ACTIVE to initiate a write and any of these
signals terminate a write by going INACTIVE. The data input setup and hold timing are referenced to the edge of the signal that terminates the write.
25. Data I/O is high impedance if OE = VIH.
26. If CE goes HIGH simultaneously with WE = VIH, the output remains in a high impedance state.
27. During this period, the I/Os are in output state. Do not apply input signals.
Document Number: 001-48147 Rev. *L
Page 9 of 17
CY62136ESL MoBL®
Switching Waveforms (continued)
Figure 8. Write Cycle No. 3 (WE Controlled, OE LOW) [28, 29]
tWC
ADDRESS
tSCE
CE
tBW
BHE/BLE
tAW
tHA
tSA
WE
tPWE
tSD
DATA I/O
NOTE 30
tHD
DATAIN
tLZWE
tHZWE
Figure 9. Write Cycle No. 4 (BHE/BLE Controlled, OE LOW) [28]
tWC
ADDRESS
CE
tSCE
tAW
tHA
tBW
BHE/BLE
tSA
tPWE
WE
tHZWE
DATA I/O
NOTE 30
tSD
tHD
DATAIN
tLZWE
Notes
28. If CE goes HIGH simultaneously with WE = VIH, the output remains in a high impedance state.
29. The minimum write cycle pulse width should be equal to the sum of tHZWE and tSD.
30. During this period, the I/Os are in output state. Do not apply input signals.
Document Number: 001-48147 Rev. *L
Page 10 of 17
CY62136ESL MoBL®
Truth Table
CE [31]
WE
OE
BHE
BLE
[31]
[31]
High Z
Deselect/power-down
Standby (ISB)
X
X
Inputs/Outputs
Mode
Power
H
X
X
L
X
X
H
H
High Z
Output disabled
Active (ICC)
L
H
L
L
L
Data out (I/O0–I/O15)
Read
Active (ICC)
L
H
L
H
L
Data out (I/O0–I/O7);
I/O8–I/O15 in High Z
Read
Active (ICC)
L
H
L
L
H
Data out (I/O8–I/O15);
I/O0–I/O7 in High Z
Read
Active (ICC)
L
H
H
L
L
High Z
Output disabled
Active (ICC)
L
H
H
H
L
High Z
Output disabled
Active (ICC)
L
H
H
L
H
High Z
Output disabled
Active (ICC)
L
L
X
L
L
Data in (I/O0–I/O15)
Write
Active (ICC)
L
L
X
H
L
Data in (I/O0–I/O7);
I/O8–I/O15 in High Z
Write
Active (ICC)
L
L
X
L
H
Data in (I/O8–I/O15);
I/O0–I/O7 in High Z
Write
Active (ICC)
Note
31. The ‘X’ (Don’t care) state for the Chip enable (CE) and Byte enables (BHE and BLE) in the truth table refer to the logic state (either HIGH or LOW). Intermediate
voltage levels on these pins is not permitted.
Document Number: 001-48147 Rev. *L
Page 11 of 17
CY62136ESL MoBL®
Ordering Information
Speed
(ns)
45
Package
Diagram
Ordering Code
CY62136ESL-45ZSXI
Package Type
51-85087 44-pin TSOP Type II (Pb-free)
Operating
Range
Industrial
Ordering Code Definitions
CY 621 3
6
E
SL - 45 ZS
X
I
Temperature Grade: I = Industrial
Pb-free
Package Type: ZS = 44-pin TSOP II
Speed Grade: 45 ns
Wide Voltage Range (3 V and 5 V)
Process Technology: E = 90 nm Technology
Bus width: 6 = × 16
Density: 3 = 2-Mbit
Family Code: 621 = MoBL SRAM family
Company ID: CY = Cypress
Document Number: 001-48147 Rev. *L
Page 12 of 17
CY62136ESL MoBL®
Package Diagram
Figure 10. 44-pin TSOP Z44-II Package Outline, 51-85087
51-85087 *E
Document Number: 001-48147 Rev. *L
Page 13 of 17
CY62136ESL MoBL®
Acronyms
Acronym
Document Conventions
Description
Units of Measure
BLE
Byte Low Enable
BHE
Byte High Enable
°C
degree Celsius
CE
Chip Enable
MHz
megahertz
CMOS
Complementary Metal Oxide Semiconductor
A
microampere
I/O
Input/Output
s
microsecond
OE
Output Enable
mA
milliampere
SRAM
Static Random Access Memory
mm
millimeter
TSOP
Thin Small Outline Package
ns
nanosecond
WE
Write Enable
ohm
%
percent
pF
picofarad
V
volt
W
watt
Document Number: 001-48147 Rev. *L
Symbol
Unit of Measure
Page 14 of 17
CY62136ESL MoBL®
Document History Page
Document Title: CY62136ESL MoBL®, 2-Mbit (128 K × 16) Static RAM
Document Number: 001-48147
Rev.
ECN No.
Orig. of
Change
Submission
Date
**
2615537
VKN / PYRS
12/03/08
Description of Change
New data sheet.
*A
2718906
VKN
06/15/2009
Post to external web.
*B
2944332
VKN
06/04/2010
Added Contents.
Updated Electrical Characteristics:
Added Note 9 and referred the same note in ISB2 parameter.
Updated Switching Characteristics:
Added Note 16 and referred the same note in “Parameter” column.
Updated Truth Table:
Added Note 31 and referred the same note in “CE”, “BHE” and “BLE” columns.
Updated Package Diagram.
Updated links in Sales, Solutions, and Legal Information.
*C
3126445
RAME
01/03/2011
Changed all table notes to footnotes in all instances across the document.
Added Acronyms and Units of Measure.
Added Ordering Code Definitions.
Updated to new template,
*D
3283711
RAME
06/15/2011
Updated Functional Description (Removed “For best practice
recommendations, refer to the Cypress application note AN1064, SRAM
System Guidelines.”).
Updated to new template.
*E
3499186
TAVA
01/17/2012
Updated Product Portfolio.
Updated Package Diagram.
*F
3874351
NILE
01/18/2013
Updated Package Diagram:
spec 51-85087 – Changed revision from *D to *E.
*G
4019657
MEMJ
06/04/2013
Updated Functional Description.
Updated Electrical Characteristics:
Added one more Test Condition “4.5 < VCC < 5.5, IOH = –0.1 mA” for VOH
parameter and added maximum value corresponding to that Test Condition.
Added Note 8 and referred the same note in maximum value for VOH
parameter corresponding to Test Condition “4.5 < VCC < 5.5, IOH = –0.1 mA”.
*H
4100920
VINI
08/21/2013
Updated Switching Characteristics:
Added Note 15 and referred the same note in “Parameter” column.
Updated to new template.
*I
4540548
VINI
10/28/2014
Updated Maximum Ratings:
Referred Notes 4, 5 in “Supply voltage to ground potential”.
Updated Electrical Characteristics:
Updated Note 8.
Updated Switching Characteristics:
Added Note 20 and referred the same note in “Write Cycle”.
Updated Switching Waveforms:
Added Note 29 and referred the same note in Figure 8.
*J
4575393
VINI
11/20/2014
Updated Functional Description:
Added “For a complete list of related documentation, click here.” at the end.
Updated Switching Waveforms:
Updated Figure 5 (Added shading to BHE/BLE in the waveform).
Document Number: 001-48147 Rev. *L
Page 15 of 17
CY62136ESL MoBL®
Document History Page (continued)
Document Title: CY62136ESL MoBL®, 2-Mbit (128 K × 16) Static RAM
Document Number: 001-48147
Rev.
ECN No.
Orig. of
Change
Submission
Date
Description of Change
*K
5059123
NILE
12/21/2015
Update Thermal Resistance:
Changed value of JA parameter corresponding to 44-pin TSOP II package
from 77 C/W to 57 C/W.
Changed value of JC parameter corresponding to 44-pin TSOP II package
from 13 C/W to 17 C/W.
Updated to new template.
Completing Sunset Review.
*L
5978618
AESATMP9
11/29/2017
Updated logo and copyright.
Document Number: 001-48147 Rev. *L
Page 16 of 17
CY62136ESL MoBL®
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© Cypress Semiconductor Corporation, 2008-2017. This document is the property of Cypress Semiconductor Corporation and its subsidiaries, including Spansion LLC ("Cypress"). This document,
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Document Number: 001-48147 Rev. *L
Revised November 29, 2017
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