Please note that Cypress is an Infineon Technologies Company.
The document following this cover page is marked as “Cypress” document as this is the
company that originally developed the product. Please note that Infineon will continue
to offer the product to new and existing customers as part of the Infineon product
portfolio.
Continuity of document content
The fact that Infineon offers the following product as part of the Infineon product
portfolio does not lead to any changes to this document. Future revisions will occur
when appropriate, and any changes will be set out on the document history page.
Continuity of ordering part numbers
Infineon continues to support existing part numbers. Please continue to use the
ordering part numbers listed in the datasheet for ordering.
www.infineon.com
CY62146ESL MoBL
4-Mbit (256K × 16) Static RAM
4-Mbit (256K × 16) Static RAM
Features
Functional Description
■
Very high speed: 45 ns
■
Wide voltage range: 2.2 V to 3.6 V and 4.5 V to 5.5 V
■
Ultra low standby power
❐ Typical Standby current: 2.5 A
❐ Maximum Standby current: 7 A
■
Ultra low active power
❐ Typical active current: 3.5 mA at f = 1 MHz
■
Easy memory expansion with CE and OE features
■
Automatic power down when deselected
■
Complementary metal oxide semiconductor (CMOS) for
optimum speed and power
■
Available in Pb-free 44-pin thin small outline package (TSOP) II
package
The CY62146ESL is a high performance CMOS static RAM
organized as 256K words by 16 bits. This device features
advanced circuit design to provide ultra low active current. This
is ideal for providing More Battery Life™ (MoBL®) in portable
applications such as cellular telephones. The device also has an
automatic power down feature that reduces power consumption
when addresses are not toggling. Placing the device into standby
mode reduces power consumption by more than 99% when
deselected (CE HIGH). The input and output pins (I/O0 through
I/O15) are placed in a high impedance state when the device is
deselected (CE HIGH), the outputs are disabled (OE HIGH),
both Byte High Enable and Byte Low Enable are disabled (BHE,
BLE HIGH) or during a write operation (CE LOW and WE LOW).
To write to the device, take Chip Enable (CE) and Write Enable
(WE) inputs LOW. If Byte Low Enable (BLE) is LOW, then data
from I/O pins (I/O0 through I/O7) is written into the location
specified on the address pins (A0 through A17). If Byte High
Enable (BHE) is LOW, then data from I/O pins (I/O8 through
I/O15) is written into the location specified on the address pins
(A0 through A17).
To read from the device, take Chip Enable (CE) and Output
Enable (OE) LOW while forcing the Write Enable (WE) HIGH. If
Byte Low Enable (BLE) is LOW, then data from the memory
location specified by the address pins appears on I/O0 to I/O7. If
Byte High Enable (BHE) is LOW, then data from memory
appears on I/O8 to I/O15. See the Truth Table on page 11 for a
complete description of read and write modes.
For a complete list of related documentation, click here.
Logic Block Diagram
SENSE AMPS
A10
A9
A8
A7
A6
A5
A4
A3
A2
A1
A0
ROW DECODER
DATA IN DRIVERS
256K × 16
RAM Array
I/O0–I/O7
I/O8–I/O15
•
BHE
WE
CE
OE
BLE
A17
A15
A16
A14
A13
A11
Cypress Semiconductor Corporation
Document Number: 001-43142 Rev. *J
A12
COLUMN DECODER
198 Champion Court
•
San Jose, CA 95134-1709
•
408-943-2600
Revised June 26, 2020
CY62146ESL MoBL
Contents
Pin Configurations ........................................................... 3
Product Portfolio .............................................................. 3
Maximum Ratings ............................................................. 4
Operating Range ............................................................... 4
Electrical Characteristics ................................................. 4
Capacitance ...................................................................... 5
Thermal Resistance .......................................................... 5
AC Test Loads and Waveforms ....................................... 5
Data Retention Characteristics ....................................... 6
Data Retention Waveform ................................................ 6
Switching Characteristics ................................................ 7
Switching Waveforms ...................................................... 8
Truth Table ...................................................................... 11
Document Number: 001-43142 Rev. *J
Ordering Information ...................................................... 12
Ordering Code Definitions ......................................... 12
Package Diagram ............................................................ 13
Acronyms ........................................................................ 14
Document Conventions ................................................. 14
Units of Measure ....................................................... 14
Document History Page ................................................. 15
Sales, Solutions, and Legal Information ...................... 17
Worldwide Sales and Design Support ....................... 17
Products .................................................................... 17
PSoC® Solutions ...................................................... 17
Cypress Developer Community ................................. 17
Technical Support ..................................................... 17
Page 2 of 17
CY62146ESL MoBL
Pin Configurations
Figure 1. 44-pin TSOP II pinout (Top View) [1]
A4
A3
A2
A1
A0
CE
I/O0
I/O1
I/O2
I/O3
VCC
VSS
I/O4
I/O5
I/O6
I/O7
WE
A17
A16
A15
A14
A13
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
A5
A6
A7
OE
BHE
BLE
I/O15
I/O14
I/O13
I/O12
VSS
VCC
I/O11
I/O10
I/O9
I/O8
NC
A8
A9
A10
A11
A12
Product Portfolio
Power Dissipation
Product
CY62146ESL
Range
Industrial
VCC Range (V) [2]
2.2 V–3.6 V and 4.5 V–5.5 V
Speed
(ns)
45
Operating ICC, (mA)
f = 1MHz
f = fmax
Standby, ISB2 (A)
Typ [3]
Max
Typ [3]
Max
Typ [3]
Max
3.5
6
15
20
2.5
7
Notes
1. NC pins are not connected on the die.
2. Datasheet specifications are not guaranteed for VCC in the range of 3.6 V to 4.5 V.
3. Typical values are included for reference only and are not guaranteed or tested. Typical values are measured at VCC = 3 V, and VCC = 5 V, TA = 25 °C.
Document Number: 001-43142 Rev. *J
Page 3 of 17
CY62146ESL MoBL
Maximum Ratings
Output current into outputs (LOW) ............................. 20 mA
Exceeding the maximum ratings may impair the useful life of the
device. These user guidelines are not tested.
Storage temperature ................................ –65 °C to +150 °C
Ambient temperature with
power applied .......................................... –55 °C to +125 °C
Static discharge voltage
(MIL-STD-883, Method 3015) .................................. >2001 V
Latch up current ...................................................... >200 mA
Operating Range
Supply voltage to ground potential ................–0.5 V to 6.0 V
Device
Range
Ambient
Temperature
VCC[6]
DC voltage applied to outputs
in High Z State [4, 5] ........................................–0.5 V to 6.0 V
CY62146ESL
Industrial
–40 °C to +85 °C
2.2 V–3.6 V,
and
4.5 V–5.5 V
DC input voltage [4, 5] .....................................–0.5 V to 6.0 V
Electrical Characteristics
Over the Operating Range
Parameter
VOH
VOL
VIH
VIL
Description
Output high voltage
Output low voltage
Input high voltage
Input low voltage
Test Conditions
45 ns
Min
Typ [7]
Max
2.2 < VCC < 2.7
IOH = –0.1 mA
2.0
–
–
2.7 < VCC < 3.6
IOH = –1.0 mA
2.4
–
–
4.5 < VCC < 5.5
IOH = –1.0 mA
2.4
–
–
2.2 < VCC < 2.7
IOL = 0.1 mA
–
–
0.4
2.7 < VCC < 3.6
IOL = 2.1mA
–
–
0.4
4.5 < VCC < 5.5
IOL = 2.1mA
–
–
0.4
2.2 < VCC < 2.7
1.8
–
VCC + 0.3
2.7 < VCC < 3.6
2.2
–
VCC + 0.3
4.5 < VCC < 5.5
2.2
–
VCC + 0.5
2.2 < VCC < 2.7
–0.3
–
0.6
2.7 < VCC < 3.6
–0.3
–
0.8
4.5 < VCC < 5.5
–0.5
–
0.8
GND < VI < VCC
–1
–
+1
Unit
V
V
V
V
A
IIX
Input Leakage Current
IOZ
Output Leakage Current
GND < VO < VCC, Output Disabled
–1
–
+1
A
ICC
VCC Operating Supply Current
f = fmax = 1/tRC
VCC = VCCmax
IOUT = 0 mA,
CMOS levels
–
15
20
mA
–
3.5
6
f = 1 MHz
ISB1[8]
Automatic CE Power down
Current – CMOS Inputs
CE > VCC 0.2 V,
VIN > VCC – 0.2 V or VIN < 0.2 V,
f = fmax (Address and Data Only),
f = 0 (OE, BHE, BLE and WE),
VCC = VCC(max)
–
2.5
7
A
ISB2[8]
Automatic CE Power down
Current – CMOS Inputs
CE > VCC – 0.2 V,
VIN > VCC – 0.2 V or VIN < 0.2 V,
f = 0, VCC = VCC(max)
–
2.5
7
A
Notes
4. VIL(min) = –2.0V for pulse durations less than 20 ns.
5. VIH(max) = VCC + 0.75 V for pulse durations less than 20 ns.
6. Full Device AC operation assumes a 100 s ramp time from 0 to VCC (min) and 200 s wait time after VCC stabilization.
7. Typical values are included for reference only and are not guaranteed or tested. Typical values are measured at VCC = 3 V, and VCC = 5 V, TA = 25 °C.
8. Chip enable (CE) must be HIGH at CMOS level to meet the ISB1/ISB2/ICCDR spec. Other inputs can be left floating.
Document Number: 001-43142 Rev. *J
Page 4 of 17
CY62146ESL MoBL
Capacitance
Parameter [9]
Description
CIN
Input capacitance
COUT
Output capacitance
Test Conditions
Max
Unit
10
pF
10
pF
Test Conditions
TSOP II
Unit
Still Air, soldered on a 3 × 4.5 inch, four-layer printed circuit
board
57.92
C/W
17.44
C/W
TA = 25 °C, f = 1 MHz, VCC = VCC(typ)
Thermal Resistance
Parameter [9]
Description
JA
Thermal resistance
(junction to ambient)
JC
Thermal resistance
(junction to case)
AC Test Loads and Waveforms
Figure 2. AC Test Loads and Waveforms
R1
VCC
Output
All Input Pulses
VCC
10%
30 pF
90%
GND
R2 Rise Time = 1 V/ns
Including
JIG and
Scope
90%
10%
Fall Time = 1 V/ns
Equivalent to:
Thé venin Equivalent
RTH
OUTPUT
V TH
Parameter
2.5 V
3.0 V
5.0 V
Unit
R1
16667
1103
1800
R2
15385
1554
990
RTH
8000
645
639
VTH
1.20
1.75
1.77
V
Note
9. Tested initially and after any design or process changes that may affect these parameters.
Document Number: 001-43142 Rev. *J
Page 5 of 17
CY62146ESL MoBL
Data Retention Characteristics
Over the Operating Range
Parameter
Description
Conditions
Min
Typ [10]
Max
Unit
1.5
–
–
V
–
3
8.8
A
VDR
VCC for data retention
ICCDR[11]
Data retention current
tCDR [12]
Chip deselect to data retention
time
0
–
–
ns
tR [13]
Operation recovery time
45
–
–
ns
CE > VCC – 0.2 V,
VCC = 1.5 V
VIN > VCC – 0.2 V or
VIN < 0.2 V
Data Retention Waveform
Figure 3. Data Retention Waveform
DATA RETENTION MODE
VCC
VCC(min)
tCDR
VDR > 1.5 V
VCC(min)
tR
CE
Notes
10. Typical values are included for reference only and are not guaranteed or tested. Typical values are measured at VCC = 3 V, and VCC = 5 V, TA = 25 °C.
11. Chip enable (CE) must be HIGH at CMOS level to meet the ISB1 / ISB2 / ICCDR spec. Other inputs can be left floating.
12. Tested initially and after any design or process changes that may affect these parameters.
13. Full device operation requires linear VCC ramp from VDR to VCC(min) > 100 s or stable at VCC(min) > 100 s.
Document Number: 001-43142 Rev. *J
Page 6 of 17
CY62146ESL MoBL
Switching Characteristics
Over the Operating Range
Parameter [14, 15]
Description
45 ns
Min
Max
Unit
Read Cycle
tRC
Read cycle time
45
–
ns
tAA
Address to data valid
–
45
ns
tOHA
Data hold from address change
10
–
ns
tACE
CE LOW to data valid
–
45
ns
tDOE
OE LOW to data valid
–
22
ns
tLZOE
OE LOW to Low Z [16]
5
–
ns
–
18
ns
10
–
ns
–
tHZOE
tLZCE
OE HIGH to High Z
CE LOW to Low Z
[16, 17]
[16]
[16, 17]
tHZCE
CE HIGH to High Z
18
ns
tPU
CE LOW to power up
0
–
ns
tPD
CE HIGH to power down
–
45
ns
tDBE
BLE/BHE LOW to data valid
–
22
ns
5
–
ns
–
18
ns
45
–
ns
ns
[16]
tLZBE
BLE/BHE LOW to Low Z
tHZBE
BLE/BHE HIGH to High Z [16, 17]
Write Cycle
tWC
[18, 19]
Write cycle time
tSCE
CE LOW to write end
35
–
tAW
Address setup to write end
35
–
ns
tHA
Address hold from write end
0
–
ns
tSA
Address setup to Write Start
0
–
ns
ns
tPWE
WE pulse width
35
–
tBW
BLE/BHE LOW to write end
35
–
ns
tSD
Data Setup to write end
25
–
ns
tHD
Data Hold from write end
0
–
ns
–
18
ns
10
–
ns
[16, 17]
tHZWE
WE LOW to High Z
tLZWE
WE HIGH to Low Z [16]
Notes
14. In an earlier revision of this device, under a specific application condition, READ and WRITE operations were limited to switching of the byte enable and/or chip enable
signals as described in the Application Note AN66311. However, the issue has been fixed and in production now, and hence, this Application Note is no longer
applicable. It is available for download on our website as it contains information on the date code of the parts, beyond which the fix has been in production.
15. Test conditions for all parameters other than tri-state parameters assume signal transition time of 3 ns or less, timing reference levels of 1.5 V, input pulse levels of
0 to 3 V, and output loading of the specified IOL/IOH as shown in the Figure 2 on page 5.
16. At any temperature and voltage condition, tHZCE is less than tLZCE, tHZBE is less than tLZBE, tHZOE is less than tLZOE, and tHZWE is less than tLZWE for any device.
17. tHZOE, tHZCE, tHZBE, and tHZWE transitions are measured when the outputs enter a high-impedance state.
18. The internal write time of the memory is defined by the overlap of WE, CE = VIL, BHE, BLE or both = VIL. All signals must be active to initiate a write and any of these
signals can terminate a write by going inactive. The data input setup and hold timing must be referenced to the edge of the signal that terminates the write.
19. The minimum write cycle time for Write Cycle No. 4 (WE Controlled, OE LOW) is the sum of tHZWE and tSD.
Document Number: 001-43142 Rev. *J
Page 7 of 17
CY62146ESL MoBL
Switching Waveforms
Figure 4. Read Cycle No. 1 (Address Transition Controlled) [20, 21]
tRC
RC
ADDRESS
tOHA
DATA OUT
tAA
PREVIOUS DATA VALID
DATA VALID
Figure 5. Read Cycle No. 2 (OE Controlled) [21, 22]
ADDRESS
tRC
CE
tPD
tHZCE
tACE
OE
tHZOE
tDOE
tLZOE
BHE/BLE
tHZBE
tDBE
tLZBE
DATA OUT
HIGHIMPEDANCE
HIGH
IMPEDANCE
DATA VALID
tLZCE
tPU
VCC
SUPPLY
CURRENT
50%
50%
ICC
ISB
Notes
20. The device is continuously selected. OE, CE = VIL, BHE, BLE, or both = VIL.
21. WE is HIGH for read cycle.
22. Address valid before or similar to CE, BHE, BLE transition LOW.
Document Number: 001-43142 Rev. *J
Page 8 of 17
CY62146ESL MoBL
Switching Waveforms (continued)
Figure 6. Write Cycle No. 1 (WE Controlled) [23, 24]
tWC
ADDRESS
tSCE
CE
tAW
tHA
tSA
tPWE
WE
tBW
BHE/BLE
tHD
tSD
DATA I/O
NOTE 25
DATAIN
Figure 7. Write Cycle No. 2 (CE Controlled) [23, 24]
tWC
ADDRESS
tSCE
CE
tSA
tAW
tHA
tPWE
WE
tBW
BHE/BLE
tSD
DATA I/O
NOTE 25
tHD
DATAIN
Notes
23. The internal write time of the memory is defined by the overlap of WE, CE = VIL, BHE, BLE or both = VIL. All signals must be active to initiate a write and any of these
signals can terminate a write by going inactive. The data input setup and hold timing must be referenced to the edge of the signal that terminates the write.
24. If CE goes HIGH simultaneously with WE = VIH, the output remains in a high impedance state.
25. During this period, the I/Os are in output state. Do not apply input signals.
Document Number: 001-43142 Rev. *J
Page 9 of 17
CY62146ESL MoBL
Switching Waveforms (continued)
Figure 8. Write Cycle No. 3 (BHE/BLE Controlled) [26]
tWC
ADDRESS
CE
tSCE
tAW
tHA
tBW
BHE/BLE
tSA
tPWE
WE
tHZWE
DATA I/O
tSD
NOTE 27
tHD
DATAIN
tLZWE
Figure 9. Write Cycle No. 4 (WE Controlled, OE LOW) [28]
tWC
ADDRESS
CE
tAW
t HA
tSA
WE
tSD
DATA I/O
NOTE 27
t HD
DATA INVALID
t HZWE
tLZWE
Notes
26. If CE goes HIGH simultaneously with WE = VIH, the output remains in a high impedance state.
27. During this period, the I/Os are in output state. Do not apply input signals.
28. The minimum write cycle time for Write Cycle No. 4 (WE Controlled, OE LOW) is the sum of tHZWE and tSD.
Document Number: 001-43142 Rev. *J
Page 10 of 17
CY62146ESL MoBL
Truth Table
CE [29]
WE
OE
BHE
BLE
H
X
X
X
X
High-Z
Deselect/Power down
Standby (ISB)
L
X
X
H
H
High-Z
Output disabled
Active (ICC)
L
H
L
L
L
Data Out (I/O0–I/O15)
Read
Active (ICC)
L
H
L
H
L
Data Out (I/O0–I/O7);
I/O8–I/O15 in High-Z
Read
Active (ICC)
L
H
L
L
H
Data Out (I/O8–I/O15);
I/O0–I/O7 in High-Z
Read
Active (ICC)
L
H
H
L
L
High-Z
Output disabled
Active (ICC)
L
H
H
H
L
High-Z
Output disabled
Active (ICC)
L
H
H
L
H
High-Z
Output disabled
Active (ICC)
L
L
X
L
L
Data In (I/O0–I/O15)
Write
Active (ICC)
L
L
X
H
L
Data In (I/O0–I/O7);
I/O8–I/O15 in High-Z
Write
Active (ICC)
L
L
X
L
H
Data In (I/O8–I/O15);
I/O0–I/O7 in High-Z
Write
Active (ICC)
Inputs/Outputs
Mode
Power
Note
29. Chip enable must be at CMOS levels (not floating). Intermediate voltage levels on this pin is not permitted.
Document Number: 001-43142 Rev. *J
Page 11 of 17
CY62146ESL MoBL
Ordering Information
Speed
(ns)
45
Ordering Code
CY62146ESL-45ZSXI
Package
Diagram
Package Type
51-85087 44-pin TSOP Type II (Pb-free)
Operating
Range
Industrial
Ordering Code Definitions
CY 621 4
6
E
SL - 45 ZS X
I
Temperature Range: I = Industrial
Pb-free
Package Type: ZS = 44-pin TSOP II
Speed Grade: 45 ns
Voltage Range: SL = (3 V typical; 5 V typical)
Process Technology: E = 90 nm
Bus Width: 6 = × 16
Density: 4 = 4-Mbit
Family Code: MoBL SRAM family
Company ID: CY = Cypress
Document Number: 001-43142 Rev. *J
Page 12 of 17
CY62146ESL MoBL
Package Diagram
Figure 10. 44-pin TSOP II (18.4 × 10.2 × 1.194 mm) Package Outline, 51-85087
51-85087 *F
Document Number: 001-43142 Rev. *J
Page 13 of 17
CY62146ESL MoBL
Acronyms
Acronym
Document Conventions
Description
Units of Measure
BHE
Byte High Enable
BLE
Byte Low Enable
°C
degree Celsius
CE
Chip Enable
MHz
megahertz
CMOS
Complementary Metal Oxide Semiconductor
A
microampere
I/O
Input/Output
mA
milliampere
OE
Output Enable
ns
nanosecond
SRAM
Static Random Access Memory
ohm
TSOP
Thin Small Outline Package
pF
picofarad
VFBGA
Very Fine-Pitch Ball Grid Array
V
volt
WE
Write Enable
W
watt
Document Number: 001-43142 Rev. *J
Symbol
Unit of Measure
Page 14 of 17
CY62146ESL MoBL
Document History Page
Document Title: CY62146ESL MoBL, 4-Mbit (256K × 16) Static RAM
Document Number: 001-43142
Rev.
ECN No.
Submission
Date
**
1875228
01/02/2008
New data sheet.
*A
2944332
06/04/2010
Updated Electrical Characteristics:
Added Note 8 and referred the same note in ISB2 parameter.
Updated Truth Table:
Added Note 29 and referred the same note in CE column.
Updated Package Diagram:
spec 51-85087 – Changed revision from *A to *C.
Added Acronyms.
Updated to new template.
*B
3109186
12/13/2010
Changed Table Footnotes to Footnotes.
Updated Ordering Information:
No change in part numbers.
Added Ordering Code Definitions.
Completing Sunset Review.
*C
3296704
06/29/2011
Updated Functional Description:
Updated description (Removed “For best practice recommendations, refer to the Cypress
Application Note AN1064, SRAM System Guidelines.”).
Updated Electrical Characteristics:
Updated Note 8 (Added ISB1) and referred the same note in ISB1 parameter.
Updated Capacitance:
Added Note 9 and referred the same note in parameter column.
Updated Thermal Resistance:
Added Note 9 and referred the same note in parameter column.
Updated Data Retention Characteristics:
Added Note 11 and referred the same note in ICCDR parameter.
Changed minimum value of tR parameter from tRC to 45 ns.
Updated Switching Characteristics:
Moved Note 14 to parameter column.
Added Units of Measure.
*D
3903350
02/13/2013
Updated Switching Waveforms:
Updated Figure 6 (Removed OE signal).
Updated Figure 7 (Removed OE signal).
Removed the Note “Data I/O is high impedance if OE = VIH.” and its reference in Figure 6,
Figure 7.
Removed the figure “Write Cycle 3: WE controlled, OE LOW”.
Updated Figure 8 (Removed “OE LOW” in caption only).
Updated Package Diagram:
spec 51-85087 – Changed revision from *C to *E.
Completing Sunset Review.
*E
4100920
08/21/2013
Updated Switching Characteristics:
Added Note 14 and referred the same note in “Parameter” column.
Updated to new template.
*F
4576406
01/16/2015
Updated Functional Description:
Added “For a complete list of related documentation, click here.” at the end.
Updated Switching Characteristics:
Added Note 19 and referred the same note in “Write Cycle”.
Updated Switching Waveforms:
Added Figure 9.
Added Note 28 and referred the same note in Figure 9.
Document Number: 001-43142 Rev. *J
Description of Change
Page 15 of 17
CY62146ESL MoBL
Document History Page (continued)
Document Title: CY62146ESL MoBL, 4-Mbit (256K × 16) Static RAM
Document Number: 001-43142
Rev.
ECN No.
Submission
Date
*G
5169392
03/10/2016
Updated Thermal Resistance:
Replaced “two-layer” with “four-layer” in “Test Conditions” column.
Changed value of JA parameter from 77 C/W to 57.92 C/W.
Changed value of JC parameter from 13 C/W to 17.44 C/W.
Updated to new template.
Completing Sunset Review.
*H
5983493
12/04/2017
Updated Cypress Logo and Copyright.
*I
6529117
04/01/2019
Updated to new template.
Completing Sunset Review.
*J
6906316
06/26/2020
Updated Features:
Changed value of Typical standby current from 1 µA to 2.5 µA.
Changed value of Typical active current from 2 mA to 3.5 mA.
Updated Product Portfolio:
Changed typical value of Operating ICC from 2 mA to 3.5 mA corresponding to “f = 1 MHz”.
Changed maximum value of Operating ICC from 2.5 mA to 6 mA corresponding to
“f = 1 MHz”.
Changed typical value of Standby, ISB2 from 1 µA to 2.5 µA.
Updated Electrical Characteristics:
Changed typical value of ICC parameter from 2 mA to 3.5 mA corresponding to Test
Condition “f = 1 MHz”.
Changed maximum value of ICC parameter from 2.5 mA to 6 mA corresponding to Test
Condition “f = 1 MHz”.
Changed typical value of ISB1 parameter from 1 µA to 2.5 µA.
Changed typical value of ISB2 parameter from 1 µA to 2.5 µA.
Updated Data Retention Characteristics:
Changed typical value of ICCDR parameter from 1 μA to 3 μA.
Changed maximum value of ICCDR parameter from 7 µA to 8.8 µA.
Updated Package Diagram:
spec 51-85087 – Changed revision from *E to *F.
Updated to new template.
Document Number: 001-43142 Rev. *J
Description of Change
Page 16 of 17
CY62146ESL MoBL
Sales, Solutions, and Legal Information
Worldwide Sales and Design Support
Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office
closest to you, visit us at Cypress Locations.
PSoC® Solutions
Products
Arm® Cortex® Microcontrollers
Automotive
cypress.com/arm
cypress.com/automotive
Clocks & Buffers
Interface
cypress.com/clocks
cypress.com/interface
Internet of Things
Memory
cypress.com/iot
cypress.com/memory
Microcontrollers
cypress.com/mcu
PSoC
cypress.com/psoc
Power Management ICs
Touch Sensing
USB Controllers
Wireless Connectivity
PSoC 1 | PSoC 3 | PSoC 4 | PSoC 5LP | PSoC 6 MCU
Cypress Developer Community
Community | Code Examples | Projects | Video | Blogs |
Training | Components
Technical Support
cypress.com/support
cypress.com/pmic
cypress.com/touch
cypress.com/usb
cypress.com/wireless
© Cypress Semiconductor Corporation, 2008–2020. This document is the property of Cypress Semiconductor Corporation and its subsidiaries (“Cypress”). This document, including any software or
firmware included or referenced in this document (“Software”), is owned by Cypress under the intellectual property laws and treaties of the United States and other countries worldwide. Cypress
reserves all rights under such laws and treaties and does not, except as specifically stated in this paragraph, grant any license under its patents, copyrights, trademarks, or other intellectual property
rights. If the Software is not accompanied by a license agreement and you do not otherwise have a written agreement with Cypress governing the use of the Software, then Cypress hereby grants
you a personal, non-exclusive, nontransferable license (without the right to sublicense) (1) under its copyright rights in the Software (a) for Software provided in source code form, to modify and reproduce
the Software solely for use with Cypress hardware products, only internally within your organization, and (b) to distribute the Software in binary code form externally to end users (either directly or
indirectly through resellers and distributors), solely for use on Cypress hardware product units, and (2) under those claims of Cypress’s patents that are infringed by the Software (as provided by
Cypress, unmodified) to make, use, distribute, and import the Software solely for use with Cypress hardware products. Any other use, reproduction, modification, translation, or compilation of the
Software is prohibited.
TO THE EXTENT PERMITTED BY APPLICABLE LAW, CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS DOCUMENT OR ANY SOFTWARE
OR ACCOMPANYING HARDWARE, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. No computing
device can be absolutely secure. Therefore, despite security measures implemented in Cypress hardware or software products, Cypress shall have no liability arising out of any security breach, such
as unauthorized access to or use of a Cypress product. CYPRESS DOES NOT REPRESENT, WARRANT, OR GUARANTEE THAT CYPRESS PRODUCTS, OR SYSTEMS CREATED USING
CYPRESS PRODUCTS, WILL BE FREE FROM CORRUPTION, ATTACK, VIRUSES, INTERFERENCE, HACKING, DATA LOSS OR THEFT, OR OTHER SECURITY INTRUSION (collectively, “Security
Breach”). Cypress disclaims any liability relating to any Security Breach, and you shall and hereby do release Cypress from any claim, damage, or other liability arising from any Security Breach. In
addition, the products described in these materials may contain design defects or errors known as errata which may cause the product to deviate from published specifications. To the extent permitted
by applicable law, Cypress reserves the right to make changes to this document without further notice. Cypress does not assume any liability arising out of the application or use of any product or
circuit described in this document. Any information provided in this document, including any sample design information or programming code, is provided only for reference purposes. It is the
responsibility of the user of this document to properly design, program, and test the functionality and safety of any application made of this information and any resulting product. “High-Risk Device”
means any device or system whose failure could cause personal injury, death, or property damage. Examples of High-Risk Devices are weapons, nuclear installations, surgical implants, and other
medical devices. “Critical Component” means any component of a High-Risk Device whose failure to perform can be reasonably expected to cause, directly or indirectly, the failure of the High-Risk
Device, or to affect its safety or effectiveness. Cypress is not liable, in whole or in part, and you shall and hereby do release Cypress from any claim, damage, or other liability arising from any use of
a Cypress product as a Critical Component in a High-Risk Device. You shall indemnify and hold Cypress, its directors, officers, employees, agents, affiliates, distributors, and assigns harmless from
and against all claims, costs, damages, and expenses, arising out of any claim, including claims for product liability, personal injury or death, or property damage arising from any use of a Cypress
product as a Critical Component in a High-Risk Device. Cypress products are not intended or authorized for use as a Critical Component in any High-Risk Device except to the limited extent that (i)
Cypress’s published data sheet for the product explicitly states Cypress has qualified the product for use in a specific High-Risk Device, or (ii) Cypress has given you advance written authorization to
use the product as a Critical Component in the specific High-Risk Device and you have signed a separate indemnification agreement.
Cypress, the Cypress logo, Spansion, the Spansion logo, and combinations thereof, WICED, PSoC, CapSense, EZ-USB, F-RAM, and Traveo are trademarks or registered trademarks of Cypress in
the United States and other countries. For a more complete list of Cypress trademarks, visit cypress.com. Other names and brands may be claimed as property of their respective owners.
Document Number: 001-43142 Rev. *J
Revised June 26, 2020
Page 17 of 17
工商网监
湘ICP备2023018690号
