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CY62157ESL MoBL®
8-Mbit (512K × 16) Static RAM
8-Mbit (512K × 16) Static RAM
Features
■
Very high speed: 45 ns
■
Wide voltage range: 2.2 V to 3.6 V and 4.5 V to 5.5 V
■
Ultra low standby power
❐ Typical Standby current: 2 A
❐ Maximum Standby current: 8 A
addresses are not toggling. Place the device into standby mode
when deselected (CE HIGH or both BHE and BLE are HIGH).
The input or output pins (I/O0 through I/O15) are placed in a high
impedance state when the device is deselected (CE HIGH), the
outputs are disabled (OE HIGH), both the Byte High Enable and
the Byte Low Enable are disabled (BHE, BLE HIGH), or during
an active write operation (CE LOW and WE LOW).
To write to the device, take Chip Enable (CE) and Write Enable
(WE) inputs LOW. If Byte Low Enable (BLE) is LOW, then data
from I/O pins (I/O0 through I/O7) is written into the location
specified on the address pins (A0 through A18). If Byte High
Enable (BHE) is LOW, then data from I/O pins (I/O8 through
I/O15) is written into the location specified on the address pins
(A0 through A18).
■
Ultra low active power
❐ Typical active current: 1.8 mA at f = 1 MHz
■
Easy memory expansion with CE and OE features
■
Automatic power down when deselected
■
Complementary metal oxide semiconductor (CMOS) for
optimum speed and power
■
Available in Pb-free 44-pin thin small outline package (TSOP) II
package
Functional Description
The CY62157ESL is a high performance CMOS static RAM
organized as 512K words by 16 bits. This device features
advanced circuit design to provide ultra low active current. This
is ideal for providing More Battery Life™ (MoBL®) in portable
applications. The device also has an automatic power down
feature that significantly reduces power consumption when
To read from the device, take Chip Enable (CE) and Output
Enable (OE) LOW while forcing the Write Enable (WE) HIGH. If
Byte Low Enable (BLE) is LOW, then data from the memory
location specified by the address pins appear on I/O0 to I/O7. If
Byte High Enable (BHE) is LOW, then data from memory
appears on I/O8 to I/O15. See the Truth Table on page 11 for a
complete description of read and write modes.
The CY62157ESL device is suitable for interfacing with
processors that have TTL I/P levels. It is not suitable for
processors that require CMOS I/P levels. Please see Electrical
Characteristics on page 4 for more details and suggested
alternatives.
For a complete list of related documentation, click here.
Logic Block Diagram
ROW DECODER
A10
A9
A8
A7
A6
A5
A4
A3
A2
A1
A0
SENSE AMPS
DATA IN DRIVERS
512K × 16
RAM Array
I/O0–I/O7
I/O8–I/O15
COLUMN DECODER
Cypress Semiconductor Corporation
Document Number: 001-43141 Rev. *J
•
198 Champion Court
A17
A18
A16
A15
BLE
A14
BHE
A11
A12
A13
CE
Power Down
Circuit
•
BHE
WE
CE
OE
BLE
San Jose, CA 95134-1709
•
408-943-2600
Revised April 1, 2019
CY62157ESL MoBL®
Contents
Pin Configurations ........................................................... 3
Product Portfolio .............................................................. 3
Maximum Ratings ............................................................. 4
Operating Range ............................................................... 4
Electrical Characteristics ................................................. 4
Capacitance ...................................................................... 5
Thermal Resistance .......................................................... 5
AC Test Loads and Waveforms ....................................... 5
Data Retention Characteristics ....................................... 6
Data Retention Waveform ................................................ 6
Switching Characteristics ................................................ 7
Switching Waveforms ...................................................... 8
Truth Table ...................................................................... 11
Document Number: 001-43141 Rev. *J
Ordering Information ...................................................... 12
Ordering Code Definitions ......................................... 12
Package Diagram ............................................................ 13
Acronyms ........................................................................ 14
Document Conventions ................................................. 14
Units of Measure ....................................................... 14
Document History Page ................................................. 15
Sales, Solutions, and Legal Information ...................... 17
Worldwide Sales and Design Support ....................... 17
Products .................................................................... 17
PSoC® Solutions ...................................................... 17
Cypress Developer Community ................................. 17
Technical Support ..................................................... 17
Page 2 of 17
CY62157ESL MoBL®
Pin Configurations
Figure 1. 44-pin TSOP II pinout (Top View)
A4
A3
A2
A1
A0
CE
I/O0
I/O1
I/O2
I/O3
VCC
VSS
I/O4
I/O5
I/O6
I/O7
WE
A18
A17
A16
A15
A14
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
A5
A6
A7
OE
BHE
BLE
I/O15
I/O14
I/O13
I/O12
VSS
VCC
I/O11
I/O10
I/O9
I/O8
A8
A9
A10
A11
A12
A13
Product Portfolio
Power Dissipation
Product
CY62157ESL
Range
VCC Range (V) [1]
Industrial 2.2 V–3.6 V and 4.5 V–5.5 V
Speed
(ns)
45
Operating ICC, (mA)
f = 1MHz
f = fmax
Standby, ISB2 (A)
Typ[2]
Max
Typ [2]
Max
Typ [2]
Max
1.8
3
18
25
2
8
Notes
1. Datasheet specifications are not guaranteed for VCC in the range of 3.6 V to 4.5 V.
2. Typical values are included for reference only and are not guaranteed or tested. Typical values are measured at VCC = 3 V, and VCC = 5 V, TA = 25 °C.
Document Number: 001-43141 Rev. *J
Page 3 of 17
CY62157ESL MoBL®
Maximum Ratings
Output Current into Outputs (LOW) ............................ 20 mA
Exceeding the maximum ratings may impair the useful life of the
device. These user guidelines are not tested.
Storage Temperature ............................... –65 °C to +150 °C
Ambient Temperature with
Power Applied ......................................... –55 °C to +125 °C
Static Discharge Voltage
(MIL-STD-883, Method 3015) .................................. >2001 V
Latch up Current ..................................................... >200 mA
Operating Range
Supply Voltage to Ground Potential ...............–0.5 V to 6.0 V
Device
Range
DC Voltage Applied to Outputs
in High Z State [3, 4] ........................................–0.5 V to 6.0 V
CY62157ESL
Industrial
Ambient
Temperature
–40 °C to +85 °C
DC Input Voltage [3, 4] ....................................–0.5 V to 6.0 V
VCC[5]
2.2 V–3.6 V,
and
4.5 V–5.5 V
Electrical Characteristics
Over the Operating Range
Parameter
VOH
VOL
VIH
VIL
Description
Output high voltage
Output low voltage
Input high voltage
Input low voltage
Test Conditions
45 ns
Min
Typ [6]
Max
2.2 < VCC < 2.7
IOH = –0.1 mA
2.0
–
–
2.7 < VCC < 3.6
IOH = –1.0 mA
2.4
–
–
4.5 < VCC < 5.5
IOH = –1.0 mA
2.4
–
–
4.5 < VCC < 5.5
IOH = –0.1 mA
–
–
3.4 [7]
2.2 < VCC < 2.7
IOL = 0.1 mA
–
–
0.4
2.7 < VCC < 3.6
IOL = 2.1 mA
–
–
0.4
4.5 < VCC < 5.5
IOL = 2.1 mA
–
–
0.4
2.2 < VCC < 2.7
1.8
–
VCC + 0.3
2.7 < VCC < 3.6
2.2
–
VCC + 0.3
4.5 < VCC < 5.5
2.2
–
VCC + 0.5
2.2 < VCC < 2.7
–0.3
–
0.6
2.7 < VCC < 3.6
–0.3
–
0.8
4.5 < VCC < 5.5
–0.5
–
0.8
GND < VI < VCC
–1
–
+1
Unit
V
V
V
V
A
IIX
Input leakage current
IOZ
Output leakage current
GND < VO < VCC, Output Disabled
–1
–
+1
A
ICC
VCC operating supply current
f = fmax = 1/tRC
VCC = VCCmax
IOUT = 0 mA,
CMOS levels
–
18
25
mA
–
1.8
3
f = 1 MHz
ISB1[8]
Automatic CE power down
current – CMOS inputs
CE > VCC 0.2 V,
VIN > VCC – 0.2 V or VIN < 0.2 V,
f = fmax (address and data only),
f = 0 (OE, BHE, BLE and WE),
VCC = VCC(max)
–
2
8
A
ISB2[8]
Automatic CE power down
current – CMOS inputs
CE > VCC – 0.2 V,
VIN > VCC – 0.2 V or VIN < 0.2 V,
f = 0, VCC = VCC(max)
–
2
8
A
Notes
3. VIL (min) = –2.0 V for pulse durations less than 20 ns.
4. VIH (max) = VCC + 0.75 V for pulse durations less than 20 ns.
5. Full device AC operation assumes a 100 s ramp time from 0 to VCC (min) and 200 s wait time after VCC stabilization.
6. Typical values are included for reference only and are not guaranteed or tested. Typical values are measured at VCC = 3 V, and VCC = 5 V, TA = 25 °C.
7. Please note that the maximum VOH limit does not exceed minimum CMOS VIH of 3.5 V. If you are interfacing this SRAM with 5 V legacy processors that require a
minimum VIH of 3.5 V, please refer to Application Note AN6081 for technical details and options you may consider.
8. Chip enable (CE) needs to be tied to CMOS levels to meet the ISB1/ISB2 / ICCDR spec. Other inputs can be left floating.
Document Number: 001-43141 Rev. *J
Page 4 of 17
CY62157ESL MoBL®
Capacitance
Parameter [9]
Description
CIN
Input capacitance
COUT
Output capacitance
Test Conditions
Max
Unit
10
pF
10
pF
Test Conditions
TSOP II
Unit
Still Air, soldered on a 3 × 4.5 inch, four-layer printed circuit
board
57.92
C/W
17.44
C/W
TA = 25 °C, f = 1 MHz, VCC = VCC(typ)
Thermal Resistance
Parameter [9]
Description
θJA
Thermal resistance
(junction to ambient)
θJC
Thermal resistance
(junction to case)
AC Test Loads and Waveforms
Figure 2. AC Test Loads and Waveforms
R1
VCC
OUTPUT
30 pF
VCC
10%
GND
R2 Rise Time = 1 V/ns
INCLUDING
JIG AND
SCOPE
ALL INPUT PULSES
90%
90%
10%
Fall Time = 1 V/ns
Equivalent to:
THÉVENIN EQUIVALENT
RTH
OUTPUT
V TH
Parameters
2.5 V
3.0 V
5.0 V
Unit
R1
16667
1103
1800
R2
15385
1554
990
RTH
8000
645
639
VTH
1.20
1.75
1.77
V
Note
9. Tested initially and after any design or process changes that may affect these parameters.
Document Number: 001-43141 Rev. *J
Page 5 of 17
CY62157ESL MoBL®
Data Retention Characteristics
Over the Operating Range
Parameter
Description
VDR
VCC for data retention
ICCDR[10]
Data retention current
Conditions
CE > VCC – 0.2 V,
VCC = 1.5 V
VIN > VCC – 0.2 V or V = 2.0 V
CC
VIN < 0.2 V
Min
Typ [10]
Max
Unit
1.5
–
–
V
–
2
5
A
–
2
8
tCDR [12]
Chip deselect to data retention
time
0
–
–
ns
tR [13]
Operation recovery time
45
–
–
ns
Data Retention Waveform
Figure 3. Data Retention Waveform
DATA RETENTION MODE
VCC
CE or
BHE.BLE
VCC(min)
tCDR
VDR > 1.5 V
VCC(min)
tR
[14]
Notes
10. Typical values are included for reference only and are not guaranteed or tested. Typical values are measured at VCC = 3 V, and VCC = 5 V, TA = 25 °C.
11. Chip enable (CE) needs to be tied to CMOS levels to meet the ISB1/ISB2 / ICCDR spec. Other inputs can be left floating.
12. Tested initially and after any design or process changes that may affect these parameters.
13. Full device operation requires linear VCC ramp from VDR to VCC(min) > 100 s or stable at VCC(min) > 100 s.
14. BHE.BLE is the AND of both BHE and BLE. Deselect the chip by either disabling chip enable signals or by disabling both BHE and BLE.
Document Number: 001-43141 Rev. *J
Page 6 of 17
CY62157ESL MoBL®
Switching Characteristics
Over the Operating Range
Parameter [15, 16]
Description
45 ns
Min
Max
Unit
Read Cycle
tRC
Read cycle time
45
–
ns
tAA
Address to data valid
–
45
ns
tOHA
Data hold from address change
10
–
ns
tACE
CE LOW to data valid
–
45
ns
tDOE
OE LOW to data valid
–
22
ns
tLZOE
OE LOW to Low Z [17]
5
–
ns
–
18
ns
10
–
ns
–
tHZOE
tLZCE
OE HIGH to High Z
CE LOW to Low Z
[17, 18]
[17]
[17, 18]
tHZCE
CE HIGH to High Z
18
ns
tPU
CE LOW to power up
0
–
ns
tPD
CE HIGH to power down
–
45
ns
tDBE
BLE/BHE LOW to data valid
–
45
ns
5
–
ns
–
18
ns
45
–
ns
ns
[17, 19]
tLZBE
BLE/BHE LOW to Low Z
tHZBE
BLE/BHE HIGH to High Z [17, 18]
Write Cycle
tWC
[20, 21]
Write cycle time
tSCE
CE LOW to write end
35
–
tAW
Address setup to write end
35
–
ns
tHA
Address hold from write end
0
–
ns
tSA
Address setup to write start
0
–
ns
ns
tPWE
WE pulse width
35
–
tBW
BLE/BHE LOW to write end
35
–
ns
tSD
Data setup to write end
25
–
ns
tHD
Data hold from write end
0
–
ns
–
18
ns
10
–
ns
[17, 18]
tHZWE
WE LOW to High Z
tLZWE
WE HIGH to Low Z [17]
Notes
15. In an earlier revision of this device, under a specific application condition, READ and WRITE operations were limited to switching of the byte enable and/or chip enable
signals as described in the Application Note AN66311. However, the issue has been fixed and in production now, and hence, this Application Note is no longer
applicable. It is available for download on our website as it contains information on the date code of the parts, beyond which the fix has been in production.
16. Test conditions for all parameters other than tri-state parameters assume signal transition time of 3 ns or less, timing reference levels of 1.5 V, input pulse levels of 0
to 3 V, and output loading of the specified IOL/IOH as shown in the Figure 2 on page 5.
17. At any temperature and voltage condition, tHZCE is less than tLZCE, tHZBE is less than tLZBE, tHZOE is less than tLZOE, and tHZWE is less than tLZWE for any device.
18. tHZOE, tHZCE, tHZBE, and tHZWE transitions are measured when the outputs enter a high-impedance state.
19. If both byte enables are toggled together, this value is 10 ns.
20. The internal write time of the memory is defined by the overlap of WE, CE = VIL, BHE, BLE or both = VIL. All signals must be active to initiate a write and any of these
signals can terminate a write by going inactive. The data input setup and hold timing must be referenced to the edge of the signal that terminates the write.
21. The minimum write cycle pulse width for Write Cycle No. 4 (WE Controlled, OE LOW) should be equal to the sum of tSD and tHZWE.
Document Number: 001-43141 Rev. *J
Page 7 of 17
CY62157ESL MoBL®
Switching Waveforms
Figure 4. Read Cycle No. 1 (Address Transition Controlled) [22, 23]
tRC
RC
ADDRESS
tOHA
DATA OUT
tAA
PREVIOUS DATA VALID
DATA VALID
Figure 5. Read Cycle No. 2 (OE Controlled) [23, 24]
ADDRESS
tRC
CE
tPD
tHZCE
tACE
OE
tHZOE
tDOE
tLZOE
BHE/BLE
tHZBE
tDBE
tLZBE
DATA OUT
HIGHIMPEDANCE
HIGH
IMPEDANCE
DATA VALID
tLZCE
tPU
VCC
SUPPLY
CURRENT
50%
50%
ICC
ISB
Notes
22. The device is continuously selected. OE, CE = VIL, BHE, BLE, or both = VIL.
23. WE is HIGH for read cycle.
24. Address valid before or similar to CE, BHE, BLE transition LOW.
Document Number: 001-43141 Rev. *J
Page 8 of 17
CY62157ESL MoBL®
Switching Waveforms (continued)
Figure 6. Write Cycle No. 1 (WE Controlled) [25, 26]
tWC
ADDRESS
tSCE
CE
tAW
tHA
tSA
tPWE
WE
tBW
BHE/BLE
tSD
DATA I/O
NOTE 27
tHD
DATAIN
Figure 7. Write Cycle No. 2 (CE Controlled) [25, 26]
tWC
ADDRESS
tSCE
CE
tSA
tAW
tHA
tPWE
WE
tBW
BHE/BLE
tSD
DATA I/O
NOTE 27
tHD
DATAIN
Notes
25. The internal write time of the memory is defined by the overlap of WE, CE = VIL, BHE, BLE or both = VIL. All signals must be active to initiate a write and any of these
signals can terminate a write by going inactive. The data input setup and hold timing must be referenced to the edge of the signal that terminates the write.
26. If CE goes HIGH simultaneously with WE = VIH, the output remains in a high impedance state.
27. During this period, the I/Os are in output state. Do not apply input signals.
Document Number: 001-43141 Rev. *J
Page 9 of 17
CY62157ESL MoBL®
Switching Waveforms (continued)
Figure 8. Write Cycle No. 3 (BHE/BLE Controlled) [28, 29]
tWC
ADDRESS
CE
tSCE
tAW
tHA
tBW
BHE/BLE
tSA
tPWE
WE
tHZWE
DATA I/O
tHD
tSD
NOTE 30
DATAIN
tLZWE
Figure 9. Write Cycle No. 4 (WE Controlled, OE LOW) [28, 29, 31]
tWC
Address
tSCE
CE
tAW
tHA
tSA
tPWE
WE
tBW
BHE, BLE
tHZWE
Data I/O
tSD
tHD
Data In Valid
tLZWE
Notes
28. The internal write time of the memory is defined by the overlap of WE, CE = VIL, BHE, BLE or both = VIL. All signals must be active to initiate a write and any of these
signals can terminate a write by going inactive. The data input setup and hold timing must be referenced to the edge of the signal that terminates the write.
29. If CE goes HIGH simultaneously with WE = VIH, the output remains in a high impedance state.
30. During this period, the I/Os are in output state. Do not apply input signals.
31. The minimum write cycle pulse width should be equal to the sum of tSD and tHZWE.
Document Number: 001-43141 Rev. *J
Page 10 of 17
CY62157ESL MoBL®
Truth Table
CE
WE
OE
BHE
BLE
Inputs/Outputs
Mode
Power
H
X
X
X
X
High Z
Deselect/power down
Standby (ISB)
X[32]
X
X
H
H
High Z
Deselect/power down
Standby (ISB)
L
H
L
L
L
Data Out (I/O0–I/O15)
Read
Active (ICC)
L
H
L
H
L
Data Out (I/O0–I/O7);
I/O8–I/O15 in High Z
Read
Active (ICC)
L
H
L
L
H
Data Out (I/O8–I/O15);
I/O0–I/O7 in High Z
Read
Active (ICC)
L
H
H
L
L
High-Z
Output disabled
Active (ICC)
L
H
H
H
L
High-Z
Output disabled
Active (ICC)
L
H
H
L
H
High-Z
Output disabled
Active (ICC)
L
L
X
L
L
Data In (I/O0–I/O15)
Write
Active (ICC)
L
L
X
H
L
Data In (I/O0–I/O7);
I/O8–I/O15 in High Z
Write
Active (ICC)
L
L
X
L
H
Data In (I/O8–I/O15);
I/O0–I/O7 in High Z
Write
Active (ICC)
Note
32. The ‘X’ (Don’t care) state for the Chip enable in the truth table refers to the logic state (either HIGH or LOW). Intermediate voltage levels on this pin is not permitted.
Document Number: 001-43141 Rev. *J
Page 11 of 17
CY62157ESL MoBL®
Ordering Information
Speed
(ns)
45
Ordering Code
CY62157ESL-45ZSXI
Package
Diagram
Package Type
51-85087 44-pin TSOP Type II (Pb-free)
Operating
Range
Industrial
Ordering Code Definitions
CY 621 5
7
E SL - 45 ZS
X
I
Temperature Range: I = Industrial
Pb-free
Package Type: ZS = 44-pin TSOP II
Speed Grade: 45 ns
Voltage Range: SL = 3 V typical; 5 V typical
Process Technology: E = 90 nm
Bus Width: 7 = × 16
Density: 5 = 8-Mbit
Family Code: MoBL SRAM family
Company ID: CY = Cypress
Document Number: 001-43141 Rev. *J
Page 12 of 17
CY62157ESL MoBL®
Package Diagram
Figure 10. 44-pin TSOP II Package Outline, 51-85087
51-85087 *E
Document Number: 001-43141 Rev. *J
Page 13 of 17
CY62157ESL MoBL®
Acronyms
Acronym
Document Conventions
Description
Units of Measure
BHE
Byte High Enable
BLE
Byte Low Enable
°C
degrees Celsius
CE
Chip Enable
MHz
megahertz
CMOS
Complementary Metal Oxide Semiconductor
A
microampere
I/O
Input/Output
mA
milliampere
OE
Output Enable
ns
nanosecond
SRAM
Static Random Access Memory
ohm
TSOP
Thin Small Outline Package
pF
picofarad
WE
Write Enable
V
volt
W
watt
Document Number: 001-43141 Rev. *J
Symbol
Unit of Measure
Page 14 of 17
CY62157ESL MoBL®
Document History Page
Document Title: CY62157ESL MoBL®, 8-Mbit (512K × 16) Static RAM
Document Number: 001-43141
Rev.
ECN No.
Orig. of
Change
Submission
Date
**
1875228
VKN / AESA
01/02/2008
New data sheet.
*A
2943752
VKN
06/03/2010
Added Contents.
Updated Electrical Characteristics:
Added Note 8 and referred the same note in ISB2 parameter.
Updated Truth Table:
Added Note 32 and referred the same note in CE column.
Updated Package Diagram:
spec 51-85087 – Changed revision from *A to *C.
Added Acronyms.
Updated to new template.
*B
3109266
PRAS
12/13/2010
Changed Table Footnotes to Footnotes.
Updated Ordering Information:
No change in part numbers.
Added Ordering Code Definitions.
Completing Sunset Review.
*C
3295175
RAME
06/29/2011
Updated Functional Description:
Updated description (Removed “For best practice recommendations, refer
to the Cypress application note AN1064, SRAM System Guidelines.”).
Updated Electrical Characteristics:
Updated Note 8 (Added ISB1) and referred the same note in ISB1 parameter.
Updated Capacitance:
Added Note 9 and referred the same note in parameter column.
Updated Thermal Resistance:
Added Note 9 and referred the same note in parameter column.
Updated Data Retention Characteristics:
Added Note 11 and referred the same note in ICCDR parameter.
Updated Ordering Information:
No change in part numbers.
Updated Ordering Code Definitions.
Added Units of Measure.
*D
3904207
MEMJ
02/14/2013
Updated Switching Waveforms:
Updated Figure 6 (Removed OE signal).
Updated Figure 7 (Removed OE signal).
Removed the Note “Data I/O is high impedance if OE = VIH.” and its
reference in Figure 6, Figure 7.
Removed the figure “Write Cycle 3: WE controlled, OE LOW”.
Updated Figure 8 (Removed “OE LOW” in caption only).
Removed the Note “Data I/O is high impedance if OE = VIH.” and its
reference in Figure 8.
Updated Package Diagram:
spec 51-85087 – Changed revision from *C to *E.
Completing Sunset Review.
*E
4019657
MEMJ
06/04/2013
Updated Functional Description:
Updated description.
Updated Electrical Characteristics:
Added one more Test Condition “4.5 < VCC < 5.5, IOH = –0.1 mA” for VOH
parameter and added maximum value corresponding to that Test Condition.
Added Note 7 and referred the same note in maximum value for VOH
parameter corresponding to Test Condition “4.5 < VCC < 5.5, IOH = –0.1 mA”.
*F
4100920
VINI
08/21/2013
Updated Switching Characteristics:
Added Note 15 and referred the same note in “Parameter” column.
Updated to new template.
Document Number: 001-43141 Rev. *J
Description of Change
Page 15 of 17
CY62157ESL MoBL®
Document History Page (continued)
Document Title: CY62157ESL MoBL®, 8-Mbit (512K × 16) Static RAM
Document Number: 001-43141
Rev.
ECN No.
Orig. of
Change
Submission
Date
Description of Change
*G
4576406
VINI
01/16/2015
Updated Functional Description:
Added “For a complete list of related documentation, click here.” at the end.
Updated Switching Characteristics:
Added Note 21 and referred the same note in “Write Cycle”.
Updated Switching Waveforms:
Added Figure 9.
Added Note 31 and referred the same note in Figure 9.
*H
5169392
VINI
03/10/2016
Updated Thermal Resistance:
Replaced “two-layer” with “four-layer” in “Test Conditions” column.
Changed value of θJA parameter from 77 °C/W to 57.92 °C/W.
Changed value of θJC parameter from 13 C/W to 17.44 C/W.
Updated to new template.
Completing Sunset Review.
*I
5963507
AESATMP8
11/10/2017
Updated Cypress Logo and Copyright.
*J
6529321
VINI
04/01/2019
Updated to new template.
Completing Sunset Review.
Document Number: 001-43141 Rev. *J
Page 16 of 17
CY62157ESL MoBL®
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Document Number: 001-43141 Rev. *J
Revised April 1, 2019
Page 17 of 17
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