CY62148E_09

CY62148E MoBL® 4-Mbit (512K x 8) Static RAM Features • Very high speed: 45 ns • Voltage range: 4.5V–5.5V • Pin compatible with CY62148B • Ultra low standby power — Typical standby current: 1 µA — Maximum standby current: 7 µA (Industrial) • Ultra low active power — Typical active current: 2.0 mA @ f = 1 MHz • Easy memory expansion with CE, and OE features • Automatic power down when deselected • CMOS for optimum speed and power • Available in Pb-free 32-pin TSOP II and 32-pin SOIC packages [2] Functional Description [1] The CY62148E is a high performance CMOS static RAM organized as 512K words by 8 bits. This device features advanced circuit design to provide ultra low active current. This is ideal for providing More Battery Life™ (MoBL®) in portable applications such as cellular telephones. The device also has an automatic power down feature that significantly reduces power consumption when addresses are not toggling. Placing the device into standby mode reduces power consumption by more than 99% when deselected (CE HIGH). The eight input and output pins (IO0 through IO7) are placed in a high impedance state when: • Deselected (CE HIGH) • Outputs are disabled (OE HIGH) • Write operation is active (CE LOW and WE LOW) To write to the device, take Chip Enable (CE) and Write Enable (WE) inputs LOW. Data on the eight IO pins (IO0 through IO7) is then written into the location specified on the address pins (A0 through A18). To read from the device, take Chip Enable (CE) and Output Enable (OE) LOW while forcing Write Enable (WE) HIGH. Under these conditions, the contents of the memory location specified by the address pins appear on the IO pins. Product Portfolio Power Dissipation Product Range VCC Range (V) Min CY62148ELL CY62148ELL TSOP II SOIC Ind’l Ind’l/Auto-A 4.5 4.5 Typ [3] 5.0 5.0 Max 5.5 5.5 45 55 Speed (ns) Operating ICC (mA) f = 1MHz Typ [3] 2 2 Max 2.5 2.5 f = fmax Typ [3] 15 15 Max 20 20 Standby ISB2 (µA) Typ [3] 1 1 Max 7 7 Notes 1. For best practice recommendations, refer to the Cypress application note “System Design Guidelines” at http://www.cypress.com. 2. SOIC package is available only in 55 ns speed bin. 3. Typical values are included for reference only and are not guaranteed or tested. Typical values are measured at VCC = VCC(typ), TA = 25°C. Cypress Semiconductor Corporation Document #: 38-05442 Rev. *F • 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600 Revised March 28, 2007 [+] Feedback CY62148E MoBL® Logic Block Diagram A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 CE WE OE INPUT BUFFER ROW DECODER IO0 IO1 SENSE AMPS IO2 IO3 IO4 IO5 IO6 512K x 8 ARRAY COLUMN DECODER POWER DOWN IO7 A13 A14 A15 A16 A17 Pin Configuration [2, 4] 32-pin SOIC/TSOP II Pinout Top View A17 A16 A14 A12 A7 A6 A5 A4 A3 A2 A1 A0 IO0 IO1 IO2 VSS 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 A18 VCC A15 A18 WE A13 A8 A9 A11 OE A10 CE IO7 IO6 IO5 IO4 IO3 Note 4. NC pins are not connected on the die. Document #: 38-05442 Rev. *F Page 2 of 10 [+] Feedback CY62148E MoBL® Maximum Ratings Exceeding maximum ratings may impair the useful life of the device. These user guidelines are not tested. Storage Temperature ................................ –65°C to + 150°C Ambient Temperature with Power Applied............................................ –55°C to + 125°C Supply Voltage to Ground Potential .................................–0.5V to 6.0V (VCCmax + 0.5V) DC Voltage Applied to Outputs in High-Z State [5, 6] ................–0.5V to 6.0V (VCCmax + 0.5V) DC Input Voltage [5, 6] ............ –0.5V to 6.0V (VCCmax + 0.5V) Output Current into Outputs (LOW)............................. 20 mA Static Discharge Voltage........................................... > 2001V (per MIL-STD-883, Method 3015) Latch-up Current ......................................................>200mA Operating Range Device CY62148E Range Ind’l/Auto-A Ambient Temperature –40°C to +85°C VCC [7] 4.5V to 5.5V Electrical Characteristics (Over the Operating Range) Parameter VOH VOL VIH VIL Description Output HIGH Voltage Test Conditions IOH = –1 mA 45 ns Min 2.4 0.4 2.2 –0.5 VCC + 0.5 2.2 0.8 –0.5 –1 –1 15 2 1 +1 +1 20 2.5 7 –1 –1 15 2 1 0.6 [8] +1 +1 20 2.5 7 µA µA µA mA Typ [3] Max 2.4 0.4 VCC + 0.5 55 ns [2] Min Typ [3] Max Unit V V V V Output LOW Voltage IOL = 2.1 mA Input HIGH Voltage VCC = 4.5V to 5.5V Input LOW voltage VCC = 4.5V to 5.5V For TSOPII package For SOIC package IIX IOZ ICC ISB2 [9] Input Leakage Current Output Leakage Current VCC Operating Supply Current GND < VI < VCC GND < VO < VCC, Output Disabled f = fmax = 1/tRC f = 1 MHz VCC = VCC(max) IOUT = 0 mA CMOS levels Automatic CE Power CE > VCC – 0.2V down Current — VIN > VCC – 0.2V or VIN < 0.2V, CMOS Inputs f = 0, VCC = VCC(max) Capacitance (For All Packages) [10] Parameter CIN COUT Description Input Capacitance Output Capacitance Test Conditions TA = 25°C, f = 1 MHz, VCC = VCC(typ) Max 10 10 Unit pF pF Notes 5. VIL(min) = –2.0V for pulse durations less than 20 ns for I < 30 mA. 6. VIH(max) = VCC+0.75V for pulse durations less than 20 ns. 7. Full device AC operation assumes a minimum of 100 µs ramp time from 0 to VCC(min) and 200 µs wait time after VCC stabilization. 8. Under DC conditions the device meets a VIL of 0.8V. However, in dynamic conditions Input LOW Voltage applied to the device must not be higher than 0.6V. This is applicable to SOIC package only. Refer to AN13470 for details. 9. Only chip enable (CE) must be HIGH at CMOS level to meet the ISB2 spec. Other inputs can be left floating. 10. Tested initially and after any design or process changes that may affect these parameters. Document #: 38-05442 Rev. *F Page 3 of 10 [+] Feedback CY62148E MoBL® Thermal Resistance [10] Parameter ΘJA ΘJC Description Thermal Resistance (Junction to Ambient) Thermal Resistance (Junction to Case) Test Conditions Still Air, soldered on a 3 × 4.5 inch, two-layer printed circuit board SOIC Package 75 10 TSOP II Package 77 13 Unit °C/W °C/W AC Test Loads and Waveforms VCC OUTPUT R1 3.0V 30 pF INCLUDING JIG AND SCOPE R2 GND Rise Time = 1 V/ns 10% ALL INPUT PULSES 90% 90% 10% Fall Time = 1 V/ns Equivalent to: THEVENIN EQUIVALENT OUTPUT Parameters R1 R2 RTH VTH 5.0V 1800 990 639 1.77 RTH V Unit Ω Ω Ω V Data Retention Characteristics (Over the Operating Range) Parameter VDR ICCDR tCDR [10] tR [11] Description VCC for Data Retention Data Retention Current Chip Deselect to Data Retention Time Operation Recovery Time Ind’l/Auto-A VCC= VDR, CE > VCC – 0.2V, VIN > VCC – 0.2V or VIN < 0.2V 0 tRC Conditions Min 2 1 7 Typ [3] Max Unit V µA ns ns Data Retention Waveform DATA RETENTION MODE VCC VCC(min) tCDR VDR > 2.0V VCC(min) tR CE Note 11. Full device operation requires linear VCC ramp from VDR to VCC(min) > 100 µs or stable at VCC(min) > 100 µs. Document #: 38-05442 Rev. *F Page 4 of 10 [+] Feedback CY62148E MoBL® Switching Characteristics (Over the Operating Range) [12] Parameter Read Cycle tRC tAA tOHA tACE tDOE tLZOE tHZOE tLZCE tHZCE tPU tPD Write Cycle tWC tSCE tAW tHA tSA tPWE tSD tHD tHZWE tLZWE [15] Description 45 ns Min Max Min 55 ns [2] Max Unit Read Cycle Time Address to Data Valid Data Hold from Address Change CE LOW to Data Valid OE LOW to Data Valid OE LOW to LOW Z [13] OE HIGH to High Z [13, 14] CE LOW to Low Z [13] CE HIGH to High Z [13, 14] CE LOW to Power up CE HIGH to Power down Write Cycle Time CE LOW to Write End Address Setup to Write End Address Hold from Write End Address Setup to Write Start WE Pulse Width Data Setup to Write End Data Hold from Write End WE LOW to High-Z [13, 14] WE HIGH to Low-Z [13] 45 45 10 45 22 5 18 10 18 0 45 55 55 10 55 25 5 20 10 20 0 55 ns ns ns ns ns ns ns ns ns ns ns 45 35 35 0 0 35 25 0 18 10 55 40 40 0 0 40 25 0 20 10 ns ns ns ns ns ns ns ns ns ns Notes 12. Test conditions for all parameters other than tri-state parameters assume signal transition time of 3 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3V, and output loading of the specified IOL/IOH as shown in the “AC Test Loads and Waveforms” on page 4. 13. At any given temperature and voltage condition, tHZCE is less than tLZCE, tHZOE is less than tLZOE, and tHZWE is less than tLZWE for any given device. 14. tHZOE, tHZCE, and tHZWE transitions are measured when the outputs enter a high impedance state. 15. The internal write time of the memory is defined by the overlap of WE, CE = VIL. All signals must be ACTIVE to initiate a write and any of these signals can terminate a write by going INACTIVE. The data input setup and hold timing should be referenced to the edge of the signal that terminates the write. Document #: 38-05442 Rev. *F Page 5 of 10 [+] Feedback CY62148E MoBL® Switching Waveforms Read Cycle No. 1 (Address Transition Controlled) [16, 17] tRC RC ADDRESS tOHA DATA OUT PREVIOUS DATA VALID tAA DATA VALID Read Cycle No. 2 (OE Controlled) [17, 18] ADDRESS tRC CE tACE OE tDOE tLZOE HIGH IMPEDANCE DATA OUT VCC SUPPLY CURRENT tPU 50% tLZCE DATA VALID tPD 50% tHZOE tHZCE HIGH IMPEDANCE ICC ISB Write Cycle No. 1 (WE Controlled, OE HIGH During Write) [19, 20] tWC ADDRESS tSCE CE tAW tSA WE tPWE tHA OE tSD DATA IO NOTE 21 tHZOE Notes: 16. Device is continuously selected. OE, CE = VIL. 17. WE is HIGH for read cycles. 18. Address valid before or similar to CE transition LOW. 19. Data IO is high impedance if OE = VIH. 20. If CE goes HIGH simultaneously with WE HIGH, the output remains in high impedance state. 21. During this period, the IOs are in output state and input signals must not be applied. tHD DATA VALID Document #: 38-05442 Rev. *F Page 6 of 10 [+] Feedback CY62148E MoBL® Switching Waveforms (continued) Write Cycle No. 2 (CE Controlled) [19, 20] tWC ADDRESS tSCE tSA tAW tPWE WE tSD DATA IO DATA VALID tHD tHA CE Write Cycle No. 3 (WE Controlled, OE LOW) [20] tWC ADDRESS tSCE CE tAW tSA WE tSD DATA IO NOTE 21 tHZWE DATA VALID tPWE tHA tHD tLZWE Truth Table CE H L L L WE X H L H OE X L X H High Z Data Out Data In High Z IO’s Read Write Selected, Outputs Disabled Mode Deselect/Power down Power Standby (ISB) Active (ICC) Active (ICC) Active (ICC) Document #: 38-05442 Rev. *F Page 7 of 10 [+] Feedback CY62148E MoBL® Ordering Information Speed (ns) 45 55 55 Ordering Code CY62148ELL-45ZSXI CY62148ELL-55SXI CY62148ELL-55SXA Package Diagram Package Type Operating Range Industrial Industrial Automotive-A 51-85095 32-pin Thin Small Outline Package II (Pb-free) 51-85081 32-pin Small Outline Integrated Circuit (Pb-free) 51-85081 32-pin Small Outline Integrated Circuit (Pb-free) Contact your local Cypress sales representative for availability of these parts. Package Diagrams Figure 1. 32-pin TSOP II, 51-85095 51-85095-** Document #: 38-05442 Rev. *F Page 8 of 10 [+] Feedback CY62148E MoBL® Package Diagrams (continued) Figure 2. 32-pin (450 MIL) Molded SOIC, 51-85081 16 1 0.546[13.868] 0.566[14.376] 0.440[11.176] 0.450[11.430] 17 32 0.793[20.142] 0.817[20.751] 0.006[0.152] 0.012[0.304] 0.101[2.565] 0.111[2.819] 0.118[2.997] MAX. 0.004[0.102] 0.047[1.193] 0.063[1.600] 0.023[0.584] 0.039[0.990] 0.050[1.270] BSC. 0.004[0.102] MIN. 0.014[0.355] 0.020[0.508] SEATING PLANE 51-85081-*B MoBL is a registered trademark, and More Battery Life is a trademark of Cypress Semiconductor. All product and company names mentioned in this document are the trademarks of their respective holders. Document #: 38-05442 Rev. *F Page 9 of 10 © Cypress Semiconductor Corporation, 2006-2007. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. [+] Feedback CY62148E MoBL® Document History Page Document Title: CY62148E MoBL®, 4-Mbit (512K x 8) Static RAM Document Number: 38-05442 REV. ** *A ECN NO. 201580 249276 Issue Date 01/08/04 See ECN Orig. of Change AJU SYT New Data Sheet Changed from Advance Information to Preliminary Moved Product Portfolio to Page 2 Added RTSOP II and Removed FBGA Package Changed VCC stabilization time in footnote #7 from 100 µs to 200 µs Changed ICCDR from 2.0 µA to 2.5 µA Changed typo in Data Retention Characteristics(tR) from 100 µs to tRC ns Changed tOHA from 6 ns to 10 ns for both 35 ns and 45 ns Speed Bin Changed tHZOE, tHZWE from 12 to 15 ns for 35 ns Speed Bin and 15 to 18 ns for 45 ns Speed Bin Changed tSCE from 25 to 30 ns for 35 ns Speed Bin and 40 to 35 ns for 45 ns Speed Bin Changed tHZCE from 12 to18 ns for 35 ns Speed Bin and 15 to 22 ns for 45 ns Speed Bin Changed tSD from 15 to 18 ns for 35 ns Speed Bin and 20 to 22 ns for 45 ns Speed Bin Changed tDOE from 15 to 18 ns for 35 ns Speed Bin Corrected typo in Package Name Changed Ordering Information to include Pb-Free Packages Changed from Preliminary to Final Changed the address of Cypress Semiconductor Corporation on Page #1 from “3901 North First Street” to “198 Champion Court” Removed 35ns Speed Bin Removed “L” version of CY62148E Changed ICC (Typ) value from 1.5 mA to 2 mA at f=1 MHz Changed ICC (Max) value from 2 mA to 2.5 mA at f=1 MHz Changed ICC (Typ) value from 12 mA to 15 mA at f=fmax Removed ISB1 spec from the Electrical characteristics table Changed ISB2 Typ values from 0.7 µA to 1 µA and Max values from 2.5 µA to 7 µA Modified footnote #4 to include current limit Removed redundant footnote on DNU pins Changed the AC testload capacitance from 100 pF to 30 pF on page #4 Changed test load parameters R1, R2, RTH and VTH from 1838 Ω, 994 Ω, 645 Ω and 1.75V to 1800 Ω, 990 Ω, 639 Ω and 1.77V Changed ICCDR from 2.5 µA to 7 µA Added ICCDR typical value Changed tLZOE from 3 ns to 5 ns Changed tLZCE and tLZWE from 6 ns to 10 ns Changed tHZCE from 22 ns to 18 ns Changed tPWE from 30 ns to 35 ns Changed tSD from 22 ns to 25 ns Updated the ordering information table and replaced Package Name column with Package Diagram Included Automotive Range in product offering Updated the Ordering Information Corrected the operating range to 4.5V - 5.5V on page# 3 Added footnote #8 Added VILspec for SOIC package Added Automotive-A part and its related information Removed Automotive-E part and its related information Added footnote #2 related to SOIC package Added footnote #9 related to ISB2 Added AC values for 55 ns Industrial-SOIC range Updated Ordering Information table Description of Change *B 414820 See ECN ZSD *C *D *E *F 464503 485639 833080 890962 See ECN See ECN See ECN See ECN NXR VKN VKN VKN Document #: 38-05442 Rev. *F Page 10 of 10 [+] Feedback