CY62167DV18LL-55BVXIT

CY62167DV18 MoBL® 16-Mbit (1M x 16) Static RAM Features consumption by more than 99% when deselected (CE1 HIGH or CE2 LOW or both BHE and BLE are HIGH). The input and output pins (IO0 through IO15) are placed in a high impedance state when: • Deselected (CE1 HIGH or CE2 LOW) • Outputs are disabled (OE HIGH) • Both Byte High Enable (BHE) and Byte Low Enable (BLE) are disabled (BHE, BLE HIGH) • Write operation is active (CE1 LOW, CE2 HIGH and WE LOW) • Very high speed: 55 ns • Wide voltage range: 1.65V–1.95V • Ultra low active power — Typical active current: 1.5 mA @ f = 1 MHz • • • • • — Typical active current: 15 mA @ f = fmax Ultra low standby power Easy memory expansion with CE1, CE2, and OE features Automatic power down when deselected CMOS for optimum speed and power Available in Pb-free 48-ball VFBGA package Functional Description[1] The CY62167DV18 is a high performance CMOS static RAM organized as 1M words by 16 bits. This device features advanced circuit design to provide ultra low active current. This is ideal for providing More Battery Life™ (MoBL®) in portable applications such as cellular telephones. The device also has an automatic power down feature that significantly reduces power consumption by 99% when addresses are not toggling. Placing the device into standby mode reduces power To write to the device, take Chip Enables (CE1 LOW and CE2 HIGH) and Write Enable (WE) input LOW. If BLE is LOW, then data from IO pins (IO0 through IO7) is written into the location specified on the address pins (A0 through A19). If BHE is LOW then data from IO pins (IO8 through IO15) is written into the location specified on the address pins (A0 through A19). To read from the device, take Chip Enables (CE1 LOW and CE2 HIGH) and OE LOW while forcing the WE HIGH. If BLE is LOW, then data from the memory location specified by the address pins appear on IO0 to IO7. If BHE is LOW, then data from memory appears on IO8 to IO15. See the “Truth Table” on page 9 for a complete description of read and write modes. Logic Block Diagram 1M × 16 RAM Array SENSE AMPS A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 ROW DECODER DATA IN DRIVERS IO0–IO7 IO8–IO15 COLUMN DECODER BYTE A11 A12 A13 A14 A15 A16 A17 A18 A19 BHE WE Power Down Circuit OE BLE CE2 CE1 BHE BLE CE2 CE1 Note 1. For best practice recommendations, refer to the Cypress application note “System Design Guidelines” at http://www.cypress.com. Cypress Semiconductor Corporation Document #: 38-05326 Rev. *C • 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600 Revised April 25, 2007 [+] Feedback CY62167DV18 MoBL® Product Portfolio Power Dissipation VCC Range (V) Product CY62167DV18LL Operating ICC (mA) Speed (ns) Min Typ[2] Max 1.65 1.8 1.95 f = 1MHz 55 f = fmax Standby ISB2 (µA) Typ[2] Max Typ[2] Max Typ[2] Max 1.5 5 15 30 2.5 20 Pin Configuration [3] 48-Ball VFBGA Top View 1 2 3 4 5 6 BLE OE A0 A1 A2 CE2 A IO8 BHE A3 A4 CE1 IO0 B IO9 IO10 A5 A6 IO1 IO2 C VSS IO11 A17 A7 IO3 VCC D VCC IO12 DNU A16 IO4 VSS E IO14 IO13 A14 A15 IO5 IO6 F IO15 A19 A12 A13 WE IO7 G A18 A8 A9 A10 A11 DNU H Notes 2. Typical values are included for reference only and are not guaranteed or tested. Typical values are measured at VCC = VCC(typ), TA = 25°C. 3. DNU pins must be left floating or tied to VSS to ensure proper operation. Document #: 38-05326 Rev. *C Page 2 of 11 [+] Feedback CY62167DV18 MoBL® DC Input Voltage[4, 5] ........................–0.2V to VCCmax + 0.2V Maximum Ratings Exceeding the maximum ratings may impair the useful life of the device. These user guidelines are not tested. Storage Temperature ................................. –65°C to +150°C Output Current into Outputs (LOW)............................. 20 mA Static Discharge Voltage.......................................... > 2001V (MIL-STD-883, Method 3015) Latch up Current..................................................... > 200 mA Ambient Temperature with Power Applied............................................. –55°C to +125°C Operating Range Supply Voltage to Ground Potential . –0.2V to VCCmax + 0.2V DC Voltage Applied to Outputs in High-Z State[4, 5] ........................... –0.2V to VCCmax + 0.2V Range Ambient Temperature VCC[6] Industrial –40°C to +85°C 1.65V to 1.95V DC Electrical Characteristics (Over the Operating Range) 55 ns Parameter Description Test Conditions VOH Output HIGH Voltage IOH = −0.1 mA VOL Output LOW Voltage IOL = 0.1 mA VIH Input HIGH Voltage VIL Input LOW Voltage IIX Input Leakage Current IOZ ICC Min Typ[2] Max 1.4 Unit V 0.2 V 1.4 VCC + 0.2 V –0.2 0.4 V GND < VI < VCC –1 +1 µA Output Leakage Current GND < VO < VCC, Output Disabled –1 +1 µA VCC Operating Supply Current f = fMAX = 1/tRC 15 30 mA 1.5 5 f = 1 MHz VCC = 1.95V, IOUT = 0 mA, CMOS level ISB1 Automatic CE Power down Current − CMOS Inputs CE1 > VCC − 0.2V, CE2 < 0.2V, VIN > VCC − 0.2V, VIN < 0.2V, f = fMAX (Address and Data Only), f = 0 (OE, WE, BHE and BLE) 2.5 20 µA ISB2 Automatic CE Power down Current − CMOS Inputs CE1 > VCC − 0.2V, CE2 < 0.2V, VIN > VCC − 0.2V or VIN < 0.2V, f = 0, VCC=1.95V 2.5 20 µA Capacitance [7] Parameter Description CIN Input Capacitance COUT Output Capacitance Test Conditions TA = 25°C, f = 1 MHz, VCC = VCC(typ) Max Unit 6 pF 8 pF Notes 4. VIL(min) = –2.0V for pulse durations less than 20 ns. 5. VIH(max) = VCC + 0.75V for pulse durations less than 20 ns. 6. Full device AC operation requires linear VCC ramp from 0 to VCC(min) and VCC must be stable at VCC(min) for 500 µs. 7. Tested initially and after any design or process changes that may affect these parameters. Document #: 38-05326 Rev. *C Page 3 of 11 [+] Feedback CY62167DV18 MoBL® Thermal Resistance [7] Parameter Description ΘJA Thermal Resistance (Junction to Ambient) ΘJC Thermal Resistance (Junction to Case) Test Conditions VFBGA Unit 55 °C/W 16 °C/W Still Air, soldered on a 3 × 4.5 inch, two-layer printed circuit board AC Test Loads and Waveforms R1 VCC OUTPUT ALL INPUT PULSES VCC 10% GND Rise Time = 1 V/ns R2 30 pF INCLUDING JIG AND SCOPE 90% 90% 10% Fall Time = 1 V/ns Equivalent to: THEVENIN EQUIVALENT RTH OUTPUT V Parameters 1.8V Unit R1 13500 Ω R2 10800 Ω RTH 6000 Ω VTH 0.80 V Data Retention Characteristics (Over the Operating Range) Parameter Description Conditions VCC for Data Retention VDR Min Typ [2] Max 1.0 1.95 V 10 µA VCC= 1.0V, CE > V – 0.2V, CE < 0.2V, 1 CC 2 VIN > VCC – 0.2V or VIN < 0.2V ICCDR Data Retention Current tCDR[7] Chip Deselect to Data Retention Time tR[8] Operation Recovery Time Unit 0 ns tRC ns Data Retention Waveform[9] VCC CE1 or VCC, min tCDR DATA RETENTION MODE VDR > 1.0V VCC, min tR BHE,BLE or CE2 Notes 8. Full device operation requires linear VCC ramp from VDR to VCC(min) > 100 µs or stable at VCC(min) > 100 µs. 9. BHE.BLE is the AND of both BHE and BLE. Deselect the chip by either disabling the chip enable signals or by disabling both BHE and BLE. Document #: 38-05326 Rev. *C Page 4 of 11 [+] Feedback CY62167DV18 MoBL® Switching Characteristics (Over the Operating Range)[10] Parameter 55 ns Description Min Max Unit Read Cycle tRC Read Cycle Time tAA Address to Data Valid tOHA Data Hold from Address Change tACE CE1 LOW and CE2 HIGH to Data Valid 55 ns tDOE OE LOW to Data Valid 25 ns tLZOE OE LOW to LOW Z[11] 55 OE HIGH to High Z tHZOE 55 10 [11] tLZCE CE1 LOW and CE2 HIGH to Low Z CE1 HIGH and CE2 LOW to High Z[11, 12] tPU CE1 LOW and CE2 HIGH to Power up tPD CE1 HIGH and CE2 LOW to Power down tDBE BLE/BHE LOW to Data Valid tLZBE BLE/BHE LOW to Low Z[11] BLE/BHE HIGH to HIGH Write Cycle ns 20 ns 20 ns 10 ns 0 ns 55 ns 55 ns 5 Z[11, 12] ns ns 5 [11, 12] tHZCE tHZBE ns ns 20 ns [13] tWC Write Cycle Time 55 ns tSCE CE1 LOW and CE2 HIGH to Write End 40 ns tAW Address Setup to Write End 40 ns tHA Address Hold from Write End 0 ns tSA Address Setup to Write Start 0 ns tPWE WE Pulse Width 40 ns tBW BLE/BHE LOW to Write End 45 ns tSD Data Setup to Write End 25 ns tHD Data Hold from Write End 0 tHZWE WE LOW to High- [11, 12] tLZWE [11] WE HIGH to Low-Z ns 20 10 ns ns Notes 10. Test conditions for all parameters other than tri-state parameters assume signal transition time of 1 ns/V, timing reference levels of VCC(typ)/2, input pulse levels of 0 to VCC(typ), and output loading of the specified IOL/IOH as shown in “AC Test Loads and Waveforms” on page 4. 11. At any given temperature and voltage condition, tHZCE is less than tLZCE, tHZBE is less than tLZBE, tHZOE is less than tLZOE, and tHZWE is less than tLZWE for any given device. 12. tHZOE, tHZCE, tHZBE, and tHZWE transitions are measured when the outputs enter a high impedance state. 13. The internal write time of the memory is defined by the overlap of WE, CE1 = VIL, BHE, BLE or both = VIL, and CE2 = VIH. All signals must be ACTIVE to initiate a write and any of these signals can terminate a write by going INACTIVE. The data input setup and hold timing must be referenced to the edge of the signal that terminates the write. Document #: 38-05326 Rev. *C Page 5 of 11 [+] Feedback CY62167DV18 MoBL® Switching Waveforms Read Cycle 1 (Address Transition Controlled)[14, 15] tRC RC ADDRESS tOHA DATA OUT tAA PREVIOUS DATA VALID DATA VALID Read Cycle 2 (OE Controlled)[15, 16] ADDRESS tRC CE1 tPD tHZCE CE2 tACE BHE/BLE tDBE tHZBE tLZBE OE tHZOE tDOE DATA OUT tLZOE HIGH IMPEDANCE HIGH IMPEDANCE DATA VALID tLZCE VCC SUPPLY CURRENT tPU 50% 50% ICC ISB Notes 14. The device is continuously selected. OE, CE1 = VIL, BHE and/or BLE = VIL, and CE2 = VIH. 15. WE is HIGH for read cycle. 16. Address valid before or similar to CE1, BHE, BLE transition LOW and CE2 transition HIGH. Document #: 38-05326 Rev. *C Page 6 of 11 [+] Feedback CY62167DV18 MoBL® Switching Waveforms (continued) Write Cycle 1 (WE Controlled)[13, 17, 18] tWC ADDRESS tSCE CE1 CE2 tAW tHA tSA WE tPWE tBW BHE/BLE OE tHD tSD DATA IO NOTE 19 VALID DATA tHZOE Write Cycle 2 (CE1 or CE2 Controlled)[13, 17, 18] tWC ADDRESS tSCE CE1 CE2 tSA tAW tHA tPWE WE tBW BHE/BLE OE tSD DATA IO NOTE 19 tHD VALID DATA tHZOE Notes 17. Data IO is high impedance if OE = VIH. 18. If CE1 goes HIGH and CE2 goes LOW simultaneously with WE = VIH, the output remains in a high impedance state. 19. During this period, the IOs are in output state. Do not apply input signals. Document #: 38-05326 Rev. *C Page 7 of 11 [+] Feedback CY62167DV18 MoBL® Switching Waveforms (continued) Write Cycle 3 (WE Controlled, OE LOW)[18] tWC ADDRESS tSCE CE1 CE2 tBW BHE/BLE tAW tHA tSA tPWE WE tSD DATA IO NOTE 19 tHD VALID DATA tLZWE tHZWE Write Cycle 4 (BHE/BLE Controlled, OE LOW)[18] tWC ADDRESS CE1 CE2 tSCE tAW tHA tBW BHE/BLE tSA tPWE WE tSD DATA IO NOTE 19 Document #: 38-05326 Rev. *C tHD VALID DATA Page 8 of 11 [+] Feedback CY62167DV18 MoBL® Truth Table CE1 CE2 WE OE BHE BLE H X X X X X X L X X X X X X X L H H L H L Inputs/Outputs Mode Power High Z Deselect/Power Down Standby (ISB) X High Z Deselect/Power Down Standby (ISB) H H High Z Deselect/Power Down Standby (ISB) L L L Data Out (IO0–IO15) Read Active (ICC) H L H L High Z (IO8–IO15); Data Out (IO0–IO7) Read Active (ICC) H H L L H Data Out (IO8–IO15); High Z (IO0–IO7) Read Active (ICC) L H L X L L Data In (IO0–IO15) Write Active (ICC) L H L X H L High Z (IO8–IO15); Data In (IO0–IO7) Write Active (ICC) L H L X L H Data In (IO8–IO15); High Z (IO0–IO7) Write Active (ICC) L H H H L H High Z Output Disabled Active (ICC) L H H H H L High Z Output Disabled Active (ICC) L H H H L L High Z Output Disabled Active (ICC) Ordering Information Speed (ns) Ordering Code 55 CY62167DV18LL-55BVXI Document #: 38-05326 Rev. *C Package Diagram Package Type 51-85178 48-ball Fine Pitch BGA (8 x 9.5 x 1 mm) (Pb-free) Operating Range Industrial Page 9 of 11 [+] Feedback CY62167DV18 MoBL® Package Diagrams Figure 1. 48-Ball VFBGA (8 x 9.5 x 1 mm), 51-85178 BOTTOM VIEW TOP VIEW A1 CORNER Ø0.05 M C Ø0.25 M C A B A1 CORNER Ø0.30±0.05(48X) 2 3 4 5 6 6 5 4 3 2 1 C C E F G D E 2.625 D 0.75 A B 5.25 A B 9.50±0.10 9.50±0.10 1 F G H H A 1.875 A B 0.75 8.00±0.10 0.55 MAX. B 0.10 C 0.21±0.05 0.25 C 3.75 8.00±0.10 0.15(4X) 1.00 MAX 0.26 MAX. SEATING PLANE C 51-85178-** MoBL is a registered trademark, and More Battery Life is a trademark of Cypress Semiconductor. All product and company names mentioned in this document are the trademarks of their respective holders. Document #: 38-05326 Rev. *C Page 10 of 11 © Cypress Semiconductor Corporation, 2002-2007. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. [+] Feedback CY62167DV18 MoBL® Document History Page Document Title: CY62167DV18 MoBL®, 16-Mbit (1M x 16) Static RAM Document Number: 38-05326 REV. ECN NO. Issue Date Orig. of Change Description of Change ** 118406 09/30/02 GUG New Data Sheet *A 123690 02/11/03 DPM Changed Advance to Preliminary Added package diagram *B 126554 04/25/03 DPM Minor Change: Changed sunset owner from DPM to HRT *C 1015643 See ECN VKN Converted from preliminary to final Removed “L” parts Removed 70 ns speed bin Updated footnote #3 Updated Ordering Information table Document #: 38-05326 Rev. *C Page 11 of 11 [+] Feedback