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Continuity of document content
The fact that Infineon offers the following product as part of the Infineon product
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CY62177ESL MoBL®
32-Mbit (2M × 16/4M × 8) Static RAM
32-Mbit (2M × 16/4M × 8) Static RAM
Features
Functional Description
■
Thin small outline package I (TSOP I) configurable as
2M × 16 or as 4M × 8 static RAM (SRAM)
■
High-speed up to 55 ns
■
Wide voltage range: 2.2 V to 3.6 V and 4.5 V to 5.5 V
■
Ultra low standby power
❐ Typical standby current: 3 µA
❐ Maximum standby current: 25 µA
■
Ultra low active power
❐ Typical active current: 4.5 mA at f = 1 MHz
■
Easy memory expansion with CE1, CE2, and OE Features
■
Automatic power-down when deselected
■
Complementary metal oxide semiconductor (CMOS) for
optimum speed and power
■
Available in Pb-free 48-ball TSOP I package
The CY62177ESL is a high performance CMOS static RAM
organized as 2M words by 16 bits and 4M words by 8 bits. This
device features advanced circuit design to provide ultra low
active current. It is ideal for providing More Battery Life
(MoBL®) in portable applications such as cellular telephones.
The device also has an automatic power-down feature that
significantly reduces power consumption by 99 percent when
addresses are not toggling. The device can also be put into
standby mode when deselected (CE1 HIGH or CE2 LOW or both
BHE and BLE are HIGH). The input and output pins (I/O0 through
I/O15) are placed in a high impedance state when: deselected
(CE1HIGH or CE2 LOW), outputs are disabled (OE HIGH), both
Byte High Enable and Byte Low Enable are disabled (BHE, BLE
HIGH), or during a write operation (CE1 LOW, CE2 HIGH and WE
LOW).
To write to the device, take Chip Enables (CE1 LOW and CE2
HIGH) and Write Enable (WE) input LOW. If Byte Low Enable
(BLE) is LOW, then data from I/O pins (I/O0 through I/O7), is
written into the location specified on the address pins (A0 through
A20). If Byte High Enable (BHE) is LOW, then data from I/O pins
(I/O8 through I/O15) is written to the location specified on the
address pins (A0 through A20). To read from the device, take
Chip Enables (CE1 LOW and CE2 HIGH) and Output Enable
(OE) LOW while forcing the Write Enable (WE) HIGH. If Byte
Low Enable (BLE) is LOW, then data from the memory location
specified by the address pins appear on I/O0 to I/O7. If Byte High
Enable (BHE) is LOW, then data from memory appears on I/O8
to I/O15. See the Truth Table on page 11 for a complete
description of read and write modes.
For a complete list of related documentation, click here.
Logic Block Diagram
2M × 16
RAM Array
SENSE AMPS
ROW DECODER
DATA IN DRIVERS
A10
A9
A8
A7
A6
A5
A4
A3
A2
A1
A0
I/O0–I/O7
I/O8–I/O15
COLUMN DECODER
BYTE
A11
A12
A13
A14
A15
A16
A17
A18
A19
A20
BHE
WE
CE2
CE1
OE
BLE
Power-down
Circuit
Cypress Semiconductor Corporation
Document Number: 001-64709 Rev. *F
•
198 Champion Court
BHE
BLE
•
CE2
CE1
San Jose, CA 95134-1709
• 408-943-2600
Revised November 13, 2018
CY62177ESL MoBL®
Contents
Pin Configuration ............................................................... 3
Product Portfolio ................................................................ 3
Maximum Ratings ............................................................... 4
Operating Range ................................................................. 4
Electrical Characteristics ................................................... 4
Capacitance ........................................................................ 5
Thermal Resistance ............................................................ 5
AC Test Loads and Waveforms ......................................... 5
Data Retention Characteristics ......................................... 6
Data Retention Waveform .................................................. 6
Switching Characteristics .................................................. 7
Switching Waveforms ........................................................ 8
Truth Table ........................................................................ 11
Document Number: 001-64709 Rev. *F
Ordering Information ....................................................... 12
Ordering Code Definitions ........................................... 12
Package Diagrams ........................................................... 13
Acronyms .......................................................................... 14
Document Conventions ................................................... 14
Units of Measure ......................................................... 14
Document History Page ................................................... 15
Sales, Solutions, and Legal Information ........................ 16
Worldwide Sales and Design Support ......................... 16
Products ...................................................................... 16
PSoC® Solutions ........................................................ 16
Cypress Developer Community .................................. 16
Technical Support ....................................................... 16
Page 2 of 16
CY62177ESL MoBL®
Pin Configuration
Figure 1. 48-pin TSOP I pinout (Front View) [1, 2]
A15
A14
A13
A12
A11
A10
A9
A8
A19
A20
WE
CE2
NC
DNU
BHE
BLE
A18
A17
A7
A6
A5
A4
A3
A2
A1
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
A16
BYTE
Vss
I/O15/A21
I/O7
I/O14
I/O6
I/O13
I/O5
I/O12
I/O4
Vcc
I/O11
I/O3
I/O10
I/O2
I/O9
I/O1
I/O8
I/O0
OE
Vss
CE1
A0
Product Portfolio
Product
CY62177ESL
VCC Range
(V)[3]
2.2 V to 3.6 V and 4.5 V to 5.5 V
Speed
(ns)
55
Power Dissipation
Operating ICC (mA)
f = 1 MHz
Standby ISB2 (µA)
f = fMax
Typ[4]
Max
Typ[4]
Max
Typ[4]
Max
4.5
5.5
35
45
3
25
Notes
1. NC pins are not connected on the die.
2. The BYTE pin in the 48-pin TSOP-I package has to be tied to VCC to use the device as a 2M × 16 SRAM. The 48-pin TSOP I package can also be used as a 4M × 8
SRAM by tying the BYTE signal to VSS. In the 4M × 8 configuration, Pin 45 is A21, while BHE, BLE, and I/O8 to I/O14 pins are not used.
3. Datasheet Specifications are not guaranteed in the range of 3.6 V to 4.5 V.
4. Typical values are included for reference only and are not guaranteed or tested. Typical values are measured at VCC = 3 V, and VCC = 5 V, TA = 25 °C.
Document Number: 001-64709 Rev. *F
Page 3 of 16
CY62177ESL MoBL®
Maximum Ratings
Output current into outputs (LOW) ............................. 20 mA
Exceeding maximum ratings may shorten the useful life of the
device. User guidelines are not tested.
Storage temperature ............................... –65 °C to + 150 °C
Ambient temperature
with power applied .................................. –55 °C to + 125 °C
Supply voltage
to ground potential ....................... –0.3 V to VCC(max) + 0.3 V
DC voltage applied to outputs
in high Z state [5, 6] ....................... –0.3 V to VCC(max) + 0.3 V
Static discharge voltage
(per MIL-STD-883, method 3015) ......................... 2001 V
Latch-up current 200 mA
Operating Range
Device
CY62177ESL
Range
Industrial
Ambient
Temperature
VCC[7]
–40 °C to +85 °C 2.2 V to 3.6 V
and
4.5 V to 5.5 V
DC input voltage [5, 6] ................... –0.3 V to VCC(max) + 0.3 V
Electrical Characteristics
Over the operating range
Parameter
VOH
VOL
Description
Output HIGH voltage
Output LOW voltage
Test Conditions
VIL
Input HIGH voltage
Input LOW voltage
Unit
Min
Typ [8]
Max
2.2 V VCC 2.7 V IOH = –0.1 mA
2.7 V VCC 3.6 V IOH = –1.0 mA
2.0
–
–
V
2.4
–
–
V
4.5 V VCC 5.5 V IOH = –1.0 mA
2.2 V VCC 2.7 V IOL = 0.1 mA
2.4
–
–
V
–
–
0.4
V
–
–
0.4
V
2.7 V VCC 3.6 V IOL = 2.1 mA
4.5 V VCC 5.5 V IOL = 2.1 mA
VIH
55 ns
–
–
0.4
V
2.2 V VCC 2.7 V
1.8
–
VCC + 0.3 V
V
2.7 V VCC 3.6 V
2.2
–
VCC + 0.3 V
V
4.5 V VCC 5.5 V
2.2
–
VCC + 0.3 V
V
2.2 V VCC 2.7 V
–0.3
–
0.6
V
2.7 V VCC 3.6 V
–0.3
–
0.7[9]
V
–0.3
–
0.7[9]
V
–1
–
+1
A
4.5 V VCC 5.5 V
IIX
Input leakage current
GND VI VCC
IOZ
Output leakage current
GND VO VCC, Output disabled
–1
–
+1
A
ICC
VCC operating supply current
f = fMax = 1/tRC
–
35
45
mA
–
4.5
5.5
mA
–
3
25
A
f = 1 MHz
ISB2 [10]
Automatic power-down
current — CMOS inputs
VCC = VCC(max)
IOUT = 0 mA
CMOS levels
CE1 VCC – 0.2 V or CE2 0.2 V or
(BHE and BLE) VCC – 0.2 V,
VIN VCC – 0.2 V or VIN 0.2 V,
f = 0, VCC = 3.6 V
Notes
5. VIL(min) = –2.0 V for pulse durations less than 20 ns.
6. VIH(max) = VCC + 0.75 V for pulse durations less than 20 ns.
7. Full Device AC operation assumes a 100 s ramp time from 0 to VCC (min) and 200 s wait time after VCC stabilization.
8. Typical values are included for reference only and are not guaranteed or tested. Typical values are measured at VCC = 3 V, and VCC = 5 V, TA = 25 °C
9. Under DC conditions the device meets a VIL of 0.8 V. However, in dynamic conditions Input LOW voltage applied to the device must not be higher than 0.7 V.
10. Chip enables (CE1 and CE2), byte enables (BHE and BLE) and BYTE must be tied to CMOS levels to meet the ISB2/ICCDR spec. Other inputs can be left floating.
Document Number: 001-64709 Rev. *F
Page 4 of 16
CY62177ESL MoBL®
Capacitance
Parameter [11]
Description
CIN
Input capacitance
COUT
Output capacitance
Test Conditions
Max
Unit
15
pF
15
pF
Test Conditions
TSOP I
Unit
Still air, soldered on a 3 × 4.5 inch, four-layer printed circuit
board
55.91
C/W
9.39
C/W
TA = 25 °C, f = 1 MHz, VCC = VCC(typ)
Thermal Resistance
Parameter [11]
Description
JA
Thermal resistance
(junction to ambient)
JC
Thermal resistance
(junction to case)
AC Test Loads and Waveforms
R1
VCC
Output
30 pF
Figure 2. AC Test Loads and Waveforms
All Input Pulses
VCC
90%
10%
GND
R2
Rise Time = 1 V/ns
Including
JIG and
scope
90%
10%
Fall Time = 1 V/ns
Equivalent to: THEVENIN EQUIVALENT
RTH
Output
V
Table 1. AC Test Loads
Parameter
2.5 V
3.0 V
5.0 V
Unit
R1
16667
1103
1800
R2
15385
1554
990
RTH
8000
645
639
VTH
1.20
1.75
1.77
V
Note
11. Tested initially and after any design or process changes that may effect these parameters.
Document Number: 001-64709 Rev. *F
Page 5 of 16
CY62177ESL MoBL®
Data Retention Characteristics
Over the operating range
Parameter
VDR
Description
Conditions
VCC for data retention
ICCDR
[13]
Data retention current
VCC = 1.5 V,
Min
Typ [12]
Max
Unit
1.5
–
–
V
–
–
17
A
CE1 VCC – 0.2 V or CE2 0.2 V
or
(BHE and BLE) VCC – 0.2 V,
VIN VCC – 0.2 V or VIN 0.2 V
tCDR[14]
Chip deselect to data retention
time
–
0
–
–
ns
tR[15]
Operation recovery time
–
55
–
–
ns
Data Retention Waveform
Figure 3. Data Retention Waveform [16]
VCC
VCC(min)
tCDR
Data Retention Mode
VDR 1.5 V
VCC(min)
tR
CE1 or
BHE.BLE
CE2
or
Notes
12. Typical values are included only for reference and are not guaranteed or tested. Typical values are measured at VCC = 3 V, and VCC = 5 V, TA = 25 °C.
13. Chip enables (CE1 and CE2), byte enables (BHE and BLE) and BYTE must be tied to CMOS levels to meet the ISB2/ICCDR spec. Other inputs can be left floating.
14. Tested initially and after any design or process changes that may affect these parameters.
15. Full device operation requires linear VCC ramp from VDR to VCC(min) 100 s or stable at VCC(min) 100 s.
16. BHE.BLE is the AND of both BHE and BLE. Chip is deselected by either disabling the chip enable signals or by disabling both BHE and BLE.
Document Number: 001-64709 Rev. *F
Page 6 of 16
CY62177ESL MoBL®
Switching Characteristics
Over the operating range
Parameter [17, 18]
Description
55 ns
Min
Max
Unit
Read Cycle
tRC
Read cycle time
55
–
ns
tAA
Address to data valid
–
55
ns
tOHA
Data hold from address change
6
–
ns
tACE
CE1 LOW and CE2 HIGH to data valid
–
55
ns
tDOE
OE LOW to data valid
–
25
ns
5
–
ns
–
18
ns
10
–
ns
–
18
ns
[19]
tLZOE
OE LOW to low Z
tHZOE
OE HIGH to high Z[19, 20]
tLZCE
CE1 LOW and CE2 HIGH to low
Z[19]
Z[19, 20]
tHZCE
CE1 HIGH and CE2 LOW to high
tPU
CE1 LOW and CE2 HIGH to power-up
0
–
ns
tPD
CE1 HIGH and CE2 LOW to power-down
–
55
ns
tDBE
BLE/BHE LOW to data valid
–
55
ns
10
–
ns
–
18
ns
tLZBE
tHZBE
BLE/BHE LOW to low Z
[19]
BLE/BHE HIGH to high Z
[19, 20]
Write Cycle[21]
tWC
Write cycle time
55
–
ns
tSCE
CE1 LOW and CE2 HIGH to write end
40
–
ns
tAW
Address setup to write end
40
–
ns
tHA
Address hold from write end
0
–
ns
tSA
Address setup to write start
0
–
ns
tPWE
WE pulse width
40
–
ns
tBW
BLE/BHE LOW to write end
40
–
ns
tSD
Data setup to write end
25
–
ns
tHD
Data hold from write end
0
–
ns
WE LOW to high
Z[19, 20]
–
20
ns
WE HIGH to low
Z[19]
10
–
ns
tHZWE
tLZWE
Notes
17. In an earlier revision of this device, under a specific application condition, READ and WRITE operations were limited to switching of the byte enable and/or chip enable
signals as described in the Application Note AN66311. However, the issue has been fixed and in production now, and hence, this Application Note is no longer applicable.
It is available for download on our website as it contains information on the date code of the parts, beyond which the fix has been in production.
18. Test conditions for all parameters other than tristate parameters assume signal transition time of 1 V/ns, timing reference levels of VCC(typ)/2, input pulse levels of 0 to
VCC(typ), and output loading of the specified IOL/IOH as shown in Figure 2 on page 5.
19. At any temperature and voltage condition, tHZCE is less than tLZCE, tHZBE is less than tLZBE, tHZOE is less than tLZOE, and tHZWE is less than tLZWE for any device.
20. tHZOE, tHZCE, tHZBE, and tHZWE transitions are measured when the outputs enter a high impedence state.
21. The internal Write time of the memory is defined by the overlap of WE, CE1 = VIL, BHE and/or BLE = VIL, and CE2 = VIH. All signals must be ACTIVE to initiate a write
and any of these signals can terminate a write by going INACTIVE. The data input setup and hold timing should be referenced to the edge of the signal that terminates
the write.
Document Number: 001-64709 Rev. *F
Page 7 of 16
CY62177ESL MoBL®
Switching Waveforms
Figure 4. Read Cycle No. 1 (Address Transition Controlled) [22, 23]
tRC
Address
tOHA
Data Out
tAA
Previous Data Valid
Data Valid
Figure 5. Read Cycle No. 2 (OE Controlled) [23, 24]
Address
tRC
CE1
tPD
CE2
tHZCE
tACE
BHE/BLE
tDBE
tLZBE
tHZBE
OE
Data Out
VCC
Supply
Current
tLZOE
High Impedance
tPU
tHZOE
tDOE
High
Impedance
Data Valid
tLZCE
50%
50%
ICC
ISB
Notes
22. The device is continuously selected. OE, CE1 = VIL, BHE and/or BLE = VIL, and CE2 = VIH.
23. WE is HIGH for read cycle.
24. Address valid prior to or coincident with CE1, BHE, BLE transition LOW and CE2 transition HIGH.
Document Number: 001-64709 Rev. *F
Page 8 of 16
CY62177ESL MoBL®
Switching Waveforms (continued)
Figure 6. Write Cycle No. 1 (WE Controlled) [25, 26, 27]
tWC
Address
tSCE
CE1
CE2
tAW
tSA
tHA
tPWE
WE
tBW
BHE/BLE
OE
tSD
Data
I/O
tHD
Valid Data
NOTE 28
tHZOE
Figure 7. Write Cycle No. 2 (CE1 or CE2 Controlled) [25, 26, 27]
tWC
Address
tSCE
CE1
CE2
tSA
tAW
tHA
tPWE
WE
tBW
BHE/BLE
OE
tSD
Data I/O
tHD
Valid Data
NOTE 28
tHZOE
Notes
25. The internal Write time of the memory is defined by the overlap of WE, CE1 = VIL, BHE and/or BLE = VIL, and CE2 = VIH. All signals must be ACTIVE to initiate a write
and any of these signals can terminate a write by going INACTIVE. The data input setup and hold timing should be referenced to the edge of the signal that terminates
the write.
26. Data I/O is high impedance if OE = VIH.
27. If CE1 goes HIGH and CE2 goes LOW simultaneously with WE = VIH, the output remains in a high impedance state.
28. During this period the I/Os are in output state and input signals should not be applied.
Document Number: 001-64709 Rev. *F
Page 9 of 16
CY62177ESL MoBL®
Switching Waveforms (continued)
Figure 8. Write Cycle No. 3 (WE Controlled, OE LOW) [29]
tWC
Address
tSCE
CE1
CE2
tBW
BHE/BLE
tAW
tSA
WE
tHA
tPWE
tSD
Data I/O
NOTE 30
tHD
Valid Data
tLZWE
tHZWE
Figure 9. Write Cycle No. 4 (BHE/BLE Controlled, OE LOW) [29]
tWC
Address
CE1
CE2
tSCE
tAW
tHA
tBW
BHE/BLE
tSA
WE
tPWE
tSD
Data I/O
NOTE 30
tHD
Valid Data
Notes
29. If CE1 goes HIGH and CE2 goes LOW simultaneously with WE = VIH, the output remains in a high impedance state.
30. During this period the I/Os are in output state and input signals should not be applied.
Document Number: 001-64709 Rev. *F
Page 10 of 16
CY62177ESL MoBL®
Truth Table
CE1
CE2
H
X[31]
X[31]
WE
X
OE
X
BHE
BLE
[31]
[31]
[31]
X
[31]
Power
High Z
Deselect/Power-down
Standby (ISB)
High Z
Deselect/Power-down
Standby (ISB)
Deselect/Power-down
Standby (ISB)
L
X
X
X
X
H
H
High Z
L
H
H
L
L
L
Data out (I/O0–I/O15)
Read
Active (ICC)
L
H
H
L
H
L
High Z (I/O8–I/O15);
Data out (I/O0–I/O7)
Read
Active (ICC)
L
H
H
L
L
H
Data out (I/O8–I/O15);
High Z (I/O0–I/O7)
Read
Active (ICC)
L
H
L
X
L
L
Data in (I/O0–I/O15)
Write
Active (ICC)
L
H
L
X
H
L
High Z (I/O8–I/O15);
Data in (I/O0–I/O7)
Write
Active (ICC)
L
H
L
X
L
H
Data in (I/O8–I/O15);
High Z (I/O0–I/O7)
Write
Active (ICC)
L
H
H
H
L
H
High Z
Output disabled
Active (ICC)
L
H
H
H
H
L
High Z
Output disabled
Active (ICC)
L
H
H
H
L
L
High Z
Output disabled
Active (ICC)
X
X
X
Mode
[31]
[31]
X
X
Inputs Outputs
Note
31. The ‘X’ (Don’t care) state for the chip enables and byte enables in the truth table refer to the logic state (either HIGH or LOW). Intermediate voltage levels on these
pins is not permitted.
Document Number: 001-64709 Rev. *F
Page 11 of 16
CY62177ESL MoBL®
Ordering Information
Table 2 lists the CY62177ESL MoBL® key package features and ordering codes. The table contains only the parts that are currently
available. If you do not see what you are looking for, contact your local sales representative. For more information, visit the Cypress
website at www.cypress.com and refer to the product summary page at http://www.cypress.com/products.
Table 2. Key Features and Ordering Information
Speed
(ns)
55
Package
Diagram
Ordering Code
CY62177ESL-55ZXI
Package Type
51-85183
48-pin TSOP-I (12 × 18.4 × 1 mm) Pb-free
Operating
Range
Industrial
Ordering Code Definitions
CY 621 7
7
E
SL
55
ZX
I
Temperature grades:
I = Industrial
Package type:
TSOP I (Pb-free)
Speed grade
Wide voltage range (3 V and 5 V)
Process Technology: 90 nm
Bus Width: x16
Density: 32 Mbit
Family: MoBL SRAM
Company ID: CY = Cypress
Document Number: 001-64709 Rev. *F
Page 12 of 16
CY62177ESL MoBL®
Package Diagrams
Figure 10. 48-pin TSOP I (12 × 18.4 × 1 mm) Z48A Package Outline, 51-85183
STANDARD PIN OUT (TOP VIEW)
2X (N/2 TIPS)
0.10
2X
2
1
0.10
2X
N
SEE DETAIL B
A
0.10 C
A2
8
R
B
E
(c)
5
e
N/2 +1
N/2
5
D1
D
0.20
2X (N/2 TIPS)
GAUGE PLANE
9
C
PARALLEL TO
SEATING PLANE
C
SEATING PLANE
4
0.25 BASIC
0°
A1
L
DETAIL A
B
A
B
SEE DETAIL A
0.08MM M C A-B
b
6
7
WITH PLATING
REVERSE PIN OUT (TOP VIEW)
e/2
3
1
N
7
c
c1
X
X = A OR B
b1
N/2
N/2 +1
SYMBOL
DIMENSIONS
MIN.
NOM.
MAX.
1.
2.
PIN 1 IDENTIFIER FOR STANDARD PIN OUT (DIE UP).
PIN 1 IDENTIFIER FOR REVERSE PIN OUT (DIE DOWN): INK OR LASER MARK.
1.00
1.05
4.
TO BE DETERMINED AT THE SEATING PLANE
0.20
0.23
A2
0.95
0.17
0.22
b
0.17
c1
0.10
0.16
c
0.10
0.21
D
20.00 BASIC
18.40 BASIC
E
12.00 BASIC
5.
DIMENSIONS D1 AND E DO NOT INCLUDE MOLD PROTRUSION. ALLOWABLE
MOLD PROTRUSION ON E IS 0.15mm PER SIDE AND ON D1 IS 0.25mm PER SIDE.
6.
DIMENSION b DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.08mm TOTAL IN EXCESS OF b DIMENSION AT MAX.
MATERIAL CONDITION. DAMBAR CANNOT BE LOCATED ON LOWER RADIUS OR
THE FOOT. MINIMUM SPACE BETWEEN PROTRUSION AND AN ADJACENT LEAD
TO BE 0.07mm .
7.
THESE DIMENSIONS APPLY TO THE FLAT SECTION OF THE LEAD BETWEEN
0.10mm AND 0.25mm FROM THE LEAD TIP.
8.
LEAD COPLANARITY SHALL BE WITHIN 0.10mm AS MEASURED FROM THE
SEATING PLANE.
0.50 BASIC
0
0°
R
0.08
0.60
0.70
8
0.20
48
-C- . THE SEATING PLANE IS
DEFINED AS THE PLANE OF CONTACT THAT IS MADE WHEN THE PACKAGE
LEADS ARE ALLOWED TO REST FREELY ON A FLAT HORIZONTAL SURFACE.
0.27
D1
0.50
DIMENSIONS ARE IN MILLIMETERS (mm).
3.
b1
N
NOTES:
0.15
0.05
L
DETAIL B
1.20
A
A1
e
BASE METAL
SECTION B-B
9. DIMENSION "e" IS MEASURED AT THE CENTERLINE OF THE LEADS.
10. JEDEC SPECIFICATION NO. REF: MO-142(D)DD.
51-85183 *F
Document Number: 001-64709 Rev. *F
Page 13 of 16
CY62177ESL MoBL®
Acronyms
Acronym
Document Conventions
Description
Units of Measure
CMOS
Complementary Metal Oxide Semiconductor
I/O
Input/Output
°C
degree Celsius
SRAM
Static Random Access Memory
MHz
megahertz
TSOP
Thin Small Outline Package
A
microampere
mA
milliampere
ns
nanosecond
ohm
pF
picofarad
V
volt
W
watt
Document Number: 001-64709 Rev. *F
Symbol
Unit of Measure
Page 14 of 16
CY62177ESL MoBL®
Document History Page
Document Title: CY62177ESL MoBL®, 32-Mbit (2M × 16/4M × 8) Static RAM
Document Number: 001-64709
Revision
ECN
Orig. of
Change
Submission
Date
Description of Change
**
3077028
RAME
11/02/2010
New data sheet.
*A
3103863
RAME
12/07/2010
Updated Ordering Information:
No change in part numbers.
The MPN CY62177ESL-55ZXI is moved to production.
*B
3433813
TAVA
11/16/2011
Updated Functional Description:
Removed Note “For best practice recommendations, refer to the Cypress
application note System Design Guidelines.” and its reference.
Updated Pin Configuration:
Updated Figure 1 (Changed pin 13 from NC to DNU).
Completing Sunset Review.
*C
4101093
VINI
08/21/2013
Updated Switching Characteristics:
Added Note 17 and referred the same note in “Parameter” column.
Updated to new template.
*D
4573215
VINI
11/18/2014
Updated Functional Description:
Added “For a complete list of related documentation, click here.” at the end.
Completing Sunset Review.
*E
5016184
NILE
11/17/2015
Updated Thermal Resistance:
Replaced “two-layer” with “four-layer” in “Test Conditions” column.
Changed value of JA parameter corresponding to TSOP I package from
44.66 C/W to 55.91 C/W.
Changed value of JC parameter corresponding to TSOP I package from
12.12 C/W to 9.39 C/W.
Updated Package Diagrams:
spec 51-85183 – Changed revision from *C to *D.
Updated to new template.
Completing Sunset Review.
*F
6383009
NILE
11/13/2018
Updated Package Diagrams:
spec 51-85183 – Changed revision from *D to *F.
Updated to new template.
Completing Sunset Review.
Document Number: 001-64709 Rev. *F
Page 15 of 16
CY62177ESL MoBL®
Sales, Solutions, and Legal Information
Worldwide Sales and Design Support
Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office
closest to you, visit us at Cypress Locations.
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Products
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cypress.com/arm
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cypress.com/clocks
cypress.com/interface
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cypress.com/iot
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cypress.com/mcu
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cypress.com/psoc
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Cypress Developer Community
Community | Projects | Video | Blogs | Training | Components
Technical Support
cypress.com/support
cypress.com/pmic
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cypress.com/touch
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Wireless Connectivity
PSoC 1 | PSoC 3 | PSoC 4 | PSoC 5LP | PSoC 6 MCU
cypress.com/usb
cypress.com/wireless
© Cypress Semiconductor Corporation, 2010–2018. This document is the property of Cypress Semiconductor Corporation and its subsidiaries, including Spansion LLC (“Cypress”). This document,
including any software or firmware included or referenced in this document (“Software”), is owned by Cypress under the intellectual property laws and treaties of the United States and other countries
worldwide. Cypress reserves all rights under such laws and treaties and does not, except as specifically stated in this paragraph, grant any license under its patents, copyrights, trademarks, or other
intellectual property rights. If the Software is not accompanied by a license agreement and you do not otherwise have a written agreement with Cypress governing the use of the Software, then Cypress
hereby grants you a personal, non-exclusive, nontransferable license (without the right to sublicense) (1) under its copyright rights in the Software (a) for Software provided in source code form, to
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(either directly or indirectly through resellers and distributors), solely for use on Cypress hardware product units, and (2) under those claims of Cypress’s patents that are infringed by the Software (as
provided by Cypress, unmodified) to make, use, distribute, and import the Software solely for use with Cypress hardware products. Any other use, reproduction, modification, translation, or compilation
of the Software is prohibited.
TO THE EXTENT PERMITTED BY APPLICABLE LAW, CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS DOCUMENT OR ANY SOFTWARE
OR ACCOMPANYING HARDWARE, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. No computing
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liability arising out of the application or use of any product or circuit described in this document. Any information provided in this document, including any sample design information or programming
code, is provided only for reference purposes. It is the responsibility of the user of this document to properly design, program, and test the functionality and safety of any application made of this
information and any resulting product. Cypress products are not designed, intended, or authorized for use as critical components in systems designed or intended for the operation of weapons, weapons
systems, nuclear installations, life-support devices or systems, other medical devices or systems (including resuscitation equipment and surgical implants), pollution control or hazardous substances
management, or other uses where the failure of the device or system could cause personal injury, death, or property damage (“Unintended Uses”). A critical component is any component of a device
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shall and hereby do release Cypress from any claim, damage, or other liability arising from or related to all Unintended Uses of Cypress products. You shall indemnify and hold Cypress harmless from
and against all claims, costs, damages, and other liabilities, including claims for personal injury or death, arising from or related to any Unintended Uses of Cypress products.
Cypress, the Cypress logo, Spansion, the Spansion logo, and combinations thereof, WICED, PSoC, CapSense, EZ-USB, F-RAM, and Traveo are trademarks or registered trademarks of Cypress in
the United States and other countries. For a more complete list of Cypress trademarks, visit cypress.com. Other names and brands may be claimed as property of their respective owners.
Document Number: 001-64709 Rev. *F
Revised November 13, 2018
MoBL is a registered trademark, and More Battery Life is a trademark, of Cypress Semiconductor Corporation.
Page 16 of 16
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