PRELIMINARY
CY62177G30/CY62177GE30 MoBL
32-Mbit (2M words × 16-bit/
4M words × 8-bit) Static RAM
with Error-Correcting Code (ECC)
CY62177G30/CY62177GE30 MoBL, 16-Mbit (1M words × 16-bit/2M words × 8-bit) Static RAM with Error-Correcting Code (ECC)
Features
through I/O15) and address pins (A0 through A20) respectively.
The Byte High Enable (BHE) and Byte Low Enable (BLE) inputs
control byte writes and write data on the corresponding I/O lines
to the memory location specified. BHE controls I/O8 through
I/O15 and BLE controls I/O0 through I/O7.
■
Ultra-low standby current
❐ Typical standby current: 3 µA
❐ Maximum standby current: 19 µA
■
High speed: 55 ns
■
Embedded error-correcting code (ECC) for single-bit error
correction[1]
■
Operating voltage range: 2.2 V to 3.6 V
■
1.5-V data retention
■
Transistor-transistor logic (TTL) compatible inputs and outputs
■
Error indication (ERR) pin to indicate 1-bit error detection and
correction
■
48-pin TSOP I package configurable as 2M × 16 or 4M × 8
SRAM
■
Available in Pb-free 48-ball VFBGA and 48-pin TSOP I
packages
Functional Description
CY62177G30 and CY62177GE30 are high-performance CMOS,
low-power (MoBL®) SRAM devices with embedded ECC[2]. Both
devices are offered in single and dual chip enable options and in
multiple pin configurations. The CY62177GE30 device includes
an ERR pin that signals a single-bit error-detection and
correction event during a read cycle.
To perform data reads, assert the Output Enable (OE) input and
provide the required address on the address lines. You can
access read data on the I/O lines (I/O0 through I/O15). To perform
byte accesses, assert the required byte enable signal (BHE or
BLE) to read either the upper byte or the lower byte of data from
the specified address location.
All I/Os (I/O0 through I/O15) are placed in a high-impedance state
when the device is deselected (CE HIGH for a single chip enable
device and CE1 HIGH / CE2 LOW for a dual chip enable device),
or the control signals are de-asserted (OE, BLE, BHE).
These devices have a unique Byte Power-down feature where,
if both the Byte Enables (BHE and BLE) are disabled, the
devices seamlessly switch to the standby mode irrespective of
the state of the chip enables, thereby saving power.
On the CY62177GE30 devices, the detection and correction of
a single-bit error in the accessed location is indicated by the
assertion of the ERR output (ERR = High). See the Truth Table
– CY62177G30/CY62177GE30 on page 15 for a complete
description of read and write modes.
The CY62177G30 and CY62177GE30 devices are available in
a Pb-free 48-pin TSOP I package and 48-ball VFBGA packages.
The logic block diagrams are on page 2.
To access devices with a single chip enable input, assert the chip
enable (CE) input LOW. To access dual chip enable devices,
assert both chip enable inputs – CE1 as LOW and CE2 as HIGH.
The device in the 48-pin TSOP I package can also be configured
to function as a 4M words × 8 bit device. Refer to the Pin
Configurations section for details.
To perform data writes, assert the Write Enable (WE) input LOW,
and provide the data and address on the device data pins (I/O0
For a complete list of related documentation, click here.
Product Portfolio
Current Consumption
Product
Features and Options
(see the Pin
Configurations section)
CY62177G30/ Single or dual Chip Enables
CY62177GE30 Optional ERR pin
Range
Industrial
Operating ICC, (mA)
VCC Range (V) Speed
(ns)
f = fmax
Max
Typ[3]
2.2 V–3.6 V
55
35
45
Standby, ISB2 (µA)
Typ[3]
Max
3
19
Notes
1. SER FIT rate 2001 V
Latch-up current ..................................................... >140 mA
Operating Range
Supply voltage
to ground potential .............................. –0.5 V to VCC + 0.5 V
DC voltage applied to outputs
in High Z state[10] ................................. –0.5 V to VCC + 0.5 V
Grade
Ambient Temperature
VCC[11]
Industrial
–40 C to +85 C
2.2 V to 3.6 V
DC Electrical Characteristics
Over the operating range of –40 C to 85 C
Parameter
VOH
VOL
VIH
VIL
Description
Test Conditions
55 ns
Min
Typ [12]
Max
Output HIGH
2.2 V to 2.7 V
VCC = Min, IOH = –0.1 mA
2.0
–
–
voltage
2.7 V to 3.6 V
VCC = Min, IOH = –1.0 mA
2.4
–
–
Output LOW
2.2 V to 2.7 V
VCC = Min, IOL = 0.1 mA
–
–
0.4
voltage
2.7 V to 3.6 V
VCC = Min, IOL = 2.1 mA
–
–
0.4
Input HIGH
2.2 V to 2.7 V
–
1.8
–
VCC + 0.3
voltage[10]
2.7 V to 3.6 V
–
2.0
–
VCC + 0.3
Input LOW
2.2 V to 2.7 V
–
–0.3
–
0.6
voltage[10]
2.7 V to 3.6 V
–
–0.3
–
0.8
IIX
Input leakage current
GND < VIN < VCC
–1.0
–
+1.0
IOZ
Output leakage current
GND < VOUT < VCC, Output disabled
–1.0
–
+1.0
ICC
VCC operating supply current
VCC = Max,
–
35.0
45.0
ISB1
[13]
f = 22.22 MHz
Unit
V
µA
mA
IOUT = 0 mA,
(45 ns)
CMOS levels
f = 1 MHz
–
10.0
18.0
Automatic Power-down
CE1 > VCC – 0.2 V or CE2 < 0.2 V
–
3.0
19.0
µA
Current – CMOS Inputs;
or (BHE and BLE) > VCC – 0.2 V,
VCC = 2.2 V to 3.6 V
VIN > VCC – 0.2 V, VIN < 0.2 V,
–
3.0
19.0
µA
f = fmax (address and data only),
f = 0 (OE, and WE), VCC = VCC(max)
ISB2[13]
Automatic Power-down
CE1 > VCC – 0.2V or CE2 < 0.2 V or
Current – CMOS Inputs
(BHE and BLE) > VCC – 0.2 V,
VCC = 2.2 V to 3.6 V
VIN > VCC – 0.2 V or VIN < 0.2 V,
f = 0, VCC = VCC(max)
Notes
10. VIL(min) = –2.0 V and VIH(max) = VCC + 2 V for pulse durations of less than 20 ns.
11. Full device AC operation assumes a 100-µs ramp time from 0 to VCC (min) and 400-µs wait time after VCC stabilizes to its operational value.
12. Indicates the value for the center of distribution at 3.0 V, 25 °C and not 100% tested.
13. The ISB2 maximum limits at 25 °C are guaranteed by design and not 100% tested.
Document Number: 002-24704 Rev. *B
Page 7 of 22
PRELIMINARY
CY62177G30/CY62177GE30 MoBL
Capacitance
Parameter [14]
Description
CIN
Input capacitance
COUT
Output capacitance
Test Conditions
TA = 25 °C, f = 1 MHz, VCC = VCC(typ)
Max
Unit
15.0
pF
15.0
Thermal Resistance
Parameter [14]
Description
JA
Thermal resistance
(junction to ambient)
JC
Thermal resistance
(junction to case)
Test Conditions
48-ball VFBGA 48-ball FBGA 48-pin TSOP I Unit
Still air, soldered on a
3 × 4.5 inch, four-layer
printed circuit board
54.8
51.5
50.98
11.9
7.8
9.4
°C/W
AC Test Loads and Waveforms
Figure 6. AC Test Loads and Waveforms
R1
VCC
OUTPUT
VHIGH
GND
30 pF
R2
INCLUDING
JIG AND
SCOPE
10%
ALL INPUT PULSES
90%
90%
10%
Fall Time = 1 V/ns
Rise Time = 1 V/ns
Equivalent to: THÉVENIN EQUIVALENT
RTH
OUTPUT
VTH
Parameters
2.5 V
3.0 V
Unit
R1
16667
1103
R2
15385
1554
RTH
8000
645
VTH
1.20
1.75
VHIGH
2.5
3.0
V
Note
14. Tested initially and after any design or process changes that may affect these parameters.
Document Number: 002-24704 Rev. *B
Page 8 of 22
PRELIMINARY
CY62177G30/CY62177GE30 MoBL
Data Retention Characteristics
Over the Operating Range
Parameter
Description
Conditions
Min
Typ [15]
Max
Unit
VDR
VCC for data retention
–
1.5
–
–
V
ICCDR[16, 17]
Data retention current
2.2 V < VCC < 3.6 V
CE1 > VCC 0.2 V or CE2 < 0.2 V
or (BHE and BLE) > VCC – 0.2 V,
VIN > VCC 0.2 V or VIN < 0.2 V
–
3.0
19.0
µA
1.5 V < VCC < 2.2 V,
CE1 > VCC 0.2 V or CE2 < 0.2 V
or (BHE and BLE) > VCC – 0.2 V,
VIN > VCC 0.2 V or VIN < 0.2 V
–
–
20.0
tCDR[18]
Chip deselect to data retention
time
–
0.0
–
–
–
tR[18, 19]
Operation recovery time
–
55
–
–
ns
Data Retention Waveform
Figure 7. Data Retention Waveform [20]
VCC
VCC (min)
tCDR
DATA RETENTION MODE
VDR = 1.0 V
VCC (min)
tR
CE1 or
BHE. BLE
CE2
Notes
15. Indicates the value for the center of distribution at 3.0 V, 25 °C and not 100% tested.
16. Chip enables (CE1 and CE2) and BYTE must be tied to CMOS levels to meet the ISB1 / ISB2 / ICCDR spec. Other inputs can be left floating.
17. ICCDR is guaranteed only after the device is first powered up to VCC(min) and then brought down to VDR.
18. These parameters are guaranteed by design and are not tested.
19. Full-device operation requires linear VCC ramp from VDR to VCC(min) > 400 s or stable at VCC(min) > 400 s.
20. BHE.BLE is the AND of both BHE and BLE. Deselect the chip by either disabling the chip enable signals or by disabling both BHE and BLE.
Document Number: 002-24704 Rev. *B
Page 9 of 22
PRELIMINARY
CY62177G30/CY62177GE30 MoBL
Switching Characteristics
Parameter [21]
Description
55 ns
Min
Max
55.0
–
Unit
Read Cycle
tRC
Read cycle time
tAA
Address to data valid / Address to ERR valid
tOHA
Data hold from address change / ERR hold from address change
tACE
tDOE
–
55.0
10.0
–
CE1 LOW and CE2 HIGH to data valid / CE LOW to ERR valid
–
55.0
OE LOW to data valid / OE LOW to ERR valid
–
25.0
[22, 23]
tLZOE
OE LOW to Low Z
tHZOE
OE HIGH to High Z [22, 23, 24]
tLZCE
CE1 LOW and CE2 HIGH to Low Z [22, 23]
tHZCE
CE1 HIGH and CE2 LOW to High Z
5.0
–
–
18.0
10.0
–
[22, 23, 24]
–
18.0
[25]
tPU
CE1 LOW and CE2 HIGH to power-up
0.0
–
tPD
CE1 HIGH and CE2 LOW to power-down [25]
–
55.0
tDBE
BLE / BHE LOW to data valid
–
55.0
5.0
–
–
18.0
tLZBE
tHZBE
BLE / BHE LOW to Low Z
[22]
BLE / BHE HIGH to High Z
[22, 24]
ns
Write Cycle [26, 27]
tWC
Write cycle time
55.0
–
tSCE
CE1 LOW and CE2 HIGH to write end
40.0
–
tAW
Address setup to write end
40.0
–
tHA
Address hold from write end
0
–
tSA
Address setup to write start
0
–
tPWE
WE pulse width
40.0
–
tBW
BLE / BHE LOW to write end
40.0
–
tSD
Data setup to write end
25.0
–
tHD
Data hold from write end
0.0
–
–
18.0
10.0
–
tHZWE
tLZWE
WE LOW to High Z
[22, 23, 24]
WE HIGH to Low Z
[22, 23]
ns
Notes
21. Test conditions assume signal transition time (rise/fall) of 3 ns or less, timing reference levels of 1.5 V (for VCC > 3 V) and VCC/2 (for VCC < 3 V), and input pulse levels
of 0 to 3 V (for VCC > 3 V) and 0 to VCC (for VCC < 3V). Test conditions for the read cycle use the output loading shown in Figure 6 on page 8, unless specified otherwise.
22. At any temperature and voltage condition, tHZCE is less than tLZCE, tHZBE is less than tLZBE, tHZOE is less than tLZOE, and tHZWE is less than tLZWE for any device.
23. Tested initially and after any design or process changes that may affect these parameters.
24. tHZOE, tHZCE, tHZBE, and tHZWE transitions are measured when the outputs enter a high-impedance state.
25. These parameters are guaranteed by design and are not tested.
26. The internal write time of the memory is defined by the overlap of WE = VIL, CE1 = VIL, BHE or BLE or both = VIL, and CE2 = VIH. All signals must be ACTIVE to initiate
a write and any of these signals can terminate a write by going INACTIVE. The data input setup and hold timing must refer to the edge of the signal that terminates
the write.
27. The minimum write cycle pulse width for Write Cycle No. 1 (WE Controlled, OE LOW) should be equal to the sum of tHZWE and tSD.
Document Number: 002-24704 Rev. *B
Page 10 of 22
PRELIMINARY
CY62177G30/CY62177GE30 MoBL
Switching Waveforms
Figure 8. Read Cycle No. 1 of CY62177G30 (Address Transition Controlled) [28, 29]
tRC
ADDRESS
tAA
tOHA
DATA I/O
PREVIOUS DATAOUT
VALID
DATAOUT VALID
Figure 9. Read Cycle No. 1 of CY62177GE30 (Address Transition Controlled) [28, 29]
tRC
ADDRESS
tAA
tOHA
DATA I/O
PREVIOUS DATAOUT VALID
DATAOUT VALID
tAA
tOHA
ERR
PREVIOUS ERR VALID
ERR VALID
Notes
28. The device is continuously selected. OE = VIL, CE = VIL, BHE or BLE, or both = VIL.
29. WE is HIGH for read cycle.
Document Number: 002-24704 Rev. *B
Page 11 of 22
PRELIMINARY
CY62177G30/CY62177GE30 MoBL
Switching Waveforms (continued)
Figure 10. Read Cycle No. 2 (OE Controlled) [30, 31, 32, 34]
ADDRESS
tR C
CE
tP D
tH Z C E
tA C E
OE
tH Z O E
tD O E
tL Z O E
BHE/
BLE
tD B E
tL Z B E
D A T A I/O
tH Z B E
H IG H IM P E D A N C E
H IG H
IM P E D A N C E
D A T A O U T V A L ID
tLZC E
tP U
V CC
SUPPLY
CURRENT
IS B
Figure 11. Write Cycle No. 1 (WE Controlled, OE LOW) [31, 33, 34, 35]
tW C
ADDRESS
tS C E
CE
tB W
BHE/
BLE
tS A
tA W
tH A
tP W E
WE
tH Z W E
D A T A I/O
Note 35
tS D
tLZW E
tH D
D A T A IN V A L ID
Notes
30. WE is HIGH for read cycle.
31. For all dual chip enable devices, CE is the logical combination of CE1 and CE2. When CE1 is LOW and CE2 is HIGH, CE is LOW; when CE1 is HIGH or CE2 is LOW,
CE is HIGH.
32. Address valid prior to or coincident with CE LOW transition.
33. The internal write time of the memory is defined by the overlap of WE = VIL, CE1 = VIL, BHE or BLE, or both = VIL, and CE2 = VIH. All signals must be ACTIVE to initiate
a write and any of these signals can terminate a write by going INACTIVE. The data input setup and hold timing must refer to the edge of the signal that terminates the
write.
34. Data I/O is in the high-impedance state if CE = VIH, or OE = VIH, or BHE, and/or BLE = VIH.
35. During this period, the I/Os are in the output state. Do not apply input signals.
36. The minimum write cycle pulse width should be equal to the sum of tHZWE and tSD.
Document Number: 002-24704 Rev. *B
Page 12 of 22
PRELIMINARY
CY62177G30/CY62177GE30 MoBL
Switching Waveforms (continued)
Figure 12. Write Cycle No. 2 (CE Controlled) [37, 38, 39]
tWC
ADDRESS
tSA
t SCE
CE
tAW
tHA
t PWE
WE
tBW
BHE/
BLE
OE
t HZOE
DATA I/ O
Note 40
tHD
tSD
DATAIN VALID
Notes
37. For all dual chip enable devices, CE is the logical combination of CE1 and CE2. When CE1 is LOW and CE2 is HIGH, CE is LOW; when CE1 is HIGH or CE2 is LOW,
CE is HIGH.
38. The internal write time of the memory is defined by the overlap of WE = VIL, CE1 = VIL, BHE or BLE or both = VIL, and CE2 = VIH. All signals must be ACTIVE to initiate
a write and any of these signals can terminate a write by going INACTIVE. The data input setup and hold timing must refer to the edge of the signal that terminates the
write.
39. Data I/O is in the high-impedance state if CE = VIH, or OE = VIH, or BHE, and/or BLE = VIH.
40. During this period, the I/Os are in output state. Do not apply input signals.
Document Number: 002-24704 Rev. *B
Page 13 of 22
PRELIMINARY
CY62177G30/CY62177GE30 MoBL
Switching Waveforms (continued)
Figure 13. Write Cycle No. 4 (BHE/BLE Controlled, OE LOW) [41, 42, 43]
tW C
ADDRESS
tS C E
CE
t AW
tS A
tH A
t BW
BHE/
B LE
tP W E
WE
t H ZW E
D A TA I/O
tH D
tS D
Note 44
t LZW E
D A TA IN V A LID
Figure 14. Write Cycle No. 5 (WE Controlled) [41, 42, 43]
tW C
ADDRESS
tS C E
CE
tA W
tS A
tH A
tP W E
WE
tB W
B H E /B L E
OE
tH Z O E
D A T A I/O
Note 44
tH D
tS D
D A T A IN V A L I D
Notes
41. For all dual chip enable devices, CE is the logical combination of CE1 and CE2. When CE1 is LOW and CE2 is HIGH, CE is LOW; when CE1 is HIGH or CE2 is LOW,
CE is HIGH.
42. The internal write time of the memory is defined by the overlap of WE = VIL, CE1 = VIL, BHE or BLE or both = VIL, and CE2 = VIH. All signals must be ACTIVE to
initiate a write and any of these signals can terminate a write by going INACTIVE. The data input setup and hold timing must refer to the edge of the signal that
terminates the write.
43. Data I/O is in the high-impedance state if CE = VIH, or OE = VIH, or BHE, and/or BLE = VIH.
44. During this period, the I/Os are in output state. Do not apply input signals.
Document Number: 002-24704 Rev. *B
Page 14 of 22
PRELIMINARY
CY62177G30/CY62177GE30 MoBL
Truth Table – CY62177G30/CY62177GE30
BYTE[45]
CE1
WE
OE
BHE
BLE
[46]
X
X
X
X
High-Z
Deselect/Power-down Standby (ISB) 4M × 8/2M × 16
X
L
X
X
X
X
High-Z
Deselect/Power-down Standby (ISB) 4M × 8/2M × 16
X
X[46]
[46]
X
X
H
H
High-Z
Deselect/Power-down Standby (ISB)
H
L
H
H
L
L
L
Data Out (I/O0–I/O15)
Read
Active (ICC)
2M × 16
H
L
H
H
L
H
L
Data Out (I/O0–I/O7);
High-Z (I/O8–I/O15)
Read
Active (ICC)
2M × 16
H
L
H
H
L
L
H
High Z (I/O0–I/O7);
Data Out (I/O8–I/O15)
Read
Active (ICC)
2M × 16
H
L
H
H
H
L
H
High-Z
Output disabled
Active (ICC)
2M × 16
H
L
H
H
H
H
L
High-Z
Output disabled
Active (ICC)
2M × 16
H
L
H
H
H
L
L
High-Z
Output disabled
Active (ICC)
2M × 16
H
L
H
L
X
L
L
Data In (I/O0–I/O15)
Write
Active (ICC)
2M × 16
H
L
H
L
X
H
L
Data In (I/O0–I/O7);
High-Z (I/O8–I/O15)
Write
Active (ICC)
2M × 16
H
L
H
L
X
L
H
High-Z (I/O0–I/O7);
Data In (I/O8–I/O15)
Write
Active (ICC)
2M × 16
L
L
H
H
L
X
X
Data Out (I/O0–I/O7)
Read
Active (ICC)
2M × 16
L
L
H
H
H
X
X
High-Z
Output disabled
Active (ICC)
2M × 16
L
L
H
L
X
X
X
Data In (I/O0–I/O7)
Write
Active (ICC)
4M × 8
[46]
H
X
[46]
X
CE2
X
X
Inputs/Outputs
Mode
Power
Configuration
2M × 16
ERR Output – CY62177GE30
Output[47]
Mode
0
Read operation, no single-bit error in the stored data.
1
Read operation, single-bit error detected and corrected.
High-Z
Device deselected / outputs disabled / Write operation
Notes
45. This pin is available only in the 48-pin TSOP I package. Tie the BYTE to VCC to configure the device in the 2M × 16 option. The 48-pin TSOP I package can also be
used as a 4M × 8 SRAM by tying the BYTE signal to VSS.
46. The ‘X’ (Don’t care) state for the chip enables refer to the logic state (either HIGH or LOW). Intermediate voltage levels on these pins is not permitted.
47. ERR is an Output pin. If not used, this pin should be left floating.
Document Number: 002-24704 Rev. *B
Page 15 of 22
PRELIMINARY
CY62177G30/CY62177GE30 MoBL
Ordering Information
Speed
(ns)
55
Voltage
Range
Package
Diagram
Ordering Code
2.2 V–3.6 V CY62177G30-55BAXI
Package Type
(all Pb-free)
51-85191
48-ball FBGA
51-85193
48-ball VFBGA
51-85183
48-pin TSOP I
Key Features /
Differentiators
ERR Pin / Operating
Ball
Range
Dual Chip Enable
No
Industrial
CY62177G30-55BAXIT
CY62177G30-55BKXI
CY62177G30-55BKXIT
CY62177G30-55ZXI
CY62177G30-55ZXIT
Ordering Code Definitions
CY 621
7
7
G
E
30 - 55
XX X X
I
X
X = blank or T
blank = Bulk; T = Tape and Reel
Temperature Grade: I = Industrial
Pb-free
X = blank or 1
blank = Dual Chip Enable; 1 = Single Chip Enable
Package Type: XX = BA or BK or Z
BA = 48-ball FBGA; BK = 48-ball VFBGA; Z = 48-pin TSOP I
Speed Grade: XX: 55 = 55 ns
Voltage Range: 30 = 3 V typ
ERR Output: Single-bit error correction indicator
Process Technology: Ultra Low-power
Bus Width: 7 = ×16
Density: 7 = 32-Mbit
Family Code: 621 = MoBL® SRAM family
Company ID: CY = Cypress
Document Number: 002-24704 Rev. *B
Page 16 of 22
PRELIMINARY
CY62177G30/CY62177GE30 MoBL
Package Diagrams
Figure 15. 48-ball FBGA (8 × 9.5 × 1.2 mm) Package Outline, 51-85191
51-85191 *C
Document Number: 002-24704 Rev. *B
Page 17 of 22
PRELIMINARY
CY62177G30/CY62177GE30 MoBL
Package Diagrams (continued)
Figure 16. 48-pin TSOP I (12 × 18.4 × 1.0 mm) Z48A Package Outline, 51-85183
STANDARD PIN OUT (TOP VIEW)
2X (N/2 TIPS)
0.10
2X
2
1
N
SEE DETAIL B
A
0.10 C
A2
0.10
2X
8
R
B
E
(c)
5
e
N/2 +1
N/2
5
D1
D
0.20
2X (N/2 TIPS)
GAUGE PLANE
9
C
PARALLEL TO
SEATING PLANE
C
SEATING PLANE
4
0.25 BASIC
0°
A1
L
DETAIL A
B
A
B
SEE DETAIL A
0.08MM M C A-B
b
6
7
WITH PLATING
REVERSE PIN OUT (TOP VIEW)
e/2
3
1
N
7
c
c1
X
X = A OR B
b1
N/2
N/2 +1
SYMBOL
DIMENSIONS
MIN.
NOM.
MAX.
1.
2.
PIN 1 IDENTIFIER FOR STANDARD PIN OUT (DIE UP).
PIN 1 IDENTIFIER FOR REVERSE PIN OUT (DIE DOWN): INK OR LASER MARK.
1.00
1.05
4.
TO BE DETERMINED AT THE SEATING PLANE
0.20
0.23
A2
0.95
0.17
0.22
b
0.17
c1
0.10
0.16
c
0.10
0.21
D
20.00 BASIC
18.40 BASIC
E
12.00 BASIC
5.
DIMENSIONS D1 AND E DO NOT INCLUDE MOLD PROTRUSION. ALLOWABLE
MOLD PROTRUSION ON E IS 0.15mm PER SIDE AND ON D1 IS 0.25mm PER SIDE.
6.
DIMENSION b DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.08mm TOTAL IN EXCESS OF b DIMENSION AT MAX.
MATERIAL CONDITION. DAMBAR CANNOT BE LOCATED ON LOWER RADIUS OR
THE FOOT. MINIMUM SPACE BETWEEN PROTRUSION AND AN ADJACENT LEAD
TO BE 0.07mm .
7.
THESE DIMENSIONS APPLY TO THE FLAT SECTION OF THE LEAD BETWEEN
0.10mm AND 0.25mm FROM THE LEAD TIP.
8.
LEAD COPLANARITY SHALL BE WITHIN 0.10mm AS MEASURED FROM THE
SEATING PLANE.
0.50 BASIC
0
0°
R
0.08
0.60
0.70
8
0.20
48
-C- . THE SEATING PLANE IS
DEFINED AS THE PLANE OF CONTACT THAT IS MADE WHEN THE PACKAGE
LEADS ARE ALLOWED TO REST FREELY ON A FLAT HORIZONTAL SURFACE.
0.27
D1
0.50
DIMENSIONS ARE IN MILLIMETERS (mm).
3.
b1
N
NOTES:
0.15
0.05
L
DETAIL B
1.20
A
A1
e
BASE METAL
SECTION B-B
9. DIMENSION "e" IS MEASURED AT THE CENTERLINE OF THE LEADS.
10. JEDEC SPECIFICATION NO. REF: MO-142(D)DD.
51-85183 *F
Document Number: 002-24704 Rev. *B
Page 18 of 22
PRELIMINARY
CY62177G30/CY62177GE30 MoBL
Package Diagrams (continued)
Figure 17. 48-pin FBGA (6 × 8 × 1.2 mm) Package Outline, 51-85193
51-85193 *E
Document Number: 002-24704 Rev. *B
Page 19 of 22
PRELIMINARY
CY62177G30/CY62177GE30 MoBL
Acronyms
Document Conventions
Table 1. Acronyms Used in this Document
Units of Measure
Acronym
Description
Table 2. Units of Measure
BHE
Byte High Enable
BLE
Byte Low Enable
°C
degree Celsius
CE
Chip Enable
MHz
megahertz
CMOS
Complementary metal oxide semiconductor
µA
microampere
I/O
Input/output
µs
microsecond
OE
Output Enable
mA
milliampere
SRAM
Static random access memory
mm
millimeter
TSOP
Thin small outline package
ns
nanosecond
VFBGA
Very fine-pitch ball grid array
ohm
WE
Write Enable
%
percent
pF
picofarad
V
volt
W
watt
Document Number: 002-24704 Rev. *B
Symbol
Unit of Measure
Page 20 of 22
PRELIMINARY
CY62177G30/CY62177GE30 MoBL
Document History Page
Document Title: CY62177G30/CY62177GE30 MoBL, 32-Mbit (2M words × 16-bit/4M words × 8-bit) Static RAM with
Error-Correcting Code (ECC)
Document Number: 002-24704
Rev.
ECN No.
Submission
Date
Description of Change
**
6284145
08/17/2018
New data sheet.
*A
6714290
10/30/2019
Changed status from Advance to Preliminary.
Added 48-ball FBGA package related information in all instances across the document.
Updated Product Portfolio:
Changed maximum value of “Operating Current” from 40 mA to 45 mA.
Changed maximum value of “Standby Current” from 16 µA to 19 µA.
Updated DC Electrical Characteristics:
Changed maximum value of ICC parameter from 40 mA to 45 mA corresponding to Test
Condition “f = 22.22 MHz (45 ns)”.
Changed maximum value of ICC parameter from 12 mA to 18 mA corresponding to Test
Condition “f = 1 MHz”.
Changed maximum value of ISB1 parameter from 16 µA to 19 µA.
Removed Temperature Ranges from “Test Conditions” column of ISB2 parameter and also
the corresponding values.
Added 3 µA under “Typ” column and 19 µA under “Max” column of ISB2 parameter.
Updated Thermal Resistance:
Replaced “TBD” with corresponding values.
Updated Data Retention Characteristics:
Changed minimum value of VDR parameter from 1.0 V to 1.5 V.
Changed maximum value of ICCDR parameter from 16 µA to 19 µA corresponding to Test
Condition “2.2 V < VCC < 3.6 V”.
Changed maximum value of ICCDR parameter from 28 µA to 20 µA corresponding to Test
Condition “1.5 V < VCC < 2.2 V”.
Updated Ordering Information:
Updated part numbers.
Updated Package Diagrams:
Added spec 51-85193 *E.
*B
6745626
12/05/2019
Updated Ordering Information:
Updated part numbers.
Updated Ordering Code Definitions.
Document Number: 002-24704 Rev. *B
Page 21 of 22
PRELIMINARY
CY62177G30/CY62177GE30 MoBL
Sales, Solutions, and Legal Information
Worldwide Sales and Design Support
Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office
closest to you, visit us at Cypress Locations.
PSoC® Solutions
Products
Arm® Cortex® Microcontrollers
Automotive
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cypress.com/automotive
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Interface
cypress.com/clocks
cypress.com/interface
Internet of Things
Memory
cypress.com/iot
cypress.com/memory
Microcontrollers
cypress.com/mcu
PSoC
cypress.com/psoc
Power Management ICs
Cypress Developer Community
Community | Projects | Video | Blogs | Training | Components
Technical Support
cypress.com/support
cypress.com/pmic
Touch Sensing
cypress.com/touch
USB Controllers
Wireless Connectivity
PSoC 1 | PSoC 3 | PSoC 4 | PSoC 5LP | PSoC 6 MCU
cypress.com/usb
cypress.com/wireless
© Cypress Semiconductor Corporation, 2018–2019. This document is the property of Cypress Semiconductor Corporation and its subsidiaries (“Cypress”). This document, including any software or
firmware included or referenced in this document (“Software”), is owned by Cypress under the intellectual property laws and treaties of the United States and other countries worldwide. Cypress
reserves all rights under such laws and treaties and does not, except as specifically stated in this paragraph, grant any license under its patents, copyrights, trademarks, or other intellectual property
rights. If the Software is not accompanied by a license agreement and you do not otherwise have a written agreement with Cypress governing the use of the Software, then Cypress hereby grants
you a personal, non-exclusive, nontransferable license (without the right to sublicense) (1) under its copyright rights in the Software (a) for Software provided in source code form, to modify and reproduce
the Software solely for use with Cypress hardware products, only internally within your organization, and (b) to distribute the Software in binary code form externally to end users (either directly or
indirectly through resellers and distributors), solely for use on Cypress hardware product units, and (2) under those claims of Cypress’s patents that are infringed by the Software (as provided by
Cypress, unmodified) to make, use, distribute, and import the Software solely for use with Cypress hardware products. Any other use, reproduction, modification, translation, or compilation of the
Software is prohibited.
TO THE EXTENT PERMITTED BY APPLICABLE LAW, CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS DOCUMENT OR ANY SOFTWARE
OR ACCOMPANYING HARDWARE, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. No computing
device can be absolutely secure. Therefore, despite security measures implemented in Cypress hardware or software products, Cypress shall have no liability arising out of any security breach, such
as unauthorized access to or use of a Cypress product. CYPRESS DOES NOT REPRESENT, WARRANT, OR GUARANTEE THAT CYPRESS PRODUCTS, OR SYSTEMS CREATED USING
CYPRESS PRODUCTS, WILL BE FREE FROM CORRUPTION, ATTACK, VIRUSES, INTERFERENCE, HACKING, DATA LOSS OR THEFT, OR OTHER SECURITY INTRUSION (collectively, “Security
Breach”). Cypress disclaims any liability relating to any Security Breach, and you shall and hereby do release Cypress from any claim, damage, or other liability arising from any Security Breach. In
addition, the products described in these materials may contain design defects or errors known as errata which may cause the product to deviate from published specifications. To the extent permitted
by applicable law, Cypress reserves the right to make changes to this document without further notice. Cypress does not assume any liability arising out of the application or use of any product or
circuit described in this document. Any information provided in this document, including any sample design information or programming code, is provided only for reference purposes. It is the
responsibility of the user of this document to properly design, program, and test the functionality and safety of any application made of this information and any resulting product. “High-Risk Device”
means any device or system whose failure could cause personal injury, death, or property damage. Examples of High-Risk Devices are weapons, nuclear installations, surgical implants, and other
medical devices. “Critical Component” means any component of a High-Risk Device whose failure to perform can be reasonably expected to cause, directly or indirectly, the failure of the High-Risk
Device, or to affect its safety or effectiveness. Cypress is not liable, in whole or in part, and you shall and hereby do release Cypress from any claim, damage, or other liability arising from any use of
a Cypress product as a Critical Component in a High-Risk Device. You shall indemnify and hold Cypress, its directors, officers, employees, agents, affiliates, distributors, and assigns harmless from
and against all claims, costs, damages, and expenses, arising out of any claim, including claims for product liability, personal injury or death, or property damage arising from any use of a Cypress
product as a Critical Component in a High-Risk Device. Cypress products are not intended or authorized for use as a Critical Component in any High-Risk Device except to the limited extent that (i)
Cypress’s published data sheet for the product explicitly states Cypress has qualified the product for use in a specific High-Risk Device, or (ii) Cypress has given you advance written authorization to
use the product as a Critical Component in the specific High-Risk Device and you have signed a separate indemnification agreement.
Cypress, the Cypress logo, Spansion, the Spansion logo, and combinations thereof, WICED, PSoC, CapSense, EZ-USB, F-RAM, and Traveo are trademarks or registered trademarks of Cypress in
the United States and other countries. For a more complete list of Cypress trademarks, visit cypress.com. Other names and brands may be claimed as property of their respective owners.
Document Number: 002-24704 Rev. *B
Revised December 5, 2019
Page 22 of 22
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