CY7B991-2JXC

CY7B991 CY7B992 Programmable Skew Clock Buffer Features ■ ■ ■ Functional Description The CY7B991 and CY7B992 Programmable Skew Clock Buffers (PSCB) offer user selectable control over system clock functions. These multiple output clock drivers provide the system integrator with functions necessary to optimize the timing of high performance computer systems. Each of the eight individual drivers, arranged in four pairs of user controllable outputs, can drive terminated transmission lines with impedances as low as 50Ω. They can deliver minimal and specified output skews and full swing logic levels (CY7B991 TTL or CY7B992 CMOS). Each output is hardwired to one of the nine delay or function configurations. Delay increments of 0.7 to 1.5 ns are determined by the operating frequency with outputs that skew up to ±6 time units from their nominal “zero” skew position. The completely integrated PLL allows cancellation of external load and transmission line delay effects. When this “zero delay” capability of the PSCB is combined with the selectable output skew functions, you can create output-to-output delays of up to ±12 time units. Divide-by-two and divide-by-four output functions are provided for additional flexibility in designing complex clock systems. When combined with the internal PLL, these divide functions enable distribution of a low frequency clock that are multiplied by two or four at the clock destination. This facility minimizes clock distribution difficulty, allowing maximum system clock speed and flexibility. All output pair skew 2001V (MIL-STD-883, Method 3015) Latch Up Current ..................................................... >200 mA Operating Range Range Commercial Industrial Military Military [5] [5] Ambient Temperature 0°C to +70°C –40°C to +85°C –55°C to +125°C –55°C to +125°C VCC 5V ± 10% 5V ± 10% 5V ± 10% 5V ± 10% Note 5. Indicates case temperature. Document Number: 38-07138 Rev. *B Page 5 of 19 CY7B991 CY7B992 Electrical Characteristics Over the Operating Range[6] CY7B991 Parameter VOH VOL VIH VIL VIHH VIMM VILL IIH IIL IIHH IIMM IILL IOS ICCQ Description Output HIGH Voltage Output LOW Voltage Input HIGH Voltage (REF and FB inputs only) Input LOW Voltage (REF and FB inputs only) Three Level Input HIGH Voltage (Test, FS, xFn)[10] Three Level Input MID Voltage (Test, FS, xFn)[10] Three Level Input LOW Voltage (Test, FS, xFn)[10] Input HIGH Leakage Current (REF and FB inputs only) Input LOW Leakage Current (REF and FB inputs only) Input HIGH Current (Test, FS, xFn) Input MID Current (Test, FS, xFn) Input LOW Current (Test, FS, xFn) Output Short Circuit Current[8] Operating Current Used by Internal Circuitry Output Buffer Current per Output Pair[9] Power Dissipation per Output Pair[10] Min ≤ VCC ≤ Max Min ≤ VCC ≤ Max Min ≤ VCC ≤ Maximum VCC = Max, VIN = Max. VCC = Max, VIN = 0.4V VIN = VCC VIN = VCC/2 VIN = GND VCC = Max, VOUT = GND (25°C only) VCCN = VCCQ = Max, All Input Selects Open Com’l Mil/Ind –50 –500 200 50 –200 –250 85 90 14 –50 Test Conditions VCC = Min IOH = – 16 mA VCC = Min, IOH =–40 mA VCC = Min, IOL = 46 mA VCC = Min, IOL = 46 mA 2.0 –0.5 VCC – 0.85 VCC/2 – 500 mV 0.0 VCC 0.8 VCC VCC/2 + 500 mV 0.85 10 –500 200 50 –200 N/A 85 90 19 mA VCC – 1.35 –0.5 VCC – 0.85 VCC/2 – 500 mV 0.0 0.45 0.45 VCC 1.35 VCC VCC/2 + 500 mV 0.85 10 V V V V V μA μA μA μA μA mA mA Min 2.4 VCC –0.75 V Max CY7B992 Min Max Unit V ICCN VCCN = VCCQ = Max, IOUT = 0 mA Input Selects Open, fMAX VCCN = VCCQ = Max, IOUT = 0 mA Input Selects Open, fMAX PD 78 104[11] mW Notes 6. For more information see “Group A Subgroup Testing” on page 17. 7. These inputs are normally wired to VCC, GND, or left unconnected (actual threshold voltages vary as a percentage of VCC). Internal termination resistors hold unconnected inputs at VCC/2. If these inputs are switched, the function and timing of the outputs may glitch and the PLL may require an additional tLOCK time before all datasheet limits are achieved. 8. CY7B991 must be tested one output at a time, output shorted for less than one second, less than 10% duty cycle. Room temperature only. CY7B992 outputs must not be shorted to GND. Doing so may cause permanent damage. 9. Total output current per output pairis approximated by the following expression that includes device current plus load current: CY7B991: ICCN = [(4 + 0.11F) + [((835 – 3F)/Z) + (.0022FC)]N] x 1.1 CY7B992: ICCN = [(3.5+ 0.17F) + [((1160 – 2.8F)/Z) + (.0025FC)]N] x 1.1 Where F = frequency in MHz; C = capacitive load in pF; Z = line impedance in ohms; N = number of loaded outputs; 0, 1, or 2; FC = F < C. 10. Total power dissipation per output pair can be approximated by the following expression that includes device power dissipation plus power dissipation due to the load circuit: CY7B991:PD = [(22 + 0.61F) + [((1550 – 2.7F)/Z) + (.0125FC)]N] x 1.1 CY7B992:PD = [(19.25+ 0.94F) + [((700 + 6F)/Z) + (.017FC)]N] x 1.1 See note 9 for variable definition. 11. Applies to REF and FB inputs only. Tested initially and after any design or process changes that may affect these parameters. Document Number: 38-07138 Rev. *B Page 6 of 19 CY7B991 CY7B992 Capacitance CMOS output buffer current and power dissipation specified at 50 MHz reference frequency. Parameter CIN Description Input Capacitance Test Conditions TA = 25°C, f = 1 MHz, VCC = 5.0V Max 10 Unit pF AC Test Loads and Waveforms 5V R1 CL R2 R1=130 R2=91 CL = 50 pF (CL =30 pF for –2 and –5 devices) (Includes fixture and probe capacitance) 2.0V Vth =1.5V 0.8V 0.0V ≤1ns 3.0V 2.0V Vth =1.5V 0.8V ≤1ns TTL AC Test Load (CY7B991) VCC R1 CL R1=100 R2=100 CL = 50 pF (CL =30 pF for –2 and –5 devices) (Includes fixture and probe capacitance) TTL Input Test Waveform (CY7B991) VCC 80% Vth = VCC/2 20% 0.0V ≤3ns 80% Vth = VCC/2 20% ≤3ns R2 CMOS AC Test Load (CY7B992) CMOS Input Test Waveform (CY7B992) Document Number: 38-07138 Rev. *B Page 7 of 19 CY7B991 CY7B992 Switching Characteristics Over the Operating Range[2, 13] CY7B991–2[14] Parameter fNOM Description Operating Clock Frequency in MHz FS = LOW [1, 2] CY7B992–2[14] Min 15 25 40 5.0 5.0 See Table 1 Typ Max 30 50 80[15] ns ns 0.05 0.1 0.25 0.3 0.25 0.5 0.20 0.25 0.5 0.5 0.5 0.7 0.75 –0.25 –0.5 0.0 0.0 +0.25 +0.5 3.0 3.0 0.5 0.5 2.0 2.0 2.5 2.5 0.5 25 200 ns ns ns ns ns ns ns ns ns ns ns ns ns ms ps ps Unit MHz 30 50 80 Min 15 25 40 5.0 5.0 Typ Max FS = MID[1, 2] FS = HIGH[1, 2 , 3] tRPWH tRPWL tU tSKEWPR tSKEW0 tSKEW1 tSKEW2 tSKEW3 tSKEW4 tDEV tPD tODCV tPWH tPWL tORISE tOFALL tLOCK tJR REF Pulse Width HIGH REF Pulse Width LOW Programmable Skew Unit Zero Output Matched-Pair Skew (XQ0, XQ1)[16, 17] Zero Output Skew (All Outputs)[16, 18,19] Output Skew (Rise-Rise, Fall-Fall, Same Class Outputs)[16, 19] Output Skew (Rise-Fall, Nominal-Inverted, Divided-Divided)[16, 19] Output Skew (Rise-Rise, Fall-Fall, Different Class Outputs)[16, 19] Output Skew (Rise-Fall, Nominal-Divided, Divided-Inverted)[16, 19] Device-to-Device Skew[14, 21] Propagation Delay, REF Rise to FB Rise Output Duty Cycle Variation[22] 50%[23, 24] Output HIGH Time Deviation from 50%[23, 24] Output LOW Time Deviation from Output Rise Output Fall Time[23, 25] Time[23, 25] RMS[14] Peak-to-Peak[14] 0.05 0.1 0.25 0.3 0.25 0.5 0.20 0.25 0.5 0.5 0.5 0.9 0.75 –0.25 –0.65 0.0 0.0 +0.25 +0.65 2.0 1.5 0.15 0.15 1.0 1.0 1.2 1.2 0.5 25 200 PLL Lock Time[26] Cycle-to-Cycle Output Jitter Notes 12. CMOS output buffer current and power dissipation specified at 50 MHz reference frequency. 13. Test measurement levels for the CY7B991 are TTL levels (1.5V to 1.5V). Test measurement levels for the CY7B992 are CMOS levels (VCC/2 to VCC/2). Test conditions assume signal transition times of 2 ns or less and output loading as shown in the AC Test Loads and Waveforms unless otherwise specified. 14. Guaranteed by statistical correlation. Tested initially and after any design or process changes that affect these parameters. 15. Except as noted, all CY7B992–2 and –5 timing parameters are specified to 80 MHz with a 30 pF load. 16. SKEW is defined as the time between the earliest and the latest output transition among all outputs for which the same tU delay is selected when all are loaded with 50 pF and terminated with 50Ω to 2.06V (CY7B991) or VCC/2 (CY7B992). 17. tSKEWPR is defined as the skew between a pair of outputs (XQ0 and XQ1) when all eight outputs are selected for 0tU. 18. tSKEW0 is defined as the skew between outputs when they are selected for 0tU. Other outputs are divided or inverted but not shifted. 19. CL=0 pF. For CL=30 pF, tSKEW0=0.35 ns. 20. There are three classes of outputs: Nominal (multiple of tU delay), Inverted (4Q0 and 4Q1 only with 4F0 = 4F1 = HIGH), and Divided (3Qx and 4Qx only in Divide-by-2 or Divide-by-4 mode). 21. tDEV is the output-to-output skew between any two devices operating under the same conditions (VCC ambient temperature, air flow, and so on.) 22. tODCV is the deviation of the output from a 50% duty cycle. Output pulse width variations are included in tSKEW2 and tSKEW4 specifications. 23. Specified with outputs loaded with 30 pF for the CY7B99X–2 and –5 devices and 50 pF for the CY7B99X–7 devices. Devices are terminated through 50Ω to 2.06V (CY7B991) or VCC/2 (CY7B992). 24. tPWH is measured at 2.0V for the CY7B991 and 0.8 VCC for the CY7B992. tPWL is measured at 0.8V for the CY7B991 and 0.2 VCC for the CY7B992. 25. tORISE and tOFALL measured between 0.8V and 2.0V for the CY7B991 or 0.8VCC and 0.2VCC for the CY7B992. 26. tLOCK is the time that is required before synchronization is achieved. This specification is valid only after VCC is stable and within normal operating limits. This parameter is measured from the application of a new signal or frequency at REF or FB until tPD is within specified limits. Document Number: 38-07138 Rev. *B Page 8 of 19 CY7B991 CY7B992 Switching Characteristics Over the Operating Range[2, 13] (continued) CY7B991–5 Parameter fNOM Description Operating Clock Frequency in MHz FS = LOW FS = MID [1, 2] [1, 2] [1, 2 , 3] CY7B992–5 Max 30 50 80 Min 15 25 40 5.0 5.0 See Table 1 Typ Max 30 50 80[15] ns ns Unit MHz Min 15 25 40 5.0 5.0 Typ FS = HIGH tRPWH tRPWL tU tSKEWPR tSKEW0 tSKEW1 tSKEW2 tSKEW3 tSKEW4 tDEV tPD tODCV tPWH tPWL tORISE tOFALL tLOCK tJR REF Pulse Width HIGH REF Pulse Width LOW Programmable Skew Unit Zero Output Matched-Pair Skew (XQ0, XQ1)[16, 17] Zero Output Skew (All Outputs)[16, 18] 0.1 0.25 0.6 0.5 0.5 0.5 0.25 0.5 0.7 1.0 0.7 1.0 1.25 0.1 0.25 0.6 0.6 0.5 0.6 0.25 0.5 0.7 1.5 0.7 1.7 1.25 ns ns ns ns ns ns ns ns ns ns ns ns ns ms ps ps Output Skew (Rise-Rise, Fall-Fall, Same Class Outputs)[16, 19] Output Skew (Rise-Fall, Nominal-Inverted, Divided-Divided)[16, 19] Output Skew (Rise-Rise, Fall-Fall, Different Class Outputs)[16, 19] Output Skew (Rise-Fall, Nominal-Divided, Divided-Inverted)[16, 19] Device-to-Device Skew[14, 21] Propagation Delay, REF Rise to FB Rise Output Duty Cycle Variation[22] 50%[23, 24] 50%[23, 24] 0.15 0.15 [14] –0.5 –1.0 0.0 0.0 +0.5 +1.0 2.5 3 –0.5 –1.2 0.0 0.0 +0.5 +1.2 4.0 4.0 Output HIGH Time Deviation from Output LOW Time Deviation from Output Rise Time Output Fall [23, 25] 1.0 1.0 1.5 1.5 0.5 0.5 0.5 2.0 2.0 3.5 3.5 0.5 25 200 Time[23, 25] [26] PLL Lock Time Cycle-to-Cycle Output Jitter RMS 25 200 Peak-to-Peak[14] Document Number: 38-07138 Rev. *B Page 9 of 19 CY7B991 CY7B992 Switching Characteristics Over the Operating Range[2, 13] (continued) CY7B991–7 Parameter fNOM Description Operating Clock Frequency in MHz FS = LOW FS = MID [1, 2] [1, 2] CY7B992–7 Max 30 50 80 Min 15 25 40 5.0 5.0 See Table 1 Typ Max 30 50 80[15] ns ns 0.1 0.3 0.6 1.0 0.7 1.2 0.25 0.75 1.0 1.5 1.2 1.7 1.65 –0.7 –1.5 0.0 0.0 +0.7 +1.5 5.5 5.5 0.5 0.5 3.0 3.0 5.0 5.0 0.5 25 200 ns ns ns ns ns ns ns ns ns ns ns ns ns ms ps ps Unit MHz Min 15 25 40 5.0 5.0 Typ FS = HIGH[1, 2] tRPWH tRPWL tU tSKEWPR tSKEW0 tSKEW1 tSKEW2 tSKEW3 tSKEW4 tDEV tPD tODCV tPWH tPWL tORISE tOFALL tLOCK tJR REF Pulse Width HIGH REF Pulse Width LOW Programmable Skew Unit Zero Output Matched-Pair Skew (XQ0, XQ1)[16, 17] Zero Output Skew (All Outputs)[16, 18] Output Skew (Rise-Rise, Fall-Fall, Same Class Outputs)[16, 19] Output Skew (Rise-Fall, Nominal-Inverted, Divided-Divided)[16, 19] Output Skew (Rise-Rise, Fall-Fall, Different Class Outputs)[16, 19] Output Skew (Rise-Fall, Nominal-Divided, Divided-Inverted)[16, 19] Device-to-Device Skew[14, 22] Propagation Delay, REF Rise to FB Rise Output Duty Cycle Variation[22] Output HIGH Time Deviation from 50%[23, 24] Output LOW Time Deviation from 50%[23, 24] Output Rise Output Fall PLL Lock Time[23, 25] 0.1 0.3 0.6 1.0 0.7 1.2 0.25 0.75 1.0 1.5 1.2 1.7 1.65 –0.7 –1.2 0.0 0.0 +0.7 +1.2 3 3.5 0.15 0.15 RMS[14] Peak-to-Peak[14] 1.5 1.5 2.5 2.5 0.5 25 200 Time[23, 25] Time[26] Cycle-to-Cycle Output Jitter Document Number: 38-07138 Rev. *B Page 10 of 19 CY7B991 CY7B992 AC Timing Diagrams tREF tRPWH REF tPD tODCV tRPWL tODCV FB tJR Q tSKEWPR, tSKEW0, 1 OTHER Q tSKEWPR, tSKEW0, 1 tSKEW2 INVERTED Q tSKEW3, 4 tSKEW3, 4 REF DIVIDED BY 2 tSKEW1,3, 4 REF DIVIDED BY 4 tSKEW2 tSKEW3, 4 tSKEW2, 4 Document Number: 38-07138 Rev. *B Page 11 of 19 CY7B991 CY7B992 Operational Mode Descriptions Figure 2. Zero Skew and Zero Delay Clock Driver REF L1 Z0 LOAD SYSTEM CLOCK FB REF FS 4F0 4F1 3F0 3F1 2F0 2F1 1F0 1F1 TEST LENGTH L1 = L2 = L3 = L4 4Q0 4Q1 3Q0 3Q1 2Q0 2Q1 1Q0 1Q1 LOAD L2 Z0 LOAD Z0 L4 Z0 LOAD L3 Figure 2 shows the PSCB configured as a zero skew clock buffer. In this mode the 7B991/992 is used as the basis for a low-skew clock distribution tree. When all of the function select inputs (xF0, xF1) are left open, the outputs are aligned and each drives a terminated transmission line to an independent load. The FB input is tied to any output in this configuration and the operating frequency range is selected with the FS pin. The low-skew specification, coupled with the ability to drive terminated transmission lines (with impedances as low as 50 ohms), enables efficient printed circuit board design. Figure 3. Programmable Skew Clock Driver REF Z0 LOAD L1 SYSTEM CLOCK FB REF FS 4F0 4F1 3F0 3F1 2F0 2F1 1F0 1F1 TEST 4Q0 4Q1 3Q0 3Q1 2Q0 2Q1 1Q0 1Q1 LENGTH L1 = L2 L3 < L2 by 6 inches L4 > L2 by 6 inches LOAD L2 Z0 LOAD Z0 L4 Z0 LOAD L3 Figure 3 shows a configuration to equalize skew between metal traces of different lengths. In addition to low skew between outputs, the PSCB is programmed to stagger the timing of its outputs. Each of the four groups of output pairs are programmed to different output timing. Skew timing is adjusted over a wide range in small increments with the appropriate strapping of the function select pins. In this configuration the 4Q0 output is fed Document Number: 38-07138 Rev. *B back to FB and configured for zero skew. The other three pairs of outputs are programmed to yield different skews relative to the feedback. By advancing the clock signal on the longer traces or retarding the clock signal on shorter traces, all loads can receive the clock pulse at the same time. In this illustration the FB input is connected to an output with 0-ns skew (xF1, xF0 = MID) selected. The internal PLL synchronizes Page 12 of 19 CY7B991 CY7B992 the FB and REF inputs and aligns their rising edges to ensure that all outputs have precise phase alignment. Clock skews are advanced by ±6 time units (tU) when using an output selected for zero skew as the feedback. A wider range of delays is possible if the output connected to FB is also skewed. Since “Zero Skew”, +tU, and –tU are defined relative to output groups, and since the PLL aligns the rising edges of REF and FB, you can create wider output skews by proper selection of the xFn inputs. For example, a +10 tU between REF and 3Qx is achieved by connecting 1Q0 to FB and setting 1F0 = 1F1 = GND, 3F0 = MID, and 3F1 = High. (Since FB aligns at –4 tU and 3Qx skews to +6 tU, a total of +10 tU skew is realized.) Many other configurations are realized by skewing both the outputs used as the FB input and skewing the other outputs. Figure 4. Inverted Output Connections REF F Figure 5. Frequency Multiplier with Skew Connectrions REF FB REF FS 4F0 4F1 3F0 3F1 2F0 2F1 1F0 1F1 TEST 20 MHz 4Q0 4Q1 3Q0 3Q1 2Q0 2Q1 1Q0 1Q1 40 MHz 20 MHz 80 MHz FB REF FS 4F0 4F1 3F0 3F1 2F0 2F1 1F0 1F1 TEST 4Q0 4Q1 3Q0 3Q1 2Q0 2Q1 1Q0 1Q1 Figure 5 shows the PSCB configured as a clock multiplier. The 3Q0 output is programmed to divide by four and is sent to FB. This causes the PLL to increase its frequency until the 3Q0 and 3Q1 outputs are locked at 20 MHz while the 1Qx and 2Qx outputs run at 80 MHz. The 4Q0 and 4Q1 outputs are programmed to divide by two, that results in a 40 MHz waveform at these outputs. Note that the 20 and 40 MHz clocks fall simultaneously and are out of phase on their rising edge. This enables the designer to use the rising edges of the 1⁄2 frequency and 1⁄4 frequency outputs without concern for rising edge skew. The 2Q0, 2Q1, 1Q0, and 1Q1 outputs run at 80 MHz and are skewed by programming their select inputs accordingly. Note that the FS pin is wired for 80 MHz operation because that is the frequency of the fastest output. Figure 6. Frequency Divider Connections REF Figure 4 shows an example of the invert function of the PSCB. In this example the 4Q0 output used as the FB input is programmed for invert (4F0 = 4F1 = HIGH) while the other three pairs of outputs are programmed for zero skew. When 4F0 and 4F1 are tied high, 4Q0 and 4Q1 become inverted zero phase outputs. The PLL aligns the rising edge of the FB input with the rising edge of the REF. This causes the 1Q, 2Q, and 3Q outputs to become the “inverted” outputs with respect to the REF input. It is possible to have 2 inverted and 6 non-inverted outputs or 6 inverted and 2 non-inverted outputs by selecting the output connected to FB. The correct configuration is determined by the need for more (or fewer) inverted outputs. 1Q, 2Q, and 3Q outputs can also be skewed to compensate for varying trace delays independent of inversion on 4Q. 20 MHz FB REF FS 4F0 4F1 3F0 3F1 2F0 2F1 1F0 1F1 TEST 4Q0 4Q1 3Q0 3Q1 2Q0 2Q1 1Q0 1Q1 10 MHz 5 MHz 20 MHz Figure 6 demonstrates the PSCB in a clock divider application. 2Q0 is fed back to the FB input and programmed for zero skew. 3Qx is programmed to divide by four. 4Qx is programmed to divide by two. Note that the falling edges of the 4Qx and 3Qx outputs are aligned. This enables the use of rising edges of the 1⁄ frequency and 1⁄ frequency without concern for skew 2 4 mismatch. The 1Qx outputs are programmed to zero skew and are aligned with the 2Qx outputs. In this example, the FS input is grounded to configure the device in the 15 MHz to 30 MHz Document Number: 38-07138 Rev. *B Page 13 of 19 CY7B991 CY7B992 range since the highest frequency output is running at 20 MHz. Figure 7 shows some of the functions that are selectable on the 3Qx and 4Qx outputs. These include inverted outputs and outputs that offer divide-by-2 and divide-by-4 timing. An inverted output enables the system designer to clock different subsystems on opposite edges, without suffering from the pulse asymmetry typical of non-ideal loading. This function enables each of the two subsystems to clock 180 degrees out of phase and align within the skew specifications. The divided outputs offer a zero delay divider for portions of the system that need the clock divided by either two or four, and still remain within a narrow skew of the “1X” clock. Without this feature, an external divider is added, and the propagation delay of the divider adds to the skew between the different clock signals. These divided outputs, coupled with the Phase Locked Loop, enables the PSCB to multiply the clock rate at the REF input by either two or four. This mode enables the designer to distribute a low frequency clock between various portions of the system, and then locally multiply the clock rate to a more suitable frequency, still maintaining the low skew characteristics of the clock driver. The PSCB performs all of the functions described in this section at the same time. It multiplies by two and four or divides by two (and four) at the same time. In other words, it is shifting its outputs over a wide range or maintaining zero skew between selected outputs. Figure 7. Multi-Function Clock Driver REF Z0 20 MHz DISTRIBUTION CLOCK FB REF FS 4F0 4F1 3F0 3F1 2F0 2F1 1F0 1F1 TEST 4Q0 4Q1 3Q0 3Q1 2Q0 2Q1 1Q0 1Q1 80 MHz INVERTED LOAD 20 MHz Z0 LOAD 80 MHz ZERO SKEW 80 MHz SKEWED –3.125 ns (–4tU) Z0 LOAD Z0 LOAD Document Number: 38-07138 Rev. *B Page 14 of 19 CY7B991 CY7B992 Figure 8. Board-to-Board Clock Distribution REF Z0 L1 FB SYSTEM CLOCK REF FS 4F0 4F1 3F0 3F1 2F0 2F1 1F0 1F1 TEST Z0 L2 Z0 LOAD LOAD 4Q0 4Q1 3Q0 3Q1 2Q0 2Q1 1Q0 1Q1 L4 FB REF FS 4F0 4F1 3F0 3F1 2F0 2F1 1F0 1F1 TEST L3 Z0 LOAD 4Q0 4Q1 3Q0 3Q1 2Q0 2Q1 1Q0 1Q1 LOAD LOAD Figure 8 shows the CY7B991 and 992 connected in series to construct a zero skew clock distribution tree between boards. Delays of the downstream clock buffers are programmed to compensate for the wire length (that is, select negative skew equal to the wire delay) necessary to connect them to the master clock source, approximating a zero delay clock tree. Cascaded clock buffers accumulates low frequency jitter because of the non-ideal filtering characteristics of the PLL filter. Do not connect more than two clock buffers in series. Document Number: 38-07138 Rev. *B Page 15 of 19 CY7B991 CY7B992 Ordering Information Accuracy (ps) 250 500 Ordering Code CY7B991–2JC CY7B991–2JCT CY7B991–5JC CY7B991–5JCT CY7B991–5JI CY7B991–5JIT 750 CY7B991–7JC CY7B991–7JCT CY7B991–7JI CY7B991–7LMB[27] 250 500 CY7B992–2JC CY7B992–2JCT CY7B992–5JC CY7B992–5JCT CY7B992–5JI[27] CY7B992–5JIT 750 CY7B992–7JC CY7B992–7JCT CY7B992–7JI CY7B992–7LMB[27] Pb-Free 250 500 CY7B991–2JXC CY7B991–2JXCT CY7B991–5JXC CY7B991–5JXCT CY7B991–5JXI CY7B991–5JXIT 750 500 CY7B991–7JXC CY7B991–7JXCT CY7B992–5JXI CY7B992–5JXIT 32-Pb Plastic Leaded Chip Carrier 32-Pb Plastic Leaded Chip Carrier - Tape and Reel 32-Pb Plastic Leaded Chip Carrier 32-Pb Plastic Leaded Chip Carrier - Tape and Reel 32-Pb Plastic Leaded Chip Carrier 32-Pb Plastic Leaded Chip Carrier - Tape and Reel 32-Pb Plastic Leaded Chip Carrier 32-Pb Plastic Leaded Chip Carrier - Tape and Reel 32-Pb Plastic Leaded Chip Carrier 32-Pb Plastic Leaded Chip Carrier - Tape and Reel Commercial Commercial Commercial Commercial Industrial Industrial Commercial Commercial Industrial Industrial Package Type 32-Pb Plastic Leaded Chip Carrier 32-Pb Plastic Leaded Chip Carrier - Tape and Reel 32-Pb Plastic Leaded Chip Carrier 32-Pb Plastic Leaded Chip Carrier - Tape and Reel 32-Pb Plastic Leaded Chip Carrier 32-Pb Plastic Leaded Chip Carrier - Tape and Reel 32-Pb Plastic Leaded Chip Carrier 32-Pb Plastic Leaded Chip Carrier - Tape and Reel 32-Pb Plastic Leaded Chip Carrier 32-Pin Rectangular Leadless Chip Carrier 32-Pb Plastic Leaded Chip Carrier 32-Pb Plastic Leaded Chip Carrier - Tape and Reel 32-Pb Plastic Leaded Chip Carrier 32-Pb Plastic Leaded Chip Carrier - Tape and Reel 32-Pb Plastic Leaded Chip Carrier 32-Pb Plastic Leaded Chip Carrier - Tape and Reel 32-Pb Plastic Leaded Chip Carrier 32-Pb Plastic Leaded Chip Carrier - Tape and Reel 32-Pb Plastic Leaded Chip Carrier 32-Pin Rectangular Leadless Chip Carrier Operating Range Commercial Commercial Commercial Commercial Industrial Industrial Commercial Commercial Industrial Military Commercial Commercial Commercial Commercial Industrial Industrial Commercial Commercial Industrial Military Note 27. Not recommended for the new design. Document Number: 38-07138 Rev. *B Page 16 of 19 CY7B991 CY7B992 Military Specifications Group A Subgroup Testing DC Characteristics Parameter VOH VOL VIH VIL VIHH VIMM VILL IIH IIL IIHH IIMM IILL ICCQ ICCN Subgroups 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3 Package Diagrams Figure 9. 32-Pin Plastic Leaded Chip Carrier 51-85002-*B Document Number: 38-07138 Rev. *B Page 17 of 19 CY7B991 CY7B992 Package Diagrams (continued) Figure 10. 32-Pin Rectangular Leadless Chip Carrier MIL-STD-1835 C-12 51-85002-*B Document Number: 38-07138 Rev. *B Page 18 of 19 CY7B991 CY7B992 Document History Document Title: CY7B991/CY7B992 Programmable Skew Clock Buffer Document Number: 38-07138 REV. ** *A *B ECN NO. 110247 1199925 1286064 Issue Date 12/19/01 Orig. of Change SZV Description of Change Change from Specification number: 38-00513 to 38-07138 See ECN KVM/AESA Add Pb-free part numbers. Update package names in Ordering Information table. Remove Pentium reference on page 1. See ECN AESA Change status to final © Cypress Semiconductor Corporation, 2001-2007. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. 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The inclusion of Cypress’ product in a life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. Use may be limited by and subject to the applicable Cypress software license agreement. Document Number: 38-07138 Rev. *B Revised June 22, 2007 Page 19 of 19 PSoC Designer™, Programmable System-on-Chip™, and PSoC Express™ are trademarks and PSoC® is a registered trademark of Cypress Semiconductor Corp. All other trademarks or registered trademarks referenced herein are property of the respective corporations. Purchase of I2C components from Cypress or one of its sublicensed Associated Companies conveys a license under the Philips I2C Patent Rights to use these components in an I2C system, provided that the system conforms to the I2C Standard Specification as defined by Philips. All products and company names mentioned in this document may be the trademarks of their respective holders.