CY7C9915-5JXC

PRELIMINARY CY7C9915 3.3V Programmable Skew Clock Buffer Features • All output pair skew L2 by 6 inches LOAD L2 Z0 LOAD Z0 L4 Z0 LOAD L3 Figure 3. Programmable-Skew Clock Driver Figure 3 shows a configuration to equalize skew between metal traces of different lengths. In addition to low skew between outputs, the LVPSCB can be programmed to stagger the timing of its outputs. The four groups of output pairs can each be programmed to different output timing. Skew timing can be adjusted over a wide range in small increments with the appropriate strapping of the function select pins. In this configuration the 4Q0 output is fed back to FB and configured for zero skew. The other three pairs of outputs are programmed to yield different skews relative to the feedback. By advancing the clock signal on the longer traces or retarding the clock signal on shorter traces, all loads can receive the clock pulse Document #: 38-07687 Rev. *A at the same time. In this illustration the FB input is connected to an output with 0-ns skew (xF1, xF0 = MID) selected. The internal PLL synchronizes the FB and REF inputs and aligns their rising edges to insure that all outputs have precise phase alignment. Clock skews can be advanced by ±6 time units (tU) when using an output selected for zero skew as the feedback. A wider range of delays is possible if the output connected to FB is also skewed. Since “Zero Skew”, +tU, and –tU are defined relative to output groups, and since the PLL aligns the rising edges of REF and FB, it is possible to create wider output skews by Page 4 of 14 PRELIMINARY proper selection of the xFn inputs. For example a +10 tU between REF and 3Qx can be achieved by connecting 1Q0 to FB and setting 1F0 = 1F1 = GND, 3F0 = MID, and 3F1 = High. (Since FB aligns at –4 tU and 3Qx skews to +6 tU, a total of +10 tU skew is realized.) Many other configurations can be realized by skewing both the output used as the FB input and skewing the other outputs. REF CY7C9915 1Qx and 2Qx outputs run at 80 MHz. The 4Q0 and 4Q1 outputs are programmed to divide by two, which results in a 40-MHz waveform at these outputs. Note that the 20- and 40-MHz clocks fall simultaneously and are out of phase on their rising edge. This will allow the designer to use the rising edges of the 1⁄2 frequency and 1⁄4 frequency outputs without concern for rising-edge skew. The 2Q0, 2Q1, 1Q0, and 1Q1 outputs run at 80 MHz and are skewed by programming their select inputs accordingly. Note that the FS pin is wired for 80-MHz operation because that is the frequency of the fastest output. REF FB REF FS 4F0 4F1 3F0 3F1 2F0 2F1 1F0 1F1 TEST 4Q0 4Q1 3Q0 3Q1 2Q0 2Q1 1Q0 1Q1 20 MHz FB REF FS 4F0 4F1 3F0 3F1 2F0 2F1 1F0 1F1 TEST 4Q0 4Q1 3Q0 3Q1 2Q0 2Q1 1Q0 1Q1 10 MHz 5 MHz 20 MHz Figure 4. Inverted Output Connections Figure 4 shows an example of the invert function of the LVPSCB. In this example the 4Q0 output used as the FB input is programmed for invert (4F0 = 4F1 = HIGH) while the other three pairs of outputs are programmed for zero skew. When 4F0 and 4F1 are tied HIGH, 4Q0 and 4Q1 become inverted zero phase outputs. The PLL aligns the rising edge of the FB input with the rising edge of the REF. This causes the 1Q, 2Q, and 3Q outputs to become the “inverted” outputs with respect to the REF input. By selecting which output is connect to FB, it is possible to have 2 inverted and 6 non-inverted outputs or 6 inverted and 2 non-inverted outputs. The correct configuration would be determined by the need for more (or fewer) inverted outputs. 1Q, 2Q, and 3Q outputs can also be skewed to compensate for varying trace delays independent of inversion on 4Q. REF FB REF FS 4F0 4F1 3F0 3F1 2F0 2F1 1F0 1F1 TEST Figure 6. Frequency Divider Connections Figure 6 demonstrates the LVPSCB in a clock divider application. 2Q0 is fed back to the FB input and programmed for zero skew. 3Qx is programmed to divide by four. 4Qx is programmed to divide by two. Note that the falling edges of the 4Qx and 3Qx outputs are aligned. This allows use of the rising edges of the 1⁄2 frequency and 1⁄4 frequency without concern for skew mismatch. The 1Qx outputs are programmed to zero skew and are aligned with the 2Qx outputs. In this example, the FS input is grounded to configure the device in the 15- to 30-MHz range since the highest frequency output is running at 20 MHz. Figure 7 shows some of the functions that are selectable on the 3Qx and 4Qx outputs. These include inverted outputs and outputs that offer divide-by-2 and divide-by-4 timing. An inverted output allows the system designer to clock different subsystems on opposite edges, without suffering from the pulse asymmetry typical of non-ideal loading. This function allows the two subsystems to each be clocked 180 degrees out of phase, but still to be aligned within the skew spec. The divided outputs offer a zero-delay divider for portions of the system that need the clock to be divided by either two or four, and still remain within a narrow skew of the “1X” clock. Without this feature, an external divider would need to be added, and the propagation delay of the divider would add to the skew between the different clock signals. These divided outputs, coupled with the Phase Locked Loop, allow the LVPSCB to multiply the clock rate at the REF input by either two or four. This mode will enable the designer to distribute a low-frequency clock between various portions of the system, and then locally multiply the clock rate to a more suitable frequency, while still maintaining the low-skew characteristics of the clock driver. The LVPSCB can perform all of the functions described above at the same time. It can multiply by Page 5 of 14 20 MHz 4Q0 4Q1 3Q0 3Q1 2Q0 2Q1 1Q0 1Q1 40 MHz 20 MHz 80 MHz Figure 5. Frequency Multiplier with Skew Connections Figure 5 illustrates the LVPSCB configured as a clock multiplier. The 3Q0 output is programmed to divide by four and is fed back to FB. This causes the PLL to increase its frequency until the 3Q0 and 3Q1 outputs are locked at 20 MHz while the Document #: 38-07687 Rev. *A PRELIMINARY two and four or divide by two (and four) at the same time that it is shifting its outputs over a wide range or maintaining zero skew between selected outputs. REF Z0 27.5-MHz DISTRIBUTION CLOCK FB REF FS 4F0 4F1 3F0 3F1 2F0 2F1 1F0 1F1 TEST 4Q0 4Q1 3Q0 3Q1 2Q0 2Q1 1Q0 1Q1 110-MHz INVERTED LOAD 27.5-MHz Z0 LOAD 110-MHz ZERO SKEW 110-MHz SKEWED –2.273 ns (–4tU) Z0 LOAD Z0 CY7C9915 LOAD Figure 7. Multi-Function Clock Driver LOAD Z0 L1 FB SYSTEM CLOCK REF FS 4F0 4F1 3F0 3F1 2F0 2F1 1F0 1F1 TEST Z0 L2 Z0 LOAD 4Q0 4Q1 3Q0 3Q1 2Q0 2Q1 1Q0 1Q1 L4 FB REF FS 4F0 4F1 3F0 3F1 2F0 2F1 1F0 1F1 TEST REF L3 Z0 LOAD 4Q0 4Q1 3Q0 3Q1 2Q0 2Q1 1Q0 1Q1 LOAD LOAD Figure 8. Board-to-Board Clock Distribution Figure 8 shows the CY7C9915 connected in series to construct a zero-skew clock distribution tree between boards. Delays of the downstream clock buffers can be programmed to compensate for the wire length (i.e., select negative skew equal to the wire delay) necessary to connect them to the master clock source, approximating a zero-delay clock tree. Cascaded clock buffers will accumulate low-frequency jitter because of the non-ideal filtering characteristics of the PLL filter. It is recommended that not more than two clock buffers be connected in series. Document #: 38-07687 Rev. *A Page 6 of 14 PRELIMINARY Absolute Maximum Conditions Parameter VDD VIN VIN LUI TS TA TA TJ ESDh MSL UL–94 FIT TPU CIN ZOUT Description Supply Voltage Input Voltage REF Input Voltage Except REF Latch-up Immunity Temperature, Storage Temperature, Operating Ambient Temperature, Operating Ambient Junction Temperature ESD Protection (Human Body Model) Moisture Sensitivity Level Flammability Rating Failure in Time Power-up time for all VDDs to reach minimum specified voltage (power ramps must be monotonic) Input Capacitance[4] Output Impedance TA = 25°C, f = 1 MHz, VCC = 3.3V Low to High (Rising edge) High to Low (Falling edge) @ 1/8 in. Manufacturing test 0.05 Condition Nonfunctional Relative to VCC Relative to VCC Functional Nonfunctional Commercial Temperature Industrial Temperature Industrial Temperature 2000 MSL – 3 V–0 10 –65 0 –40 Min. –0.5 –0.5 –0.5 300 CY7C9915 Max. 4.6 4.6 VDD + 0.5 +125 +70 +85 125 Unit VDC VDC VDC mA °C °C °C °C V Class class ppm 500 ms – 27 7 10 pF Ω Ω Electrical Characteristics Over the Operating Range [5] CY7C9915 Parameter VCCQ VCCN[1:4] VOH VOL VIH VIL VIHH VIMM VILL IIH Description Core Power Supply Output Buffer Power Supply Output HIGH Voltage Output LOW Voltage Input HIGH Voltage (REF and FB inputs only)[6] Input LOW Voltage (REF and FB inputs only)[6] Three-Level Input HIGH Voltage (Test, FS, xFn)[7] Three-Level Input MID Voltage (Test, FS, xFn)[7] Three-Level Input LOW Voltage (Test, FS, xFn)[7] Input HIGH Leakage Current (REF and FB inputs only) Min. ≤ VCC ≤ Max. Min. ≤ VCC ≤ Max. Min. ≤ VCC ≤ Max. VCC = Max., VIN = Max. Test Conditions @3.3V ± 10% @3.3V ± 10% VCC = Min., IOH = – 20 mA VCC = Min., IOL = 36 mA Min. 2.97 2.97 2.4 – 2.0 –0.5 0.87 * VCC 0.47 * VCC 0.0 – Max. 3.63 3.63 – 0.45 VCC 0.8 VCC 0.53 * VCC 0.13 * VCC 10 Unit V V V V V V V V V µA Notes: 4. Applies to REF and FB inputs only. Tested initially and after any design or process changes that may affect these parameters. 5. See the last page of this specification for Group A subgroup testing information. 6. VIH and VIL for FB inputs guaranteed by statistical correlation. Tested initially and after any design or process changes that may affect this parameters. Document #: 38-07687 Rev. *A Page 7 of 14 PRELIMINARY Electrical Characteristics Over the Operating Range (continued)[5] CY7C9915 Parameter IIL IIHH IIMM IILL IOS ICCQ ICCN PD Description Input LOW Leakage Current (REF and FB inputs only) Input HIGH Current (Test, FS, xFn) Input MID Current (Test, FS, xFn) Input LOW Current (Test, FS, xFn) Short Circuit Current[8] Operating Current Used by Internal Circuitry Output Buffer Current per Output Pair[9] Power Dissipation per Output Pair[10] Test Conditions VCC = Max., VIN = 0.4V VIN = VCC VIN = VCC/2 VIN = GND VCC = MAX, VOUT = GND (25° only) VCCN = VCCQ = Max., All Com’l Input Selects Open Industrial VCCN = VCCQ = Max., IOUT = 0 mA Input Selects Open, fMAX VCCN = VCCQ = Max., IOUT = 0 mA Input Selects Open, fMAX Min. –10 – –50 – – – – – – CY7C9915 Max. – 200 50 –200 –200 90 100 14 78 Unit µA µA µA µA mA mA mA mA mW AC Test Loads and Waveforms VCC R1 CL R1=100 R2=100 CL = 30 pF (Includes fixture and probe capacitance) 2.0V Vth =1.5V 0.8V 0.0V ≤1ns 3.0V 2.0V Vth =1.5V 0.8V ≤1ns R2 TTL AC Test Load TTL Input Test Waveform AC Input Specifications Parameter TR,TF TPWC TDCIN FREF Description Input Rise/Fall Edge Rate Input Clock Pulse[11] Input Duty Cycle Reference Input Frequency 0.8V – 2.0V HIGH or LOW Test Mode FS=LOW FS=MID FS=HIGH Condition Min. – 2 10 30 3.75 6.25 10 Max. 10 – 90 70 30 50 150[12] Unit ns/V ns % % MHz Notes: 7. These inputs are normally wired to VCC, GND, or left unconnected (actual threshold voltages vary as a percentage of VCC). Internal termination resistors hold unconnected inputs at VCC/2. If these inputs are switched, the function and timing of the outputs may glitch and the PLL may require an additional tLOCK time before all data sheet limits are achieved. 8. CY7C9915 should be tested one output at a time, output shorted for less than one second, less than 10% duty cycle. Room temperature only. 9. Total output current per output pair can be approximated by the following expression that includes device current plus load current: CY7C9915:ICCN = [(4 + 0.11F) + [[((835 –3F)/Z) + (.0022FC)]N] x 1.1 Where F = frequency in MHz C = capacitive load in pF Z = line impedance in ohms N = number of loaded outputs; 0, 1, or 2 FC = F ∗ C 10. Total power dissipation per output pair can be approximated by the following expression that includes device power dissipation plus power dissipation due to the load circuit: PD = [(22 + 0.61F) + [[(1550 + 2.7F)/Z) + (.0125FC)]N] x 1.1 See note 9 for variable definition. 11. The minimum input clock pulse (HIGH or LOW) is the greater of the two parameters. Therefore, below 50MHz the limit is 10%; above 50MHz the limit is 2ns. 12. In test mode, Max REF input frequency is 133MHz. Document #: 38-07687 Rev. *A Page 8 of 14 PRELIMINARY Switching Characteristics Over the Operating Range [2, 13] CY7C9915 CY7C9915-1 Parameter fNOM Operating Clock Frequency in MHz Description FS = LOW[1, 2] FS = MID[1, 2] FS = HIGH[1, 2 ] FS = LOW FS = MID FS = HIGH Min. 15 25 40 3.75 6.25 10 160 – – – – – – – – –0.15 47 0.15 0.15 – Divided-Divided)[14, 19] Typ. – – – – – – – 1 0.05 0.1 0.1 0.3 0.25 0.25 – – 50 0.5 0.5 – – – – – – – – – Max. 30 50 150 30 50 150 650 – 0.1 0.2 0.3 0.5 0.5 0.5 0.75 +0.15 53 1.2 1.2 0.5 15 30 100 200 25 50 150 300 Unit MHz FOUT Output Frequency MHz FVCO FBW tU tSKEWPR tSKEW0 tSKEW1 tSKEW2 tSKEW3 tSKEW4 tDEV tPD tODC tORISE tOFALL tLOCK tJR VCO Frequency Loop Bandwidth Programmable Skew Unit Zero Output Matched-Pair Skew (XQ0, XQ1)[14, 16] Zero Output Skew (All Outputs)[14, 17,18] Output Skew (Rise-Rise, Fall-Fall, Same Class Outputs)[14, 19] Output Skew (Rise-Fall, Nominal-Inverted, Output Skew (Rise-Rise, Fall-Fall, Different Class Outputs)[14, 19] Output Skew (Rise-Fall, Nominal-Divided, Divided-Inverted)[14, 19] Device-to-Device Skew[15, 20] Propagation Delay, REF Rise to FB Rise Output Duty Cycle[21] Output Rise PLL Lock Time[22] Output Fall Time[22] Time[23] RMS, fNOM > 22MHz[15] RMS, fNOM < 22MHz[15] Peak, fNOM > 22MHz[15] Peak, fNOM < 22MHz[15] Cycle-to-Cycle Output Jitter MHz MHz ns ns ns ns ns ns ns ns % ns ns ms ps ps ps See Table 1 – – – – – – – – tPJ Period Jitter RMS, fNOM > 22MHz[15] RMS, fNOM < 22MHz[15] Peak-to-Peak, fNOM > 22 MHz[15] Peak-to-Peak, fNOM < 22 MHz[15] ps Notes: 13. Test measurement levels for the CY7C9915 are TTL levels (1.5V to 1.5V). Test conditions assume signal transition times of 2 ns or less and output loading as shown in the AC Test Loads and Waveforms unless otherwise specified. 14. SKEW is defined as the time between the earliest and the latest output transition among all outputs for which the same tU delay has been selected when all are loaded with 30 pF and terminated with TTL AC Test Load. 15. Guaranteed by statistical correlation. Tested initially and after any design or process changes that may affect these parameters. 16. tSKEWPR is defined as the skew between a pair of outputs (XQ0 and XQ1) when all eight outputs are selected for 0tU. 17. tSKEW0 is defined as the skew between all outputs when they are selected for 0tU. Other outputs are divided or inverted but not shifted. 18. CL=0 pF. For CL=30 pF, tSKEW0=0.35 ns. 19. There are three classes of outputs: Nominal (multiple of tU delay), Inverted (4Q0 and 4Q1 only with 4F0 = 4F1 = HIGH), and Divided (3Qx and 4Qx only in Divide-by-2 or Divide-by-4 mode). 20. tDEV is the output-to-output skew between the same outputs of any two devices operating under the same conditions (VCC ambient temperature, air flow, etc.) 21. tODC is measure at VCCN/2. 22. Specified with outputs loaded with 30 pF. tORISE and tOFALL measured between 0.8V and 2.0V. 23. tLOCK is the time that is required before synchronization is achieved. This specification is valid only after VCC is stable and within normal operating limits. This parameter is measured from the application of a new signal or frequency at REF or FB until tPD is within specified limits. Document #: 38-07687 Rev. *A Page 9 of 14 PRELIMINARY Switching Characteristics Over the Operating Range [2, 13] CY7C9915 CY7C9915-2 Parameter fNOM Operating Clock Frequency in MHz Description FS = LOW [1, 2] Min. 15 25 40 3.75 6.25 10 160 – – – Outputs)[14, 19] Outputs)[14, 19] – – – – – –0.25 47 0.15 0.15 – Typ. – – – – – – – 1 0.05 0.1 0.1 0.3 0.25 0.25 – – 50 0.5 0.5 – – – – – – – – – Max. 30 50 150 30 50 150 650 – 0.2 0.25 0.5 1.0 0.5 0.9 1.0 +0.25 53 1.2 1.2 0.5 15 30 100 200 25 50 150 300 Unit MHz FS = MID[1, 2] FS = HIGH[1, 2 ] FS=LOW FS=MID FS=HIGH FOUT Output Frequency MHz FVCO FBW tU tSKEWPR tSKEW0 tSKEW1 tSKEW2 tSKEW3 tSKEW4 tDEV tPD tODC tORISE tOFALL tLOCK tJR VCO Frequency Loop Bandwidth Programmable Skew Unit Zero Output Matched-Pair Skew (XQ0, XQ1)[14, 16] Zero Output Skew (All Outputs) [14, 17,18] MHz MHz ns ns ns ns ns ns ns ns % ns ns ms ps ps ps See Table 1 Output Skew (Rise-Rise, Fall-Fall, Same Class Output Skew (Rise-Fall, Nominal-Inverted, Divided-Divided)[14, 19] Output Skew (Rise-Rise, Fall-Fall, Different Class Output Skew (Rise-Fall, Nominal-Divided, Device-to-Device Skew[15, 20] Propagation Delay, REF Rise to FB Rise Output Duty Cycle[21] Output Rise Output Fall Time[22, 22] Time[22, 22] RMS, fNOM > 22MHz[15] RMS, fNOM < Peak, fNOM < 22MHz[15] 22MHz[15] 22MHz[15] Peak, fNOM > 22MHz[15] Divided-Inverted)[14, 19] PLL Lock Time[23] Cycle-to-Cycle Output Jitter – – – – – – – – tPJ Period Jitter RMS, fNOM > 22MHz[15] RMS, fNOM < Peak-to-Peak, fNOM > 22 MHz[15] Peak-to-Peak, fNOM < 22 MHz[15] ps Switching Characteristics Over the Operating Range [2, 13] CY7C9915-5 Parameter fNOM Operating Clock Frequency in MHz Description FS = LOW[1, 2] FS = MID[1, 2] FS = FOUT Output Frequency HIGH[1, 2 ] FS=LOW FS=MID FS=HIGH FVCO VCO Frequency Min. 15 25 40 3.75 6.25 10 160 Typ. – – – – – – – Max. 30 50 150 30 50 150 650 MHz MHz Unit MHz Document #: 38-07687 Rev. *A Page 10 of 14 PRELIMINARY Switching Characteristics Over the Operating Range (continued)[2, 13] CY7C9915 CY7C9915-5 Parameter FBW tU tSKEWPR tSKEW0 tSKEW1 tSKEW2 tSKEW3 tSKEW4 tDEV tPD tODC tORISE tOFALL tLOCK tJR Loop Bandwidth Programmable Skew Unit Description Min. – [14, 16] Typ. 1 0.05 0.1 0.1 0.3 0.25 0.25 – – 50 0.5 0.5 – – – – – – – – – Max. – 0.25 0.5 0.7 1.0 0.7 1.0 1.25 +0.5 55 1.2 1.2 0.5 15 30 100 200 25 50 150 300 Unit MHz ns ns ns ns ns ns ns ns % ns ns ms ps ps ps See Table 1 – – [14, 19] Zero Output Matched-Pair Skew (XQ0, XQ1) Zero Output Skew (All Outputs)[14, 17,18] Output Skew (Rise-Rise, Fall-Fall, Same Class Outputs) – – – – – –0.5 45 0.15 0.15 – Output Skew (Rise-Fall, Nominal-Inverted, Divided-Divided)[14, 19] Output Skew (Rise-Rise, Fall-Fall, Different Class Outputs) Device-to-Device Skew[15, 20] Propagation Delay, REF Rise to FB Rise Output Duty Cycle[21] Output Rise Time[22, 22] Output Fall Time[22, 22] PLL Lock Time[23] Cycle-to-Cycle Output Jitter RMS, fNOM > 22MHz[15] RMS, fNOM < Peak, fNOM < 22MHz[15] 22MHz[15] Peak, fNOM > 22MHz[15] [14, 19] [14, 19] Output Skew (Rise-Fall, Nominal-Divided, Divided-Inverted) – – – – – – – – tPJ Period Jitter RMS, fNOM > 22MHz[15] RMS, fNOM < 22MHz[15] Peak-to-Peak, fNOM > 22MHz[15] Peak-to-Peak, fNOM < 22MHz[15] ps Document #: 38-07687 Rev. *A Page 11 of 14 PRELIMINARY AC Timing Diagrams tREF tPWC REF tPD tODC tPWC CY7C9915 tODC FB tJR Q tSKEWPR, tSKEW0, 1 OTHER Q tSKEWPR, tSKEW0, 1 tSKEW2 INVERTED Q tSKEW3, 4 tSKEW3, 4 REF DIVIDED BY 2 tSKEW1,3, 4 REF DIVIDED BY 4 tSKEW2 tSKEW3, 4 tSKEW2, 4 Ordering Information Ordering Code CY7C9915-1JXC CY7C9915-1JXI CY7C9915-2JXC CY7C9915-2JXI CY7C9915-5JXC CY7C9915-5JXI 32-Lead PLCC 32-Lead PLCC 32-Lead PLCC 32-Lead PLCC 32-Lead PLCC 32-Lead PLCC Package Type Operating Range Commercial, 0°C to 70°C Industrial, –40°C to 85°C Commercial, 0°C to 70°C Industrial, –40°C to 85°C Commercial, 0°C to 70°C Industrial, –40°C to 85°C Document #: 38-07687 Rev. *A Page 12 of 14 PRELIMINARY Package Drawing and Dimensions 32-Lead Plastic Leaded Chip Carrier J65 CY7C9915 51-85002-*B All product and company names mentioned in this document are trademarks of their respective holders. Document #: 38-07687 Rev. *A Page 13 of 14 © Cypress Semiconductor Corporation, 2005. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. PRELIMINARY Document History Page Document Title: CY7C9915 3.3V Programmable Skew Clock Buffer Document Number: 38-07687 REV. ** *A ECN NO. 236268 357435 Issue Date See ECN See ECN Orig. of Change RGL RGL New Data Sheet Description of Change CY7C9915 Clarified minimum input pulse width and tDEV. Added two slower speed grades (-2 and -5). Switching Characteristics (-1 speed grade): tightened tSKEW4, tORISE and tOFALL typ. values and max. limits; relaxed tODC; relaxed tJR and tPJ below 22 MHz; eliminated phase jitter spec. Corrected AC Timing Diagrams. Document #: 38-07687 Rev. *A Page 14 of 14