CY7C1071DV33-12BAXI

CY7C1071DV33 32-Mbit (2 M × 16) Static RAM 32-Mbit (2 M × 16) Static RAM Features ■ Functional Description The CY7C1071DV33 is a high performance CMOS Static RAM organized as 2,097,152 words by 16 bits. The input and output pins (I/O0 through I/O15) are placed in a high impedance state when: ■ ■ ■ ■ High speed ❐ tAA = 12 ns Low active power ❐ ICC = 250 mA at 12 ns Low Complementary Metal Oxide Semiconductor (CMOS) standby power ❐ ISB2 = 50 mA Operating voltages of 3.3 ± 0.3 V 2.0 V data retention Automatic power down when deselected TTL compatible inputs and outputs Available in Pb-free 48-ball FBGA package ■ ■ Deselected (CE HIGH) Outputs are disabled (OE HIGH) Both byte high enable and byte low enable are disabled (BHE, BLE HIGH) The write operation is active (CE LOW and WE LOW) ■ ■ ■ ■ ■ To write to the device, take Chip Enable (CE) and Write Enable (WE) inputs LOW. If Byte Low Enable (BLE) is LOW, then data from I/O pins (I/O0 through I/O7) is written into the location specified on the address pins (A0 through A20). If Byte High Enable (BHE) is LOW, then data from I/O pins (I/O8 through I/O15) is written into the location specified on the address pins (A0 through A20). To read from the device, take Chip Enable (CE) and Output Enable (OE) LOW while forcing the Write Enable (WE) HIGH. If Byte Low Enable (BLE) is LOW, then data from the memory location specified by the address pins appears on I/O0 to I/O7. If Byte High Enable (BHE) is LOW, then data from memory appears on I/O8 to I/O15. See the Truth Table on page 10 for a complete description of read and write modes. Logic Block Diagram DATA IN DRIVERS ROW DECODER A(10:0) 2M × 16 SENSE AMPS RAM ARRAY IO0–IO7 IO8–IO15 COLUMN DECODER BHE WE CE OE BLE A(20:11) Cypress Semiconductor Corporation Document Number: 001-12063 Rev. *H • 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600 Revised May 28, 2011 [+] Feedback CY7C1071DV33 Contents Selection Guide ................................................................ 3 Pin Configuration ............................................................. 3 Maximum Ratings ............................................................. 4 Operating Range ............................................................... 4 DC Electrical Characteristics .......................................... 4 Capacitance ...................................................................... 4 Thermal Resistance .......................................................... 4 Data Retention Characteristics ....................................... 5 AC Switching Characteristics ......................................... 6 Switching Waveforms ...................................................... 7 Truth Table ...................................................................... 10 Ordering Information ...................................................... 10 Ordering Code Definitions ......................................... 10 Package Diagram ............................................................ 11 Acronyms ........................................................................ 12 Document Conventions ................................................. 12 Units of Measure ....................................................... 12 Document History Page ................................................. 13 Sales, Solutions, and Legal Information ...................... 14 Worldwide Sales and Design Support ....................... 14 Products .................................................................... 14 PSoC Solutions ......................................................... 14 Document Number: 001-12063 Rev. *H Page 2 of 14 [+] Feedback CY7C1071DV33 Selection Guide Description Maximum Access Time Maximum Operating Current Maximum CMOS Standby Current -12 12 250 50 Unit ns mA mA Pin Configuration Figure 1. 48-ball FBGA [1] 1 BLE IO8 IO9 VSS VCC IO14 IO15 A18 2 OE BHE IO10 IO11 IO12 IO13 A20 A8 3 A0 A3 A5 A17 NC A14 A12 A9 4 A1 A4 A6 A7 A16 A15 A13 A10 5 A2 CE IO1 IO3 IO4 IO5 WE A11 6 NC IO0 IO2 VCC VSS IO6 IO7 A19 A B C D E F G H Note 1. NC pins are not connected to the die. Document Number: 001-12063 Rev. *H Page 3 of 14 [+] Feedback CY7C1071DV33 Maximum Ratings Exceeding maximum ratings may impair the useful life of the device. These user guidelines are not tested. Storage Temperature ............................... –65 C to +150 C Ambient Temperature with Power Applied ......................................... –55 C to +125 C Supply Voltage on VCC Relative to GND [2] ...............................–0.3 V to +4.6 V DC Voltage Applied to Outputs in High Z State [2] ................................. –0.5 V to VCC + 0.5 V DC Input Voltage[2] ............................. –0.5 V to VCC + 0.5 V Current into Outputs (LOW) ........................................ 20 mA Static Discharge Voltage ......................................... > 2001 V (MIL-STD-883, Method 3015) Latch up Current .................................................... > 200 mA Operating Range Range Industrial Ambient Temperature –40 C to +85C VCC 3.3 V  0.3 V DC Electrical Characteristics Over the Operating Range Parameter VOH VOL VIH VIL IIX IOZ ICC ISB1 ISB2 Description Output HIGH Voltage Output LOW Voltage Input HIGH Voltage Input LOW Voltage[2] GND < VI < VCC GND < VOUT < VCC, Output Disabled VCC = Max, f = fmax = 1/tRC, IOUT = 0 mA CMOS levels Max VCC, CE > VIH, VIN > VIH or VIN < VIL, f = fmax Max VCC, CE > VCC – 0.3 V, VIN > VCC – 0.3 V, or VIN < 0.3 V, f = 0, VCC = VCC(max) Input Leakage Current Output Leakage Current VCC Operating Supply Current Automatic CE Power Down Current – TTL Inputs Automatic CE Power Down Current – CMOS Inputs Test Conditions VCC = Min, IOH = –4.0 mA VCC = Min, IOL = 8.0 mA -12 Min 2.4 – 2.0 –0.3 –1 –1 – – – Max – 0.4 VCC + 0.3 0.8 +1 +1 250 60 50 Unit V V V V A A mA mA mA Capacitance Parameter[3] CIN COUT Description Input Capacitance I/O Capacitance Test Conditions TA = 25 C, f = 1 MHz, VCC = 3.3 V Max 16 20 Unit pF pF Thermal Resistance Parameter[3] JA JC Description Thermal Resistance (Junction to Ambient) Thermal Resistance (Junction to Case) Test Conditions Still air, soldered on a 3 × 4.5 inch, four-layer printed circuit board 48-ball FBGA 24.72 5.79 Unit C/W C/W Notes 2. VIL (min) = –2.0 V and VIH(max) = VCC + 1 V for pulse durations of less than 20 ns. 3. Tested initially and after any design or process changes that may affect these parameters. Document Number: 001-12063 Rev. *H Page 4 of 14 [+] Feedback CY7C1071DV33 Figure 2. AC Test Loads and Waveforms[4] 50  OUTPUT Z0 = 50  (a) * CAPACITIVE LOAD CONSISTS OF ALL COMPONENTS OF THE TEST ENVIRONMENT ALL INPUT PULSES 90% 10% VTH = 1.5 V 30 pF* HIGH-Z CHARACTERISTICS: R1 317  3.3 V OUTPUT 5 pF* INCLUDING JIG AND SCOPE (b) R2 351 3.0 V GND 90% 10% RISE TIME: > 1 V/ns (c) FALL TIME: > 1 V/ns Data Retention Characteristics Over the Operating Range Parameter VDR ICCDR tCDR[5] tR[6] Description VCC for Data Retention Data Retention Current Chip Deselect to Data Retention Time Operation Recovery Time Figure 3. Data Retention Waveform VCC = 2 V, CE > VCC – 0.2 V, VIN > VCC – 0.2 V or VIN < 0.2 V Conditions Min 2 – 0 tRC Typ – – – – Max – 50 – – Unit V mA ns ns DATA RETENTION MODE VCC CE 3.0 V tCDR VDR > 2 V 3.0 V tR Notes 4. Valid SRAM operation does not occur until the power supplies reach the minimum operating VDD (3.0 V). 100 s (tpower) after reaching the minimum operating VDD, normal SRAM operation begins to include reduction in VDD to the data retention (VCCDR, 2.0 V) voltage. 5. Tested initially and after any design or process changes that may affect these parameters. 6. Full device operation requires linear VCC ramp from VDR to VCC(min) > 50 s or stable at VCC(min) > 50 s. Document Number: 001-12063 Rev. *H Page 5 of 14 [+] Feedback CY7C1071DV33 AC Switching Characteristics Over the Operating Range [7] Parameter Read Cycle tpower tRC tAA tOHA tACE tDOE tLZOE tHZOE tLZCE tHZCE tPU tPD tDBE tLZBE tHZBE Write tWC tSCE tAW tHA tSA tPWE tSD tHD tLZWE tHZWE tBW VCC(typ) to the first access[8] Read Cycle Time Address to Data Valid Data Hold from Address Change CE LOW to Data Valid OE LOW to Data Valid OE LOW to Low CE LOW to Low Z[9] Z[9] Z[9] Up[10] Down[10] Z[9] Z[9] Z[9] OE HIGH to High CE HIGH to High 100 12 – 3 – – 1 – 3 – 0 – – 1 – 12 9 9 0 0 9 7 0 3 – 9 – – 12 – 12 7 – 7 – 7 – 12 7 – 7 – – – – – – – – – 7 – s ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns Description -12 Min Max Unit CE LOW to Power CE HIGH to Power Byte Enable to Data Valid Byte Enable to Low Cycle[11, 12] Write Cycle Time CE LOW to Write End Address Setup to Write End Address Hold from Write End Address Setup to Write Start WE Pulse Width Data Setup to Write End Data Hold from Write End WE HIGH to Low WE LOW to High Z[9] Z[9] Byte Disable to High Byte Enable to End of Write Notes 7. Test conditions are based on signal transition time of 3 ns or less and timing reference levels of 1.5 V and input pulse levels of 0 to 3.0 V. Test conditions for the read cycle use output loading shown in part (a) of Figure 2 on page 5, unless specified otherwise. 8. tpower is the minimum amount of time that the power supply must be at typical VCC values until the first memory access can be performed. 9. tHZOE, tHZCE, tHZWE, tHZBE and tLZOE, tLZCE, tLZWE, tLZBE are specified with a load capacitance of 5 pF as in (b) of Figure 2 on page 5. Transition is measured at ±200 mV from steady-state voltage. 10. These parameters are guaranteed by design and are not tested. 11. The internal memory write time is defined by the overlap of CE, WE = VIL. Chip enables must be active and WE and byte enables must be LOW to initiate a write, and the transition of any of these signals can terminate the write. The input data setup and hold timing must be referenced to the leading edge of the signal that terminates the write. 12. The minimum write cycle time for Write Cycle 2 (WE controlled, OE LOW) is the sum of tHZWE and tSD. Document Number: 001-12063 Rev. *H Page 6 of 14 [+] Feedback CY7C1071DV33 Switching Waveforms Figure 4. Read Cycle 1 (Address Transition Controlled)[13, 14] tRC ADDRESS tOHA DATA OUT PREVIOUS DATA VALID tAA DATA VALID Figure 5. Read Cycle 2 (OE Controlled)[14, 15] ADDRESS tRC CE tACE OE tDOE BHE, BLE tLZOE tDBE tLZBE DATA OUT VCC SUPPLY CURRENT HIGH IMPEDANCE tLZCE tPU 50% DATA VALID tPD 50% tHZCE tHZBE tHZOE HIGH IMPEDANCE ICC ISB Notes 13. Device is continuously selected. OE, CE, BHE or BHE or both = VIL. 14. WE is HIGH for read cycle. 15. Address valid before or similar to CE transition LOW. Document Number: 001-12063 Rev. *H Page 7 of 14 [+] Feedback CY7C1071DV33 Switching Waveforms (continued) Figure 6. Write Cycle 1 (CE Controlled)[16, 17] tWC ADDRESS tSA CE tAW tSCE tHA tPWE WE tBW BHE, BLE tSD DATA I/O tHD Figure 7. Write Cycle 2 (WE Controlled, OE LOW)[16, 17] tWC ADDRESS tSCE CE tAW tSA WE tBW BHE, BLE tHZWE DATA I/O tLZWE tSD tHD tPWE tHA Notes 16. Data I/O is high impedance if OE or BHE, BLE or both = VIH. 17. If CE goes HIGH simultaneously with WE going HIGH, the output remains in a high impedance state. Document Number: 001-12063 Rev. *H Page 8 of 14 [+] Feedback CY7C1071DV33 Switching Waveforms (continued) Figure 8. Write Cycle 3 (BLE or BHE Controlled) tWC ADDRESS BHE, BLE tSA tBW tAW tPWE WE tSCE CE tSD DATA I/O tHD tHA Document Number: 001-12063 Rev. *H Page 9 of 14 [+] Feedback CY7C1071DV33 Truth Table CE H L L L L L L L OE X L L L X X X H WE X H H H L L L H BLE X L L H L L H X BHE X L H L L H L X I/O0–IO7 High Z Data Out Data Out High Z Data In Data In High Z High Z I/O8–I/O15 High Z Data Out High Z Data Out Data In High Z Data In High Z Power-down Read All Bits Read Lower Bits Only Read Upper Bits Only Write All Bits Write Lower Bits Only Write Upper Bits Only Selected, Outputs Disabled Mode Power Standby (ISB) Active (ICC) Active (ICC) Active (ICC) Active (ICC) Active (ICC) Active (ICC) Active (ICC) Ordering Information Speed (ns) 12 Ordering Code CY7C1071DV33-12BAXI Package Diagram Package Type Operating Range Industrial 51-85191 48-ball FBGA (8 × 9.5 × 1.2 mm) (Pb-free) Ordering Code Definitions CY 7 C 1 07 1 D V33 - 12 BAX I Temperature Range: I = Industrial Package Type: BAX = 48-ball FBGA (Pb-free) Speed: 12 ns V33 = Voltage range (3 V to 3.6 V) D = C9, 90 nm Technology 1 = Data width × 16-bits 07 = 32-Mbit density 1 = Fast Asynchronous SRAM family Technology Code: C = CMOS 7 = SRAM CY = Cypress Document Number: 001-12063 Rev. *H Page 10 of 14 [+] Feedback CY7C1071DV33 Package Diagram Figure 9. 48-ball FBGA (8 × 9.5 × 1.2 mm) BA48J, 51-85191 51-85191 *A Document Number: 001-12063 Rev. *H Page 11 of 14 [+] Feedback CY7C1071DV33 Acronyms Acronym CE CMOS FPBGA I/O OE SRAM TTL WE chip enable complementary metal oxide semiconductor fine-pitch ball grid array input/output output enable static random access memory transistor transistor logic write enable Description Document Conventions Units of Measure Symbol °C MHz µA µs mA mm ms mV ns  Unit of Measure degree Celcius Mega Hertz micro Amperes micro seconds milli Amperes milli meter milli seconds milli Volts nano seconds ohms percent pico Farad Volts Watts % pF V W Document Number: 001-12063 Rev. *H Page 12 of 14 [+] Feedback CY7C1071DV33 Document History Page Document Title: CY7C1071DV33, 32-Mbit (2 M × 16) Static RAM Document Number: 001-12063 REV. ** *A ECN NO. 605460 1192183 Submission Date See ECN See ECN Orig. of Change VKN New Data sheet Description of Change VKN/KKVTMP Removed CE2 feature Updated block diagram Changed ICC spec from 160 mA to 225 mA Changed CIN spec from 8 pF to 10 pF Changed COUT spec from 10 pF to 12 pF Changed tBW spec from 8 ns to 9 ns VKN/PYRS Added 10 ns speed bin In 12 ns speed bin, changed ISB1 from 70 to 60 mA and ISB2 from 60 to 50 mA Changed CIN from 8 pF to 16 pF and COUT from 10 pF to 20 pF Changed JA from 28.37 C/W to 24.72 C/W Removed 119-Ball PBGA package Added 48-Ball FBGA package Removed 10ns speed Marked thermal specs as “TBD” Changed tDOE, tHZOE, tHZCE, tDBE, tHZBE, tHZWE specs from 6 ns to 7ns Added -12B2XI part (Dual CE option) Changed ICC spec from 225 mA to 250 mA. Converted from Preliminary to Final Removed Dual CE option from the data sheet Updated links in Sales, Solutions, and Legal Information Added Ordering Code Definitions. Added Acronyms and Units of Measure. Changed all instances of IO to I/O. Updated in new template. Updated Functional Description (Removed “For best practice recommendations, refer to the Cypress application note AN1064, SRAM System Guidelines.”). *B 2711136 05/29/2009 *C 2759408 09/03/2009 VKN/AESA *D *E 2813370 2925803 11/23/2009 04/30/2010 VKN VKN/AESA *F *G 3109063 3132969 12/13/2010 01/11/2011 AJU AJU *H 3268861 05/28/2011 AJU Document Number: 001-12063 Rev. *H Page 13 of 14 [+] Feedback CY7C1071DV33 Sales, Solutions, and Legal Information Worldwide Sales and Design Support Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office closest to you, visit us at Cypress Locations. Products Automotive Clocks & Buffers Interface Lighting & Power Control Memory Optical & Image Sensing PSoC Touch Sensing USB Controllers Wireless/RF cypress.com/go/automotive cypress.com/go/clocks cypress.com/go/interface cypress.com/go/powerpsoc cypress.com/go/plc cypress.com/go/memory cypress.com/go/image cypress.com/go/psoc cypress.com/go/touch cypress.com/go/USB cypress.com/go/wireless PSoC Solutions psoc.cypress.com/solutions PSoC 1 | PSoC 3 | PSoC 5 © Cypress Semiconductor Corporation, 2007-2011. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. 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Cypress does not assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress’ product in a life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. Use may be limited by and subject to the applicable Cypress software license agreement. Document Number: 001-12063 Rev. *H Revised May 28, 2011 Page 14 of 14 All products and company names mentioned in this document may be the trademarks of their respective holders. [+] Feedback