CY7C1081DV33-12BAXI

CY7C1081DV33 64-Mbit (4 M × 16) Static RAM Features ■ Functional Description The CY7C1081DV33 is a high-performance CMOS static RAM organized as 4,194,304 words by 16 bits. To write to the device, take Chip Enables (CE1 LOW and CE2 HIGH) and Write Enable (WE) inputs LOW. If Byte Low Enable (BLE) is LOW, then data from I/O pins (I/O0 through I/O7) is written into the location specified on the address pins (A0 through A21). If Byte High Enable (BHE) is LOW, then data from I/O pins (I/O8 through I/O15) is written into the location specified on the address pins (A0 through A21). To read from the device, take Chip Enables (CE1 LOW and CE2 HIGH) and Output Enable (OE) LOW while forcing the Write Enable (WE) HIGH. If Byte Low Enable (BLE) is LOW, then data from the memory location specified by the address pins appears on I/O0 to I/O7. If Byte High Enable (BHE) is LOW, then data from memory appears on I/O8 to I/O15. See the Truth Table on page 9 for a complete description of read and write modes. The input and output pins (I/O0 through I/O15) are placed in a high impedance state when the device is deselected (CE1HIGH or CE2 LOW), the outputs are disabled (OE HIGH), both byte high enable and byte low enable are disabled (BHE, BLE HIGH), or during a write operation (CE1 LOW, CE2 HIGH, and WE LOW). High speed ❐ tAA = 12 ns Low active power ❐ ICC = 300 mA at 12 ns Low complementary metal oxide semiconductor (CMOS) standby power ❐ ISB2 = 100 mA Operating voltages of 3.3 ± 0.3 V 2.0-V data retention Automatic power-down when deselected Transistor-transistor logic (TTL)-compatible inputs and outputs Easy memory expansion with CE1 and CE2 features Available in Pb-free 48-ball fine ball grid array (FBGA) package ■ ■ ■ ■ ■ ■ ■ ■ Logic Block Diagram DATAIN DRIVERS ROW DECODER A(10:0) 4M × 16 SENSE AMPS RAM ARRAY I/O0–I/O7 I/O8–I/O15 COLUMN DECODER BHE WE OE BLE A(21:11) CE2 CE1 Cypress Semiconductor Corporation Document #: 001-53992 Rev. *C • 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600 Revised May 4, 2011 [+] Feedback CY7C1081DV33 Contents Selection Guide ................................................................ Pin Configuration ............................................................. Maximum Ratings............................................................. Operating Range............................................................... DC Electrical Characteristics .......................................... Capacitance ...................................................................... Thermal Resistance.......................................................... Data Retention Characteristics ....................................... AC Switching Characteristics ......................................... Switching Waveforms ...................................................... Truth Table ........................................................................ 3 3 4 4 4 4 4 5 6 7 9 Ordering Information ..................................................... Ordering Code Definition........................................... Package Diagrams ......................................................... Acronyms........................................................................ Document Conventions ................................................. Units of Measure ....................................................... Document History Page................................................. Sales, Solutions, and Legal Information ...................... Worldwide Sales and Design Support....................... Products .................................................................... PSoC Solutions ......................................................... 10 10 11 11 11 11 12 12 12 12 12 Document #: 001-53992 Rev. *C Page 2 of 13 [+] Feedback CY7C1081DV33 Selection Guide Description Maximum access time Maximum operating current Maximum CMOS standby current –12 12 300 100 Unit ns mA mA Pin Configuration Figure 1. 48-Ball FBGA (Top View) 1 BLE I/O8 I/O9 VSS VCC 2 OE BHE I/O10 I/O11 I/O12 3 A0 A3 A5 A17 A21 4 A1 A4 A6 A7 A16 A15 A13 A10 5 A2 CE1 I/O1 I/O3 I/O4 I/O5 WE A11 6 CE2 I/O0 I/O2 VCC VSS I/O6 I/O7 A19 A B C D E F G H I/O14 I/O13 A14 I/O15 A18 A20 A8 A12 A9 Document #: 001-53992 Rev. *C Page 3 of 13 [+] Feedback CY7C1081DV33 Maximum Ratings Exceeding maximum ratings may impair the useful life of the device. These user guidelines are not tested. Storage temperature ..................................... –65 C to +150 C Ambient temperature with power applied ................................................ –55 C to +125 C Supply voltage on VCC relative to GND [1] ........ –0.5 V to +4.6 V DC voltage applied to outputs in high-Z state[1]........................................–0.5 V to VCC + 0.5 V DC input voltage[1] ....................................–0.5 V to VCC + 0.5 V Current into outputs (LOW) ..............................................20 mA Static discharge voltage.................................................>2001 V (MIL-STD-883, Method 3015) Latch up current ...........................................................>140 mA Operating Range Range Industrial Ambient Temperature –40 °C to +85 °C VCC 3.3 V  0.3 V Speed 12 ns DC Electrical Characteristics Over the Operating Range Parameter VOH VOL VIH VIL IIX IOZ ICC ISB1 ISB2 Description Output HIGH voltage Output LOW voltage Input HIGH voltage Input LOW voltage[1] GND < VIN < VCC GND < VOUT < VCC, Output Disabled VCC = Max, f = fmax = 1/tRC, IOUT = 0 mA CMOS levels Max VCC, CE1 > VIH, CE2 < VIL, VIN > VIH or VIN < VIL, f = fmax Max VCC, CE1 > VCC – 0.3 V, CE2 < 0.3 V, VIN > VCC – 0.3 V, or VIN < 0.3 V, f = 0, Input leakage current Output leakage current VCC operating supply current Automatic CE power-down current – TTL inputs Automatic CE power-down current – CMOS inputs Test Conditions VCC = Min, IOH = –4.0 mA VCC = Min, IOL = 8.0 mA –12 Min 2.4 – 2.0 –0.3 –1 –1 – – – Max – 0.4 VCC + 0.3 0.8 +1 +1 300 120 100 Unit V V V V A A mA mA mA Capacitance Tested initially and after any design or process changes that may affect these parameters. Parameter CIN COUT Description Input capacitance I/O capacitance Test Conditions TA = 25 C, f = 1 MHz, VCC = 3.3 V Max 32 40 Unit pF pF Thermal Resistance Tested initially and after any design or process changes that may affect these parameters. Parameter JA JC Description Thermal resistance (junction to ambient) Thermal resistance (junction to case) Test Conditions Still air, soldered on a 3 × 4.5 inch, four-layer printed circuit board FBGA 55 23.04 Unit C/W C/W Note 1. VIL (min) = –2.0 V and VIH(max) = VCC + 2 V for pulse durations of less than 20 ns. Document #: 001-53992 Rev. *C Page 4 of 13 [+] Feedback CY7C1081DV33 Figure 2. AC Test Loads and Waveforms[2] HIGH-Z CHARACTERISTICS: R1 317  3.3 V OUTPUT 5 pF* INCLUDING JIG AND SCOPE (b) 3.0 V GND ALL INPUT PULSES 90% 10% 90% 10% 50  OUTPUT Z0 = 50  (a) * CAPACITIVE LOAD CONSISTS OF ALL COMPONENTS OF THE TEST ENVIRONMENT VTH = 1.5 V 30 pF* R2 351 RISE TIME: > 1 V/ns (c) FALL TIME: > 1 V/ns Data Retention Characteristics Over the Operating Range Parameter VDR ICCDR tCDR[3] tR[4] Description VCC for data retention Data retention current Chip deselect to data retention time Operation recovery time Figure 3. Data Retention Waveform DATA RETENTION MODE VCC CE1 CE2 3.0 V tCDR VDR > 2 V 3.0 V tR Conditions Min 2 Typ – – – – Max – 100 – – Unit V mA ns ns VCC = 2 V, CE1 > VCC – 0.2 V, CE2 < 0.2 V, VIN > VCC – 0.2 V or VIN < 0.2 V – 0 12 Notes 2. Valid SRAM operation does not occur until the power supplies reach the minimum operating VDD (3.0 V). 100 s (tpower) after reaching the minimum operating VDD, normal SRAM operation begins to include reduction in VDD to the data retention (VCCDR, 2.0 V) voltage. 3. Tested initially and after any design or process changes that may affect these parameters. 4. Full device operation requires linear VCC ramp from VDR to VCC(min) > 50 s or stable at VCC(min) > 50 s. Document #: 001-53992 Rev. *C Page 5 of 13 [+] Feedback CY7C1081DV33 AC Switching Characteristics Over the Operating Range [5] Parameter Read Cycle tpower tRC tAA tOHA tACE tDOE tLZOE tHZOE tLZCE tHZCE tPU tPD tDBE tLZBE tHZBE Write Cycle tWC tSCE tAW tHA tSA tPWE tSD tHD tLZWE tHZWE tBW [9, 10] Description –12 Min 100 12 – 3 – – 1 – Max – – 12 – 12 7 – 7 – 7 – 12 7 – 7 – – – – – – – – – 7 – Unit VCC(typ) to the first access [6] Read cycle time Address to data valid Data hold from address change CE1 LOW and CE2 HIGH to Data Valid OE LOW to data valid OE LOW to low-Z OE HIGH to high-Z [7] [7] [7] [8] [8] s ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns CE1 LOW and CE2 HIGH to low-Z 3 – 0 – – 1 – 12 9 9 0 0 9 7 0 3 – 9 CE1 HIGH and CE2 LOW to high-Z CE1 LOW and CE2 HIGH to power-up Byte enable to data valid Byte enable to low-Z Byte disable to high-Z Write cycle time CE1 LOW and CE2 HIGH to write end Address setup to write end Address hold from write end Address setup to write start WE pulse width Data setup to write end Data hold from write end WE HIGH to low-Z WE LOW to high-Z [7] [7] CE1 HIGH and CE2 LOW to power-down Byte enable to end of write Notes 5. Test conditions are based on signal transition time of 3 ns or less and timing reference levels of 1.5 V and input pulse levels of 0 to 3.0 V. Test conditions for the read cycle use output loading shown in part a) of AC Test Loads and Waveforms[2], unless specified otherwise. 6. tpower is the minimum amount of time that the power supply must be at typical VCC values until the first memory access can be performed. 7. tHZOE, tHZCE, tHZWE, tHZBE and tLZOE, tLZCE, t\LZWE, tLZBE are specified with a load capacitance of 5 pF as in (b) of AC Test Loads and Waveforms[2]. 8. These parameters are guaranteed by design and are not tested. 9. The internal memory write time is defined by the overlap of WE, CE1 = VIL, and CE2 = VIH. Chip enables must be active and WE and byte enables must be LOW to initiate a write, and the transition of any of these signals can terminate the write. The input data setup and hold timing must be referenced to the leading edge of the signal that terminates the write. 10. The minimum write cycle time for Write Cycle 2 (WE controlled, OE LOW) is the sum of tHZWE and tSD. Document #: 001-53992 Rev. *C Page 6 of 13 [+] Feedback CY7C1081DV33 Switching Waveforms Figure 4. Read Cycle 1 (Address Transition Controlled) [11, 12] tRC ADDRESS tOHA DATA OUT PREVIOUS DATA VALID tAA DATA VALID Figure 5. Read Cycle 2 (OE Controlled) [12, 13, 14] ADDRESS tRC CE tACE OE BHE, BLE tDOE tLZOE tDBE tLZBE DATA OUT VCC SUPPLY CURRENT HIGH IMPEDANCE tLZCE tPU 50% DATA VALID tPD 50% tHZCE tHZBE tHZOE HIGH IMPEDANCE ICC ISB Notes 11. Device is continuously selected. OE, CE1 = VIL, BHE or BHE or both = VIL, and CE2 = VIH. 12. WE is HIGH for read cycle. 13. Address valid before or similar to CE1 transition LOW and CE2 transition HIGH. 14. CE refers to the internal logical combination of CE1 and CE2 such that when CE1 is LOW and CE2 is HIGH, CE is LOW. For all other combinations, CE is HIGH. Document #: 001-53992 Rev. *C Page 7 of 13 [+] Feedback CY7C1081DV33 Switching Waveforms (continued) Figure 6. Write Cycle 1 (CE Controlled) [15, 16, 17] tWC ADDRESS tSA CE tAW tSCE tHA tPWE WE t BW BHE, BLE tSD DATA I/O DATAIN VALID tHD Figure 7. Write Cycle 2 (WE Controlled, OE LOW) [15, 16, 17] tWC ADDRESS tSCE CE tAW tSA WE tBW BHE, BLE tHZWE DATA I/O tSD DATAIN VALID tLZWE tHD tPWE tHA Notes 15. CE refers to the internal logical combination of CE1 and CE2 such that when CE1 is LOW and CE2 is HIGH, CE is LOW. For all other combinations, CE is HIGH. 16. Data I/O is high impedance if OE or BHE, BLE or both = VIH. 17. If CE goes HIGH simultaneously with WE going HIGH, the output remains in a high impedance state. Document #: 001-53992 Rev. *C Page 8 of 13 [+] Feedback CY7C1081DV33 Switching Waveforms (continued) Figure 8. Write Cycle 3 (BLE or BHE Controlled) [18] tWC ADDRESS BHE, BLE tSA tBW tAW tPWE WE tSCE CE tSD DATA I/O DATAIN VALID tHD tHA Truth Table CE1 H X L L L L L L L CE2 X L H H H H H H H OE X X L L L X X X H WE X X H H H L L L H BLE BHE X X L L H L L H X X X L H L L H L X I/O0 – I/O7 High-Z High-Z Data Out Data Out High-Z Data In Data In High-Z High-Z I/O8 – I/O15 High-Z High-Z Data Out High-Z Data Out Data In High-Z Data In High-Z Mode Power down Power down Read all bits Read lower bits only Read upper bits only Write all bits Write lower bits only Write upper bits only Selected, Outputs disabled Power Standby (ISB) Standby (ISB) Active (ICC) Active (ICC) Active (ICC) Active (ICC) Active (ICC) Active (ICC) Active (ICC) Note 18. CE refers to the internal logical combination of CE1 and CE2 such that when CE1 is LOW and CE2 is HIGH, CE is LOW. For all other combinations, CE is HIGH. Document #: 001-53992 Rev. *C Page 9 of 13 [+] Feedback CY7C1081DV33 Ordering Information Speed (ns) 12 Ordering Code CY7C1081DV33-12BAXI Package Diagram 001-50044 Package Type 48-Ball FBGA (8 × 9.5 × 1.4 mm) (Pb-free) Operating Range Industrial Ordering Code Definition CY 7 C 1 08 1 D V33 - xx xxx x Temperature Range: x = I I = Industrial Package Type: xxx = BAX BAX = 48-ball FBGA (Pb-free) Speed: xx = 12 ns V33 = Voltage range (3 V to 3.6 V) D = C9, 90 nm Technology 1 = Data width × 16 bits 08 = 64-Mbit density 1 = Fast Asynchronous SRAM family Technology Code: C = CMOS 7 = SRAM CY = Cypress Document #: 001-53992 Rev. *C Page 10 of 13 [+] Feedback CY7C1081DV33 Package Diagram Figure 9. 48-Ball FBGA (8 x 9.5 x 1.4 mm) (001-50044) 001-50044 *C Acronyms Acronym CMOS FBGA I/O SRAM TTL Description complementary metal oxide semiconductor fine ball grid array input/output static random access memory transistor-transistor logic Document Conventions Units of Measure Symbol °C A mA MHz ns pF V  W Unit of Measure degrees Celsius microamperes milliampere megahertz nanoseconds picofarads volts ohms watts Document #: 001-53992 Rev. *C Page 11 of 13 [+] Feedback CY7C1081DV33 Document History Page Document Title: CY7C1081DV33, 64-Mbit (4 M × 16) Static RAM Document Number: 001-53992 REV. ** *A ECN NO. 2746867 3100499 Submission Date 07/31/2009 12/02/2010 Orig. of Change VKN/AESA PRAS New datasheet Updated Note 14. Changed datasheet status from Preliminary to Final. Updated Package Diagram and Sales, Solutions, and Legal Information. Added Acronyms, Document Conventions and Ordering Code Definition. Post to external web Modified Figure 44-B all FBGA pin configuration. Description of Change *B *C 3178249 3246293 21/02/2011 05/04/2011 PRAS PRAS Document #: 001-53992 Rev. *C Page 12 of 13 [+] Feedback CY7C1081DV33 Sales, Solutions, and Legal Information Worldwide Sales and Design Support Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office closest to you, visit us at Cypress Locations. Products Automotive Clocks & Buffers Interface Lighting & Power Control Memory Optical & Image Sensing PSoC Touch Sensing USB Controllers Wireless/RF cypress.com/go/automotive cypress.com/go/clocks cypress.com/go/interface cypress.com/go/powerpsoc cypress.com/go/plc cypress.com/go/memory cypress.com/go/image cypress.com/go/psoc cypress.com/go/touch cypress.com/go/USB cypress.com/go/wireless PSoC Solutions psoc.cypress.com/solutions PSoC 1 | PSoC 3 | PSoC 5 © Cypress Semiconductor Corporation, 2009-2011. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. 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Cypress does not assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress’ product in a life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. Use may be limited by and subject to the applicable Cypress software license agreement. Document #: 001-53992 Rev. *C Revised May 4, 2011 Page 13 of 13 All product and company names mentioned in this document are the trademarks of their respective holders. [+] Feedback