CY7C1079DV33-12BAXI

CY7C1079DV33 32-Mbit (4 M × 8) Static RAM 32-Mbit (4 M × 8) Static RAM Features ■ Functional Description The CY7C1079DV33 is a high performance CMOS Static RAM organized as 4,194,304 words by 8 bits. To write to the device, take Chip Enable (CE [1]) and Write Enable (WE) input LOW. Data on the eight I/O pins (I/O0 through I/O7) is then written into the location specified on the address pins (A0 through A21). To read from the device, take Chip Enable (CE [1]) LOW and Output Enable (OE) LOW while forcing the Write Enable (WE) HIGH. Under these conditions, the contents of the memory location specified by the address pins appear on the I/O pins. See Truth Table (Single Chip Enable) on page 9 for a complete description of Read and Write modes. The input and output pins (I/O0 through I/O7) are placed in a high impedance state when the device is deselected (CE [1] HIGH), the outputs are disabled (OE HIGH), or during a write operation (CE [1] LOW and WE LOW). The CY7C1079DV33 is available in a 48-ball FBGA package. High Speed ❐ tAA = 12 ns Low Active Power ❐ ICC = 250 mA at 12 ns Low CMOS Standby Power ❐ ISB2 = 50 mA Operating Voltages of 3.3 ± 0.3 V 2.0 V Data Retention Automatic Power Down when Deselected TTL Compatible Inputs and Outputs Available in Pb-free 48-ball FBGA Package ■ ■ ■ ■ ■ ■ ■ Logic Block Diagram INPUT BUFFER A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 ROW DECODER SENSE AMPS 4M x 8 ARRAY IO0 – IO7 COLUMN DECODER WE OE CE [1] Note 1. BGA packaged device is offered in single CE and dual CE options. In this data sheet, for a dual CE device, CE refers to the internal logical combination of CE1 and CE2 such that when CE1 is LOW and CE2 is HIGH, CE is LOW. For all other cases CE is HIGH. A10 A11 A 12 A 13 A 14 A15 A16 A17 A18 A19 A20 A21 Cypress Semiconductor Corporation Document Number: 001-50282 Rev. *D • 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600 Revised April 27, 2011 [+] Feedback CY7C1079DV33 Contents Selection Guide ................................................................ 3 Pin Configuration ............................................................. 3 Maximum Ratings ............................................................. 4 Operating Range ............................................................... 4 DC Electrical Characteristics .......................................... 4 Capacitance ...................................................................... 5 Thermal Resistance .......................................................... 5 Data Retention Characteristics ....................................... 5 AC Switching Characteristics ......................................... 6 Switching Waveforms ...................................................... 7 Truth Table (Single Chip Enable) .................................... 9 Truth Table (Dual Chip Enable) ....................................... 9 Ordering Information ...................................................... 10 Ordering Code Definitions ......................................... 10 Package Diagrams .......................................................... 11 Acronyms ........................................................................ 12 Document Conventions ................................................. 12 Units of Measure ....................................................... 12 Document History Page ................................................. 13 Sales, Solutions, and Legal Information ...................... 14 Worldwide Sales and Design Support ....................... 14 Products .................................................................... 14 PSoC Solutions ......................................................... 14 Document Number: 001-50282 Rev. *D Page 2 of 14 [+] Feedback CY7C1079DV33 Selection Guide Description Maximum Access Time Maximum Operating Current Maximum CMOS Standby Current –12 12 250 50 Unit ns mA mA Pin Configuration Figure 1. 48-ball FBGA (Single Chip Enable) [2] Figure 2. 48-ball FBGA (Dual Chip Enable) [2] 1 NC NC IO0 VSS VCC IO3 NC A19 2 OE NC NC IO1 IO2 NC A21 A8 3 A0 A3 A5 A17 A18 A14 A12 A9 4 A1 A4 A6 A7 A16 A15 A13 A10 5 A2 CE NC IO5 IO6 NC WE A11 6 NC NC IO4 VCC VSS IO7 NC A20 A B C D E F G H 1 NC NC IO0 VSS VCC IO3 NC A19 2 OE NC NC IO1 IO2 NC A21 A8 3 A0 A3 A5 A17 A18 A14 A12 A9 4 A1 A4 A6 A7 A16 A15 A13 A10 5 A2 CE1 NC IO5 IO6 NC WE A11 6 CE2 NC IO4 VCC VSS IO7 NC A20 A B C D E F G H Note 2. NC pins are not connected to the die. Document Number: 001-50282 Rev. *D Page 3 of 14 [+] Feedback CY7C1079DV33 Maximum Ratings Exceeding maximum ratings may shorten the useful life of the device. These user guidelines are not tested. Storage Temperature ............................... –65 C to +150 C Ambient Temperature with Power Applied .......................................... –55 C to +125 C Supply Voltage on VCC Relative to GND [3] ..–0.5 V to +4.6 V DC Voltage Applied to Outputs in High Z State [3] ................................. –0.5 V to VCC + 0.5 V DC Input Voltage [3] ............................. –0.5 V to VCC + 0.5 V Current into Outputs (LOW)......................................... 20 mA Static Discharge Voltage.......................................... > 2001 V (MIL-STD-883, Method 3015) Latch Up Current .................................................... > 200 mA Operating Range Range Industrial Ambient Temperature –40 C to +85 C VCC 3.3 V  0.3 V DC Electrical Characteristics Over the Operating Range Parameter VOH VOL VIH VIL IIX IOZ ICC ISB1 ISB2 Description Output HIGH Voltage Output LOW Voltage Input HIGH Voltage Input LOW Voltage [3] Input Leakage Current Output Leakage Current VCC Operating Supply Current Automatic CE Power Down Current — TTL Inputs Automatic CE Power Down Current —CMOS Inputs GND < VI < VCC GND < VOUT < VCC, Output disabled VCC = Max, f = fMAX = 1/tRC, IOUT = 0 mA CMOS levels Max VCC, CE [4] > VIH, VIN > VIH or VIN < VIL, f = fMAX Max VCC, CE [4] > VCC – 0.3 V, VIN > VCC – 0.3 V, or VIN < 0.3 V, f = 0 Test Conditions VCC = Min, IOH = –4.0 mA VCC = Min, IOL = 8.0 mA –12 Min 2.4 – 2.0 –0.3 –1 –1 – – – Max – 0.4 VCC + 0.3 0.8 +1 +1 250 60 50 Unit V V V V A A mA mA mA Notes 3. VIL (min) = –2.0 V and VIH(max) = VCC + 2 V for pulse durations of less than 20 ns. 4. BGA packaged device is offered in single CE and dual CE options. In this data sheet, for a dual CE device, CE refers to the internal logical combination of CE1 and CE2 such that when CE1 is LOW and CE2 is HIGH, CE is LOW. For all other cases CE is HIGH. Document Number: 001-50282 Rev. *D Page 4 of 14 [+] Feedback CY7C1079DV33 Capacitance Tested initially and after any design or process changes that may affect these parameters. Parameter CIN COUT Description Input Capacitance I/O Capacitance Test Conditions TA = 25 C, f = 1 MHz, VCC = 3.3 V 48-ball FBGA 16 20 Unit pF pF Thermal Resistance Tested initially and after any design or process changes that may affect these parameters. Parameter JA JC Description Thermal Resistance (Junction to Ambient) Thermal Resistance (Junction to Case) Figure 3. AC Test Loads and Waveforms[5] 50  OUTPUT Z0 = 50  30 pF* ALL INPUT PULSES 90% 10% 90% 10% VTH = 1.5 V High-Z characteristics 3.3 V OUTPUT 5 pF* 3.0 V GND Rise Time > 1 V/ns INCLUDING JIG AND SCOPE (b) R2 351 R1 317  Test Conditions Still air, soldered on a 3 × 4.5 inch, four layer printed circuit board 48-ball FBGA 30.91 13.60 Unit C/W C/W (a) * Capacitive load consists of all components of the test environment (c) Fall Time: > 1 V/ns Data Retention Characteristics Over the Operating Range Parameter VDR ICCDR tCDR [7] tR [ 8] Description VCC for Data Retention Data Retention Current Chip Deselect to Data Retention Time Operation Recovery Time Conditions VCC = 2 V, CE [6] > VCC – 0.2 V, VIN > VCC – 0.2 V or VIN < 0.2 V Min 2 – 0 tRC Typ – – – – Max – 50 – – Unit V mA ns ns Figure 4. Data Retention Waveform DATA RETENTION MODE VCC CE [6] 3.0 V tCDR VDR > 2 V 3.0 V tR Notes 5. Valid SRAM operation does not occur until the power supplies have reached the minimum operating VDD (3.0 V). 100 s (tpower) after reaching the minimum operating VDD, normal SRAM operation begins including reduction in VDD to the data retention (VCCDR, 2.0 V) voltage. 6. BGA packaged device is offered in single CE and dual CE options. In this data sheet, for a dual CE device, CE refers to the internal logical combination of CE1 and CE2 such that when CE1 is LOW and CE2 is HIGH, CE is LOW. For all other cases CE is HIGH. 7. Tested initially and after any design or process changes that may affect these parameters. 8. Full device operation requires linear VCC ramp from VDR to VCC(min.) > 50 s or stable at VCC(min.) > 50 s. Document Number: 001-50282 Rev. *D Page 5 of 14 [+] Feedback CY7C1079DV33 AC Switching Characteristics Over the Operating Range [9] Parameter Read Cycle tpower tRC tAA tOHA tACE tDOE tLZOE tHZOE tLZCE tHZCE tPU tPD Write Cycle [14, 15] tWC tSCE tAW tHA tSA tPWE tSD tHD tLZWE tHZWE Write Cycle Time CE [11] LOW HIGH to Write End Address Setup to Write End Address Hold from Write End Address Setup to Write Start WE Pulse Width Data Setup to Write End Data Hold from Write End WE HIGH to Low Z WE LOW to High Z [12] [12] Description –12 Min 100 12 – 3 – – 1 – 3 Max – – 12 – 12 7 – 7 – 7 – 12 – – – – – – – – – 7 Unit VCC(Typical) to the First Access [10] Read Cycle Time Address to Data Valid Data Hold from Address Change CE [11]LOW s ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns to Data Valid OE LOW to Data Valid OE LOW to Low Z OE HIGH to High Z [12] CE LOW to Low Z [11, 12] [11, 12] [11, 13] CE HIGH LOW to High Z – 0 – 12 9 9 0 0 9 7 0 3 – CE LOW HIGH to Power Up CE HIGH LOW to Power Down [11, 13] Notes 9. Test conditions assume signal transition time of 3 ns or less, timing reference levels of 1.5 V, and input pulse levels of 0 to 3.0 V. Test conditions for the read cycle use output loading shown in part a) of Figure 3 on page 5, unless specified otherwise. 10. tPOWER gives the minimum amount of time that the power supply is at typical VCC values until the first memory access is performed. 11. BGA packaged device is offered in single CE and dual CE options. In this data sheet, for a dual CE device, CE refers to the internal logical combination of CE1 and CE2 such that when CE1 is LOW and CE2 is HIGH, CE is LOW. For all other cases CE is HIGH. 12. tHZOE, tHZCE, tHZWE, tLZOE, tLZCE, and tLZWE are specified with a load capacitance of 5 pF as in (b) of Figure 3 on page 5. Transition is measured 200 mV from steady state voltage. 13. These parameters are guaranteed by design and are not tested. 14. The internal write time of the memory is defined by the overlap of WE, CE = VIL. CE and WE are LOW to initiate a write, and the transition of any of these signals can terminate. The input data setup and hold timing should be referenced to the edge of the signal that terminates the write. 15. The minimum write cycle time for Write Cycle No. 2 (WE controlled, OE LOW) is the sum of tHZWE and tSD. Document Number: 001-50282 Rev. *D Page 6 of 14 [+] Feedback CY7C1079DV33 Switching Waveforms Figure 5. Read Cycle No. 1 [16, 17] tRC RC ADDRESS tOHA DATA OUT PREVIOUS DATA VALID tAA DATA VALID Figure 6. Read Cycle No. 2 (OE Controlled) [17, 18, 19] tRC ADDRESS CE tACE OE tDOE tLZOE DATA OUT VCC SUPPLY CURRENT HIGH IMPEDANCE tLZCE tPU 50% DATA VALID tPD 50% tHZOE tHZCE HIGH IMPEDANCE ICC ISB Notes 16. The device is continuously selected. CE = VIL. 17. WE is HIGH for read cycle. 18. BGA packaged device is offered in single CE and dual CE options. In this data sheet, for a dual CE device, CE refers to the internal logical combination of CE1 and CE2 such that when CE1 is LOW and CE2 is HIGH, CE is LOW. For all other cases CE is HIGH. 19. Address valid before or similar to CE transition LOW. Document Number: 001-50282 Rev. *D Page 7 of 14 [+] Feedback CY7C1079DV33 Switching Waveforms (continued) Figure 7. Write Cycle No. 1 (CE Controlled) [20, 21, 22] tWC ADDRESS CE tSA tSCE tAW tPWE WE tSD DATA I/O tHD tHA Figure 8. Write Cycle No. 2 (WE Controlled, OE LOW) [20, 21, 22] tWC ADDRESS tSCE CE tAW tSA WE tPWE tHA tHZWE DATA I/O tSD tHD tLZWE Notes 20. BGA packaged device is offered in single CE and dual CE options. In this data sheet, for a dual CE device, CE refers to the internal logical combination of CE1 and CE2 such that when CE1 is LOW and CE2 is HIGH, CE is LOW. For all other cases CE is HIGH. 21. Data I/O is high impedance if OE = VIH. 22. If CE goes HIGH simultaneously with WE going HIGH, the output remains in a high impedance state. Document Number: 001-50282 Rev. *D Page 8 of 14 [+] Feedback CY7C1079DV33 Truth Table (Single Chip Enable) CE [1] H L L L OE X L X H WE X H L H I/O0 – I/O7 High Z Data Out Data In High Z Power Down Read All Bits Write All Bits Selected, Outputs Disabled Mode Standby (ISB) Active (ICC) Active (ICC) Active (ICC) Power Truth Table (Dual Chip Enable) CE1 H X L L L CE2 X L H H H OE X X L X H WE X X H L H I/O0 – I/O7 High Z High Z Data Out Data In High Z Power Down Power Down Read All Bits Write All Bits Selected, Outputs Disabled Mode Standby (ISB) Standby (ISB) Active (ICC) Active (ICC) Active (ICC) Power Document Number: 001-50282 Rev. *D Page 9 of 14 [+] Feedback CY7C1079DV33 Ordering Information Speed (ns) 12 12 Ordering Code CY7C1079DV33-12BAXI CY7C1079DV33-12B2XI Package Diagram Package Type Operating Range Industrial Industrial 51-85191 48-ball FBGA (8 × 9.5 × 1.2 mm) (Pb-free) [23] 51-85191 48-ball FBGA (8 × 9.5 × 1.2 mm) (Pb-free) [24] Contact sales for part availability. Ordering Code Definitions CY 7 C 1 07 9 D V33 - 12 XXX I Temperature Range: I = Industrial Package Type: XXX = BAX or B2X BAX = 48-ball FBGA (Pb-free) - single chip enable B2X = 48-ball FBGA (Pb-free) - dual chip enable Speed: 12 ns V33 = Voltage range (3 V to 3.6 V) D = C9, 90 nm Technology 9 = Data width × 8-bits 07 = 32-Mbit density 1 = Fast Asynchronous SRAM family Technology Code: C = CMOS 7 = SRAM CY = Cypress Notes 23. This BGA package is offered with single chip enable. 24. This BGA package is offered with dual chip enable. Document Number: 001-50282 Rev. *D Page 10 of 14 [+] Feedback CY7C1079DV33 Package Diagrams Figure 9. 48-ball FBGA (8 × 9.5 × 1.2 mm), 51-85191 51-85191 *A Document Number: 001-50282 Rev. *D Page 11 of 14 [+] Feedback CY7C1079DV33 Acronyms Acronym CE CMOS FPBGA I/O OE SRAM TTL WE chip enable complementary metal oxide semiconductor fine-pitch ball grid array input/output output enable static random access memory transistor transistor logic write enable V µA µs mV mA ms mm MHz pF W %  Document Conventions Description Units of Measure Symbol ns nano seconds Volts micro Amperes micro seconds milli Volts milli Amperes milli seconds milli meter Mega Hertz pico Farad Watts percent ohms degree Celcius Unit of Measure °C Document Number: 001-50282 Rev. *D Page 12 of 14 [+] Feedback CY7C1079DV33 Document History Page Document Title: CY7C1079DV33 32-Mbit (4 M × 8) Static RAM Document Number: 001-50282 REV. ** *A ECN NO. 2711136 2759408 Submission Date 05/29/2009 09/03/2009 Orig. of Change Description of Change VKN/PYRS New Data sheetAdded -45B2XI part (Dual CE option) VKN/AESA Removed 10ns speed Marked thermal specs as “TBD” Changed tDOE, tHZOE, tHZCE, tHZWE specs from 6 ns to 7ns Added -12B2XI part (Dual CE option) VKN PRAS Changed ICC spec from 225 mA to 250 mA Added Ordering Code Definitions. Updated Package Diagrams. Added Acronyms and Units of Measure. Changed all instances of IO to I/O. Updated in new template. Changed status from Preliminary to Final. Updated Pin Configuration (Figure 2). Updated Thermal Resistance. *B *C 2813370 3132969 11/23/2009 01/11/2011 *D 3232668 04/18/2011 PRAS Document Number: 001-50282 Rev. *D Page 13 of 14 [+] Feedback CY7C1079DV33 Sales, Solutions, and Legal Information Worldwide Sales and Design Support Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office closest to you, visit us at cypress.com/sales. Products Automotive Clocks & Buffers Interface Lighting & Power Control Memory Optical & Image Sensing PSoC Touch Sensing USB Controllers Wireless/RF cypress.com/go/automotive cypress.com/go/clocks cypress.com/go/interface cypress.com/go/powerpsoc cypress.com/go/plc cypress.com/go/memory cypress.com/go/image cypress.com/go/psoc cypress.com/go/touch cypress.com/go/USB cypress.com/go/wireless PSoC Solutions psoc.cypress.com/solutions PSoC 1 | PSoC 3 | PSoC 5 © Cypress Semiconductor Corporation, 2009-2011. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. 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Cypress does not assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress’ product in a life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. Use may be limited by and subject to the applicable Cypress software license agreement. Document Number: 001-50282 Rev. *D Revised April 27, 2011 Page 14 of 14 All products and company names mentioned in this document may be the trademarks of their respective holders. [+] Feedback