CY7C1324H-133AXC

CY7C1324H 2-Mbit (128K x 18) Flow-Through Sync SRAM Features • 128K x 18 common I/O • 3.3V core power supply • 3.3V/2.5V I/O supply • Fast clock-to-output times — 6.5 ns (133-MHz version) • Provide high-performance 2-1-1-1 access rate • User-selectable burst counter supporting Intel® Pentium® interleaved or linear burst sequences • Separate processor and controller address strobes • Synchronous self-timed write • Asynchronous output enable • Offered in JEDEC-standard lead-free 100-pin TQFP package • “ZZ” Sleep Mode option first address in a burst and increments the address automatically for the rest of the burst access. All synchronous inputs are gated by registers controlled by a positive-edge-triggered Clock Input (CLK). The synchronous inputs include all addresses, all data inputs, address-pipelining Chip Enable (CE1), depth-expansion Chip Enables (CE2 and CE3), Burst Control inputs (ADSC, ADSP, and ADV), Write Enables (BW[A:B], and BWE), and Global Write (GW). Asynchronous inputs include the Output Enable (OE) and the ZZ pin. The CY7C1324H allows either interleaved or linear burst sequences, selected by the MODE input pin. A HIGH selects an interleaved burst sequence, while a LOW selects a linear burst sequence. Burst accesses can be initiated with the Processor Address Strobe (ADSP) or the cache Controller Address Strobe (ADSC) inputs. Address advancement is controlled by the Address Advancement (ADV) input. Addresses and chip enables are registered at rising edge of clock when either Address Strobe Processor (ADSP) or Address Strobe Controller (ADSC) are active. Subsequent burst addresses can be internally generated as controlled by the Advance pin (ADV). The CY7C1324H operates from a +3.3V core power supply while all outputs may operate with either a +3.3V or +2.5V supply. All inputs and outputs are JEDEC-standard JESD8-5-compatible. Functional Description[1] The CY7C1324H is a 128K x 18 synchronous cache RAM designed to interface with high-speed microprocessors with minimum glue logic. Maximum access delay from clock rise is 6.5 ns (133-MHz version). A 2-bit on-chip counter captures the Logic Block Diagram A0,A1,A MODE ADV CLK ADDRESS REGISTER A[1:0] BURST Q1 COUNTER AND LOGIC CLR Q0 ADSC ADSP DQB,DQPB WRITE REGISTER DQB,DQPB WRITE DRIVER BWB MEMORY ARRAY SENSE AMPS OUTPUT BUFFERS BWA BWE GW CE1 CE2 CE3 OE DQA,DQPA WRITE REGISTER DQA,DQPA WRITE DRIVER INPUT REGISTERS DQs DQPA DQPB ENABLE REGISTER ZZ SLEEP CONTROL Note: 1. For best-practices recommendations, please refer to the Cypress application note System Design Guidelines on www.cypress.com. Cypress Semiconductor Corporation Document #: 001-00208 Rev. *B • 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600 Revised April 26, 2006 [+] [+] Feedback CY7C1324H Selection Guide 133 MHz Maximum Access Time Maximum Operating Current Maximum Standby Current 6.5 225 40 Unit ns mA mA Pin Configurations 100-pin TQFP Pinout BWB BWA CE3 CE1 NC NC VDD VSS OE ADSC ADSP ADV 86 85 84 83 CE2 CLK GW A BWE A 82 A A 81 99 98 97 96 95 94 93 92 91 90 89 88 NC NC NC VDDQ VSS NC NC DQB DQB VSS VDDQ DQB DQB NC VDD NC VSS DQB DQB VDDQ VSS DQB DQB DQPB NC VSS VDDQ NC NC NC BYTE B 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 100 87 CY7C1324H 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 44 45 46 47 48 49 50 A NC NC VDDQ VSS NC DQPB DQA DQA VSS VDDQ DQA DQA VSS NC VDD ZZ DQA DQA VDDQ VSS DQA DQA NC NC VSS VDDQ NC NC NC BYTE A 38 39 40 41 VDD 42 NC/72M NC/36M NC/18M NC/9M A A A1 A0 VSS 43 MODE A Document #: 001-00208 Rev. *B NC/4M A A A A A A A Page 2 of 15 [+] [+] Feedback CY7C1324H Pin Definitions Name A0, A1, A I/O Description InputAddress Inputs used to select one of the 128K address locations. Sampled at the rising Synchronous edge of the CLK if ADSP or ADSC is active LOW, and CE1, CE2, and CE3 are sampled active. A[1:0] feed the 2-bit counter. InputByte Write Select Inputs, active LOW. Qualified with BWE to conduct Byte Writes to the Synchronous SRAM. Sampled on the rising edge of CLK. InputGlobal Write Enable Input, active LOW. When asserted LOW on the rising edge of CLK, a Synchronous global Write is conducted (ALL bytes are written, regardless of the values on BW[A:B] and BWE). InputByte Write Enable Input, active LOW. Sampled on the rising edge of CLK. This signal must Synchronous be asserted LOW to conduct a Byte Write. Input-Clock Clock Input. Used to capture all synchronous inputs to the device. Also used to increment the burst counter when ADV is asserted LOW, during a burst operation. BWA,BWB GW BWE CLK CE1 InputChip Enable 1 Input, active LOW. Sampled on the rising edge of CLK. Used in conjunction Synchronous with CE2 and CE3 to select/deselect the device. ADSP is ignored if CE1 is HIGH. CE1 is sampled only when a new external address is loaded. InputChip Enable 2 Input, active HIGH. Sampled on the rising edge of CLK. Used in conjunction Synchronous with CE1 and CE3 to select/deselect the device. CE2 is sampled only when a new external address is loaded. InputChip Enable 3 Input, active LOW. Sampled on the rising edge of CLK. Used in conjunction Synchronous with CE1 and CE2 to select/deselect the device. CE3 is sampled only when a new external address is loaded. InputOutput Enable, asynchronous input, active LOW. Controls the direction of the I/O pins. Asynchronous When LOW, the I/O pins behave as outputs. When deasserted HIGH, I/O pins are tri-stated, and act as input data pins. OE is masked during the first clock of a Read cycle when emerging from a deselected state. InputAdvance Input signal, sampled on the rising edge of CLK. When asserted, it automatically Synchronous increments the address in a burst cycle. InputAddress Strobe from Processor, sampled on the rising edge of CLK, active LOW. When Synchronous asserted LOW, addresses presented to the device are captured in the address registers. A[1:0] are also loaded into the burst counter. When ADSP and ADSC are both asserted, only ADSP is recognized. ASDP is ignored when CE1 is deasserted HIGH InputAddress Strobe from Controller, sampled on the rising edge of CLK, active LOW. When Synchronous asserted LOW, addresses presented to the device are captured in the address registers. A[1:0] are also loaded into the burst counter. When ADSP and ADSC are both asserted, only ADSP is recognized. InputZZ “sleep” Input, active HIGH. When asserted HIGH places the device in a non-time-critical Asynchronous “sleep” condition with data integrity preserved. For normal operation, this pin has to be LOW or left floating. ZZ pin has an internal pull-down. I/OBidirectional Data I/O Lines. As inputs, they feed into an on-chip data register that is triggered Synchronous by the rising edge of CLK. As outputs, they deliver the data contained in the memory location specified by the addresses presented during the previous clock rise of the Read cycle. The direction of the pins is controlled by OE. When OE is asserted LOW, the pins behave as outputs. When HIGH, DQs and DQP[A:B] are placed in a tri-state condition. Power Supply Ground I/O Power Supply InputStatic Power supply inputs to the core of the device. Ground for the device. Power supply for the I/O circuitry. Selects Burst Order. When tied to GND selects linear burst sequence. When tied to VDD or left floating selects interleaved burst sequence. This is a strap pin and should remain static during device operation. Mode Pin has an internal pull-up. No Connects. Not Internally connected to the die. 4M, 9M, 18M, 72M, 144M, 288M, 576M, and 1G are address expansion pins and are not internally connected to the die. CE2 CE3 OE ADV ADSP ADSC ZZ DQs DQPA, DQPB VDD VSS VDDQ MODE NC Document #: 001-00208 Rev. *B Page 3 of 15 [+] [+] Feedback CY7C1324H Functional Overview All synchronous inputs pass through input registers controlled by the rising edge of the clock. Maximum access delay from the clock rise (t CDV) is 6.5 ns (133-MHz device). The CY7C1324H supports secondary cache in systems utilizing either a linear or interleaved burst sequence. The interleaved burst order supports Pentium and i486™ processors. The linear burst sequence is suited for processors that utilize a linear burst sequence. The burst order is user-selectable, and is determined by sampling the MODE input. Accesses can be initiated with either the Processor Address Strobe (ADSP) or the Controller Address Strobe (ADSC). Address advancement through the burst sequence is controlled by the ADV input. A two-bit on-chip wraparound burst counter captures the first address in a burst sequence and automatically increments the address for the rest of the burst access. Byte write operations are qualified with the Byte Write Enable (BWE) and Byte Write Select (BW[A:B]) inputs. A Global Write Enable (GW) overrides all byte write inputs and writes data to all four bytes. All writes are simplified with on-chip synchronous self-timed write circuitry. Three synchronous Chip Selects (CE1, CE2, CE3) and an asynchronous Output Enable (OE) provide for easy bank selection and output tri-state control. ADSP is ignored if CE1 is HIGH. Single Read Accesses A single read access is initiated when the following conditions are satisfied at clock rise: (1) CE1, CE2, and CE3 are all asserted active, and (2) ADSP or ADSC is asserted LOW (if the access is initiated by ADSC, the write inputs must be deasserted during this first cycle). The address presented to the address inputs is latched into the address register and the burst counter/control logic and presented to the memory core. If the OE input is asserted LOW, the requested data will be available at the data outputs a maximum to tCDV after clock rise. ADSP is ignored if CE1 is HIGH. Single Write Accesses Initiated by ADSP This access is initiated when the following conditions are satisfied at clock rise: (1) CE1, CE2, CE3 are all asserted active, and (2) ADSP is asserted LOW. The addresses presented are loaded into the address register and the burst inputs (GW, BWE, and BW[A:B]) are ignored during this first clock cycle. If the write inputs are asserted active (see Write Cycle Descriptions table for appropriate states that indicate a Write) on the next clock rise, the appropriate data will be latched and written into the device. Byte Writes are allowed. During Byte Writes, BWA controls DQA and BWB controls DQB. All I/Os are tri-stated during a Byte Write. Since this is a common I/O device, the asynchronous OE input signal must be deasserted and the I/Os must be tri-stated prior to the presentation of data to DQs. As a safety precaution, the data lines are tri-stated once a write cycle is detected, regardless of the state of OE. Single Write Accesses Initiated by ADSC This write access is initiated when the following conditions are satisfied at clock rise: (1) CE1, CE2, and CE3 are all asserted active, (2) ADSC is asserted LOW, (3) ADSP is deasserted HIGH, and (4) the write input signals (GW, BWE, and BW[A:B]) indicate a write access. ADSC is ignored if ADSP is active LOW. The addresses presented are loaded into the address register and the burst counter/control logic and delivered to the memory core. The information presented to DQ[A:D] will be written into the specified address location. Byte Writes are allowed. During Byte Writes, BWA controls DQA and BWB controls DQB. All I/Os are tri-stated when a Write is detected, even a Byte Write. Since this is a common I/O device, the asynchronous OE input signal must be deasserted and the I/Os must be tri-stated prior to the presentation of data to DQs. As a safety precaution, the data lines are tri-stated once a Write cycle is detected, regardless of the state of OE. Burst Sequences The CY7C1324H provides an on-chip two-bit wraparound burst counter inside the SRAM. The burst counter is fed by A[1:0], and can follow either a linear or interleaved burst order. The burst order is determined by the state of the MODE input. A LOW on MODE will select a linear burst sequence. A HIGH on MODE will select an interleaved burst order. Leaving MODE unconnected will cause the device to default to an interleaved burst sequence. Sleep Mode The ZZ input pin is an asynchronous input. Asserting ZZ places the SRAM in a power conservation “sleep” mode. Two clock cycles are required to enter into or exit from this “sleep” mode. While in this mode, data integrity is guaranteed. Accesses pending when entering the “sleep” mode are not considered valid nor is the completion of the operation guaranteed. The device must be deselected prior to entering the “sleep” mode. CEs, ADSP, and ADSC must remain inactive for the duration of tZZREC after the ZZ input returns LOW. Interleaved Burst Address Table (MODE = Floating or VDD) First Address A1, A0 00 01 10 11 Second Address A1, A0 01 00 11 10 Third Address A1, A0 10 11 00 01 Fourth Address A1, A0 11 10 01 00 Linear Burst Address Table (MODE = GND) First Address A1, A0 00 01 10 11 Second Address A1, A0 01 10 11 00 Third Address A1, A0 10 11 00 01 Fourth Address A1, A0 11 00 01 10 Document #: 001-00208 Rev. *B Page 4 of 15 [+] [+] Feedback CY7C1324H ZZ Mode Electrical Characteristics Parameter IDDZZ tZZS tZZREC tZZI tRZZI Description Sleep mode standby current Device operation to ZZ ZZ recovery time ZZ Active to sleep current ZZ Inactive to exit sleep current Test Conditions ZZ > VDD – 0.2V ZZ > VDD – 0.2V ZZ < 0.2V This parameter is sampled This parameter is sampled 0 2tCYC 2tCYC Min. Max. 40 2tCYC Unit mA ns ns ns ns Truth Table[2, 3, 4, 5] Cycle Description Deselected Cycle, Power-down Deselected Cycle, Power-down Deselected Cycle, Power-down Deselected Cycle, Power-down Deselected Cycle, Power-down Sleep Mode, Power-down Read Cycle, Begin Burst Read Cycle, Begin Burst Write Cycle, Begin Burst Read Cycle, Begin Burst Read Cycle, Begin Burst Read Cycle, Continue Burst Read Cycle, Continue Burst Read Cycle, Continue Burst Read Cycle, Continue Burst Write Cycle, Continue Burst Write Cycle, Continue Burst Read Cycle, Suspend Burst Read Cycle, Suspend Burst Read Cycle, Suspend Burst Read Cycle, Suspend Burst Write Cycle, Suspend Burst Write Cycle, Suspend Burst ADDRESS Used CE1 CE2 CE3 None H X X None None None None None External External External External External Next Next Next Next Next Next Current Current Current Current Current Current L L L X X L L L L L X X H H X H X X H H X H L X L X X H H H H H X X X X X X X X X X X X X H X X X L L L L L X X X X X X X X X X X X ZZ L L L L L H L L L L L L L L L L L L L L L L L ADSP X L L H H X L L H H H H H X X H X H H X X H X ADSC L X X L L X X X L L L H H H H H H H H H H H H ADV X X X X X X X X X X X L L L L L L H H H H H H WE OE CLK X X X X X X X X L H H H H H H L L H H H H L L X X X X X X L H X L H L H L H X X L H L H X X L-H L-H L-H L-H L-H X L-H L-H L-H L-H L-H L-H L-H L-H L-H L-H L-H L-H L-H L-H L-H L-H L-H DQ Tri-State Tri-State Tri-State Tri-State Tri-State Tri-State Q Tri-State D Q Tri-State Q Tri-State Q Tri-State D D Q Tri-State Q Tri-State D D Notes: 2. X = “Don't Care.” H = Logic HIGH, L =Logic LOW. 3. WRITE = L when any one or more Byte Write Enable signals (BWA, BWB) and BWE = L or GW= L. WRITE = H when all Byte Write Enable signals (BWA, BWB), BWE, GW = H.The DQ pins are controlled by the current cycle and the OE signal. OE is asynchronous and is not sampled with the clock. 4. The SRAM always initiates a Read cycle when ADSP is asserted, regardless of the state of GW, BWE, or BW[A: B]. Writes may occur only on subsequent clocks after the ADSP or with the assertion of ADSC. As a result, OE must be driven HIGH prior to the start of the Write cycle to allow the outputs to tri-state. OE is a don't care for the remainder of the Write cycle 5. OE is asynchronous and is not sampled with the clock rise. It is masked internally during Write cycles. During a read cycle all data bits are Tri-State when OE is inactive or when the device is deselected, and all data bits behave as output when OE is active (LOW) Document #: 001-00208 Rev. *B Page 5 of 15 [+] [+] Feedback CY7C1324H Truth Table for Read/Write[2, 3] Function Read Read Write Byte (A, DQPA) Write Byte (B, DQPB) Write All Bytes Write All Bytes GW H H H H H L BWE H L L L L X BWB X H H L L X BWA X H L H L X Document #: 001-00208 Rev. *B Page 6 of 15 [+] [+] Feedback CY7C1324H Maximum Ratings (Above which the useful life may be impaired. For user guidelines, not tested.) Storage Temperature ................................. –65°C to +150°C Ambient Temperature with Power Applied............................................. –55°C to +125°C Supply Voltage on VDD Relative to GND........ –0.5V to +4.6V Supply Voltage on VDDQ Relative to GND ...... –0.5V to +VDD DC Voltage Applied to Outputs in Tri-State........................................... –0.5V to VDDQ + 0.5V Range Commercial Industrial DC Input Voltage ................................... –0.5V to VDD + 0.5V Current into Outputs (LOW)......................................... 20 mA Static Discharge Voltage.......................................... > 2001V (per MIL-STD-883, Method 3015) Latch-up Current.................................................... > 200 mA Operating Range Ambient Temperature 0°C to +70°C –40°C to +85°C VDD 3.3V −5%/+10% VDDQ 2.5V –5% to VDD Electrical Characteristics Over the Operating Range [6, 7] Parameter VDD VDDQ VOH VOL VIH VIL IX Description Power Supply Voltage I/O Supply Voltage Output HIGH Voltage Output LOW Voltage Input HIGH Voltage Input LOW Voltage[6] Input Leakage Current except ZZ and MODE for 3.3V I/O for 2.5V I/O for 3.3V I/O, IOH = –4.0 mA for 2.5V I/O, IOH = –1.0 mA for 3.3V I/O, IOL = 8.0 mA for 2.5V I/O, IOL = 1.0 mA for 3.3V I/O for 2.5V I/O for 3.3V I/O for 2.5V I/O GND ≤ VI ≤ VDDQ 2.0 1.7 –0.3 –0.3 −5 –30 5 –5 30 –5 5 225 90 7.5-ns cycle, 133 MHz Test Conditions Min. 3.135 3.135 2.375 2.4 2.0 0.4 0.4 VDD + 0.3V VDD + 0.3V 0.8 0.7 5 µA µA µA µA µA µA mA mA V V V Max. 3.6 VDD 2.625 Unit V V V V Input Current of MODE Input = VSS Input = VDD Input Current of ZZ IOZ IDD ISB1 Input = VSS Input = VDD Output Leakage Current GND ≤ VI ≤ VDDQ, Output Disabled VDD Operating Supply Current Automatic CE Power-Down Current—TTL Inputs VDD = Max., IOUT = 0 mA, f = fMAX= 1/tCYC Max. VDD, Device Deselected, 7.5-ns cycle, 133 MHz VIN ≥ VIH or VIN ≤ VIL, f = fMAX, inputs switching ISB2 Automatic CE Max. VDD, Device Deselected, 7.5-ns cycle, 133 MHz Power-Down VIN ≥ VDD – 0.3V or VIN ≤ 0.3V, Current—CMOS Inputs f = 0, inputs static Automatic CE Max. VDD, Device Deselected, 7.5-ns cycle, 133 MHz Power-Down VIN ≥ VDDQ – 0.3V or VIN ≤ Current—CMOS Inputs 0.3V, f = fMAX, inputs switching Automatic CE Power-Down Current—TTL Inputs Max. VDD, Device Deselected, 7.5-ns cycle, 133 MHz VIN ≥ VDD – 0.3V or VIN ≤ 0.3V, f = 0, inputs static 40 mA ISB3 75 mA ISB4 45 mA Notes: 6. Overshoot: VIH(AC) < VDD +1.5V (Pulse width less than tCYC/2), undershoot: VIL(AC) > –2V (Pulse width less than tCYC/2). 7. TPower-up: Assumes a linear ramp from 0v to VDD(min.) within 200 ms. During this time VIH < VDD and VDDQ < VDD. Document #: 001-00208 Rev. *B Page 7 of 15 [+] [+] Feedback CY7C1324H Capacitance[8] Parameter CIN CCLK CI/O Description Input Capacitance Clock Input Capacitance Input/Output Capacitance Test Conditions TA = 25°C, f = 1 MHz, VDD = 3.3V. VDDQ = 2.5V 100 TQFP Max. 5 5 5 Unit pF pF pF Thermal Resistance[8] Parameter ΘJA ΘJC Description Thermal Resistance (Junction to Ambient) Thermal Resistance (Junction to Case) Test Conditions Test conditions follow standard test methods and procedures for measuring thermal impedance, per EIA/JESD51 100 TQFP Package 30.32 6.85 Unit °C/W °C/W AC Test Loads and Waveforms 3.3V I/O Test Load OUTPUT Z0 = 50Ω 3.3V OUTPUT RL = 50Ω 5 pF R = 351Ω INCLUDING JIG AND SCOPE R = 317Ω ALL INPUT PULSES VDD 10% GND ≤ 1 ns 90% 90% 10% ≤ 1 ns VL = 1.5V (a) 2.5V I/O Test Load OUTPUT Z0 = 50Ω (b) R = 1667Ω VDDQ 10% (c) 2.5V OUTPUT RL = 50Ω 5 pF VT = 1.25V INCLUDING JIG AND SCOPE ALL INPUT PULSES 90% 90% 10% ≤ 1 ns GND R =1538Ω ≤ 1 ns (a) (b) (c) Notes: 8. Tested initially and after any design or process change that may affect these parameters. Document #: 001-00208 Rev. *B Page 8 of 15 [+] [+] Feedback CY7C1324H Switching Characteristics Over the Operating Range[9, 10] -133 Parameter tPOWER Clock tCYC tCH tCL Output Times tCDV tDOH tCLZ tCHZ tOEV tOELZ tOEHZ Set-up Times tAS tADS tADVS tWES tDS tCES Hold Times tAH tADH tWEH tADVH tDH tCEH Address Hold after CLK Rise ADSP, ADSC Hold after CLK Rise GW, BWE, BW[A:B] Hold after CLK Rise ADV Hold after CLK Rise Data Input Hold after CLK Rise Chip Enable Hold after CLK Rise 0.5 0.5 0.5 0.5 0.5 0.5 ns ns ns ns ns ns Address Set-up before CLK Rise ADSP, ADSC Set-up before CLK Rise ADV Set-up before CLK Rise GW, BWE, BW[A:B] Set-up before CLK Rise Data Input Set-up before CLK Rise Chip Enable Set-up 1.5 1.5 1.5 1.5 1.5 1.5 ns ns ns ns ns ns Data Output Valid after CLK Rise Data Output Hold after CLK Rise Clock to Low-Z[12, 13, 14] Clock to High-Z[12, 13, 14] OE LOW to Output Valid OE LOW to Output Low-Z[12, 13, 14] OE HIGH to Output High-Z[12, 13, 14] 0 3.5 2.0 0 3.5 3.5 6.5 ns ns ns ns ns ns ns Clock Cycle Time Clock HIGH Clock LOW 7.5 2.5 2.5 ns ns ns Description VDD(Typical) to the First Access [11] Min. 1 Max. Unit ms Notes: 9. Timing reference level is 1.5V when VDDQ = 3.3V and 1.25V when VDDQ = 2.5V 10. Test conditions shown in (a) of AC Test Loads unless otherwise noted. 11. This part has a voltage regulator internally; tPOWER is the time that the power needs to be supplied above VDD(minimum) initially before a Read or Write operation can be initiated. 12. tCHZ, tCLZ, tOELZ, and tOEHZ are specified with AC test conditions shown in part (b) of AC Test Loads. Transition is measured ± 200 mV from steady-state voltage. 13. At any given voltage and temperature, tOEHZ is less than tOELZ and tCHZ is less than tCLZ to eliminate bus contention between SRAMs when sharing the same data bus. These specifications do not imply a bus contention condition, but reflect parameters guaranteed over worst case user conditions. Device is designed to achieve High-Z prior to Low-Z under the same system conditions. 14. This parameter is sampled and not 100% tested. Document #: 001-00208 Rev. *B Page 9 of 15 [+] [+] Feedback CY7C1324H Timing Diagrams Read Cycle Timing[15] tCYC CLK t CH t CL tADS tADH ADSP tADS tADH ADSC tAS tAH ADDRESS A1 t WES t WEH A2 GW, BWE,BW [A:B] tCES t CEH Deselect Cycle CE t ADVS t ADVH ADV ADV suspends burst. OE t OEV t CLZ t OEHZ t OELZ tCDV tDOH t CHZ Data Out (Q) High-Z Q(A1) t CDV Q(A2) Q(A2 + 1) Q(A2 + 2) Q(A2 + 3) Q(A2) Q(A2 + 1) Q(A2 + 2) Single READ DON’T CARE BURST READ UNDEFINED Burst wraps around to its initial state Note: 15. On this diagram, when CE is LOW, CE1 is LOW, CE2 is HIGH and CE3 is LOW. When CE is HIGH, CE1 is HIGH or CE2 is LOW or CE3 is HIGH. Document #: 001-00208 Rev. *B Page 10 of 15 [+] [+] Feedback CY7C1324H Timing Diagrams (continued) Write Cycle Timing[15, 16] t CYC CLK t CH t CL tADS tADH ADSP tADS tADH ADSC extends burst. tADS tADH ADSC tAS tAH ADDRESS A1 A2 Byte write signals are ignored for first cycle when ADSP initiates burst. A3 tWES tWEH BWE, BW[A:B] t t WES WEH GW tCES tCEH CE tADVS tADVH ADV ADV suspends burst. OE t t DS DH D(A1) D(A2) D(A2 + 1) D(A2 + 1) D(A2 + 2) D(A2 + 3) D(A3) D(A3 + 1) D(A3 + 2) Data in (D) High-Z t OEHZ Data Out (Q) BURST READ Single WRITE BURST WRITE Extended BURST WRITE DON’T CARE UNDEFINED Note: 16. Full width Write can be initiated by either GW LOW; or by GW HIGH, BWE LOW and BW[A:B] LOW. Document #: 001-00208 Rev. *B Page 11 of 15 [+] [+] Feedback CY7C1324H Timing Diagrams (continued) Read/Write Timing[15, 17, 18] tCYC CLK t CH tADS tADH t CL ADSP ADSC tAS tAH ADDRESS A1 A2 A3 t t WES WEH A4 A5 A6 BWE, BW[A:B] tCES tCEH CE ADV OE tDS tDH tOELZ Data In (D) Data Out (Q) High-Z t OEHZ D(A3) tCDV D(A5) D(A6) Q(A1) Q(A2) Single WRITE DON’T CARE Q(A4) Q(A4+1) Q(A4+2) Q(A4+3) Back-to-Back WRITEs Back-to-Back READs BURST READ UNDEFINED Notes: 17. The data bus (Q) remains in High-Z following a Write cycle unless an ADSP, ADSC, or ADV cycle is performed. 18. GW is HIGH. Document #: 001-00208 Rev. *B Page 12 of 15 [+] [+] Feedback CY7C1324H Timing Diagrams (continued) ZZ Mode Timing[19, 20] CLK t ZZ t ZZREC ZZ t ZZI I SUPPLY I DDZZ t RZZI DESELECT or READ Only ALL INPUTS (except ZZ) Outputs (Q) High-Z DON’T CARE Notes: 19. Device must be deselected when entering ZZ mode. See Cycle Descriptions table for all possible signal conditions to deselect the device. 20. DQs are in High-Z when exiting ZZ sleep mode. Document #: 001-00208 Rev. *B Page 13 of 15 [+] [+] Feedback CY7C1324H Ordering Information “Not all of the speed, package and temperature ranges are available. Please contact your local sales representative or visit www.cypress.com for actual products offered”. Speed (MHz) 133 Ordering Code CY7C1324H-133AXI Package Diagram Package Type Operating Range Commercial Industrial CY7C1324H-133AXC 51-85050 100-pin Thin Quad Flat Pack (14 x 20 x 1.4 mm) Lead-Free 51-85050 100-pin Thin Quad Flat Pack (14 x 20 x 1.4 mm) Lead-Free Package Diagram 100-pin TQFP (14 x 20 x 1.4 mm) (51-85050) 16.00±0.20 14.00±0.10 100 1 81 80 1.40±0.05 0.30±0.08 22.00±0.20 20.00±0.10 0.65 TYP. 30 31 50 51 12°±1° (8X) SEE DETAIL A 0.20 MAX. 1.60 MAX. 0° MIN. SEATING PLANE 0.25 GAUGE PLANE STAND-OFF 0.05 MIN. 0.15 MAX. NOTE: 1. JEDEC STD REF MS-026 2. BODY LENGTH DIMENSION DOES NOT INCLUDE MOLD PROTRUSION/END FLASH MOLD PROTRUSION/END FLASH SHALL NOT EXCEED 0.0098 in (0.25 mm) PER SIDE BODY LENGTH DIMENSIONS ARE MAX PLASTIC BODY SIZE INCLUDING MOLD MISMATCH 3. DIMENSIONS IN MILLIMETERS 0°-7° R 0.08 MIN. 0.20 MAX. 0.60±0.15 0.20 MIN. 1.00 REF. DETAIL 51-85050-*B A Intel and Pentium are registered trademarks and i486 is a trademark of Intel Corporation. All product and company names mentioned in this document may be the trademarks of their respective holders. Document #: 001-00208 Rev. *B 0.10 R 0.08 MIN. 0.20 MAX. Page 14 of 15 © Cypress Semiconductor Corporation, 2006. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. [+] [+] Feedback CY7C1324H Document History Page Document Title: CY7C1324H 2-Mbit (128K x 18) Flow-Through Sync SRAM Document Number: 001-00208 REV. ** *A ECN NO. 347377 428408 Issue Date See ECN See ECN Orig. of Change PCI NXR New Data Sheet Converted from Preliminary to Final. Changed address of Cypress Semiconductor Corporation on Page# 1 from “3901 North First Street” to “198 Champion Court” Removed 100 MHz Speed-bin Changed Three-State to Tri-State. Modified “Input Load” to “Input Leakage Current except ZZ and MODE” in the Electrical Characteristics Table. Modified test condition from VIH < VDD to VIH < VDD Replaced Package Name column with Package Diagram in the Ordering Information table. Updated the Ordering Information Table. Replaced Package Diagram of 51-85050 from *A to *B Included 2.5V I/O option Updated the Ordering Information table. Description of Change *B 459347 See ECN NXR Document #: 001-00208 Rev. *B Page 15 of 15 [+] [+] Feedback