CY7C1441AV33-133AXCT

CY7C1441AV33 CY7C1443AV33,CY7C1447AV33 36-Mbit (1M x 36/2M x 18/512K x 72) Flow-Through SRAM Features Functional Description ■ Supports 133-MHz bus operations ■ 1M x 36/2M x 18/512K x 72 common IO ■ 3.3V core power supply ■ 2.5V or 3.3V IO power supply ■ Fast clock-to-output times ❐ 6.5 ns (133-MHz version) ■ Provide high-performance 2-1-1-1 access rate ■ User-selectable burst counter supporting Intel® Pentium® interleaved or linear burst sequences ■ Separate processor and controller address strobes The CY7C1441AV33/CY7C1443AV33/CY7C1447AV33[1] are 3.3V, 1M x 36/2M x 18/512K x 72 Synchronous Flow-through SRAMs, respectively designed to interface with high-speed microprocessors with minimum glue logic. Maximum access delay from clock rise is 6.5 ns (133-MHz version). A 2-bit on-chip counter captures the first address in a burst and increments the address automatically for the rest of the burst access. All synchronous inputs are gated by registers controlled by a positive-edge-triggered Clock Input (CLK). The synchronous inputs include all addresses, all data inputs, address-pipelining Chip Enable (CE1), depth-expansion Chip Enables (CE2 and CE3), Burst Control inputs (ADSC, ADSP, and ADV), Write Enables (BWx, and BWE), and Global Write (GW). Asynchronous inputs include the Output Enable (OE) and the ZZ pin. ■ Synchronous self-timed write ■ Asynchronous output enable ■ CY7C1441AV33, CY7C1443AV33 available in JEDEC-standard Pb-free 100-pin TQFP package, Pb-free and non-lead-free 165-ball FBGA package. CY7C1447AV33 available in Pb-free and non-lead-free 209-ball FBGA package ■ IEEE 1149.1 JTAG-Compatible Boundary Scan ■ “ZZ” Sleep Mode option The CY7C1441AV33/CY7C1443AV33/CY7C1447AV33 allows either interleaved or linear burst sequences, selected by the MODE input pin. A HIGH selects an interleaved burst sequence, while a LOW selects a linear burst sequence. Burst accesses can be initiated with the Processor Address Strobe (ADSP) or the cache Controller Address Strobe (ADSC) inputs. Address advancement is controlled by the Address Advancement (ADV) input. Addresses and chip enables are registered at rising edge of clock when either Address Strobe Processor (ADSP) or Address Strobe Controller (ADSC) are active. Subsequent burst addresses can be internally generated as controlled by the Advance pin (ADV). The CY7C1441AV33/CY7C1443AV33/CY7C1447AV33 operates from a +3.3V core power supply while all outputs may operate with either a +2.5 or +3.3V supply. All inputs and outputs are JEDEC-standard JESD8-5-compatible. Selection Guide Description 133 MHz 100 MHz Unit Maximum Access Time 6.5 8.5 ns Maximum Operating Current 310 290 mA Maximum CMOS Standby Current 120 120 mA Note 1. For best-practices recommendations, please refer to the Cypress application note System Design Guidelines on www.cypress.com. Cypress Semiconductor Corporation Document #: 38-05357 Rev. *G • 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600 Revised May 09, 2008 [+] Feedback CY7C1441AV33 CY7C1443AV33,CY7C1447AV33 Logic Block Diagram – CY7C1441AV33 (1M x 36) ADDRESS REGISTER A 0, A1, A A [1:0] MODE BURST Q1 COUNTER AND LOGIC Q0 CLR ADV CLK ADSC ADSP DQ D , DQP D DQ D , DQP D BW D BYTE BYTE WRITE REGISTER WRITE REGISTER DQ C, DQP C DQ C, DQP C BW C BYTE BYTE WRITE REGISTER WRITE REGISTER DQ B , DQP B BW B DQ B , DQP B BYTE BYTE WRITE REGISTER MEMORY ARRAY SENSE AMPS OUTPUT BUFFERS DQ s DQP A DQP B DQP C DQP D WRITE REGISTER DQ A , DQP A BW A BWE DQ A , DQPA BYTE BYTE WRITE REGISTER WRITE REGISTER INPUT REGISTERS GW ENABLE REGISTER CE1 CE2 CE3 OE ZZ SLEEP CONTROL Logic Block Diagram – CY7C1443AV33 (2Mx 18) ADDRESS REGISTER A0,A1,A A[1:0] MODE BURST Q1 COUNTER AND LOGIC CLR Q0 ADV CLK ADSC ADSP BW B BW A DQ B ,DQP B WRITE REGISTER DQ A ,DQP A WRITE REGISTER DQ B ,DQP B WRITE DRIVER MEMORY ARRAY SENSE AMPS OUTPUT BUFFERS DQs DQP A DQP B DQ A ,DQP A WRITE DRIVER BWE GW CE 1 CE 2 CE 3 ENABLE REGISTER INPUT REGISTERS OE ZZ Document #: 38-05357 Rev. *G SLEEP CONTROL Page 2 of 31 [+] Feedback CY7C1441AV33 CY7C1443AV33,CY7C1447AV33 Logic Block Diagram – CY7C1447AV33 (512K x 72) ADDRESS REGISTER A0, A1,A A[1:0] MODE BURST Q1 COUNTER AND LOGIC CLR Q0 ADV CLK ADSC ADSP BW H DQ H , DQPH WRITE REGISTER DQ H , DQPH WRITE DRIVER BW G DQ F, DQPF WRITE REGISTER DQ G , DQPG WRITE DRIVER BW F DQ F, DQPF WRITE REGISTER DQ F, DQPF WRITE DRIVER BW E DQ E , DQPE WRITE REGISTER DQ E , DQP “a” E BYTE WRITE DRIVER BW D DQ D , DQPD WRITE REGISTER DQ D , DQPD WRITE DRIVER BW C DQ C, DQPC WRITE REGISTER DQ C, DQPC WRITE DRIVER MEMORY ARRAY SENSE AMPS BW B BW A BWE GW CE1 CE2 CE3 OE ZZ Document #: 38-05357 Rev. *G DQ B , DQPB WRITE REGISTER DQ A , DQPA WRITE REGISTER ENABLE REGISTER OUTPUT BUFFERS DQs DQP A DQP B DQP C DQP D DQP E DQP F DQP G DQP H DQ B , DQPB WRITE DRIVER DQ A , DQPA WRITE DRIVER INPUT REGISTERS SLEEP CONTROL Page 3 of 31 [+] Feedback CY7C1441AV33 CY7C1443AV33,CY7C1447AV33 Pin Configurations NC NC NC VDDQ VSSQ NC NC DQB DQB VSSQ VDDQ DQB DQB NC VDD NC VSS DQB DQB VDDQ VSSQ DQB DQB DQPB NC VSSQ VDDQ NC NC NC 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 CY7C1443AV33 (2M x 18) 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 Document #: 38-05357 Rev. *G A NC NC VDDQ VSSQ NC DQPA DQA DQA VSSQ VDDQ DQA DQA VSS NC VDD ZZ DQA DQA VDDQ VSSQ DQA DQA NC NC VSSQ VDDQ NC NC NC A A A A A A A A A A A A A A A A A A 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 DQPB DQB DQB VDDQ VSSQ DQB DQB DQB DQB VSSQ VDDQ DQB DQB VSS NC VDD ZZ DQA DQA VDDQ VSSQ DQA DQA DQA DQA VSSQ VDDQ DQA DQA DQPA MODE A A A A A1 A0 NC/72M A VSS VDD CY7C1441AV33 (1Mx 36) 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 MODE A A A A A1 A0 NC/72M A VSS VDD DQPC DQC DQC VDDQ VSSQ DQC DQC DQC DQC VSSQ VDDQ DQC DQC NC VDD NC VSS DQD DQD VDDQ VSSQ DQD DQD DQD DQD VSSQ VDDQ DQD DQD DQPD 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 A A CE1 CE2 NC NC BWB BWA CE3 VDD VSS CLK GW BWE OE ADSC ADSP ADV A A A A CE1 CE2 BWD BWC BWB BWA CE3 VDD VSS CLK GW BWE OE ADSC ADSP ADV A A Figure 1. 100-Pin TQFP Pinout Page 4 of 31 [+] Feedback CY7C1441AV33 CY7C1443AV33,CY7C1447AV33 Pin Configurations (continued) 165-ball FBGA (15 x 17 x 1.4 mm) Pinout CY7C1441AV33 (1M x 36) 1 2 3 4 5 6 7 8 9 10 11 A B C D E F G H J K L M N P NC/288M A CE1 BWC BWB CE3 BWE ADSC ADV A NC R NC/144M A CE2 BWD BWA CLK GW OE ADSP A NC/576M DQPC DQC NC DQC VDDQ VSS VSS VSS VSS VSS VSS VSS VDD VDDQ VDDQ VSS VDD VDDQ NC/1G DQB DQPB DQB DQC DQC VDDQ VDD VSS VSS VSS VDD VDDQ DQB DQB DQC DQC NC DQD DQC VDDQ VDDQ NC VDDQ VDD VSS VDD VDD VDD VDDQ VDDQ NC VDDQ DQB VSS VSS VSS VSS VSS VSS VSS VDD VDD VDD VDD VSS VSS VSS VSS DQB NC DQA DQB DQB ZZ DQA DQC NC DQD DQD DQD VDDQ VDD VSS VSS VSS VDD VDDQ DQA DQA DQD DQD VDDQ VDD VSS VSS VSS VDD VDDQ DQA DQA DQD DQPD DQD NC VDDQ VDDQ VDD VSS VSS NC VSS VDD VSS VDDQ VDDQ DQA NC DQA DQPA NC NC/72M A A TDI A A1 VSS NC TDO A A A A MODE A A A TMS A0 TCK A A A A 9 10 11 CY7C1443AV33 (2M x 18) 1 2 3 4 A B C D E F G H J K L M N P NC/288M A CE1 BWB NC/144M A CE2 NC NC NC NC DQB VDDQ VDDQ VSS VDD NC DQB VDDQ NC DQB NC NC DQB DQB NC NC R 5 6 7 8 NC CE3 BWE ADSC ADV A BWA CLK GW OE ADSP A VSS VSS VSS VSS VSS VSS VSS VDD VDDQ VDDQ NC/1G NC DQPA DQA VDD VSS VSS VSS VDD VDDQ NC DQA VDDQ VDD VSS VSS VSS VDD VDDQ NC DQA VDDQ NC VDDQ VDD VDD VDD VSS VSS VSS VSS VSS VSS VSS VSS VSS VDD VDD VDD VDDQ NC VDDQ NC NC DQA DQA ZZ NC A NC/576M DQB NC VDDQ VDD VSS VSS VSS VDD VDDQ DQA NC DQB NC VDDQ VDD VSS VSS VSS VDD VDDQ DQA NC DQB DQPB NC NC VDDQ VDDQ VDD VSS VSS NC VSS A VSS NC VDD VSS VDDQ VDDQ DQA NC NC NC NC NC/72M A A TDI A1 TDO A A A A MODE A A A TMS A0 TCK A A A A Document #: 38-05357 Rev. *G Page 5 of 31 [+] Feedback CY7C1441AV33 CY7C1443AV33,CY7C1447AV33 Pin Configurations (continued) 209-ball FBGA (14 x 22 x 1.76 mm) Pinout CY7C1447AV33 (512K × 72) 1 2 3 4 5 6 7 8 9 10 11 A DQG DQG A CE2 ADSP ADSC ADV CE3 A DQB DQB B DQG DQG BWSC BWSG NC288M A BWSB BWSF DQB DQB C DQG DQG BWSH BWSD NC/144M CE1 NC/576M BWSE BWSA DQB DQB D DQG DQG VSS NC NC/1G OE NC VSS DQB DQB E DQPG DQPC VDDQ VDDQ VDD VDD VDD VDDQ VDDQ DQPF DQPB F DQC DQC VSS VSS VSS NC VSS VSS VSS DQF DQF G DQC DQC VDDQ VDDQ VDD NC VDD VDDQ VDDQ DQF DQF H DQC DQC VSS VSS VSS NC VSS VSS VSS DQF DQF J DQC DQC VDDQ VDDQ VDD NC VDD VDDQ VDDQ DQF DQF K NC NC CLK NC VSS VSS VSS NC NC NC NC L DQH DQH VDDQ VDDQ VDD NC VDD VDDQ VDDQ DQA DQA M DQH DQH VSS VSS VSS NC VSS VSS VSS DQA DQA N DQH DQH VDDQ VDDQ VDD NC VDD VDDQ VDDQ DQA DQA P DQH DQH VSS VSS VSS ZZ VSS VSS VSS DQA DQA R DQPD DQPH VDDQ VDDQ VDD VDD VDD VDDQ VDDQ T DQD DQD VSS NC NC MODE NC NC VSS DQE DQE U DQD DQD V DQD DQD W DQD DQD Document #: 38-05357 Rev. *G BW GW DQPA DQPE A A A A A A DQE DQE A A A A1 A A A DQE DQE TMS TDI A A0 A TCK DQE DQE NC/72M TDO Page 6 of 31 [+] Feedback CY7C1441AV33 CY7C1443AV33,CY7C1447AV33 Pin Definitions Name IO Description A0, A1, A InputSynchronous Address Inputs Used to Select One of the Address Locations. Sampled at the rising edge of the CLK if ADSP or ADSC is active LOW, and CE1, CE2, and CE3 are sampled active. A[1:0] feed the 2-bit counter. BWA, BWB BWC, BWD, BWE, BWF, BWG, BWH InputSynchronous Byte Write Select Inputs, Active LOW. Qualified with BWE to conduct byte writes to the SRAM. Sampled on the rising edge of CLK. GW InputSynchronous Global Write Enable Input, Active LOW. When asserted LOW on the rising edge of CLK, a global write is conducted (ALL bytes are written, regardless of the values on BWX and BWE). CLK InputClock Clock Input. Used to capture all synchronous inputs to the device. Also used to increment the burst counter when ADV is asserted LOW, during a burst operation. CE1 InputSynchronous Chip Enable 1 Input, Active LOW. Sampled on the rising edge of CLK. Used in conjunction with CE2 and CE3 to select/deselect the device. ADSP is ignored if CE1 is HIGH. CE1 is sampled only when a new external address is loaded. CE2 InputSynchronous Chip Enable 2 Input, Active HIGH. Sampled on the rising edge of CLK. Used in conjunction with CE1 and CE3 to select/deselect the device. CE2 is sampled only when a new external address is loaded. CE3 InputSynchronous Chip Enable 3 Input, Active LOW. Sampled on the rising edge of CLK. Used in conjunction with CE1 and CE2 to select/deselect the device. CE3 is assumed active throughout this document for BGA. CE3 is sampled only when a new external address is loaded. OE InputAsynchronous Output Enable, Asynchronous Input, Active LOW. Controls the direction of the IO pins. When LOW, the IO pins behave as outputs. When deasserted HIGH, IO pins are tri-stated, and act as input data pins. OE is masked during the first clock of a read cycle when emerging from a deselected state. ADV InputSynchronous Advance Input Signal, Sampled on the Rising Edge of CLK. When asserted, it automatically increments the address in a burst cycle. ADSP InputSynchronous Address Strobe from Processor, Sampled on the Rising Edge of CLK, Active LOW. When asserted LOW, addresses presented to the device are captured in the address registers. A[1:0] are also loaded into the burst counter. When ADSP and ADSC are both asserted, only ADSP is recognized. ASDP is ignored when CE1 is deasserted HIGH ADSC InputSynchronous Address Strobe from Controller, Sampled on the Rising Edge of CLK, Active LOW. When asserted LOW, addresses presented to the device are captured in the address registers. A[1:0] are also loaded into the burst counter. When ADSP and ADSC are both asserted, only ADSP is recognized. BWE InputSynchronous Byte Write Enable Input, Active LOW. Sampled on the rising edge of CLK. This signal must be asserted LOW to conduct a byte write. ZZ InputAsynchronous ZZ “sleep” Input, Active HIGH. When asserted HIGH places the device in a non-time-critical “sleep” condition with data integrity preserved. For normal operation, this pin must be LOW or left floating. ZZ pin has an internal pull down. Document #: 38-05357 Rev. *G Page 7 of 31 [+] Feedback CY7C1441AV33 CY7C1443AV33,CY7C1447AV33 Pin Definitions (continued) Name IO Description DQs IOSynchronous Bidirectional Data IO lines. As inputs, they feed into an on-chip data register that is triggered by the rising edge of CLK. As outputs, they deliver the data contained in the memory location specified by the addresses presented during the previous clock rise of the read cycle. The direction of the pins is controlled by OE. When OE is asserted LOW, the pins behave as outputs. When HIGH, DQs and DQPX are placed in a tri-state condition.The outputs are automatically tri-stated during the data portion of a write sequence, during the first clock when emerging from a deselected state, and when the device is deselected, regardless of the state of OE. DQPX IOSynchronous Bidirectional Data Parity IO Lines. Functionally, these signals are identical to DQs. During write sequences, DQPx is controlled by BW[A:H] correspondingly. MODE Input-Static Selects Burst Order. When tied to GND selects linear burst sequence. When tied to VDD or left floating selects interleaved burst sequence. This is a strap pin and should remain static during device operation. Mode Pin has an internal pull up. VDD VDDQ Power Supply Power Supply Inputs to the Core of the Device. IO Power Supply Power Supply for the IO Circuitry. Ground Ground for the Core of the Device. VSS VSSQ IO Ground TDO JTAG serial output Synchronous Serial Data-Out to the JTAG Circuit. Delivers data on the negative edge of TCK. If the JTAG feature is not being utilized, this pin should be left unconnected. This pin is not available on TQFP packages. TDI JTAG serial input Synchronous Serial Data-In to the JTAG Circuit. Sampled on the rising edge of TCK. If the JTAG feature is not being utilized, this pin can be left floating or connected to VDD through a pull up resistor. This pin is not available on TQFP packages. TMS JTAG serial input Synchronous Serial Data-In to the JTAG Circuit. Sampled on the rising edge of TCK. If the JTAG feature is not being utilized, this pin can be disconnected or connected to VDD. This pin is not available on TQFP packages. TCK JTAG-Clock Clock Input to the JTAG Circuitry. If the JTAG feature is not being utilized, this pin must be connected to VSS. This pin is not available on TQFP packages. NC - No Connects. Not internally connected to the die. 72M, 144M and 288M are address expansion pins are not internally connected to the die. NC/72M, NC/144M, NC/288M, NC/576M NC/1G - No Connects. Not internally connected to the die. NC/72M, NC/144M, NC/288M, NC/576M and NC/1G are address expansion pins are not internally connected to the die. Document #: 38-05357 Rev. *G Ground for the IO Circuitry. Page 8 of 31 [+] Feedback CY7C1441AV33 CY7C1443AV33,CY7C1447AV33 Functional Overview Single Write Accesses Initiated by ADSC All synchronous inputs pass through input registers controlled by the rising edge of the clock. Maximum access delay from the clock rise (t CDV) is 6.5 ns (133-MHz device). This write access is initiated when the following conditions are satisfied at clock rise: (1) CE1, CE2, and CE3 are all asserted active, (2) ADSC is asserted LOW, (3) ADSP is deasserted HIGH, and (4) the write input signals (GW, BWE, and BWX) indicate a write access. ADSC is ignored if ADSP is active LOW. The CY7C1441AV33/CY7C1443AV33/CY7C1447AV33 supports secondary cache in systems utilizing either a linear or interleaved burst sequence. The interleaved burst order supports Pentium and i486™ processors. The linear burst sequence is suited for processors that utilize a linear burst sequence. The burst order is user-selectable, and is determined by sampling the MODE input. Accesses can be initiated with either the Processor Address Strobe (ADSP) or the Controller Address Strobe (ADSC). Address advancement through the burst sequence is controlled by the ADV input. A two-bit on-chip wraparound burst counter captures the first address in a burst sequence and automatically increments the address for the rest of the burst access. Byte write operations are qualified with the Byte Write Enable (BWE) and Byte Write Select (BWx) inputs. A Global Write Enable (GW) overrides all byte write inputs and writes data to all four bytes. All writes are simplified with on-chip synchronous self-timed write circuitry. Three synchronous Chip Selects (CE1, CE2, CE3) and an asynchronous Output Enable (OE) provide for easy bank selection and output tri-state control. ADSP is ignored if CE1 is HIGH. Single Read Accesses A single read access is initiated when the following conditions are satisfied at clock rise: (1) CE1, CE2, and CE3 are all asserted active, and (2) ADSP or ADSC is asserted LOW (if the access is initiated by ADSC, the write inputs must be deasserted during this first cycle). The address presented to the address inputs is latched into the address register and the burst counter/control logic and presented to the memory core. If the OE input is asserted LOW, the requested data is available at the data outputs a maximum to tCDV after clock rise. ADSP is ignored if CE1 is HIGH. Single Write Accesses Initiated by ADSP This access is initiated when the following conditions are satisfied at clock rise: (1) CE1, CE2, CE3 are all asserted active, and (2) ADSP is asserted LOW. The addresses presented are loaded into the address register and the burst inputs (GW, BWE, and BWX)are ignored during this first clock cycle. If the write inputs are asserted active (see Write Cycle Descriptions table for appropriate states that indicate a write) on the next clock rise, the appropriate data is latched and written into the device. Byte writes are allowed. All IOs are tri-stated during a byte write.Since this is a common IO device, the asynchronous OE input signal must be deasserted and the IOs must be tri-stated prior to the presentation of data to DQs. As a safety precaution, the data lines are tri-stated once a write cycle is detected, regardless of the state of OE. Document #: 38-05357 Rev. *G The addresses presented are loaded into the address register and the burst counter/control logic and delivered to the memory core. The information presented to DQS is written into the specified address location. Byte writes are allowed. All IOs are tri-stated when a write is detected, even a byte write. Since this is a common IO device, the asynchronous OE input signal must be deasserted and the IOs must be tri-stated prior to the presentation of data to DQs. As a safety precaution, the data lines are tri-stated once a write cycle is detected, regardless of the state of OE. Burst Sequences The CY7C1441AV33/CY7C1443AV33/CY7C1447AV33 provides an on-chip two-bit wraparound burst counter inside the SRAM. The burst counter is fed by A[1:0], and can follow either a linear or interleaved burst order. The burst order is determined by the state of the MODE input. A LOW on MODE selects a linear burst sequence. A HIGH on MODE selects an interleaved burst order. Leaving MODE unconnected causes the device to default to a interleaved burst sequence. Interleaved Burst Address Table (MODE = Floating or VDD) First Address A1: A0 Second Address A1: A0 Third Address A1: A0 Fourth Address A1: A0 00 01 10 11 01 00 11 10 10 11 00 01 11 10 01 00 Linear Burst Address Table (MODE = GND) First Address A1: A0 Second Address A1: A0 Third Address A1: A0 Fourth Address A1: A0 00 01 10 11 01 10 11 00 10 11 00 01 11 00 01 10 Sleep Mode The ZZ input pin is an asynchronous input. Asserting ZZ places the SRAM in a power conservation “sleep” mode. Two clock cycles are required to enter into or exit from this “sleep” mode. While in this mode, data integrity is guaranteed. Accesses pending when entering the “sleep” mode are not considered valid nor is the completion of the operation guaranteed. The device must be deselected prior to entering the “sleep” mode. CE1, CE2, CE3, ADSP, and ADSC must remain inactive for the duration of tZZREC after the ZZ input returns LOW. Page 9 of 31 [+] Feedback CY7C1441AV33 CY7C1443AV33,CY7C1447AV33 ZZ Mode Electrical Characteristics Parameter IDDZZ tZZS tZZREC tZZI tRZZI Description Test Conditions Sleep mode standby current Device operation to ZZ ZZ recovery time ZZ active to sleep current ZZ Inactive to exit sleep current Min. ZZ > VDD – 0.2V ZZ > VDD – 0.2V ZZ < 0.2V This parameter is sampled This parameter is sampled Max. Unit 100 2tCYC mA ns ns ns ns 2tCYC 2tCYC 0 Truth Table tThe truth table for CY7C1441AV33/CY7C1443AV33/CY7C1447AV33 follows.[2, 3, 4, 5, 6] Cycle Description ADDRESS Used CE1 CE2 CE3 ZZ ADSP Deselected Cycle, Power down None H Deselected Cycle, Power down None L Deselected Cycle, Power down None L Deselected Cycle, Power down None L Deselected Cycle, Power down None X Sleep Mode, Power down X ADSC ADV WRITE OE CLK DQ X L X L X X X L-H Tri-State L X L L X X X X L-H Tri-State X H L L X X X X L-H Tri-State L X L H L X X X L-H Tri-State X X L H L X X X L-H Tri-State None X X X H X X X X X X Tri-State Read Cycle, Begin Burst Read Cycle, Begin Burst Write Cycle, Begin Burst Read Cycle, Begin Burst Read Cycle, Begin Burst Read Cycle, Continue Burst Read Cycle, Continue Burst Read Cycle, Continue Burst External External External External External Next Next Next L L L L L X X H H H H H H X X X L L L L L X X X L L L L L L L L L L H H H H H X X X L L L H H H X X X X X L L L X X L H H H H H L H X L H L H L L-H L-H L-H L-H L-H L-H L-H L-H Q Tri-State Read Cycle, Continue Burst Next H X X L X H L H H L-H Tri-State Write Cycle, Continue Burst Next X X X L H H L L X L-H D Write Cycle, Continue Burst Next H X X L X H L L X L-H D Read Cycle, Suspend Burst Current X X X L H H H H L L-H Q Read Cycle, Suspend Burst Current X X X L H H H H H L-H Tri-State Read Cycle, Suspend Burst Current H X X L X H H H L L-H Q Read Cycle, Suspend Burst Current H X X L X H H H H L-H Tri-State Write Cycle, Suspend Burst Current X X X L H H H L X L-H D Write Cycle, Suspend Burst Current H X X L X H H L X L-H D D Q Tri-State Q Tri-State Q Notes 2. X = “Don't Care.” H = Logic HIGH, L = Logic LOW. 3. WRITE = L when any one or more Byte Write enable signals and BWE = L or GW = L. WRITE = H when all Byte write enable signals, BWE, GW = H. 4. The DQ pins are controlled by the current cycle and the OE signal. OE is asynchronous and is not sampled with the clock. 5. The SRAM always initiates a read cycle when ADSP is asserted, regardless of the state of GW, BWE, or BWX. Writes may occur only on subsequent clocks after the ADSP or with the assertion of ADSC. As a result, OE must be driven HIGH prior to the start of the write cycle to allow the outputs to tri-state. OE is a don't care for the remainder of the write cycle. 6. OE is asynchronous and is not sampled with the clock rise. It is masked internally during write cycles. During a read cycle all data bits are tri-state when OE is inactive or when the device is deselected, and all data bits behave as output when OE is active (LOW). Document #: 38-05357 Rev. *G Page 10 of 31 [+] Feedback CY7C1441AV33 CY7C1443AV33,CY7C1447AV33 Partial Truth Table for Read/Write Function (CY7C1441AV33)[2, 7] GW BWE BWD BWC BWB BWA Read H H X X X X Read H L H H H H Write Byte A (DQA, DQPA) H L H H H L Write Byte B(DQB, DQPB) H L H H L H Write Bytes A, B (DQA, DQB, DQPA, DQPB) H L H H L L Write Byte C (DQC, DQPC) H L H L H H Write Bytes C, A (DQC, DQA, DQPC, DQPA) H L H L H L Write Bytes C, B (DQC, DQB, DQPC, DQPB) H L H L L H Write Bytes C, B, A (DQC, DQB, DQA, DQPC, DQPB, DQPA) H L H L L L Write Byte D (DQD, DQPD) H L L H H H Write Bytes D, A (DQD, DQA, DQPD, DQPA) H L L H H L Write Bytes D, B (DQD, DQA, DQPD, DQPA) H L L H L H Write Bytes D, B, A (DQD, DQB, DQA, DQPD, DQPB, DQPA) H L L H L L Write Bytes D, B (DQD, DQB, DQPD, DQPB) H L L L H H Write Bytes D, B, A (DQD, DQC, DQA, DQPD, DQPC, DQPA) H L L L H L Write Bytes D, C, A (DQD, DQB, DQA, DQPD, DQPB, DQPA) H L L L L H Write All Bytes H L L L L L Write All Bytes L X X X X X Truth Table for Read/Write Function (CY7C1443AV33)[2] GW BWE BWB BWA Read H H X X Read H L H H Write Byte A - (DQA and DQPA) H L H L Write Byte B - (DQB and DQPB) H L L H Write All Bytes H L L L Write All Bytes L X X X Truth Table for Read/Write Function (CY7C1447AV33)[2, 8] GW BWE BWX Read H H X Read H L All BW = H Write Byte x – (DQx and DQPx) H L L Write All Bytes H L All BW = L Write All Bytes L X X Notes 7. Table only lists a partial listing of the byte write combinations. Any Combination of BWX is valid Appropriate write is done based on which byte write is active. 8. BWx represents any byte write signal BW[A..H].To enable any byte write BWx, a Logic LOW signal should be applied at clock rise.Any number of bye writes can be enabled at the same time for any given write. Document #: 38-05357 Rev. *G Page 11 of 31 [+] Feedback CY7C1441AV33 CY7C1443AV33,CY7C1447AV33 IEEE 1149.1 Serial Boundary Scan (JTAG) The CY7C1441AV33/CY7C1443AV33/CY7C1447AV33 incorporates a serial boundary scan test access port (TAP). This part is fully compliant with 1149.1. The TAP operates using JEDEC-standard 3.3V or 2.5V IO logic levels. The CY7C1441AV33/CY7C1443AV33/CY7C1447AV33 contains a TAP controller, instruction register, boundary scan register, bypass register, and ID register. Disabling the JTAG Feature this ball unconnected if the TAP is not used. The ball is pulled up internally, resulting in a logic HIGH level. Test Data-In (TDI) The TDI ball is used to serially input information into the registers and can be connected to the input of any of the registers. The register between TDI and TDO is chosen by the instruction that is loaded into the TAP instruction register. TDI is internally pulled up and can be unconnected if the TAP is unused in an application. TDI is connected to the most significant bit (MSB) of any register. (See Tap Controller Block Diagram.) It is possible to operate the SRAM without using the JTAG feature. To disable the TAP controller, TCK must be tied LOW (VSS) to prevent clocking of the device. TDI and TMS are internally pulled up and may be unconnected. They may alternately be connected to VDD through a pull up resistor. TDO should be left unconnected. Upon power up, the device comes up in a reset state which does not interfere with the operation of the device. Test Data-Out (TDO) TAP Controller State Diagram TAP Controller State Diagram 1 1 TEST-LOGIC RESET 0 RUN-TEST/ IDLE TEST-LOGIC RESET 0 0 0 The TDO output ball is used to serially clock data-out from the registers. The output is active depending upon the current state of the TAP state machine. The output changes on the falling edge of TCK. TDO is connected to the least significant bit (LSB) of any register. (See Tap Controller State Diagram.) RUN-TEST/ IDLE 1 SELECT DR-SCAN 1 SELECT IR-SCAN 0 1 1 SELECT DR-SCAN 0 1 1 0 1 0 EXIT2-DR 0 1 UPDATE-DR 0 0 PAUSE-IR 0 EXIT2-IR 1 1 UPDATE-IR 1 0 1 UPDATE-DR UPDATE-IR 1 1 0 EXIT2-DR EXIT2-IR 1 EXIT1-IR 1 1 0 1 0 PAUSE-DR PAUSE-IR 0 1 0 PAUSE-DR SHIFT-IR 1 EXIT1-DR EXIT1-IR 0 0 0 1 1 EXIT1-DR CAPTURE-IR 0 0 1 0 SHIFT-DR SHIFT-IR SELECT IR-SCAN 1 CAPTURE-DR 0 SHIFT-DR 1 0 1 CAPTURE-IR 0 1 1 0 CAPTURE-DR 0 1 0 1 0 0 The 0/1 next to each state represents the value of TMS at the rising edge of TCK. Test Access Port (TAP) Performing a TAP Reset A RESET is performed by forcing TMS HIGH (VDD) for five rising edges of TCK. This RESET does not affect the operation of the SRAM and may be performed while the SRAM is operating. Test Clock (TCK) At power up, the TAP is reset internally to ensure that TDO comes up in a High-Z state. The test clock is used only with the TAP controller. All inputs are captured on the rising edge of TCK. All outputs are driven from the falling edge of TCK. TAP Registers Test MODE SELECT (TMS) The TMS input is used to give commands to the TAP controller and is sampled on the rising edge of TCK. It is allowable to leave Document #: 38-05357 Rev. *G Registers are connected between the TDI and TDO balls and scan data into and out of the SRAM test circuitry. Only one register can be selected at a time through the instruction register. Data is serially loaded into the TDI ball on the rising edge of TCK. Data is output on the TDO ball on the falling edge of TCK. Page 12 of 31 [+] Feedback CY7C1441AV33 CY7C1443AV33,CY7C1447AV33 Instruction Register IDCODE Three-bit instructions can be serially loaded into the instruction register. This register is loaded when it is placed between the TDI and TDO balls as shown in the Tap Controller Block Diagram. Upon power up, the instruction register is loaded with the IDCODE instruction. It is also loaded with the IDCODE instruction if the controller is placed in a reset state as described in the previous section. The IDCODE instruction loads a vendor-specific, 32-bit code into the instruction register. It also places the instruction register between the TDI and TDO balls and shifts the IDCODE out of the device when the TAP controller enters the Shift-DR state. When the TAP controller is in the Capture-IR state, the two least significant bits are loaded with a binary “01” pattern to allow for fault isolation of the board-level serial test data path. Bypass Register To save time when serially shifting data through registers, it is sometimes advantageous to skip certain chips. The bypass register is a single-bit register that can be placed between the TDI and TDO balls. This shifts data through the SRAM with minimal delay. The bypass register is set LOW (VSS) when the BYPASS instruction is executed. Boundary Scan Register The boundary scan register is connected to all the input and bidirectional balls on the SRAM. The boundary scan register is loaded with the contents of the RAM IO ring when the TAP controller is in the Capture-DR state and is then placed between the TDI and TDO balls when the controller is moved to the Shift-DR state. The EXTEST, SAMPLE/PRELOAD and SAMPLE Z instructions can be used to capture the contents of the IO ring. The Boundary Scan Order tables show the order in which the bits are connected. Each bit corresponds to one of the bumps on the SRAM package. The MSB of the register is connected to TDI, and the LSB is connected to TDO. Identification (ID) Register The ID register is loaded with a vendor-specific, 32-bit code during the Capture-DR state when the IDCODE command is loaded in the instruction register. The IDCODE is hardwired into the SRAM and can be shifted out when the TAP controller is in the Shift-DR state. The ID register has a vendor code and other information described in the Identification Register Definitions table. TAP Instruction Set Overview The IDCODE instruction is loaded into the instruction register upon power up or whenever the TAP controller is given a test logic reset state. SAMPLE Z The SAMPLE Z instruction connects the boundary scan register between the TDI and TDO pins when the TAP controller is in a Shift-DR state. The SAMPLE Z command puts the output bus into a High-Z state until the next command is given during the “Update IR” state. SAMPLE/PRELOAD SAMPLE/PRELOAD is a 1149.1 mandatory instruction. When the SAMPLE/PRELOAD instructions are loaded into the instruction register and the TAP controller is in the Capture-DR state, a snapshot of data on the inputs and output pins is captured in the boundary scan register. The user must be aware that the TAP controller clock can only operate at a frequency up to 20 MHz, while the SRAM clock operates more than an order of magnitude faster. Because there is a large difference in the clock frequencies, it is possible that during the Capture-DR state, an input or output undergoes a transition. The TAP may then try to capture a signal while in transition (metastable state). This does not harm the device, but there is no guarantee as to the value that is captured. Repeatable results may not be possible. To guarantee that the boundary scan register captures the correct value of a signal, the SRAM signal must be stabilized long enough to meet the TAP controller's capture setup plus hold times (tCS and tCH). The SRAM clock input might not be captured correctly if there is no way in a design to stop (or slow) the clock during a SAMPLE/PRELOAD instruction. If this is an issue, it is still possible to capture all other signals and simply ignore the value of the CK and CK captured in the boundary scan register. After the data is captured, it is possible to shift out the data by putting the TAP into the Shift-DR state. This places the boundary scan register between the TDI and TDO pins. PRELOAD places an initial data pattern at the latched parallel outputs of the boundary scan register cells prior to the selection of another boundary scan test operation. Eight different instructions are possible with the three bit instruction register. All combinations are listed in the Instruction Codes table. Three of these instructions are listed as RESERVED and should not be used. The other five instructions are described in this section in detail. The shifting of data for the SAMPLE and PRELOAD phases can occur concurrently when required—that is, while data captured is shifted out, the preloaded data can be shifted in. Instructions are loaded into the TAP controller during the Shift-IR state when the instruction register is placed between TDI and TDO. During this state, instructions are shifted through the instruction register through the TDI and TDO balls. To execute the instruction once it is shifted in, the TAP controller must be moved into the Update-IR state. When the BYPASS instruction is loaded in the instruction register and the TAP is placed in a Shift-DR state, the bypass register is placed between the TDI and TDO pins. The advantage of the BYPASS instruction is that it shortens the boundary scan path when multiple devices are connected together on a board. Document #: 38-05357 Rev. *G BYPASS Page 13 of 31 [+] Feedback CY7C1441AV33 CY7C1443AV33,CY7C1447AV33 instruction. When HIGH, it enables the output buffers to drive the output bus. When LOW, this bit places the output bus into a High-Z condition. EXTEST The EXTEST instruction drives the preloaded data out through the system output pins. This instruction also connects the boundary scan register for serial access between the TDI and TDO in the shift-DR controller state. This bit can be set by entering the SAMPLE/PRELOAD or EXTEST command, and then shifting the desired bit into that cell, during the “Shift-DR” state. During “Update-DR”, the value loaded into that shift-register cell latches into the preload register. When the EXTEST instruction is entered, this bit directly controls the output Q-bus pins. Note that this bit is pre-set HIGH to enable the output when the device is powered-up, and also when the TAP controller is in the “Test-Logic-Reset” state. EXTEST OUTPUT BUS TRI-STATE IEEE Standard 1149.1 mandates that the TAP controller be able to put the output bus into a tri-state mode. The boundary scan register has a special bit located at bit #89 (for 165-FBGA package) or bit #138 (for 209-FBGA package). When this scan cell, called the “extest output bus tri-state”, is latched into the preload register during the “Update-DR” state in the TAP controller, it directly controls the state of the output (Q-bus) pins, when the EXTEST is entered as the current Reserved These instructions are not implemented but are reserved for future use. Do not use these instructions. TAP Timing 1 2 Test Clock (TCK) 3 t t TH t TMSS t TMSH t TDIS t TDIH TL 4 5 6 t CYC Test Mode Select (TMS) Test Data-In (TDI) t TDOV t TDOX Test Data-Out (TDO) DON’T CARE Document #: 38-05357 Rev. *G UNDEFINED Page 14 of 31 [+] Feedback CY7C1441AV33 CY7C1443AV33,CY7C1447AV33 TAP AC Switching Characteristics Over the Operating Range[9, 10] Parameter Description Min. Max. Unit 20 MHz Clock tTCYC TCK Clock Cycle Time tTF TCK Clock Frequency tTH TCK Clock HIGH time 20 ns tTL TCK Clock LOW time 20 ns 50 ns Output Times tTDOV TCK Clock LOW to TDO Valid tTDOX TCK Clock LOW to TDO Invalid 0 ns tTMSS TMS Setup to TCK Clock Rise 5 ns tTDIS TDI Setup to TCK Clock Rise 5 ns tCS Capture Setup to TCK Rise 5 ns tTMSH TMS Hold after TCK Clock Rise 5 ns tTDIH TDI Hold after Clock Rise 5 ns tCH Capture Hold after Clock Rise 5 ns 10 ns Setup Times Hold Times Notes 9. tCS and tCH refer to the setup and hold time requirements of latching data from the boundary scan register. 10. Test conditions are specified using the load in TAP AC test Conditions. tR/tF = 1 ns. Document #: 38-05357 Rev. *G Page 15 of 31 [+] Feedback CY7C1441AV33 CY7C1443AV33,CY7C1447AV33 3.3V TAP AC Test Conditions 2.5V TAP AC Test Conditions Input pulse levels.................................................VSS to 3.3V Input pulse levels................................................. VSS to 2.5V Input rise and fall times....................................................1 ns Input rise and fall time .....................................................1 ns Input timing reference levels........................................... 1.5V Input timing reference levels......................................... 1.25V Output reference levels .................................................. 1.5V Output reference levels ................................................ 1.25V Test load termination supply voltage .............................. 1.5V Test load termination supply voltage ............................ 1.25V 3.3V TAP AC Output Load Equivalent 2.5V TAP AC Output Load Equivalent 1.25V 1.5V 50Ω 50Ω TDO TDO Z O = 50 Ω Z O = 50 Ω 20p F 20p F TAP DC Electrical Characteristics And Operating Conditions (0°C < TA < +70°C; VDD = 3.135V to 3.6V unless otherwise noted)[11] Parameter Description Description Conditions Min. Max. Unit VOH1 Output HIGH Voltage IOH = –4.0 mA VDDQ = 3.3V 2.4 V IOH = –1.0 mA VDDQ = 2.5V 2.0 V VOH2 Output HIGH Voltage IOH = –100 µA VDDQ = 3.3V 2.9 V VDDQ = 2.5V 2.1 VOL1 Output LOW Voltage VOL2 Output LOW Voltage VIH Input HIGH Voltage VIL Input LOW Voltage IX Input Load Current IOL = 8.0 mA V VDDQ = 3.3V 0.4 V IOL = 1.0 mA VDDQ = 2.5V 0.4 V IOL = 100 µA VDDQ = 3.3V 0.2 V VDDQ = 2.5V 0.2 V 2.0 VDD + 0.3 V VDDQ = 2.5V 1.7 VDD + 0.3 V VDDQ = 3.3V –0.3 0.8 V VDDQ = 2.5V –0.3 0.7 V –5 5 µA VDDQ = 3.3V GND < VIN < VDDQ Note 11. All voltages referenced to VSS (GND). Document #: 38-05357 Rev. *G Page 16 of 31 [+] Feedback CY7C1441AV33 CY7C1443AV33,CY7C1447AV33 Identification Register Definitions CY7C1441AV33 CY7C1443AV33 CY7C1447AV33 (1M x 36) (2M x 18) (512K x 72) Instruction Field Revision Number (31:29) Description 000 000 000 Device Depth (28:24) 01011 01011 01011 Architecture/Memory Type(23:18)[12] 000001 000001 000001 Defines memory type and architecture Defines width and density Bus Width/Density(17:12) Cypress JEDEC ID Code (11:1) Describes the version number. Reserved for Internal Use 100111 010111 110111 00000110100 00000110100 00000110100 1 1 1 ID Register Presence Indicator (0) Allows unique identification of SRAM vendor. Indicates the presence of an ID register. Scan Register Sizes Bit Size (x36) Bit Size (x18) Bit Size (x18) Instruction Register Name 3 3 3 Bypass 1 1 1 ID 32 32 32 Boundary Scan Order (165-ball FBGA package) 89 89 - Boundary Scan Order (209-ball FBGA package) - - 138 Identification Codes Instruction Code Description EXTEST 000 Captures IO ring contents. IDCODE 001 Loads the ID register with the vendor ID code and places the register between TDI and TDO. This operation does not affect SRAM operations. SAMPLE Z 010 Captures IO ring contents. Places the boundary scan register between TDI and TDO. Forces all SRAM output drivers to a High-Z state. RESERVED 011 Do Not Use: This instruction is reserved for future use. SAMPLE/PRELOAD 100 Captures IO ring contents. Places the boundary scan register between TDI and TDO. Does not affect SRAM operation. RESERVED 101 Do Not Use: This instruction is reserved for future use. RESERVED 110 Do Not Use: This instruction is reserved for future use. BYPASS 111 Places the bypass register between TDI and TDO. This operation does not affect SRAM operations. Note 12. Bit #24 is “1” in the ID Register Definitions for both 2.5V and 3.3V versions of this device. Document #: 38-05357 Rev. *G Page 17 of 31 [+] Feedback CY7C1441AV33 CY7C1443AV33,CY7C1447AV33 165-ball FBGA Boundary Scan Order[13,14] CY7C1441AV33 (1M x 36), CY7C1443AV33 (2M x 18) Bit # Ball ID Bit # Ball ID 1 26 E11 N6 2 27 D11 N7 3 N10 28 G10 4 P11 29 F10 5 P8 30 E10 6 R8 31 D10 7 R9 32 C11 8 P9 33 A11 9 P10 34 B11 10 R10 35 A10 11 R11 36 B10 12 H11 37 A9 13 N11 38 B9 14 M11 39 C10 15 L11 40 A8 16 K11 41 B8 17 J11 42 A7 18 M10 43 B7 19 L10 44 B6 20 K10 45 A6 21 J10 46 B5 22 H9 47 A5 23 H10 48 A4 24 G11 49 B4 25 F11 50 B3 Bit # 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 Ball ID A3 A2 B2 C2 B1 A1 C1 D1 E1 F1 G1 D2 E2 F2 G2 H1 H3 J1 K1 L1 M1 J2 K2 L2 M2 Bit # 76 77 78 79 80 81 82 83 84 85 86 87 88 89 Ball ID N1 N2 P1 R1 R2 P3 R3 P2 R4 P4 N5 P6 R6 Internal Notes 13. Balls which are NC (No Connect) are preset LOW. 14. Bit# 89 is preset HIGH. Document #: 38-05357 Rev. *G Page 18 of 31 [+] Feedback CY7C1441AV33 CY7C1443AV33,CY7C1447AV33 Maximum Ratings DC Input Voltage ................................... –0.5V to VDD + 0.5V Exceeding maximum ratings may shorten the useful life of the device. User guidelines are not tested. Storage Temperature ................................. –65°C to +150°C Current into Outputs (LOW)......................................... 20 mA Static Discharge Voltage........................................... >2001V (per MIL-STD-883, Method 3015) Latch-up Current..................................................... >200 mA Ambient Temperature with Power Applied ............................................ –55°C to +125°C Operating Range Supply Voltage on VDD Relative to GND ........–0.3V to +4.6V Range Supply Voltage on VDDQ Relative to GND ...... –0.3V to +VDD Commercial DC Voltage Applied to Outputs in Tri-State ...........................................–0.5V to VDDQ + 0.5V Industrial Ambient Temperature VDD VDDQ 0°C to +70°C 3.3V –5%/+10% 2.5V –5% to VDD –40°C to +85°C Electrical Characteristics Over the Operating Range[15, 16] DC Electrical Characteristics Over the Operating Range Parameter Description Test Conditions Min. Max. Unit 3.135 3.6 V for 3.3V IO 3.135 VDD V for 2.5V IO 2.375 2.625 V VDD Power Supply Voltage VDDQ IO Supply Voltage VOH Output HIGH Voltage for 3.3V IO, IOH = –4.0 mA 2.4 for 2.5V IO, IOH = –1.0 mA 2.0 VOL Output LOW Voltage VIH Input HIGH Voltage[15] [15] V V for 3.3V IO, IOL = 8.0 mA 0.4 V for 2.5V IO, IOL = 1.0 mA 0.4 V for 3.3V IO 2.0 VDD + 0.3V V for 2.5V IO 1.7 VDD + 0.3V V for 3.3V IO –0.3 0.8 V for 2.5V IO VIL Input LOW Voltage –0.3 0.7 V IX Input Leakage Current except ZZ and MODE GND ≤ VI ≤ VDDQ –5 5 μA Input Current of MODE Input = VSS –30 Input = VDD Input Current of ZZ μA 5 Input = VSS Input = VDD μA μA –5 30 μA 5 μA 310 mA IOZ Output Leakage Current GND ≤ VI ≤ VDDQ, Output Disabled IDD VDD Operating Supply Current VDD = Max., IOUT = 0 mA, f = fMAX = 1/tCYC 7.5-ns cycle, 133 MHz 10-ns cycle, 100 MHz 290 mA ISB1 Automatic CE Power down Current—TTL Inputs Max. VDD, Device Deselected, VIN ≥ VIH or VIN ≤ VIL, f = fMAX, inputs switching All Speeds 180 mA ISB2 Automatic CE Power down Current—CMOS Inputs Max. VDD, Device Deselected, VIN ≥ VDD – 0.3V or VIN ≤ 0.3V, f = 0, inputs static All speeds 120 mA ISB3 Automatic CE Power down Current—CMOS Inputs Max. VDD, Device Deselected, VIN ≥ VDDQ – 0.3V or VIN ≤ 0.3V, f = fMAX, inputs switching All Speeds 180 mA ISB4 Automatic CE Power down Current—TTL Inputs Max. VDD, Device Deselected, VIN ≥ VDD – 0.3V or VIN ≤ 0.3V, f = 0, inputs static All Speeds 135 mA –5 Notes 15. Overshoot: VIH(AC) < VDD +1.5V (Pulse width less than tCYC/2), undershoot: VIL(AC) > –2V (Pulse width less than tCYC/2). 16. TPower-up: Assumes a linear ramp from 0V to VDD(min.) within 200 ms. During this time VIH < VDD and VDDQ < VDD. Document #: 38-05357 Rev. *G Page 19 of 31 [+] Feedback CY7C1441AV33 CY7C1443AV33,CY7C1447AV33 Capacitance Parameter[17] Test Conditions 100 TQFP Max. 165 FBGA Max. 209 FBGA Max. Unit TA = 25°C, f = 1 MHz, VDD = 3.3V VDDQ = 2.5V 6.5 7 5 pF 3 7 5 pF 5.5 6 7 pF Test Conditions 100 TQFP Package 165 FBGA Package 209 FBGA Package Unit Test conditions follow standard test methods and procedures for measuring thermal impedance, per EIA/JESD51. 25.21 20.8 25.31 °C/W 2.28 3.2 4.48 °C/W Description CIN Input Capacitance CCLK Clock Input Capacitance CIO Input/Output Capacitance Thermal Resistance Parameter[17] Description ΘJA Thermal Resistance (Junction to Ambient) ΘJC Thermal Resistance (Junction to Case) Figure 2. AC Test Loads and Waveforms 3.3V IO Test Load R = 317Ω 3.3V OUTPUT ALL INPUT PULSES VDDQ OUTPUT RL = 50Ω Z0 = 50Ω 10% 90% 10% 90% GND 5 pF R = 351Ω ≤ 1 ns ≤ 1 ns VT = 1.5V INCLUDING JIG AND SCOPE (a) (c) (b) 2.5V IO Test Load R = 1667Ω 2.5V OUTPUT Z0 = 50Ω 10% R = 1538Ω VT = 1.25V INCLUDING JIG AND SCOPE 90% 10% 90% GND 5 pF (a) ALL INPUT PULSES VDDQ OUTPUT RL = 50Ω (b) ≤ 1 ns ≤ 1 ns (c) Note 17. Tested initially and after any design or process change that may affect these parameters Document #: 38-05357 Rev. *G Page 20 of 31 [+] Feedback CY7C1441AV33 CY7C1443AV33,CY7C1447AV33 Switching Characteristics Over the Operating Range[22, 23] Description Parameter tPOWER VDD (Typical) to the first Access[18] –133 Min. –100 Max. Min. Max. Unit 1 1 ms 7.5 10 ns Clock tCYC Clock Cycle Time tCH Clock HIGH 2.5 3.0 ns tCL Clock LOW 2.5 3.0 ns Output Times tCDV Data Output Valid After CLK Rise tDOH Data Output Hold After CLK Rise 2.5 2.5 ns tCLZ Clock to Low-Z[19, 20, 21] 2.5 2.5 ns tCHZ Clock to High-Z[19, 20, 21] 3.8 tOEV OE LOW to Output Valid 3.0 Low-Z[19, 20, 21] tOELZ OE LOW to Output tOEHZ OE HIGH to Output High-Z[19, 20, 21] 6.5 0 8.5 0 4.5 ns 3.8 ns 0 3.0 ns ns 4.0 ns Setup Times tAS Address Setup Before CLK Rise 1.5 1.5 ns tADS ADSP, ADSC Setup Before CLK Rise 1.5 1.5 ns tADVS ADV Setup Before CLK Rise 1.5 1.5 ns tWES GW, BWE, BWX Setup Before CLK Rise 1.5 1.5 ns tDS Data Input Setup Before CLK Rise 1.5 1.5 ns tCES Chip Enable Setup 1.5 1.5 ns tAH Address Hold After CLK Rise 0.5 0.5 ns tADH ADSP, ADSC Hold After CLK Rise 0.5 0.5 ns tWEH GW, BWE, BWX Hold After CLK Rise 0.5 0.5 ns tADVH ADV Hold After CLK Rise 0.5 0.5 ns tDH Data Input Hold After CLK Rise 0.5 0.5 ns tCEH Chip Enable Hold After CLK Rise 0.5 0.5 ns Hold Times Notes 18. This part has a voltage regulator internally; tPOWER is the time that the power must be supplied above VDD(minimum) initially, before a read or write operation can be initiated. 19. tCHZ, tCLZ,tOELZ, and tOEHZ are specified with AC test conditions shown in part (b) of “AC Test Loads and Waveforms” on page 20. Transition is measured ± 200 mV from steady-state voltage. 20. At any given voltage and temperature, tOEHZ is less than tOELZ and tCHZ is less than tCLZ to eliminate bus contention between SRAMs when sharing the same data bus. These specifications do not imply a bus contention condition, but reflect parameters guaranteed over worst case user conditions. Device is designed to achieve High-Z prior to Low-Z under the same system conditions. 21. This parameter is sampled and not 100% tested. 22. Timing reference level is 1.5V when VDDQ = 3.3V and is 1.25V when VDDQ = 2.5V. 23. Test conditions shown in (a) of AC Test Loads unless otherwise noted. Document #: 38-05357 Rev. *G Page 21 of 31 [+] Feedback CY7C1441AV33 CY7C1443AV33,CY7C1447AV33 Timing Diagrams Figure 3. Read Cycle Timing[24] tCYC CLK t t ADS CH t CL tADH ADSP t ADS tADH ADSC t AS tAH A1 ADDRESS A2 t GW, BWE,BW WES t WEH X t CES Deselect Cycle t CEH CE t ADVS t ADVH ADV ADV suspends burst OE t OEV t OEHZ t CLZ Data Out (Q) High-Z Q(A1) t CDV t OELZ t CHZ t DOH Q(A2) Q(A2 + 1) Q(A2 + 2) t CDV Q(A2 + 3) Q(A2) Q(A2 + 1) Q(A2 + 2) Burst wraps around to its initial state Single READ BURST READ DON’T CARE UNDEFINED . Note 24. On this diagram, when CE is LOW: CE1 is LOW, CE2 is HIGH and CE3 is LOW. When CE is HIGH: CE1 is HIGH or CE2 is LOW or CE3 is HIGH. Document #: 38-05357 Rev. *G Page 22 of 31 [+] Feedback CY7C1441AV33 CY7C1443AV33,CY7C1447AV33 Timing Diagrams (continued) Figure 4. Write Cycle Timing[24, 25] t CYC CLK t t ADS CH t CL tADH ADSP t ADS ADSC extends burst tADH t ADS tADH ADSC t AS tAH A1 ADDRESS A2 A3 Byte write signals are ignored for first cycle when ADSP initiates burst t WES tWEH BWE, BW X t WES t WEH GW t CES tCEH CE t ADVS tADVH ADV ADV suspends burst OE t Data in (D) High-Z t DS t DH D(A1) D(A2) D(A2 + 1) D(A2 + 1) D(A2 + 2) D(A2 + 3) D(A3) D(A3 + 1) D(A3 + 2) OEHZ Data Out (Q) BURST READ Single WRITE BURST WRITE DON’T CARE Extended BURST WRITE UNDEFINED . Note 25. Full width write can be initiated by either GW LOW; or by GW HIGH, BWE LOW and BWX LOW Document #: 38-05357 Rev. *G Page 23 of 31 [+] Feedback CY7C1441AV33 CY7C1443AV33,CY7C1447AV33 Timing Diagrams (continued) Figure 5. Read/Write Cycle Timing[24, 26, 27] tCYC CLK t t ADS CH t CL tADH ADSP ADSC t AS ADDRESS A1 tAH A2 A3 A4 t WES t A5 A6 WEH BWE, BW X t CES tCEH CE ADV OE t DS Data In (D) Data Out (Q) High-Z t OEHZ Q(A1) tDH t OELZ D(A3) D(A5) Q(A4) Q(A2) Back-to-Back READs D(A6) t CDV Single WRITE Q(A4+1) Q(A4+2) BURST READ DON’T CARE Q(A4+3) Back-to-Back WRITEs UNDEFINED . Note 26. The data bus (Q) remains in high-Z following a WRITE cycle, unless a new read access is initiated by ADSP or ADSC. 27. GW is HIGH Document #: 38-05357 Rev. *G Page 24 of 31 [+] Feedback CY7C1441AV33 CY7C1443AV33,CY7C1447AV33 Timing Diagrams (continued) Figure 6. ZZ Mode Timing[28, 29] CLK t ZZ ZZ I t ZZREC t ZZI SUPPLY I DDZZ t RZZI ALL INPUTS (except ZZ) Outputs (Q) DESELECT or READ Only High-Z DON’T CARE Note 28. Device must be deselected when entering ZZ mode. See Cycle Descriptions table for all possible signal conditions to deselect the device. 29. DQs are in high-Z when exiting ZZ sleep mode. Document #: 38-05357 Rev. *G Page 25 of 31 [+] Feedback CY7C1441AV33 CY7C1443AV33,CY7C1447AV33 Ordering Information Not all of the speed, package and temperature ranges are available. Please contact your local sales representative or visit www.cypress.com for actual products offered. Speed (MHz) 133 Ordering Code CY7C1441AV33-133AXC Package Diagram Part and Package Type 51-85050 100-Pin Thin Quad Flat Pack (14 x 20 x 1.4 mm) Pb-free Operating Range Commercial CY7C1443AV33-133AXC CY7C1441AV33-133BZC 51-85165 165-ball Fine-Pitch Ball Grid Array (15 x 17 x 1.4 mm) CY7C1443AV33-133BZC CY7C1441AV33-133BZXC 51-85165 165-ball Fine-Pitch Ball Grid Array (15 x 17 x 1.4 mm) Pb-free CY7C1443AV33-133BZXC CY7C1447AV33-133BGC CY7C1447AV33-133BGXC CY7C1441AV33-133AXI 51-85167 209-ball Fine-Pitch Ball Grid Array (14 x 22 x 1.76 mm) 209-ball Fine-Pitch Ball Grid Array (14 x 22 x 1.76 mm) Pb-free 51-85050 100-Pin Thin Quad Flat Pack (14 x 20 x 1.4 mm) Pb-free lndustrial CY7C1443AV33-133AXI CY7C1441AV33-133BZI 51-85165 165-ball Fine-Pitch Ball Grid Array (15 x 17 x 1.4 mm) CY7C1443AV33-133BZI CY7C1441AV33-133BZXI 51-85165 165-ball Fine-Pitch Ball Grid Array (15 x 17 x 1.4 mm) Pb-free CY7C1443AV33-133BZXI CY7C1447AV33-133BGI CY7C1447AV33-133BGXI 100 CY7C1441AV33-100AXC 51-85167 209-ball Fine-Pitch Ball Grid Array (14 x 22 x 1.76 mm) 209-ball Fine-Pitch Ball Grid Array (14 x 22 x 1.76 mm) Pb-free 51-85050 100-Pin Thin Quad Flat Pack (14 x 20 x 1.4 mm) Pb-free Commercial CY7C1443AV33-100AXC CY7C1441AV33-100BZC 51-85165 165-ball Fine-Pitch Ball Grid Array (15 x 17 x 1.4 mm) CY7C1443AV33-100BZC CY7C1441AV33-100BZXC 51-85165 165-ball Fine-Pitch Ball Grid Array (15 x 17 x 1.4 mm) Pb-free CY7C1443AV33-100BZXC CY7C1447AV33-100BGC CY7C1447AV33-100BGXC CY7C1441AV33-100AXI 51-85167 209-ball Fine-Pitch Ball Grid Array (14 x 22 x 1.76 mm) 209-ball Fine-Pitch Ball Grid Array (14 x 22 x 1.76 mm) Pb-free 51-85050 100-Pin Thin Quad Flat Pack (14 x 20 x 1.4 mm) Pb-free lndustrial CY7C1443AV33-100AXI CY7C1441AV33-100BZI 51-85165 165-ball Fine-Pitch Ball Grid Array (15 x 17 x 1.4 mm) CY7C1443AV33-100BZI CY7C1441AV33-100BZXI 51-85165 165-ball Fine-Pitch Ball Grid Array (15 x 17 x 1.4 mm) Pb-free CY7C1443AV33-100BZXI CY7C1447AV33-100BGI CY7C1447AV33-100BGXI Document #: 38-05357 Rev. *G 51-85167 209-ball Fine-Pitch Ball Grid Array (14 x 22 x 1.76 mm) 209-ball Fine-Pitch Ball Grid Array (14 x 22 x 1.76 mm) Pb-free Page 26 of 31 [+] Feedback CY7C1441AV33 CY7C1443AV33,CY7C1447AV33 Package Diagrams Figure 1. 100-pin TQFP (14 x 20 x 1.4 mm) (51-85050) 16.00±0.20 1.40±0.05 14.00±0.10 100 81 80 1 20.00±0.10 22.00±0.20 0.30±0.08 0.65 TYP. 30 12°±1° (8X) SEE DETAIL A 51 31 50 0.20 MAX. 0.10 1.60 MAX. R 0.08 MIN. 0.20 MAX. 0° MIN. SEATING PLANE STAND-OFF 0.05 MIN. 0.15 MAX. 0.25 NOTE: 1. JEDEC STD REF MS-026 GAUGE PLANE 0°-7° R 0.08 MIN. 0.20 MAX. 2. BODY LENGTH DIMENSION DOES NOT INCLUDE MOLD PROTRUSION/END FLASH MOLD PROTRUSION/END FLASH SHALL NOT EXCEED 0.0098 in (0.25 mm) PER SIDE BODY LENGTH DIMENSIONS ARE MAX PLASTIC BODY SIZE INCLUDING MOLD MISMATCH 3. DIMENSIONS IN MILLIMETERS 0.60±0.15 0.20 MIN. 1.00 REF. DETAIL A 51-85050-*B Document #: 38-05357 Rev. *G Page 27 of 31 [+] Feedback CY7C1441AV33 CY7C1443AV33,CY7C1447AV33 Package Diagrams (continued) Figure 2. 165-ball FBGA (15 x 17 x 1.4 mm) (51-85165) PIN 1 CORNER BOTTOM VIEW TOP VIEW Ø0.05 M C PIN 1 CORNER Ø0.25 M C A B Ø0.45±0.05(165X) 1 2 3 4 5 6 7 8 9 10 11 11 10 9 8 7 6 5 4 3 2 1 A B B C C 1.00 A D D F F G G H J 14.00 E 17.00±0.10 E H J K L L 7.00 K M M N N P P R R A 1.00 5.00 0.35 0.15 C +0.05 -0.10 0.53±0.05 0.25 C 10.00 B 15.00±0.10 0.15(4X) SEATING PLANE Document #: 38-05357 Rev. *G 1.40 MAX. 0.36 C 51-85165-*A Page 28 of 31 [+] Feedback CY7C1441AV33 CY7C1443AV33,CY7C1447AV33 Package Diagrams (continued) Figure 3. 209-ball FBGA (14 x 22 x1.76 mm) (51-85167) 51-85167-** Document #: 38-05357 Rev. *G Page 29 of 31 [+] Feedback CY7C1441AV33 CY7C1443AV33,CY7C1447AV33 Document History Page Document Title: CY7C1441AV33/CY7C1443AV33/CY7C1447AV33 36-Mbit (1M x 36/2M x 18/512K x 72) Flow-Through SRAM Document Number: 38-05357 REV. ECN NO. Issue Date Orig. of Change Description of Change ** 124459 03/06/03 CJM New Data Sheet *A 254910 See ECN SYT Part number changed from previous revision. New and old part number differ by the letter “A” Modified Functional Block diagrams Modified switching waveforms Added Footnote #13 (32-Bit Vendor I.D Code changed) Added Boundary scan information Added IDD, IX and ISB values in the DC Electrical Characteristics Added tPOWER specifications in Switching Characteristics table Removed 119 PBGA Package Changed 165 FBGA Package from BB165C (15 x 17 x 1.20 mm) to BB165 (15 x 17 x 1.40 mm) Changed 209-Lead PBGA BG209 (14 x 22 x 2.20 mm) to BB209A (14 x 22 x 1.76 mm) *B 300131 See ECN SYT Removed 150 and 117 MHz Speed Bins Changed ΘJA and ΘJC from TBD to 25.21 and 2.58 °C/W respectively for TQFP Package on Pg # 21 Added lead-free information for 100-pin TQFP, 165 FBGA and 209 BGA Packages. Added comment of ‘Lead-free BG and BZ packages availability’ below the Ordering Information *C 320813 See ECN SYT Changed H9 pin from VSSQ to VSS on the Pin Configuration table for 209 FBGA Changed the test condition from VDD = Min. to VDD = Max for VOL in the Electrical Characteristics table. Replaced the TBD’s for IDD, ISB1, ISB2, ISB3 and ISB4 to their respective values. Replaced TBD’s for ΘJA and ΘJC to their respective values for 165 fBGA and 209 fBGA packages on the Thermal Resistance table. Changed CIN,CCLK and CIO to 6.5, 3 and 5.5 pF from 5, 5 and 7 pF for TQFP Package. Removed “Lead-free BG and BZ packages availability” comment below the Ordering Information *D 331551 See ECN SYT Modified Address Expansion balls in the pinouts for 165 FBGA and 209 BGA Packages as per JEDEC standards and updated the Pin Definitions accordingly Modified VOL, VOH test conditions Replaced TBD to 100 mA for IDDZZ Changed CIN, CCLK and CIO to 7, 7and 6 pF from 5, 5 and 7 pF for 165 FBGA Package. Added Industrial Temperature Grade Changed ISB2 and ISB4 from 100 and 110 mA to 120 and 135 mA respectively Updated the Ordering Information by shading and unshading MPNs as per availability Document #: 38-05357 Rev. *G Page 30 of 31 [+] Feedback CY7C1441AV33 CY7C1443AV33,CY7C1447AV33 Document Title: CY7C1441AV33/CY7C1443AV33/CY7C1447AV33 36-Mbit (1M x 36/2M x 18/512K x 72) Flow-Through SRAM Document Number: 38-05357 REV. ECN NO. Issue Date Orig. of Change *E 417547 See ECN RXU Converted from Preliminary to Final. Changed address of Cypress Semiconductor Corporation on Page# 1 from “3901 North First Street” to “198 Champion Court”. Changed IX current value in MODE from –5 & 30 μA to –30 & 5 μA respectively and also Changed IX current value in ZZ from –30 & 5 μA to –5 & 30 μA respectively on page# 19. Modified test condition in note# 8 from VIH < VDD to VIH < VDD. Modified “Input Load” to “Input Leakage Current except ZZ and MODE” in the Electrical Characteristics Table. Replaced Package Name column with Package Diagram in the Ordering Information table. Replaced Package Diagram of 51-85050 from *A to *B Updated the Ordering Information. *F 473650 See ECN VKN Added the Maximum Rating for Supply Voltage on VDDQ Relative to GND. Changed tTH, tTL from 25 ns to 20 ns and tTDOV from 5 ns to 10 ns in TAP AC Switching Characteristics table. Updated the Ordering Information table. *G 2447027 See ECN Description of Change VKN/AESA Corrected typo in the Ordering Information table Corrected typo in the CY7C1447AV33 ‘s Logic Block diagram Updated the x72 block diagram © Cypress Semiconductor Corporation, 2003-2008. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. Any Source Code (software and/or firmware) is owned by Cypress Semiconductor Corporation (Cypress) and is protected by and subject to worldwide patent protection (United States and foreign), United States copyright laws and international treaty provisions. Cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of, and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress integrated circuit as specified in the applicable agreement. Any reproduction, modification, translation, compilation, or representation of this Source Code except as specified above is prohibited without the express written permission of Cypress. Disclaimer: CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress’ product in a life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. Use may be limited by and subject to the applicable Cypress software license agreement. Document #: 38-05357 Rev. *G Revised May 09, 2008 Page 31 of 31 i486 is a trademark, and Intel and Pentium are registered trademarks of Intel Corporation. PowerPC is a trademark of IBM Corporation. All product and company names mentioned in this document are the trademarks of their respective holders. [+] Feedback