78Q8430 10/100 Ethernet
MAC and PHY
Simplifying System Integration TM
DATA SHEET
March 2009
DESCRIPTION
FEATURES
The Teridian 78Q8430 is a 10/100 Fast Ethernet
controller supporting multi-media offload. The
device is optimized for host processor offloading
and throughput enhancements for demanding
multi-media applications found in Set Top Box,
IP Video and Broadband Media Appliance
applications. The 78Q8430 seamlessly
interfaces to non-PCI processors through a
simplified pseudo SRAM-like Host Bus Interface
supporting 32/16/8 bit data bus widths.
Supported features include IEEE802.3x flow
control and full IEEE802.3 and 802.3u standards
compliance.
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Supporting 10Base-T and 100Base-TX, the
transceiver provides Auto MDI-X cable
cross-over correction, AUTO Negotiation, Link
Configuration and full/half duplex support with
full duplex flow control. The line interface
requires only a dual 1:1 isolation transformer.
Numerous packet processing and IP address
resolution control functions are incorporated,
including an extensive set of Error Monitoring,
Reporting and Troubleshooting features. The
78Q8430 provides optimal 10/100 Ethernet
connectivity in demanding video streaming and
mixed-media applications.
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BENEFITS
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Support for IEEE-802.3, IEEE-802.3u and
IEEE-802.3-2000 Annex 31.B
Low host CPU utilization/overhead with
minimal software driver overhead and small
driver memory space requirements
Improved packet processing, low latency and
low host CPU utilization
Highest performance streaming Video over IP
Optimized performance in mixed media
application such as video, data and voice
Ease of use, faster development cycles, high
throughput
Optimized power conservation with automatic
turn on when needed
Reduced host CPU utilization and overhead
Improved packet processing
Optimized performance in mixed media
applications
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APPLICATIONS
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Rev. 1.2
Single chip 10Base-T/100Base-TX
IEEE-802.3 compliant MAC and PHY
Adaptive 32 kB SRAM FIFO memory
allocation between Tx and Rx paths
Queue independent user settable water
marks
Per queue status indication
Address Resolution Controller (ARC)
Multiple perfect address filtering: 8 default
(max 12)
Wildcard address filtering, individual,
multicast and broadcast address
recognition and filtering
Positive/negative filtering and promiscuous
mode
64 kB JUMBO packet support
QoS: 4 Transmit priority levels
Non-PCI pseudo-SRAM Host Bus Interface
8-bit, 16-bit and 32-bit bus width
Big/little endian support for 16-bit/32-bit bus
widths
Asynchronous (100 MHz) and synchronous
(50 MHz) bus clock support
Low power and flexible power supply
management
Power down/save
Wake on LAN (Magic Packet™, OnNow
packet)
Link status change
Traffic Offload Engine Functionality
Transfer frame: APF & ICMP Echo
IP Firewall configuration: drop frames on
source IP address
IP Checksum
Available in an industrial temperature range
(-40 °C to +85 °C)
RoHS compliant (6/6) lead-free package
Satellite, cable and IPTV Set Top Boxes
Multi Media Residential Gateways
High Definition 1080p/1080i DTVs
IP-PVR and video distribution systems
Digital Video Recorders/Players
Routers and IADs
Video over IP system, IP-PBX
IP Security Cameras / PVRs
Low latency industrial automation
© 2009 Teridian Semiconductor Corporation
1
78Q8430 Data Sheet
DS_8430_001
Table of Contents
1
Introduction ......................................................................................................................................... 7
1.1 Systems Applications ................................................................................................................... 7
1.2 System Level Application Information.......................................................................................... 8
1.2.1 Set Top Box Application .................................................................................................. 8
1.2.2 IP Security Application ..................................................................................................... 8
1.2.3 IP PBX Application ........................................................................................................... 9
1.3 Overview ...................................................................................................................................... 9
1.4 Application Environments .......................................................................................................... 10
1.5 Supply Voltages ......................................................................................................................... 10
1.6 Power Management ................................................................................................................... 10
2
Pinout ................................................................................................................................................. 11
3
Pin Description .................................................................................................................................. 12
3.1 Pin Legend ................................................................................................................................. 12
3.2 Pin Descriptions ......................................................................................................................... 12
3.2.1 Clock Pins ...................................................................................................................... 12
3.2.2 Media Dependent Interface (MDI) Pins ......................................................................... 13
3.2.3 LED Display (PHY) Pins ................................................................................................ 13
3.2.4 EEPROM Pins ............................................................................................................... 13
3.2.5 GBI Data Pins ................................................................................................................ 14
3.2.6 GBI Address Pins .......................................................................................................... 15
3.2.7 GBI Control Pins ............................................................................................................ 15
3.2.8 Mode Pins ...................................................................................................................... 16
3.2.9 JTAG Pins ...................................................................................................................... 16
3.2.10 Power Pins ..................................................................................................................... 17
4
Electrical Specification..................................................................................................................... 18
4.1 Absolute Maximum Ratings ....................................................................................................... 18
4.2 Recommended Operation Conditions........................................................................................ 18
4.3 DC Characteristics ..................................................................................................................... 18
4.4 Digital I/O Characteristics .......................................................................................................... 19
4.5 Analog Electrical Characteristics ............................................................................................... 19
4.5.1 100Base-TX Transmitter................................................................................................ 19
4.5.2 100Base-TX Transmitter (Informative) .......................................................................... 19
4.5.3 100Base-TX Receiver.................................................................................................... 20
4.5.4 10Base-T Transmitter .................................................................................................... 20
4.5.5 10Base-T Transmitter (Informative) ............................................................................... 20
4.5.6 10Base-T Receiver ........................................................................................................ 21
5
Host Interface Timing Specification ................................................................................................ 22
5.1 Host Interface ............................................................................................................................. 22
5.1.1 Synchronous Mode Timing ............................................................................................ 23
5.1.2 Bus Clock Timing ........................................................................................................... 24
5.1.3 Reset Timing .................................................................................................................. 24
6
Functional Description ..................................................................................................................... 25
6.1 Internal Block Diagrams ............................................................................................................. 25
6.1.1 Internal Digital Block ...................................................................................................... 25
6.1.2 Internal PHY................................................................................................................... 25
6.2 Data Queuing ............................................................................................................................. 26
6.3 Host Interface ............................................................................................................................. 27
6.3.1 Reading Receive Data ................................................................................................... 27
6.3.2 Writing Transmit Data .................................................................................................... 27
6.3.3 DMA Slave Mode Access .............................................................................................. 29
6.4 Snoop Mode Access .................................................................................................................. 29
6.5 Water Marking ............................................................................................................................ 30
6.5.1 Interrupt Watermark ....................................................................................................... 30
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78Q8430 Data Sheet
6.5.2 PAUSE Watermark ........................................................................................................ 30
6.5.3 Headroom Watermark ................................................................................................... 30
6.6 Counters..................................................................................................................................... 30
6.6.1 Summary of Counters .................................................................................................... 30
6.6.2 Reading and Setting Counter Values ............................................................................ 31
6.6.3 Precision Counting ......................................................................................................... 32
6.6.4 Rollover Interrupts ......................................................................................................... 32
6.7 Packet Classification .................................................................................................................. 32
6.7.1 Address Filtering ............................................................................................................ 34
6.7.2 Configuring the CAM ..................................................................................................... 38
6.7.3 Frame Format ................................................................................................................ 39
6.7.4 Default CAM Rule Summary.......................................................................................... 39
6.8 Timers ........................................................................................................................................ 44
6.8.1 PAUSE Timer................................................................................................................. 44
6.8.2 HNR Timer ..................................................................................................................... 44
6.8.3 Interrupt Delay Timer ..................................................................................................... 44
6.9 EEPROM Controller ................................................................................................................... 44
6.10 Ethernet MAC ............................................................................................................................ 44
6.10.1 MAC Transmit Block ...................................................................................................... 44
6.10.2 MAC Receive Block ....................................................................................................... 45
6.10.3 MAC Control Register .................................................................................................... 45
6.10.4 Transmitting a Frame ..................................................................................................... 45
6.10.5 IEEE 802.3 Transmit Protocols...................................................................................... 45
6.10.6 Transmit Operation ........................................................................................................ 46
6.10.7 Receiving a Frame ......................................................................................................... 46
6.10.8 Strip Padding/FCS ......................................................................................................... 47
6.11 MAC Error Reporting ................................................................................................................. 47
6.11.1 MAC Transmit Errors ..................................................................................................... 47
6.11.2 MAC Receive Errors ...................................................................................................... 48
6.12 PHY Operations ......................................................................................................................... 49
6.12.1 Automatic MDI/MDIX Cable Crossover Configuration ................................................... 49
6.12.2 100Base-TX Transmit .................................................................................................... 49
6.12.3 100Base-TX Receive ..................................................................................................... 49
6.12.4 10Base-T Transmit ........................................................................................................ 49
6.12.5 10Base-T Receive ......................................................................................................... 50
6.12.6 SQE Test ....................................................................................................................... 50
6.12.7 Polarity Correction ......................................................................................................... 50
6.12.8 Natural Loopback ........................................................................................................... 50
6.12.9 Auto-Negotiation ............................................................................................................ 51
6.12.10 LED Indicators .............................................................................................................. 51
6.12.11 PHY Interrupts .............................................................................................................. 51
6.12.12 Internal Clock PLL ........................................................................................................ 51
7
Register Descriptions ....................................................................................................................... 52
7.1 Register Overview...................................................................................................................... 52
7.2 QUE Register Overview ............................................................................................................. 53
7.3 CTL Register Overview .............................................................................................................. 54
7.4 Snoop Address Space Overview ............................................................................................... 55
7.5 QUE Registers ........................................................................................................................... 56
7.5.1 Packet Control Word Register ....................................................................................... 56
7.5.2 Packet Size Register ..................................................................................................... 56
7.5.3 Setup Transmit Data Register ....................................................................................... 57
7.5.4 Transmit Data Register .................................................................................................. 57
7.5.5 Receive Data Register ................................................................................................... 57
7.5.6 QUE First/Last Register ................................................................................................. 58
7.5.7 QUE Status Register ..................................................................................................... 58
7.6 CTL Registers ............................................................................................................................ 59
7.6.1 DMA Control and Status Register.................................................................................. 59
7.6.2 Receive Packet Status Register .................................................................................... 59
Rev. 1.2
3
78Q8430 Data Sheet
7.7
DS_8430_001
7.6.3 Transmit Packet Status Register ................................................................................... 59
7.6.4 Transmit Producer Status .............................................................................................. 60
7.6.5 Receive Producer Status ............................................................................................... 60
7.6.6 Revision ID..................................................................................................................... 61
7.6.7 Configuration.................................................................................................................. 61
7.6.8 Receive to Transmit Transfer Register .......................................................................... 61
7.6.9 Frame Disposition Register ........................................................................................... 61
7.6.10 Receive FIRST BLOCK Status Register ....................................................................... 61
7.6.11 Receive Data Status Register........................................................................................ 62
7.6.12 BIST Control Register .................................................................................................... 62
7.6.13 BIST Bypass Mode Data Register ................................................................................. 63
7.6.14 Station Management Data Register .............................................................................. 63
7.6.15 Station Management Control and Address Register ..................................................... 63
7.6.16 PROM Data Register ..................................................................................................... 63
7.6.17 PROM Control Register ................................................................................................. 64
7.6.18 MAC Control Register .................................................................................................... 64
7.6.19 Count Data Register ...................................................................................................... 65
7.6.20 Counter Control Register ............................................................................................... 65
7.6.21 Counter Management Register...................................................................................... 66
7.6.22 Snoop Control Register ................................................................................................. 66
7.6.23 Interrupt Delay Count Register ...................................................................................... 66
7.6.24 Pause Delay Count Register ......................................................................................... 66
7.6.25 Host Not Responding Count Register ........................................................................... 67
7.6.26 Wake Up Status Register .............................................................................................. 67
7.6.27 Water Mark Values Register .......................................................................................... 67
7.6.28 Power Management Capabilities ................................................................................... 67
7.6.29 Power Management Control and Status Register ......................................................... 68
7.6.30 CAM Address Register .................................................................................................. 68
7.6.31 Rule Match Register ...................................................................................................... 69
7.6.32 Rule Control Register .................................................................................................... 69
7.6.33 Que Status Interrupt Register ........................................................................................ 70
7.6.34 Que Status Mask Register ............................................................................................. 70
7.6.35 Overflow/Underrun Interrupt Register ............................................................................ 71
7.6.36 Overflow/Underrun Mask Register................................................................................. 71
7.6.37 Transmit RMON Interrupt Register ................................................................................ 71
7.6.38 Transmit RMON Mask Register ..................................................................................... 72
7.6.39 Receive RMON Interrupt Register ................................................................................. 72
7.6.40 Receive RMON Mask Register ...................................................................................... 72
7.6.41 Host Interrupt Register ................................................................................................... 72
7.6.42 Host Interrupt Mask Register ......................................................................................... 73
PHY Management Registers ..................................................................................................... 74
7.7.1 PHY Register Overview ................................................................................................. 74
7.7.2 PHY Control Register – MR0 ......................................................................................... 75
7.7.3 PHY Status Register – MR1 .......................................................................................... 76
7.7.4 PHY Identifier Registers – MR2, MR3 ........................................................................... 77
7.7.5 PHY Auto-Negotiation Advertisement Registers – MR4 ............................................... 77
7.7.6 PHY Auto-Negotiation Line Partner Ability Register – MR5 .......................................... 78
7.7.7 PHY Auto-Negotiation Expansion Register – MR6........................................................ 78
7.7.8 PHY Vendor Specific Register – MR16 ......................................................................... 79
7.7.9 PHY Interrupt Control / Status Register – MR17 ........................................................... 80
7.7.10 PHY Transceiver Control Register – MR19 ................................................................... 80
7.7.11 PHY Diagnostic Register – MR18.................................................................................. 81
7.7.12 PHY LED Configuration Register – MR23 ..................................................................... 81
7.7.13 PHY MDI / MDIX Control Register – MR24 ................................................................... 82
8
Isolation Transformers ..................................................................................................................... 83
9
Reference Crystal ............................................................................................................................. 83
10
System Bus Interface Schematic .................................................................................................... 84
11
Line Interface Schematic.................................................................................................................. 85
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78Q8430 Data Sheet
12
Package Mechanical Drawing (100-pin LQFP) ............................................................................... 86
13
Ordering Information ........................................................................................................................ 87
14
Related Documentation .................................................................................................................... 87
15
Contact Information .......................................................................................................................... 87
Tables
Table 1: Pin Legend .................................................................................................................................... 12
Table 2: Clock Pin Descriptions .................................................................................................................. 12
Table 3: MDI Pin Descriptions..................................................................................................................... 13
Table 4: LED Pin Descriptions .................................................................................................................... 13
Table 5: EEPROM Interface Pin Descriptions ............................................................................................ 13
Table 6: GBI Data Pin Descriptions ............................................................................................................ 14
Table 7: GBI Address Pin Descriptions....................................................................................................... 15
Table 8: GBI Control Pin Descriptions ........................................................................................................ 15
Table 9: Chip Mode Pin Descriptions .......................................................................................................... 16
Table 10: JTAG Pin Descriptions ................................................................................................................ 16
Table 11: Power Pin Descriptions ............................................................................................................... 17
Table 12: Absolute Maximum Ratings ........................................................................................................ 18
Table 13: Recommended Operating Conditions ......................................................................................... 18
Table 14: DC Characteristics ...................................................................................................................... 18
Table 15: Digital I/O Characteristics ........................................................................................................... 19
Table 16: MII 100Base-TX Transmit Timing ............................................................................................... 19
Table 17: MII 100Base-TX Transmitter (Informative) ................................................................................. 19
Table 18: MII 100Base-TX Receiver Timing ............................................................................................... 20
Table 19: MII 10Base-T Transmitter Timing ............................................................................................... 20
Table 20: MII 10Base-T Transmitter (Informative) ...................................................................................... 20
Table 21: MII 10Base-T Receive Timing..................................................................................................... 21
Table 22: Transmit Data Buffer Example .................................................................................................... 28
Table 23: Counter Summary ....................................................................................................................... 30
Table 24: CAM Rules Associated with Unicast Filter Bytes ........................................................................ 34
Table 25: CAM Rules Associated with Multicast Filter Bytes ..................................................................... 36
Table 26: Control Logic Actions .................................................................................................................. 38
Table 27: RCR Match Control ..................................................................................................................... 39
Table 28: Ethernet Frame for Classification................................................................................................ 39
Table 29: Process Destination Address Rules............................................................................................ 40
Table 30: Process Source Address Rules .................................................................................................. 42
Table 31: Process Length/Type, MAC Control Frames and Start IP Header Checksum Rules................. 42
Table 32: Process Rules for OnNow Packet............................................................................................... 43
Table 33: Process Rules for Magic Packet ................................................................................................. 43
Table 34: PHY Register Group ................................................................................................................... 74
Table 35: Isolation Transformers ................................................................................................................ 83
Table 36: Reference Crystal ....................................................................................................................... 83
Table 37: 78Q8430 Order Numbers and Packaging Marks........................................................................ 87
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78Q8430 Data Sheet
DS_8430_001
Figures
Figure 1: 78Q8430 Block Diagram ................................................................................................................ 7
Figure 2: Set Top Box Diagram .................................................................................................................... 8
Figure 3: Network Cameras Diagram ........................................................................................................... 8
Figure 4: Typical FXO VoIP Application........................................................................................................ 9
Figure 5: Device Block Diagram ................................................................................................................... 9
Figure 6: GBI Bus Block Diagram ............................................................................................................... 10
Figure 7: Pinout ........................................................................................................................................... 11
Figure 8: Host Interface Timing Diagram .................................................................................................... 22
Figure 9: Host Bus Output Timing Diagram ................................................................................................ 23
Figure 10: Host Bus Input Timing Diagram ................................................................................................. 23
Figure 11: Bus Clock Timing ....................................................................................................................... 24
Figure 12: Internal Digital Block Diagram ................................................................................................... 25
Figure 13: Internal PHY Block Diagram ...................................................................................................... 26
Figure 14: Classification Architecture ......................................................................................................... 33
Figure 15: System Bus Interface Schematic ............................................................................................... 84
Figure 16: Line Interface Schematic ........................................................................................................... 85
Figure 17: LQFP Drawing ........................................................................................................................... 86
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Rev. 1.2
DS_8430_001
78Q8430 Data Sheet
1 Introduction
The Teridian 78Q8430 is a single chip 10Base-T/100Base-TX capable Fast Ethernet Media Access
Controller (MAC) and Physical Layer (PHY) transceiver. The device is optimized for video applications,
such as the Set Top Box (STB), and easily interfaces to available STB core processors, such as the
STi5100, STi5516, STi5514, ARM™ and Intel® based processors. The 78Q8430 is compliant with
applicable IEEE-802.3 standards. MAC and PHY configuration and status registers are provided as
specified by IEEE-802.3u.
The 78Q8430 operates over Category-5 Unshielded Twisted Pair (Cat-5 UTP) cabling in 100Base-TX
applications and over Cat-3 UTP in 10Base-T applications requiring only a dual 1:1 isolation transformer
interface to the copper media.
The Ethernet MAC section makes use of a 32 kB deep on-chip SRAM FIFO packet memory to adaptively buffer
transmit and receive data. SRAM memory can be dynamically allocated to either the transmit queues or the
receive queues as required to optimize throughput.
The host processor accesses the FIFO(s) using a simple asynchronous pseudo-SRAM like host bus interface.
A 32 bit wide bus is provided; the bus width can be pin-configured for 8-bit, 16-bit or 32-bit bus width at boot-up.
Big endian, little endian and mixed endian options are available in 32-bit operation; little endian is available for
16-bit operation. Different End-in variations are supported through internal circuitry with minimal user
intervention required.
The MAC interface logic may assert MEMWAIT during bus transactions, requesting wait states from the host
while critical internal data transfer completes. The MAC provides both half duplex and full duplex operation, as
well as support for full duplex flow control. Complete, portable device drivers for Linux®, OS20 and VxWorks®
are available.
The 78Q8430 operates from a single 3.3 V supply. Power down modes and power saving modes are
available. The 78Q8430 defaults to use an on-chip crystal oscillator. In this mode, a 25 MHz reference
crystal is connected between the XTLP and XTLN pins. Alternatively, an externally generated 25 MHz
clock can be connected to the XTLP pin. The chip will automatically configure itself to use the external
clock. In this mode of operation, a crystal is not required.
1.1
Systems Applications
Figure 1 presents an overview of the 78Q8430 in a block diagram.
LED
Link (Programmable)
8-bit/16-bit/32-bit
System Bus
Configuration
EEPROM Interface
(Optional)
JTAG Interface
TERIDIAN
78Q8430
LED
Activity (Programmable)
Single Chip
10/100 Ethernet
Controller
RJ45
CAT 5
Cable
1:1
Transformer
Figure 1: 78Q8430 Block Diagram
Rev. 1.2
7
78Q8430 Data Sheet
1.2
DS_8430_001
System Level Application Information
This section provides an overview of system level applications in some typical high-volume consumer
equipment.
1.2.1
Set Top Box Application
Figure 2 shows a typical application diagram for a set top box.
Figure 2: Set Top Box Diagram
1.2.2
IP Security Application
Figure 3 shows a typical application diagram for an IPTV security camera application.
Figure 3: Network Cameras Diagram
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Rev. 1.2
DS_8430_001
1.2.3
78Q8430 Data Sheet
IP PBX Application
Figure 4 shows a typical application diagram for an IP PBX application.
78Q8430
10/100 MAC/PHY
78Q8430
10/100 MAC/PHY
Figure 4: Typical FXO VoIP Application
1.3
Overview
The 78Q8430 is divided into four sections, as shown in Figure 5.
•
•
•
•
Generic Bus Interface (GBI) Control Layer
Queue Memory Layer
Ethernet Media Access Control (MAC) Layer
Ethernet Physical (PHY) Layer
GBI Bus Layer
GBI
Access
Logic
Queue Memory Layer
QUE
Controller
QUE Write
Logic
DMA Slave
Mode Logic
QUE Write
Logic
RX
FIFO
MAC Read
Logic
RMON
Snoop
Controller
Packet
Classify
CTL
Controller
CAM
TX
PCS
PMD
QUEUE
SRAM
Pause/
HNR
Timers
PHY Layer
MAC TX
Logic
TX
FIFO
MAC Write
Logic
QUE Write
Logic
QUE Read
Logic
Flow
Control
Memory
Manager
QUE Write
Logic
GBI
MAC Layer
RX
PCS
MAC RX
Logic
MAC Control
& Status
Registers
SMI Control
& Status
Register
Figure 5: Device Block Diagram
Rev. 1.2
9
78Q8430 Data Sheet
1.4
DS_8430_001
Application Environments
This section provides an overview of the application environments such as the STMicroelectronics and
Embest ARM9™ processors, for which the 78Q8430 provides a seamless interface. Figure 6 shows a
simple application diagram for a design using the GBI based 10/100-Mbps Ethernet Controller. By
providing a direct connection to the GBI bus, applications requiring Ethernet network access can be
realized with a high degree of integration. The figure shows the processor and the Ethernet controller
with connected address and data buses. This connection can be either on the motherboard, or via an
expansion module. The GBI Controller controls the address and data and the system control signals.
GBI
8/16/32-bit Bus
78Q8430
10/100 Mbps
Ethernet
Controller
and PHY
EEPROM
or ROM
1:1 Transformer
And RJ45
Connector
Figure 6: GBI Bus Block Diagram
Figure 6 shows the components that are likely to be used with the 10/100-Mbps Ethernet Controller. The
integrated PHY is designed to directly connect to an integrated 1:1 transformer and RJ-45 connector,
thereby providing a minimum parts solution.
1.5
Supply Voltages
The 78Q8430 requires a single 3.3 V (+/-5%) supply voltage. No external components are required to
generate on-chip bias voltages and currents. High accuracy is maintained through a closed-loop trimmed
biasing network. On-chip power converters generate 1.8 V power for core digital logic and memory
blocks. The voltage regulator is not affected by the power-down mode.
1.6
Power Management
The 78Q8430 supports both normal and power-saving modes. When the GBI bus is active, it can be in
normal mode or Power Management low-power modes.
10
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2
78Q8430 Data Sheet
Pinout
The 78Q8430 is available in a 14x14 mm 100-pin LQFP package.
GND
TXN
TXP
VCC
VCC
RXP
RXN
LED1
GND
LED0
GND
XTLN
XTLP
VCC
CLKMODE
WAITMODE
BUSMODE
VCC
TDO
ENDIAN1
ENDIAN0
GND
PROMDI
PROMDO
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
BOOTSZ1 100
BOOTSZ0
1
75
GND
2
74
PROMCS
PROMCLK
TMS
3
73
PME
TDI
TRST
4
72
INT
5
71
VCC
TCLK
6
70
GND
RESET
7
69
DATA31
VCC
8
68
DATA30
ADDR1
9
67
DATA29
ADDR0
WR
10
66
DATA28
11
65
DATA27
OE
12
64
DATA26
MEMWAIT
13
63
DATA25
GND
14
62
DATA24
BUSCLK
CS
15
61
VCC
16
60
GND
VCC
17
59
DATA23
ADDR2
18
58
DATA22
ADDR3
19
57
DATA21
ADDR4
20
56
DATA20
ADDR5
21
55
DATA19
ADDR6
22
54
DATA18
ADDR7
23
53
DATA17
ADDR8
24
52
DATA16
ADDR9
25
51
VCC
78Q8430
47
48
DATA11
DATA12
DATA13
DATA14
DATA15
46
GND
45
VCC
50
44
GND
49
43
VCC
DATA10
GND
DATA9
36
GND
42
35
DATA5
DATA8
34
DATA4
41
33
DATA3
DATA7
32
DATA2
40
31
DATA1
39
30
DATA0
VCC
29
VCC
DATA6
28
GND
38
27
37
26
Figure 7: Pinout
Rev. 1.2
11
78Q8430 Data Sheet
DS_8430_001
3 Pin Description
3.1
Pin Legend
Table 1 lists the different pin types found on the 78Q8430 device. The Type field of the pin description
tables refers to one of these types.
Table 1: Pin Legend
Type
A
IU
IS
O
OD
S
I
ID
B
OZ
G
3.2
Description
Analog
TTL-level Input, with Pull-up
TTL-level Input, with Schmitt Trigger
TTL-level Output
TTL-level Output (Open Drain)
Supply
TTL-level Input
TTL-level Input, with Pull-down
TTL-level Bidirectional Pin
TTL-level Output (Tristate)
Ground
Pin Descriptions
The pin descriptions in the following tables are grouped by interface. A pin number, type specification per
Table 2 and a functional description is provided for each pin on the 78Q8430 device.
3.2.1
Clock Pins
Table 2: Clock Pin Descriptions
Signal
XTLP
XTLN
BUSCLK
12
Pin Number
87
88
Type
A
15
I
Description
Crystal Positive/Negative
To use the internal oscillator, connect a 25 MHz crystal across
XTLP and XTLN. To use of an external clock, XTLN is grounded
and XTLP is driven with a 25 MHz clock.
Provides timing reference for all media dependant interface
operations. An internal PLL is used to multiply this clock by four
for use as the main system clock in internal clock mode.
Peripheral Clock
The source for the main system clock in external clock mode. In
synchronous bus mode, all host bus signals are assumed to be
synchronous to this clock.
Rev. 1.2
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3.2.2
78Q8430 Data Sheet
Media Dependent Interface (MDI) Pins
Table 3: MDI Pin Descriptions
Signal
TXP
Pin Number
97
Type
A
TXN
98
A
RXP
94
A
RXN
93
A
3.2.3
Description
Transmit Output Positive/Negative
Transmitter outputs for both 10BASE-T and 100BASE-TX.
MDI-X Mode: Receive Input Positive/Negative
Receiver inputs for both 10BASE-T and 100BASE-TX.
Receive Input Positive/Negative
Receiver inputs for both 10BASE-T and 100BASE-TX.
MDI-X Mode: Transmit Output Positive/Negative
Transmitter outputs for both 10BASE-T and 100BASE- TX.
LED Display (PHY) Pins
The LED pins use standard logic drivers. They output a logic low when the LED is meant to be on and
are tri-state when it is meant to be off. The LED cathode should be connected to the output pin and a
series resistor from the power supply connected to the LED anode.
Table 4: LED Pin Descriptions
Signal
LED0
Pin Number
90
Type
OZ
LED1
92
OZ
3.2.4
Description
PHY display LED0 (Link OK)
The default for LED0 is Link OK (LED is on for link established).
PHY display LED1 (Activity)
The default for LED1 is Link Activity (LED blinks for Rx or Tx data
transferred).
EEPROM Pins
Table 5: EEPROM Interface Pin Descriptions
Signal
PROM_CS
Pin Number
75
Type
O
PROM_CLK
74
O
PROM_DI
77
I
PROM_DO
76
OZ
Rev. 1.2
Description
EEPROM Chip Select
Used to frame transmissions to and from an external
EEPROM.
EEPROM Clock
Clock for transmitting to and from an external EEPROM/ROM.
This is compatible with the slowest commercial parts, which
specify a maximum frequency of 1 MHz.
EEPROM Data In
Data line for transmitting from the external EEPROM to the
controller. Must be high with no EEPROM present.
EEPROM Data Out
Transfers data from the controller to an external
EEPROM/ROM.
13
78Q8430 Data Sheet
3.2.5
DS_8430_001
GBI Data Pins
Table 6: GBI Data Pin Descriptions
Signal
DATA31
DATA30
DATA29
DATA28
DATA27
DATA26
DATA25
DATA24
DATA23
DATA22
DATA21
DATA20
DATA19
DATA18
DATA17
DATA16
DATA15
DATA14
DATA13
DATA12
DATA11
DATA10
DATA9
DATA8
DATA7
DATA6
DATA5
DATA4
DATA3
DATA2
DATA1
DATA0
14
Pin Number
69
68
67
66
65
64
63
62
59
58
57
56
55
54
53
52
49
48
47
46
45
42
41
40
39
38
33
32
31
30
29
28
Type
B
Description
Data Bus DATA[31:0]
Bi-directional host bus data. The BOOTSZ pins determine how
many of these are actually used. The OE input will disable the
output drivers to prevent bus collisions.
Rev. 1.2
DS_8430_001
3.2.6
78Q8430 Data Sheet
GBI Address Pins
Table 7: GBI Address Pin Descriptions
Signal
ADDR9
ADDR8
ADDR7
ADDR6
ADDR5
ADDR4
ADDR3
ADDR2
ADDR1
ADDR0
3.2.7
Pin Number
25
24
23
22
21
20
19
18
9
10
Type
I
I
I
I
I
I
I
I
I
I
Description
Address Bus
The address lines are required to be stable for the entire duration
of a CS cycle. In synchronous bus mode, the address pins are
sampled on the first rising edge of BUSCLK that CS is asserted
low. In asynchronous bus mode, the address pins are sampled as
soon as the falling edge of CS is synchronized to the internal
system clock.
In 32-bit bus mode, ADDR[1:0] are ignored. In 16-bit bus mode,
ADDR[0] is ignored. In 8-bit bus mode, all ADDR bits are used to
reference a register byte.
GBI Control Pins
Table 8: GBI Control Pin Descriptions
Signal
Pin Number
7
Type
I
CS
16
I
WR
11
I
OE
12
I
MEMWAIT
13
OZ
INT
72
OD
PME
73
OD
RESET
Rev. 1.2
Description
Reset (active low)
Referred to as hardware reset. Causes all 78Q8430 outputs to
enter a high-impedance state, stops all current operations and
initializes registers.
Chip Select (active low)
The Processor asserts this signal to initiate a read or write
operation.
Write Enable (active low)
The Processor asserts WR to indicate a write operation.
Output Enable (active low)
The Processor asserts OE to enable the 78Q8430 data drivers
during a read cycle.
Memory Wait
During a bus cycle the 78Q8430 asserts MEMWAIT to indicate
that it is not ready to drive or receive valid data on the DATA
lines. The polarity is dependent on the WAITMODE pin. When
WAITMODE is high then the pin is asserted high; when
WAITMODE is low then the pin is asserted low.
Interrupt (active low)
The 78Q8430 asserts the INT signal low when it detects an
interrupt event.
Power Management Event (active low)
The 78Q8430 asserts the PME signal low when it detects a
wake-up event.
15
78Q8430 Data Sheet
3.2.8
DS_8430_001
Mode Pins
Table 9: Chip Mode Pin Descriptions
Signal
BUSMODE
CLKMODE
WAITMODE
Pin Number
83
85
84
Type
I
I
I
ENDIAN0
ENDIAN1
79
80
I
I
BOOTSZ1
BOOTSZ0
100
1
I
I
Description
BUSMODE, CLKMODE, WAITMODE Configuration
0,0,0 = Sync bus, ext. system clock, memwait act low
0,0,1 = Sync bus, ext. system clock, memwait act high
0,1,0 = Reserved
0,1,1 = Reserved
1,0,0 = Async bus, ext. system clock, memwait act low
1,0,1 = Async bus, ext. system clock, memwait act high
1,1,0 = Async bus, int. system clock, memwait act low
1,1,1 = Async bus, int. system clock, memwait act high
Data Bus Endian Select
0,0 = Big endian (MSB at high bit positions)
0,1 = Bytes are little endian inside 16-bit words
1,0 = Word endian (MSW at low bit positions)
1,1 = Little endian (MSB at low bit positions)
GBI Bus Size
BOOTSZ[1:0]: is strapped to indicate the GBI bus size:
00 = Bus is 32 bits wide
01 = Bus is 16 bits wide. Only DATA[15:0] are used.
10 = Bus is 8 bits wide. Only DATA[7:0] are used.
11 = Reserved
Notes:
1. The internal PHY should never be powered down when the internal system clock is selected by
the CLKMODE pin (CLKMODE=1)
2. There is no external visibility for the system clock when the internal clock mode is selected. The
GBI interface must therefore always be used in asynchronous bus mode.
3.2.9
JTAG Pins
Table 10: JTAG Pin Descriptions
Signal
Type
TRST
Pin Number
5
TCLK
6
I
TMS
3
IU
TDI
4
IU
TDO
81
O
16
I
Description
Test Reset (active low)
System provided reset for JTAG logic.
Test Clock
System provided clock for JTAG logic.
Test Mode Select
Enables JTAG boundary scan using serial in/serial out ports.
Sampled on rising edge of TCLK.
Test Data In
Serial input port for clocking in test data to be shifted to the
output at the end of the boundary scan chain (TDO).
Test Data Out
Serial output port for clocking out test data shifted from the
input at the beginning of the boundary scan chain (TDI).
Rev. 1.2
DS_8430_001
78Q8430 Data Sheet
3.2.10 Power Pins
Table 11: Power Pin Descriptions
Signal
VCCA
VCC
GND
Rev. 1.2
Pin Number
86
95
96
8
17
27
36-37
44
51
61
71
82
2
14
26
34-35
43
50
60
70
78
89
91
99
Type
S
Description
3.3 V supply for the analog transmit section.
S
3.3 V supply for the digital logic section.
G
Common ground return.
17
78Q8430 Data Sheet
DS_8430_001
4 Electrical Specification
4.1
Absolute Maximum Ratings
Operation above the maximum rating may permanently damage the device.
Table 12: Absolute Maximum Ratings
Parameter
DC Supply Voltage (V CC )
Storage Temperature
Pin Voltage (except TXOP/N and RXIP/N)
Pin Voltage (TXOP/N and RXIP/N only)
Pin Current
4.2
Rating
-0.5 to 4.0 VDC
-65 to 150 °C
-0.3 to (V CC +0.6) VDC
-0.3 to (V CC +1.4) VDC
± 120 mA
Recommended Operation Conditions
Unless otherwise noted all specifications are valid over these temperatures and supply voltage ranges.
Table 13: Recommended Operating Conditions
Parameter
DC Voltage Supply (V CC )
Ambient Operating Temperature (T AMB )
4.3
Rating
3.3 ± 0.17 VDC
-40 to +85 °C
DC Characteristics
Table 14: DC Characteristics
Parameter
Supply Current
Symbol
I CC
Conditions
V CC = 3.3 V
Auto-Negotiation
10BT (Idle)
10BT (Normal Activity)
100BTX
Supply Current
I CC
Power-down mode
18
Min
–
Nom
–
124
110
230
165
Max
–
150
140
250
190
Unit
–
mA
–
14
45
mA
Rev. 1.2
DS_8430_001
4.4
78Q8430 Data Sheet
Digital I/O Characteristics
Table 15: Digital I/O Characteristics
Parameter
Input Voltage Low
Input Voltage High
Input Current
Input Capacitance
Output Voltage Low
Output Voltage
High**
Output Transition
Time
Tri-state Output
Leakage Current*
Symbol
V IL
V IH
I IL , I IH
C IN
V OL
V OH
Conditions
I OL = 8 mA
I OH = -8 mA
TT
C L = 20 pF
I OH = -8 ma (H to Z )
Type tri-state only
IZ
Min
–
2.0
-1
–
–
2.4
Nom
–
–
–
8
–
–
Max
0.8
–
1
–
0.4
–
Unit
V
V
µA
pF
V
V
–
–
6
ns
-1
–
1
µA
**PMEB and INTB are active low outputs requiring external pull-up resistors. V OH for these outputs is not
specified.
4.5
4.5.1
Analog Electrical Characteristics
100Base-TX Transmitter
Table 16: MII 100Base-TX Transmit Timing
Parameter
Peak Output Amplitude (|V P +|, |V P -|)
(see note below)
Output Amplitude Symmetry
Output Overshoot
Rise/Fall time (t R , t F )
Rise/Fall time Imbalance
Duty Cycle Distortion
Jitter
Conditions
Best-fit over 14 bit times;
0.4 dB Transformer loss
|V P +|
|V P -|
Percent of V P +, V P 10-90% of V P +, V P |t R - t F |
Deviation from best-fit
time-grid;
010101... Sequence
Scrambled Idle, Internal
Oscillator Mode
Min
950
Nom
–
Max
1050
Unit
mVpk
0.98
–
1.02
–
3
–
–
–
–
–
–
5
5
500
±250
%
ns
ps
ps
–
–
1.4
ns
Note: Measured at the line side of the transformer. Test Condition: Transformer P/N: TLA-6T103. Line
Termination: 100 Ω±1%
4.5.2
100Base-TX Transmitter (Informative)
Table 17: MII 100Base-TX Transmitter (Informative)
Parameter
Return Loss
Open-Circuit Inductance
Conditions
2 < f < 30 MHz
30 < f < 60 MHz
60 < f < 80 MHz
-8 < I IN < 8 mA
Min
16
Max
–
Unit
dB
–
µH
f
16 − 20 log
30MHz
10
350
Note: The specifications in the preceding table are included for information only. They are mainly a
function of the external transformer and termination resistors used for measurements.
Rev. 1.2
19
78Q8430 Data Sheet
4.5.3
DS_8430_001
100Base-TX Receiver
Table 18: MII 100Base-TX Receiver Timing
Parameter
Signal Detect Assertion Threshold
Signal Detect De-assertion Threshold
Differential Input Resistance
Jitter Tolerance (pk-pk)
Baseline Wander Tracking
Signal Detect Assertion Time
Signal Detect De-assertion Time
4.5.4
Conditions
Not tested
Not tested
Min
600
300
–
4
-75
–
–
Nom
700
350
20
–
–
–
–
Max
800
400
–
–
+75
1000
4
Unit
mVppd
mVppd
kΩ
ns
%
µs
µs
10Base-T Transmitter
Table 19: MII 10Base-T Transmitter Timing
Parameter
Peak Differential Output Signal
(see note below)
Harmonic Content
(dB below fundamental)
Link Pulse Width
Start-of-Idle Pulse Width
Conditions
All data patterns
Any harmonic
All ones data
Not tested
Last bit 0
Last bit 1
Min
2.2
Nom
–
Max
2.8
Unit
V
27
–
–
dB
–
–
–
100
300
350
–
–
–
ns
ns
ns
Note: The Manchester-encoded data pulses, the link pulse and the start-of-idle pulse are tested against
the templates and using the procedures found in Clause 14 of IEEE 802.3. Measured at the line side of
the transformer. Test Condition: Transformer P/N: TLA-6T103. Line Termination: 100 Ω±1%
4.5.5
10Base-T Transmitter (Informative)
Table 20: MII 10Base-T Transmitter (Informative)
Parameter
Output Return Loss
Output Impedance Balance
Peak Common-mode Output Voltage
Common-mode Rejection
Common-mode Rejection Jitter
Conditions
1 MHz < freq < 20 MHz
15 V PK , 10.1 MHz sine
wave applied to transmitter
common-mode. All data
sequences.
15 V PK , 10.1 MHz sine
wave applied to transmitter
common-mode. All data
sequences.
Min
15
Nom
–
–
Max
–
–
Unit
dB
dB
–
–
–
–
50
100
mV
mV
–
–
1
ns
f
29 − 17 log
10
Note: The specifications in the preceding table are included for information only. They are mainly a
function of the external transformer and termination resistors used for measurements
20
Rev. 1.2
DS_8430_001
4.5.6
78Q8430 Data Sheet
10Base-T Receiver
Table 21: MII 10Base-T Receive Timing
Parameter
DLL Phase Acquisition Time
Jitter Tolerance (pk-pk)
Input Squelched Threshold
Input Unsquelched Threshold
Differential Input Resistance
Bit Error Ratio
Common-mode Rejection
Rev. 1.2
Conditions
Square wave
0 < f < 500 kHz
Not tested
Min
–
30
500
275
–
–
25
Nom
10
–
600
350
20
10-10
–
Max
–
–
700
425
–
–
–
Unit
BT
ns
mVppd
mVppd
kΩ
V
21
78Q8430 Data Sheet
DS_8430_001
5 Host Interface Timing Specification
5.1
Host Interface
CS
WR/OE
MEMWAIT
ADDR
DATA
TSU
TSL
TWT
THWT THCS
THOWT
THO
TL
TH
Figure 8: Host Interface Timing Diagram
Name
T SU
Description
CS and ADDR setup time
T SL
Output settling time
T WT
Maximum wait time
T HWT
Wait hold time
T HCS
CS hold time
T HO
ADDR and DATA hold time
TL
WR/OE min low pulse
TH
WR/OE min high pulse
Requirement
CS and ADDR must be stable on or
before the falling edge of WR/OE.
The maximum amount of time that it will
take the MEMWAIT, or DATA when there
is no MEMWAIT, outputs to become
stable after the falling edge of WR/OE.
The maximum amount of time that the
MEMWAIT output will held asserted.
The minimum amount of time that the
WR/OE input must be held past the
de-assertion of MEMWAIT.
The CS input must be stable low for the
entire duration of the WR/OE low cycle.
The ADDR and DATA inputs must be
stable for no less than this amount of time
after the falling edge of WR.
The minimum amount of time that the
WR/OE inputs must be held low.
The minimum amount of time that the
WR/OE inputs must be held high.
Min
0 ns
Max
–
–
13.7 ns
–
17 ck
10 ns
–
0 ns
–
2.5 ck
–
2 ck
–
2 ck
–
Note: On read cycles when MEMWAIT is asserted the DATA outputs will be valid before the
de-assertion of MEMWAIT.
22
Rev. 1.2
DS_8430_001
5.1.1
78Q8430 Data Sheet
Synchronous Mode Timing
BUSCLK
Output
Delay
TFALL
TRISE
Output
Delay
Figure 9: Host Bus Output Timing Diagram
BUSCLK
T SU
TH
Input
Figure 10: Host Bus Input Timing Diagram
Parameter
Input Setup Time
Input Hold Time
Output Fall Delay
Output Rise Delay
CSB min low
CSB min high
Rev. 1.2
Symbol
T SU
TH
T FALL
T RISE
P WL
P WH
Min
6
6
–
–
1
2
Nom
–
–
–
–
–
–
Max
–
–
8
8
–
–
Unit
ns
ns
ns
ns
clk
clk
23
78Q8430 Data Sheet
5.1.2
DS_8430_001
Bus Clock Timing
TCYC
THIGH
80%
VIH
50%
20%
VIL
TLOW
Figure 11: Bus Clock Timing
Parameter
Symbol
BUSCLK Cycle Time
BUSCLK Frequency
BUSCLK High Time
BUSCLK Low Time
BUSCLK Slew Rate
5.1.3
Async 100
Min
Max
10
–
–
100
3
–
3
–
1
3
Units
ns
MHz
ns
ns
V/ns
Reset Timing
Parameter
RESETB Minimum Duration
24
T CYC
–
T HIGH
T LOW
–
Sync 50
Min
Max
20
–
–
50
8
–
8
–
1
3
Symbol
T RESET
Min
1
Nom
–
Max
–
Units
clocks
Rev. 1.2
DS_8430_001
78Q8430 Data Sheet
6 Functional Description
6.1
Internal Block Diagrams
6.1.1
Internal Digital Block
Figure 12 presents an overview of the functional layers of the 78Q8430. On the left side are the signals,
which connect to the GBI bus. On the upper and middle right, the blocks that implement the MAC side of
the MII are shown. These blocks are connected to the embedded PHY. On the lower right, connections
to the EEPROM are shown.
Memory
Manager
Network
Wake-up
MII
Register
Controller
Flow
Control
MAC Half
Duplex
BUSCLK
EMI
System
RESETB
INTB
PMEB
EMI
Address
& Data
ADDR
DATA
4 Queue
Write Logic
1 Queue
Read Logic
Queue
Memory
BUSMODE
CLKMODE
Snoop
Controller
WAITMODE
BOOTSZ[1:0]
ENDIAN[1:0]
MAC
MII
Receive
Bus
Control
CSB
CTL
Controller
WRB/OEB
RMON
MEMWAIT
TCLK
TMS
TDI
TDO
TRSTB
MAC MII
Transmit
Queue
Read/Write
Logic
JTAG
IEEE
1149.1
Boundary QUE Status
Register
Scan
Packet
Classify
CAM
TX/RX
Packet Status DMA Status
Register
Register
MAC Status
Register
EEPROM/
ROM
Control
PROM_CS
PROM_CLK
PROM_DO
PROM_DI
Figure 12: Internal Digital Block Diagram
6.1.2
Internal PHY
Figure 13 shows the functional blocks of the internal 78Q8430 PHY. The signals shown on the left side
are the internal MII signals to the MAC. These signals are multiplexed with their respective external pins
for use with an external PHY device. The 78Q8430 is not a two-port device. Only one PHY interface can
be operational.
Rev. 1.2
25
78Q8430 Data Sheet
TX_CLK
TXD[3:0]
TX_EN
TX_ER
DS_8430_001
100M
MII
Transmit
Logic
4B/5B Encoder
Scrambler,
Parallel to Serial
NRZ/NRZI
MLT3 Encoder
Pulse Shaper
and Filter
UTP
Driver
LINK
TXA
RXA
COLI
100BT
10BT
FDX
LED
Control
Logic
Tx Clock
Generator
10M
Parallel to Serial
Manchester
Encoder
INTR
Interrupt
Logic
CRS
COL
MII
Activity
RX_CLK
RXD[3:0]
RX_DV
RX_ER
MII
Receive
Logic
Manchester
Decoder,
Serial to Parallel
Clock
Recovery
MDC
MDIO
MII
Registers
Serial to Parallel
Descrambler,
5B/4B Decoder
Clock
Reference
Carrier Sense,
Collosion Detect
XTLP/CLKIN
XTLN
TXOP
TXON
LED0
LED1
Auto
Negotiation
10M
UTP
Receiver
RXIP
RXIN
Adaptive Equalizer, 100M
Baseline Wander,
MLT3 Decoder,
NRZI/NRZ
VCC
GND
Figure 13: Internal PHY Block Diagram
On the right side are the signals, which connect to the status LEDs and a 1:1 isolation transformer before
connecting to an RJ-45 connector, or equivalent media components.
6.2
Data Queuing
Ethernet frame data in the 78Q8430 is managed in queuing structures called QUEs. The host bus
address space allocated for QUEs has enough space for eight, while the 78Q8430 circuit only
implements five. QUEs are identified numerically, QUE0 through QUE7, based on the registers in the
QUE register space that are used to access them. QUE1, QUE6 and QUE7 are unimplemented and
reserved for future use.
A QUE allocates main buffer memory as needed and stores discrete frames as they are written into the
QUE. The QUE then reads back frames in the same order that they were written and frees the main
buffer memory. A QUE can contain a maximum of 125 frames at any one time. If a QUE is unable to
allocate main buffer memory when writing a frame, the frame will be partially added to the QUE as a
truncated frame. If a QUE is unable to allocate main buffer memory to start a frame, the entire frame is
dropped.
The QUEs are divided into two categories: receive QUEs, that store received frame data and transmit
QUEs, that store transmit frame data. Frames are written to a receive QUE by the MAC and read out by
the host. Frames are written to a transmit QUE by the host and read out by the MAC. QUE0 and QUE1
are receive QUEs (only QUE0 is implemented), and QUE2 through QUE7 are transmit QUEs (QUE2
through QUE5 are implemented). Writing to the Transmit Data Register (TDR) for a receive QUE or
reading from the Read Data Register (RDR) for a transmit QUE is not supported and the result is
undefined in this specification.
The transmit QUEs are further divided into standard QUEs, as described above, and static QUEs. Static
QUEs differ from the standard QUEs in that they can only contain a single frame, and that frame must be
252 bytes or less in total size. Unlike standard QUEs, static QUEs do not remove a frame when it is read
from the QUE. Once a frame is written to a static QUE, it can be read out any number of times and the
static QUE will always read out the same one frame. If a second frame is written to a static QUE then it
will replace the first as the one frame contained in the QUE.
26
Rev. 1.2
DS_8430_001
78Q8430 Data Sheet
The purpose of a static transmit QUE is to allow the host to configure a frame that will need to be
transmitted multiple times or transmitted at a later time without any interaction with the host. Transmit
QUE2 and QUE5 are static QUEs. Transmit QUE2 is best suited for MAC control pause frames as it can
be triggered to transmit by a main buffer watermark. Transmit QUE5 is best suited to Host Not
Responding (HNR) frames as it can be triggered to transmit by a host interrupt timeout.
When the MAC transmitter is idle and ready to transmit a frame, it determines which QUE to read from on
a priority basis. The lowest numbered QUE containing data that needs to be transmitted is selected by
the MAC, which means when more than one transmit QUE is ready, the one with the lowest number
always gets priority.
6.3
6.3.1
Host Interface
Reading Receive Data
The status of the frame at the top of the receive FIFO can be obtained by reading the Receive Packet
Status Register (RPSR). The 16 LSBs of the RPSR contain a count of the total number of bytes that
have entered the receive FIFO for this frame. A value of zero means that there are no new frames in the
receive FIFO. As frame bytes enter the FIFO, the count value is incremented. However, the count value
does not decrease the bytes read out of the read FIFO such that the final value will always be the final
frame size.
The MSB of the RPSR is the DONE bit. Once the last byte in the frame has entered the receive FIFO,
the DONE bit is set indicating that the count value contained in the total bytes field now contains the final
size in bytes of the frame and the error status and classification fields now contain the final frame status.
When the DONE bit is asserted, this also indicates that the status for this frame has been removed from
the receive status FIFO and future reads of the RPSR will refer to the next frame in the receive FIFO,
even if all of the data for the current frame has not been retrieved.
The frame data is read from the receive FIFO 32 bits at a time by successive reads to the Receive Data
Register (RDR). If the frame length is not an even multiple of 4 bytes then the final read of the RPDR
register for that frame will be padded with zeros.
6.3.2
Writing Transmit Data
A transmit QUE is initialized by writing to its Packet Control Word Register (PCWR). This will assign an
ID to the frame and select various transmission options. The frame size must then be set by writing to the
QUE Packet Size Register (PSZR). Transmit data is then written to the transmit FIFO 32 bits at a time via
successive writes to the Transmit Data Register (TDR).
If more bytes are written to the TDR than indicated n the PSZR, the excess bytes are ignored. Writes to
the TDR past the end of the frame, however, will trigger a transmit FIFO overrun interrupt condition.
Similarly, if a new frame is initialized by a write to the PCWR before the frame length counter is expired, a
transmit FIFO under-run interrupt condition will result and the previous frame will be aborted. If there is
any question, the PSZR can be queried for the remaining number of bytes expected in the previous frame
before a new frame is initialized.
In the event that the host wishes to terminate a frame early without triggering an under-run interrupt and
aborting the frame, or if the size of the frame is not initially known, the PSZR can be rewritten at any time
before the end of the frame’s transmission. As an example, no matter what the current value of the PSZR
is, if it is written with a value of one then the next write to the TDR will add one byte to the completed
frame. Conversely, if the frame byte counter is about to expire then writing a larger value to the PSZR will
extend the frame. It is an error to write a value of zero to the PSZR and the circuit behavior in this case is
undefined.
As each frame egresses the transmit FIFO, its status is placed in the transmit status FIFO. Transmit
frame status is recovered by reading the Transmit Packet Status Register (TPSR). The Packet ID field
from the PCWR is also placed in the TPSR such that the status can be associated with the exact frame to
which it belongs.
Rev. 1.2
27
78Q8430 Data Sheet
6.3.2.1
DS_8430_001
Using the Setup Transmit Data Register
The Setup Transmit Data Register (STDR) can be used to control the way in which 32-bit data words are
transferred to the transmit FIFO. The STDR can be changed on a word-by-word basis to change the
network endianness or buffer-byte-alignment, or the STDR can be used to setup the transfer of an entire
buffer of transmit data. A new frame must be initialized by a write to the PCWR before the STDR is setup
for transferring frame data to the QUE.
The Count field of the STDR contains one less than the number of writes to the TDR that will be needed
to complete the transfer of the buffer. The Start Offset field contains the number of bytes in the first write
to the TDR to ignore. The End Offset field contains the number of bytes in the last write (when the Count
field is equal to zero) to ignore.
Table 22: Transmit Data Buffer Example
Transmit Order:
Start Offset = 2
Count decrements for
each write
End Offset = 3
Byte-1
X
B3
…
…
B N-4
BN
32-bit Write Data
Byte-2 Byte-3
X
B1
B4
B5
…
…
…
…
B N-3
B N-2
X
X
Byte-4
B2
B6
…
…
B N-1
X
Notes:
1. The End Offset will continue to be applied as long as the COUNT field of the STDR contains zero. If
a non-zero End Offset is used, it must be cleared at the end of the block transfer.
2. The COUNT field must expire before the PSZR expires. Frames that are entirely contained within
one block should not use the End Offset. Instead, use the PSZR to clip the last write to the TDR.
The Endian field of the STDR is used to set the transmit order of the data written on the bus, or how host
bus write data bytes are mapped to transmit buffer bytes. If the Endian bit is set then the most significant
byte of the host bus as defined by the logical endianness, is mapped to the first transmitted byte in the
buffer, otherwise, the least significant byte is mapped to the first transmitted byte.
6.3.2.2
Preloading Transmit Data
A transmit QUE signals the MAC transmitter that it is ready to transmit by asserting the QUE Data Ready
bit (QDR) in its QUE Status Register (QSR). The default behavior of the QDR for a transmit QUE is to
assert anytime the QUE contains any data. This means that a transmit QUE can potentially begin
transmitting as soon as the first BLOCK is added to the QUE. Once the QUE begins transmitting, data for
the packet being transmitted must be added to the QUE faster than the transmitter removes it or a TX
FIFO under-run condition will eventually abort the packet (see TPSR).
In the event that interrupt latency, host bus performance, or other issues may prevent the host from
loading data into the QUE faster than it is removed by the MAC, the QSR can be used to modify the QDR
behavior and prevent an under-run condition on the QUE. Bits 25 and 24 of the QSR are the Mode field.
The default setting for the Mode field is 00b. In this mode the QDR bit is set anytime the QUE contains at
least one BLOCK. In this mode, the host must be diligent in keeping the QUE populated with data to
avoid a TX FIFO under-run condition in the MAC.
If the Mode setting is 01b then the QDR bit for the QUE is set only when the number of BLOCKs in the
QUE is above the value indicated by the Threshold field. This will allow the host to fill the QUE up to the
threshold level at its leisure without risk of a TX FIFO under-run. The drawback to this mode is that a
small packet that uses fewer than the threshold number of BLOCKs will be stranded in the QUE until
more data is added to the QUE to bring the total number of BLOCKs up and over the threshold.
28
Rev. 1.2
DS_8430_001
78Q8430 Data Sheet
If small packets are a problem, then the Mode setting of 10b can be used. In this mode, the QDR bit for
the QUE is set only when there is an EOF in the QUE, or in other words, the QUE contains at least one
entire frame. In this mode, TX FIFO under-runs are not possible since the QUE will not begin to transmit
until it contains the entire frame. The draw-back to this mode is with very large frames. If a frame is too
large to fit into the QUE all at one time then it will never begin transmitting and the QUE will be stalled.
If both small and large packets are to be handled then a Mode setting of 11b should be used. In this
mode, the QDR bit for the QUE is set anytime there is an EOF in the QUE or the number of BLOCKs in
the QUE is above the threshold. In this way, large packets can preload a fixed number of BLOCKs while
small packets are guaranteed to transmit.
To facilitate the handling of very large packets by a fast host, an interrupt that is tied to the QSR
Threshold is provided. To make use of this, the host sets the Threshold field based on the interrupt
latency. The host then preloads the QUE with some number of BLOCKs. As soon as the total number of
blocks left in the QUE falls below the Threshold, an interrupt is generated. In response to the interrupt
the host writes more data to the QUE to put the number back above the threshold. The host can then go
on to other tasks until the next interrupt. This cycle is repeated until the frame is completed.
6.3.3
DMA Slave Mode Access
Reading or writing large amounts of data into and out of a single QUE involves accessing the same RDR
or TDR register repeatedly. A DMA Slave Mode is implemented to facilitate this activity and reduce
overhead on the host side. While in DMA Slave Mode, the address bus on the host interface is ignored
and all access is assumed to be to the programmed address until DMA mode is terminated. In this way
the host can use a DMA engine or block transfer facility to write or read QUE data without regard to the
addresses generated.
DMA Slave Mode is controlled by the DMA Register (DMA) at address 0x100.
To read data from a QUE using DMA Slave Mode, the host writes the address of the RDR for the desired
QUE into bits nine through zero and sets bit 17, the Read Mode bit, in the DMA register at address
0x100. The host then starts the DMA transfer and all read access to the host interface will go to the
programmed RDR address. When the DMA transfer is complete, the DMA Mode is terminated by writing
a zero to bit 17 of the DMA Register (DMA).
To write data to a QUE using DMA Slave Mode, the host writes the address of the TDR for the desired
QUE into bits nine through zero and sets bit 16, the Write Mode bit, in the DMA Register. The host then
starts the DMA transfer and all write access to the host interface will go to the programmed TDR address.
When the DMA transfer is complete, reading the cleared Write Mode bit from the DMA Register
terminates the DMA Mode.
DMA Slave Mode does not have any effect on other operations of the interface such that, for example,
the ENDIAN settings, STDR settings, etc. are all in effect during a DMA Mode transfer. During a DMA
mode transfer, the actual register address of the host bus access is ignored. This means that using DMA
Slave Mode to transfer data out of order is not supported. Data words must always be written to a
transmit QUE in the desired transmit order and are always read from a receive QUE in received order.
6.4
Snoop Mode Access
The Snoop Interface provides a means by which QUE data can be inspected and modified in situ, leaving
the state of the QUE unchanged. The Snoop Interface works by presenting the contents of a specific
BLOCK of QUE memory at the SNOOP address space 0x300-0x3FF. The Snoop Control Register
(SNCR) is used to set which BLOCK of QUE memory is mapped into the SNOOP address space.
For example, an application that wishes to inspect or modify the contents of the first frame in the receive
QUE, QUE0, first reads the value of the FIRST BLOCK in QUE0 from its QFLR Register (QFLR). The
pointer to the FIRST BLOCK in QUE0 is then written to the SNCR register. Now that the SNCR Register
has programmed the SNOOP interface to point to the FIRST BLOCK for QUE0, accessing registers in the
address space from 0x300 to 0x3FF will be directly accessing the data for the first frame contained in
QUE0.
Rev. 1.2
29
78Q8430 Data Sheet
DS_8430_001
Snooping the contents of a frame before it is read out of the receive QUE can be useful if additional
inspection of the frame is needed, beyond what is provided by classification, to determine the disposition
of a received frame. It can also be used, in conjunction with the QUE transfer feature, to minimize host
bus overhead in responding to simple ARP or ICMP requests. In this case, the host can use the Snoop
Interface to modify a received ARP or ICMP request and convert it into the appropriate response, while
the frame is still resident in the receive QUE. The QUE Transfer feature is then used to transfer the
response directly to a TX QUE and transmit it back to the source without having to read the entire frame
into host memory.
6.5
Water Marking
The Timers module (see Section 6.8) monitors the number of free memory blocks in the system input.
There are three watermarks (Interrupt, PAUSE and Headroom), accessed via the Water Mark Values
Register (WMVR), which can be used to manage memory usage based on the size of the free memory pool.
6.5.1
Interrupt Watermark
When the number of free BLOCKs falls below the interrupt threshold, the WATER MARK interrupt in the
HIR is triggered. An interrupt threshold setting of zero disables this feature.
6.5.2
PAUSE Watermark
When the number of free BLOCKs falls below the pause threshold, the QDR bit for the PAUSE QUE
triggers the transmission of the pause frame. A pause threshold setting of zero disables this feature.
6.5.3
Headroom Watermark
When the number of free BLOCKs falls below the headroom threshold then the MAC receiver is halted
causing the MAC to drop any frames received after completion of the current frame. This condition is
cleared once the number of free BLOCKs rises back above the threshold. This prevents a saturated
receiver from consuming all free memory thereby locking out the local transmitter. A headroom setting of
zero disables this feature.
6.6
Counters
A block of hardware counters is implemented to allow monitoring transmit and receive statistics. These
counters are accessed and managed by using the Count Data Register (CDR), the Counter Control
Register (CCR) and the Counter Management Register (CMR).
6.6.1
Summary of Counters
Table 23 provides a summary of all counters by address. Counters at addresses 0x00 through 0x0E are
transmit counters. Counters at addresses 0x0F through 0x27 are receive counters.
Table 23: Counter Summary
Counter
Address
0x00
0x01
0x02
0x03
0x04
0x05
0x06
0x07
0x08
0x09
0x0A
30
Counter Description
Transmitted Packets, 0 Collisions, not deferred or excessive deferred
Transmitted Packets, 1 Collision
Transmitted Packets, 2-15 Collisions
Excessive Collisions
Deferred transmissions
Late Collisions
MAC errors (TX under-run or transmit halted)
Lost carrier sense errors
Excessive deferrals
Total packets transmitted
Multicast packets
Rev. 1.2
DS_8430_001
Counter
Address
0x0B
0x0C
0x0D
0x0E
0x0F
0x10
0x11
0x12
0x13
0x14
0x15
0x16
0x17
0x18
0x19
0x1A
0x1B
0x1C
0x1D
0x1E
0x1F
0x20
0x21
0x22
0x23
0x24
0x25
0x26
0x27
6.6.2
78Q8430 Data Sheet
Counter Description
Broadcast packets
SQE errors
Pause packets transmitted
Transmitted bytes
Received packets, 63 bytes or less
Received packets, 64 bytes
Received packets, 65 to 127 bytes
Received packets, 128 to 255 bytes
Received packets, 256 to 511 bytes
Received packets, 512 to 1023 bytes
Received packets, 1024 to 1518 (1522 for VLAN tag) bytes
Received packets, 1519 bytes or more (1523 or more for VLAN tag) bytes
CRC error and no alignment error
Alignment errors
Fragment errors (less than 64 bytes with CRC or alignment error)
Jabbers (greater than 1518 or 1522 and CRC or alignment error)
MAC errors
Dropped packets
Classification dropped packet
Total received packets with no errors
Total received multicast packets with no errors
Total received broadcast packets with no errors
Range errors (length field
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