SED1335-1

SED1335 CMOS GRAPHIC LCD CONTROLLER s DESCRIPTION • For Medium-Scale LCD 2.7 to 5.0V • Low Operating Voltage • On-Chip Character Generator ROM The SED1335 is a CMOS low-power dot matrix liquid crystal graphic display controller. The device stores in external RAM display data sent by an 8-bit microcomputer, and generates all the signals required by the LCD drivers. The LSI incorporates an internal character generator ROM which supports user-defined characters (also an external CGROM can be supported). The SED1335 can be interfaced to high-speed microprocessors such as the Intel family or Motorola family. The controller supports a set of rich commands that will allow the user to create a layered display of characters and graphics. Also, the controller functions as a pipeline buffer between the MPU and display memory so that low-cost, medium-speed SRAM can be used. s FEATURES • CMOS low-power graphic and character display controller interface is compatible • Selectable MPUand the Motorola family with both the Intel family • Smooth scrolling support: • • • Horizontal and vertical scroll Scrolling of selected areas of the display Multimode display: 2 layers of overlapping characters and graphics 3 layers of overlapping graphics Selectable display synthesis: Inverse video Flashing display, cursor on/off/blink Under and bar cursor, block cursor Simple animation Programmable cursor • Internal character generator ROM • Supports external character generator ROM: • • • • • 8 × 8 or 8 × 16 pixel characters Allowing mixing of ROM and RAM character sets Supports 64K bytes of memory: 4K bytes of user-definable characters 60K bytes of display memory in 2 of 32K × 8 100ns SRAM or in 8 of 8K × 8 100ns SRAM Display duty .................... 1/2 to 1/256 Low power dissipation 5mA (typical) 0.05µA (typical), standby Logic power supply .......................... 2.7 to 5.5V Package: .................. Plastic QFP5-60 pin (F0A) Plastic QFP6-60 pin (F0B) s SYSTEM BLOCK DIAGRAM DATA CPU 68xx 80xx CONTROL SED1335F MONO LCD SRAM 139 SED1335 s BLOCK DIAGRAM Video RAM CG RAM VA0 to VA15 External CG ROM VD0 to VD7 YSCL,YDIS LCD XSCL, XECL XD0 to XD3 VCE VWR VRAM Interface VRD I/O Register LCD Controller Cursor Address Controller Display Address Controller Refresh Address Counter Dot Counter CG ROM LP, WF Layered Display Controller MPU Interface Oscillator Circuit RD, WR A0, CS D0 to D7 SEL1 SEL2 RES XD s PINOUT XG SEL1 SEL2 WR RD NC NC RES VRD VCE VWR VA0 VA1 VA2 VA3 VA4 VA5 VA6 VA7 XD CS A0 VDD D0 D1 D2 D3 D4 D5 D6 55 50 45 40 60 1 5 SED1335FOA Index 30 29 VA8 VA9 VA10 VA11 VA12 VA13 NC VA14 VA15 VD0 VD1 VD2 6 10 15 20 VD3 VD2 VD1 VD0 VA15 VA14 VA13 VA12 VA11 VA10 VA9 VA8 VA7 VA6 NC 45 46 VD4 VD5 VD6 VD7 YSCL YD YDIS WF LP VSS XSCL XECL XD0 XD1 XD2 31 30 XG 16 15 SED1335FOB Index 60 1 XD3 D7 D6 D5 D4 D3 D2 D1 D0 VDD A0 CS XD XG SEL1 D7 XD3 XD2 XD1 XD0 XECL XSCL VSS LP WF YDIS YD YSCL VD7 VD6 VD5 VD4 VD3 140 VA5 VA4 VA3 VA2 VA1 VA0 VWR VCE VRD RES NC NC RD WR SEL2 SED1335 s PIN DESCRIPTION Pin Name XG XD VDD VSS SEL1,2 D0 to D7 A0 RD WR CS RES VA15 to VA0 VD7 to VD0 VWR VRD VCE XD3 to XD0 XSCL XECL LP WF YSCL YD YDIS Pin No. SED1335FOA 54 55 58 13 53 • 52 59 to 60, 1 to 6 57 50 51 56 47 27 • 28, 30 to 43 19 to 26 44 46 45 7 to 10 12 11 14 15 18 17 16 SED1335FOB 17 18 21 36 16 • 15 22 to 29 20 13 14 19 10 1 to 6, 50 to 59 42 to 49 7 9 8 30 to 33 35 34 37 38 41 40 39 I/O I O +5V GND(0V) I I/O I I I I I O I/O O O O O O O O O O O O Functions Oscillator terminal Oscillator terminal Power supply Power supply MPU interface format selection Data bus Data type selection 80 series Read strobe signal 68 series “E” clock 80 series Write strobe signal 68 series R/W signal Chip select Reset VRAM address bus VRAM data bus VRAM write signal VRAM read signal VRAM chip enable Dot data output bus to X driver Dot data shift clock for X driver Chip enable shift clock for X driver Dot data latch pulse Frame signal Scan data shift clock for Y driver Scan data output Power down signal when display is OFF NC: No Connection s ELECTRICAL CHARACTERISTICS Absolute Maximum Ratings • (VSS = 0V) Symbol VDD VIN PD Topr Tstg Tsol Ratings –0.3 to 7.0 –0.3 to VDD+0.3 300 –20 to 75 –60 to 150 260°C, 10s (at lead) Unit V V mW °C °C — Parameter Supply voltage Input voltage Power dissipation Operating temperature Storage temperature Soldering temperature and time 141 SED1335 • DC Electrical Characteristics (1) Parameter Symbol VDD VOH VIHT VILT VOHT VOLT VIHC VILC VOHC VOLC VT+ VT– ILI ILO Iopr IQ fosc fCL Rf VIN = VDD/VSS IOH = –2.0mA IOL = 2.0mA IOH = –5.0mA IOL = 5.0mA Condition (VSS = 0V, VDD = 4.5 to 5.5V, Ta = –20 to 75°C) Min 4.5 2.0 0.5xVDD VSS 2.4 — 0.8xVDD VSS VDD–0.4 — Typ 5.0 — — — — — — — — — Max 5.5 6.0 VDD 0.2xVDD — VSS+0.4 VDD 0.2xVDD — VSS+0.4 Unit V V V V V V V V V V V V µA µA mA µA MHz MHz MΩ XG, XD VDD VDD Terminal VDD D0 to D7, A0, CS, RD, WR, VD0 to VD7, VA0 to VA15, VCE, VRD, VWR SEL1, SEL2, YD, XD0 to XD3, XSCL, YDIS, LP, WF, CL0, XECL, YSCL Operating voltage Register data retention voltage High level input voltage T Low level input voltage T L High level output voltage Low level output voltage High level input voltage C M Low level input voltage O High level output voltage S Low level output voltage S C H M I T T Positive trigger threshold voltage Negative trigger threshold voltage 0.5VDD 0.7VDD 0.8VDD 0.2VDD 0.3VDD 0.5VDD — — fosc = 10MHz, No-load 256 × 200 dot Sleep XG, CS, RD = VDD AT X’tal Duty 47.5% — — 1.0 1.0 0.5 0.05 0.10 11 0.05 — — 1.0 2.0 5.0 15 20 10.0 10.0 3.0 RES Input leakage current Output leakage current Average operating current Standby current Oscillation frequency External clock frequency Feed back resistance 142 SED1335 • DC Electrical Characteristics (2) Parameter Symbol VDD VOH VIHT VILT VOHT VOLT VIHC VILC VOHC VOLC VT+ VT– ILI ILO Iopr IQ fosc fCL Rf VIN = VDD/VSS IOH = –1.0mA IOL = 1.0mA IOH = –3.0mA IOL = 3.0mA Condition (VSS = 0V, VDD = 2.7 to 4.5V, Ta = –20 to 75°C) Min 2.7 2.0 0.8xVDD VSS VDD–0.4 — 0.8xVDD VSS VDD–0.4 — Typ 3.5 — — — — — — — — — Max 4.5 6.0 VDD 0.2xVDD — VSS+0.4 VDD 0.2xVDD — VSS+0.4 Unit V V V V V V V V V V V V µA µA mA µA MHz MHz MΩ XG, XD VDD VDD Terminal VDD D0 to D7, A0, CS, RD, WR, VD0 to VD7, VA0 to VA15, VCE, VRD, VWR SEL1, SEL2, YD, XD0 to XD3, XSCL, YDIS, LP, WF, CL0, XECL, YSCL Operating voltage Register data retention voltage High level input voltage T Low level input voltage T L High level output voltage Low level output voltage C M Low level input voltage O High level output voltage S Low level output voltage S C H M I T T High level input voltage Positive trigger threshold voltage Negative trigger threshold voltage 0.5VDD 0.7VDD 0.8VDD 0.2VDD 0.3VDD 0.5VDD — — — — 1.0 1.0 0.7 0.05 0.10 3.5 (VDD=3.5V) RES Input leakage current Output leakage current Average operating current Standby current Oscillation frequency External clock frequency Feed back resistance 2.0 5.0 7.0 20 8.0 8.0 4.0 fosc = 6.1MHz, No-load 256 × 200 dot Sleep XG, CS, RD = VDD AT X’tal Duty 47.5% 0.05 — — — 143 SED1335 • ° Timing Diagrams 8080-Family Interface Timing AO, CS tAW8 tCYC WR, RD tCC tDS8 D0 to D7 (Write) tACC8 D0 to D7 (Read) tOH8 tDH8 tAH8 Ta = –20 to 75°C Signal A0, CS WR, RD Symbol tAH8 tAW8 tCYC tCC tDS8 tDH8 tACC8 tOH8 Parameter Address hold time Address setup time System cycle time Strobe pulsewidth Data setup time Data hold time RD access time Output disable time VDD = 4.5 to 5.5V VDD = 2.7 to 4.5V min max min max 10 — 10 — 0 — 0 — See note — See note — 120 — 150 — 120 — 120 — 5 — 5 — — 50 — 80 10 50 10 55 Unit ns ns ns ns ns ns ns ns Condition CL = 100 pF D0 to D7 Note: For memory control and system control commands: tCYC8 = 2tC + tCC + tCEA + 75 > tACV + 245 For all other commands: tCYC8 = 4tC + tCC + 30 144 SED1335 ° 6800-Family Interface Timing E tCYC tAW6 R/W tAH6 AO, CS tDH6 tDS6 D0 to D7 (Write) tACC6 D0 to D7 (Read) tOH6 tEW Note: tCYC6 indicates the interval during which CS is LOW and E is HIGH. Ta = –20 to 75°C Signal A0, CS, R/W Symbol tCYC6 tAW6 tAH6 tDS6 tDH6 tOH6 tACC6 tEW Parameter System cycle time Address setup time Address hold time Data setup time Data hold time Output disable time Access time Enable pulsewidth VDD = 4.5 to 5.5V min max See note — 0 — 0 — 100 — 0 — 10 50 — 85 120 — VDD = 2.7 to 4.5V min max See note — 10 — 0 — 120 — 0 — 10 75 — 130 150 — Unit ns ns ns ns ns ns ns ns Condition D0 to D7 CL = 100 pF E Note: For memory control and system control commands: tCYC6 = 2tC + tEW + tCEA + 75 > tACV + 245 For all other commands: tCYC6 = 4tC + tEW + 30 145 SED1335 ° Display Memory Read Timing EXTΦ0 tC tW VCE tCE tW tCYR VA0 to VA15 tASC tAHC tRCH VRD tRCS tACV VD0 to VD7 (SED1335F) tCEA tCE3 tOH2 Ta = –20 to 75°C Signal EXT φ0 VCE tCE tCYR VA0 to VA15 tASC tAHC tRCS VRD tRCH tACV tCEA tOH2 tCE3 Symbol tC tW Parameter VDD = 4.5 to 5.5V min max 100 — VDD = 2.7 to 4.5V min max 125 — tC – 50 2tC – 30 3tC tC – 100 2tC – 40 tC – 60 0.5tC — — 0 0 — — — — — — — 3tC – 115 2tC – 90 — — Unit ns ns ns ns ns ns ns ns ns ns ns ns CL = 100 pF Condition VD0 to VD7 Clock period VCE HIGH-level tC – 50 — pulsewidth VCE LOW-level 2tC – 30 — pulsewidth Read cycle time 3tC — Address setup time to — tC – 70 falling edge of VCE Address hold time from 2tC – 30 — falling edge of VCE Read cycle setup time tC – 45 — to falling edge of VCE Read cycle hold time 0.5tC — from rising edge of VCE Address access time — 3tC – 100 VCE access time — 2tC – 80 Output data hold time 0 — VCE to data off time 0 — 146 SED1335 ° Display Memory Write Timing EXTφ0 tC tW VCE tASC tCYW VA0 to VA15 tAS VRW tDSC tDHC VD0 to VD7 tDH2 tWSC tWHC tAH2 tAHC tCE tCA Ta = –20 to 75°C Signal EXT φ0 VCE tCE tCYW tAHC tASC VA0 to VA15 tCA tAS tAH2 tWSC VWR tWHC tDSC VD0 to VD7 tDHC tDH2 Symbol tC tW Parameter Clock period VCE HIGH-level pulsewidth VCE LOW-level pulsewidth Write cycle time Address hold time from falling edge of VCE Address setup time to falling edge of VCE Address hold time from rising edge of VCE Address setup time to falling edge of VWR Address hold time from rising edge of VWR Write setup time to falling edge of VCE Write hold time from falling edge of VCE Data input setup time to falling edge of VCE Data input hold time from falling edge of VCE Data hold time from rising edge of VWR VDD = 4.5 to 5.5V min max 100 — tC – 50 2tC – 30 3tC 2tC – 30 tC – 70 0 0 10 tC – 80 2tC – 20 tC – 85 2tC – 30 5 — — — — — — — — — — — — 50 VDD = 2.7 to 4.5V min max 125 — tC – 50 2tC – 30 3tC 2tC – 40 tC – 110 0 0 10 tC – 115 2tC – 20 tC – 125 2tC – 30 5 — — — — — — — — — — — — 50 Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns CL = 100 pF Condition Note: VD0 to VD7 are latching input/outputs. While the bus is high impedance, VD0 to VD7 retain the write data until the data read from the memory is placed on the bus. 147 SED1335 ° SLEEP IN Command Timing VCE WR (command input) YDIS SLEEP IN write SYSTEM SET write tWRL tWRD Ta = –20 to 75°C Signal Symbol tWRD WR tWRL Notes: 1. tWRD = 18tC + tOSS + 40 (tOSS is the time delay from the sleep state until stable operation) 2. tWRL = 36tC × [TC/R] × [L/F] + 70 Parameter VCE falling-edge delay time YDIS falling-edge delay time VDD = 4.5 to 5.5V min max *1 — — *2 VDD = 2.7 to 4.5V min max *1 — — *2 Unit ns ns Condition CL = 100 pF • External Oscillator Signal Timing tRCL EXTφ0 tWL tCL tWH tFCL Ta = –20 to 75°C Signal Symbol tRCL tFCL EXT φ0 tWH tWL tC Notes: 1. (tC – tRCL – tFCL) × 475 < tWH, tWL 1000 2. (tC – tRCL – tFCL) × 525 > tWH, tWL 1000 Parameter External clock rise time External clock fall time External clock HIGH-level pulsewidth External clock LOW-level pulsewidth External clock period VDD = 4.5 to 5.5V min max — 15 — 15 *1 *1 100 *2 *2 — VDD = 2.7 to 4.5V min max — 15 — 15 *1 *1 125 *2 *2 — Unit ns ns ns ns ns Condition 148 SED1335 ° LCD Output Timing The following characteristics are for a 1/64 duty cycle. Row 62 63 64 1 2 3 4 60 61 62 63 64 LP 1 frame time YD WF WF 1 line time Row 64 LP Row 1 Row 2 XSCL XD0 to XD3 (14) (15) (16) (1) (15) (16) (1) (2) (3) (15) (16) (1) tr XSCL tWX tf tCX tDS tLS XD0 to XD3 tWL tLD LP tDH tDHY tDF WF(B) YD 149 SED1335 Ta = –20 to 75°C Signal Symbol tr tf XSCL XD0 to XD3 LP WF YD tCX tWX tDH tDS tLS tWL tLD tDF tDHY VDD = 4.5 to 5.5V VDD = 2.7 to 4.5V min max min max Rise time — 30 — 40 Fall time — 30 — 40 Shift clock cycle time 4tC — 4tC — XSCL clock pulsewidth 2tC – 60 — 2tC – 60 — X data hold time 2tC – 50 — 2tC – 50 — X data setup time 2tC – 100 — 2tC – 105 — Latch data setup time 2tC – 50 — 2tC – 50 — LP pulsewidth 4tC – 80 — 4tC – 120 — LP delay time from XSCL 0 — 0 — Permitted WF delay — 50 — 50 Y data hold time 2tC – 20 — 2tC – 20 — Parameter Unit ns ns ns ns ns ns ns ns ns ns ns Condition CL = 100pF Note: The SED1335F reads display memory data from the address of the top left corner of the display screen, then scans horizontally until it reaches the address for the bottom right corner of the display screen. Therefore, each line of X-driver data is sent starting from the left side of the display line. 150 SED1335 s EXAMPLE OF APPLICATION 10MHz XG A0 A1 to A7 A0 XD VA13 to VA15 VCE VWR VRD VA0 to VA12 A B C Y7 Y6 CS7 CS6 HC138 Y0 CS0 Chip Selector CS SED1335FOA MPU IORD VA12 A0 to A12 WE SRM2064 CS1 (RAM1) CS2 D0 to D7 OE A0 to A12 WE SRM2064 CS1 (RAM2) CS2 D0 to D7 OE A11 2732 (IXT.CG) D0 to D7 OE CE D0 to D7 RD WR RESET RESET D0 to D7 RD WR RES XD0 to XD3 VD0 to VD7 XECL XSCL LP WF YDIS YD YSCL SED1630F LAT DI INH FR YSCL LCD Voltage Converters Poff (Y Driver) V1 V2 V3 V4 V5 *1 *2 FR EI SED1600F FR EI *2 SED1600F FR EI *2 SED1600F LP XSCL LP XSCL LP XSCL D0 to D3 D0 to D3 Vreg (X Driver) LCD UNIT Recommend X Driver: SED1742F, SED1600F Recommend Y Driver: SED1743F, SED1610F, SED1631 151 D0 to D3 SED1335 s CHARACTER CODE TABLE (Built-in Character Generator) 0 2 1 2 Lower 4-bit (D0 to D3) of Character Code (Hexadecimal) 3 4 5 6 7 8 9A B C D E F Higher 4-bit (D4 to D7) of Character Code (Hexadecimal) 3 4 5 6 7 A B C D 1 152