IQE046N08LM5
MOSFET
OptiMOSTM5Power-Transistor,80V
PG-TSON-8
5
Features
•OptimizedforhighperformanceSMPS,e.g.synchronousrectification
•N-channel,logiclevel
•Verylowon-resistanceRDS(on)
•Superiorthermalresistance
•100%avalanchetested
•Pb-freeleadplating;RoHScompliant
•Halogen-freeaccordingtoIEC61249-2-21
4
3
6
2
7
8
1
Productvalidation
FullyqualifiedaccordingtoJEDECforIndustrialApplications
Drain
Pin 5-8
Table1KeyPerformanceParameters
Parameter
Value
Unit
VDS
80
V
RDS(on),max@10V
4.6
mΩ
RDS(on),max@4.5V
5.9
mΩ
ID
99
A
Qoss
39
nC
QG(0V...4.5V)
19
nC
Gate
Pin 4
Source
Pin 1-3
Type/OrderingCode
Package
Marking
RelatedLinks
IQE046N08LM5
PG-TSON-8
046N8L5
-
Final Data Sheet
1
Rev.2.0,2023-01-12
OptiMOSTM5Power-Transistor,80V
IQE046N08LM5
TableofContents
Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Electrical characteristics diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Package Outlines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Trademarks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Disclaimer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Final Data Sheet
2
Rev.2.0,2023-01-12
OptiMOSTM5Power-Transistor,80V
IQE046N08LM5
1Maximumratings
atTA=25°C,unlessotherwisespecified
Table2Maximumratings
Parameter
Symbol
Values
Unit
Note/TestCondition
99
70
62
15.6
A
VGS=10V,TC=25°C
VGS=10V,TC=100°C
VGS=4.5V,TC=100°C
VGS=10V,TA=25°C,RthJA=60°C/W2)
-
396
A
TA=25°C
-
-
170
mJ
ID=20A,RGS=25Ω
VGS
-20
-
20
V
-
Power dissipation
Ptot
-
-
100
2.5
W
TC=25°C
TA=25°C,RthJA=60°C/W2)
Operating and storage temperature
Tj,Tstg
-55
-
175
°C
-
Unit
Note/TestCondition
Min.
Typ.
Max.
ID
-
-
ID,pulse
-
Avalanche energy, single pulse
EAS
Gate source voltage
1)
Continuous drain current
Pulsed drain current3)
4)
2Thermalcharacteristics
Table3Thermalcharacteristics
Parameter
Symbol
Thermal resistance, junction - case
Values
Min.
Typ.
Max.
RthJC
-
0.9
1.5
°C/W -
Thermal resistance, junction - ambient,
RthJA
6 cm² cooling area2)
-
-
60
°C/W -
1)
Rating refers to the product only with datasheet specified absolute maximum values, maintaining case temperature
as specified. For other case temperatures please refer to Diagram 2. De-rating will be required based on the actual
environmental conditions.
2)
Device on 40 mm x 40 mm x 1.5 mm epoxy PCB FR4 with 6 cm2 (one layer, 70 µm thick) copper area for drain
connection. PCB is vertical in still air.
3)
See Diagram 3 for more detailed information
4)
See Diagram 13 for more detailed information
Final Data Sheet
3
Rev.2.0,2023-01-12
OptiMOSTM5Power-Transistor,80V
IQE046N08LM5
3Electricalcharacteristics
atTj=25°C,unlessotherwisespecified
Table4Staticcharacteristics
Parameter
Symbol
Drain-source breakdown voltage
Values
Unit
Note/TestCondition
-
V
VGS=0V,ID=1mA
1.7
2.3
V
VDS=VGS,ID=47µA
-
0.1
10
1
100
µA
VDS=80V,VGS=0V,Tj=25°C
VDS=80V,VGS=0V,Tj=125°C
IGSS
-
10
100
nA
VGS=20V,VDS=0V
Drain-source on-state resistance
RDS(on)
-
4.0
5.2
4.6
5.9
mΩ
VGS=10V,ID=20A
VGS=4.5V,ID=10A
Gate resistance
RG
-
0.6
0.9
Ω
-
gfs
-
62
-
S
|VDS|≥2|ID|RDS(on)max,ID=20A
Unit
Note/TestCondition
Min.
Typ.
Max.
V(BR)DSS
80
-
Gate threshold voltage
VGS(th)
1.1
Zero gate voltage drain current
IDSS
Gate-source leakage current
1)
Transconductance
Table5Dynamiccharacteristics
Parameter
Symbol
Input capacitance1)
Values
Min.
Typ.
Max.
Ciss
-
2500
3250
pF
VGS=0V,VDS=40V,f=1MHz
Coss
-
390
507
pF
VGS=0V,VDS=40V,f=1MHz
Reverse transfer capacitance
Crss
-
26
47
pF
VGS=0V,VDS=40V,f=1MHz
Turn-on delay time
td(on)
-
5.2
-
ns
VDD=40V,VGS=10V,ID=20A,
RG,ext=1.6Ω
Rise time
tr
-
2.6
-
ns
VDD=40V,VGS=10V,ID=20A,
RG,ext=1.6Ω
Turn-off delay time
td(off)
-
18
-
ns
VDD=40V,VGS=10V,ID=20A,
RG,ext=1.6Ω
Fall time
tf
-
4.4
-
ns
VDD=40V,VGS=10V,ID=20A,
RG,ext=1.6Ω
Unit
Note/TestCondition
Output capacitance1)
1)
Table6Gatechargecharacteristics2)
Parameter
Symbol
Gate to source charge
Gate charge at threshold
Values
Min.
Typ.
Max.
Qgs
-
7
-
nC
VDD=40V,ID=20A,VGS=0to4.5V
Qg(th)
-
4.3
-
nC
VDD=40V,ID=20A,VGS=0to4.5V
Gate to drain charge
Qgd
-
6.4
9.6
nC
VDD=40V,ID=20A,VGS=0to4.5V
Switching charge
Qsw
-
9.1
-
nC
VDD=40V,ID=20A,VGS=0to4.5V
Gate charge total
Qg
-
19
24
nC
VDD=40V,ID=20A,VGS=0to4.5V
Gate plateau voltage
Vplateau
-
2.8
-
V
VDD=40V,ID=20A,VGS=0to4.5V
Gate charge total
Qg
-
38
-
nC
VDD=40V,ID=20A,VGS=0to10V
Qoss
-
39
51
nC
VDS=40V,VGS=0V
1)
1)
1)
Output charge
1)
2)
Defined by design. Not subject to production test.
See ″Gate charge waveforms″ for parameter definition
Final Data Sheet
4
Rev.2.0,2023-01-12
OptiMOSTM5Power-Transistor,80V
IQE046N08LM5
Table7Reversediode
Parameter
Symbol
Diode continuous forward current
Diode pulse current
Diode forward voltage
1)
Reverse recovery time
1)
Reverse recovery charge
1)
Reverse recovery time
1)
Reverse recovery charge
1)
Values
Unit
Note/TestCondition
83
A
TC=25°C
-
396
A
TC=25°C
-
0.83
1.0
V
VGS=0V,IF=20A,Tj=25°C
trr
-
32
64
ns
VR=40V,IF=20A,diF/dt=100A/µs
Qrr
-
26
52
nC
VR=40V,IF=20A,diF/dt=100A/µs
trr
-
18
36
ns
VR=40V,IF=20A,diF/dt=1000A/µs
Qrr
-
129
258
nC
VR=40V,IF=20A,diF/dt=1000A/µs
Min.
Typ.
Max.
IS
-
-
IS,pulse
-
VSD
Defined by design. Not subject to production test.
Final Data Sheet
5
Rev.2.0,2023-01-12
OptiMOSTM5Power-Transistor,80V
IQE046N08LM5
4Electricalcharacteristicsdiagrams
Diagram2:Draincurrent
120
120
100
100
80
80
ID[A]
Ptot[W]
Diagram1:Powerdissipation
60
60
40
40
20
20
0
0
25
50
75
100
125
150
175
0
200
0
25
50
75
TC[°C]
100
125
150
175
200
TC[°C]
Ptot=f(TC)
ID=f(TC);VGS≥10V
Diagram3:Safeoperatingarea
Diagram4:Max.transientthermalimpedance
3
102
10
1 µs
10 µs
102
101
single pulse
0.01
0.02
0.05
0.1
0.2
0.5
100 µs
ZthJC[K/W]
ID[A]
101
1 ms
DC
100
100
10-1
10 ms
10-1
10-2
10-2
10-1
100
101
102
10-3
10-6
10-5
10-4
VDS[V]
10-2
10-1
100
tp[s]
ID=f(VDS);TC=25°C;D=0;parameter:tp
Final Data Sheet
10-3
ZthJC=f(tp);parameter:D=tp/T
6
Rev.2.0,2023-01-12
OptiMOSTM5Power-Transistor,80V
IQE046N08LM5
Diagram5:Typ.outputcharacteristics
Diagram6:Typ.drain-sourceonresistance
400
12
10 V
2.8 V
5V
350
10
3V
4V
3.5 V
300
8
4.5 V
RDS(on)[mΩ]
ID[A]
250
200
150
4V
100
3.5 V
50
3V
4.5 V
6
5V
4
10 V
2
0
2.8 V
0
1
2
3
4
0
5
0
25
50
75
VDS[V]
100
125
150
175
200
ID[A]
ID=f(VDS),Tj=25°C;parameter:VGS
RDS(on)=f(ID),Tj=25°C;parameter:VGS
Diagram7:Typ.transfercharacteristics
Diagram8:Typ.drain-sourceonresistance
400
12
350
10
300
25 °C
8
175 °C
RDS(on)[mΩ]
ID[A]
250
175 °C
200
150
6
4
25 °C
100
2
50
0
0
1
2
3
4
5
6
VGS[V]
0
2
4
6
8
10
12
14
16
VGS[V]
ID=f(VGS),|VDS|>2|ID|RDS(on)max;parameter:Tj
Final Data Sheet
0
RDS(on)=f(VGS),ID=20A;parameter:Tj
7
Rev.2.0,2023-01-12
OptiMOSTM5Power-Transistor,80V
IQE046N08LM5
Diagram10:Typ.gatethresholdvoltage
2.4
2.4
2.0
2.0
1.6
1.6
VGS(th)[V]
RDS(on)(normalizedto25°C)
Diagram9:Normalizeddrain-sourceonresistance
1.2
1.2
47 µA
0.8
0.8
0.4
0.4
0.0
-75
-50
-25
0
25
50
75
470 µA
0.0
-75
100 125 150 175 200
-50
-25
0
25
Tj[°C]
50
75
100 125 150 175 200
Tj[°C]
RDS(on)=f(Tj),ID=20A,VGS=10V
VGS(th=f(Tj),VGS=VDS;parameter:ID
Diagram11:Typ.capacitances
Diagram12:Forwardcharacteristicsofreversediode
4
103
10
25 °C
25 °C, max
175 °C
175 °C, max
Ciss
3
102
IF[A]
C[pF]
10
Coss
102
101
Crss
1
10
0
10
20
30
40
50
60
70
80
100
0.0
0.4
VDS[V]
1.2
1.6
2.0
2.4
VSD[V]
C=f(VDS);VGS=0V;f=1MHz
Final Data Sheet
0.8
IF=f(VSD);parameter:Tj
8
Rev.2.0,2023-01-12
OptiMOSTM5Power-Transistor,80V
IQE046N08LM5
Diagram13:Avalanchecharacteristics
Diagram14:Typ.gatecharge
2
10
10
16 V
40 V
64 V
8
101
25 °C
6
VGS[V]
IAV[A]
100 °C
150 °C
4
0
10
2
10-1
100
101
102
103
tAV[µs]
0
0
5
10
15
20
25
30
35
40
Qgate[nC]
IAS=f(tAV);RGS=25Ω;parameter:Tj,start
VGS=f(Qgate),ID=20Apulsed,Tj=25°C;parameter:VDD
Diagram15:Drain-sourcebreakdownvoltage
Diagram Gate charge waveforms
88
86
VBR(DSS)[V]
84
82
80
78
76
-75
-50
-25
0
25
50
75
100 125 150 175 200
Tj[°C]
VBR(DSS)=f(Tj);ID=1mA
Final Data Sheet
9
Rev.2.0,2023-01-12
OptiMOSTM5Power-Transistor,80V
IQE046N08LM5
5PackageOutlines
DIMENSION
A
A1
b
c
D
D1
E
e
L
L1
L2
L3
L4
L5
L6
MILLIMETERS
MIN.
MAX.
1.10
0.05
0.20
0.40
0.20
3.30
2.31
2.51
3.30
0.65
0.35
0.55
0.10
0.30
0.40
0.60
1.35
1.55
0.26
0.46
0.84
1.04
0.77
0.97
DOCUMENT NO.
Z8B00198723
REVISION
01
SCALE 10:1
0
2mm
1
EUROPEAN PROJECTION
ISSUE DATE
06.11.2019
Figure1OutlinePG-TSON-8,dimensionsinmm
Final Data Sheet
10
Rev.2.0,2023-01-12
OptiMOSTM5Power-Transistor,80V
IQE046N08LM5
RevisionHistory
IQE046N08LM5
Revision:2023-01-12,Rev.2.0
Previous Revision
Revision
Date
Subjects (major changes since last revision)
2.0
2023-01-12
Release of final version
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Final Data Sheet
11
Rev.2.0,2023-01-12
Mouser Electronics
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