IRAUDAMP10
300W x 2 Channel Class D Audio Power Amplifier
Using the IRS2052M and IRF6775
By
Jun Honda, Yasushi Nishimura and Liwei Zheng
CAUTION:
International Rectifier suggests the following guidelines for safe operation and handling of
IRAUDAMP10 Demo board;
Always wear safety glasses whenever operating Demo Board
Avoid personal contact with exposed metal surfaces when operating Demo Board
Turn off Demo Board when placing or removing measurement probes
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IRAUDAMP10 REV 1.1
Page 1 of 34
TABLE OF CONTENTS
PAGE
INTRODUCTION ............................................................................................................................................... 3
SPECIFICATIONS ............................................................................................................................................ 3
CONNECTION SETUP ..................................................................................................................................... 5
CONNECTOR DESCRIPTION ......................................................................................................................... 5
TEST PROCEDURES....................................................................................................................................... 6
PERFORMANCE AND TEST GRAPHS .......................................................................................................... 7
SOFT CLIPPING ............................................................................................................................................. 10
EFFICIENCY ................................................................................................................................................... 11
THERMAL CONSIDERATIONS ..................................................................................................................... 11
THERMAL INTERFACE MATERIAL’S PRESSURE CONTROL ................................................................................. 12
POWER SUPPLY REJECTION RATIO (PSRR) ............................................................................................ 14
SHORT CIRCUIT PROTECTION RESPONSE .............................................................................................. 15
IRAUDAMP10 OVERVIEW ............................................................................................................................ 16
FUNCTIONAL DESCRIPTIONS ..................................................................................................................... 18
IRS2052M GATE DRIVER IC ......................................................................................................................... 18
SELF-OSCILLATING FREQUENCY .................................................................................................................... 19
ADJUSTMENTS OF SELF-OSCILLATING FREQUENCY ......................................................................................... 19
INTERNAL CLOCK OSCILLATOR ....................................................................................................................... 19
SELECTABLE DEAD-TIME ................................................................................................................................ 20
PROTECTION SYSTEM OVERVIEW ............................................................................................................ 21
CLICK AND POP NOISE REDUCTION ......................................................................................................... 23
BUS PUMPING ............................................................................................................................................... 24
INPUT SIGNAL AND GAIN SETTING ........................................................................................................... 24
GAIN SETTING ............................................................................................................................................... 25
IRAUDAMP10 FABRICATION MATERIALS ................................................................................................. 27
IRAUDAMP10 PCB SPECIFICATIONS ......................................................................................................... 31
REVISION CHANGES DESCRIPTIONS ........................................................................................................ 34
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IRAUDAMP10 REV 1.1
Page 2 of 34
Introduction
The IRAUDAMP10 Demo board is a reference design which uses only one IC (IRS2052M) to derive
appropriate input signals, amplify the audio input, and achieve a two-channel 280 W/ch (4Ω, THD+N=1%)
half-bridge Class D audio power amplifier. The reference design demonstrates how to use the IRS2052M
Class D audio controller and gate driver IC, implement protection circuits, and design an optimum PCB
layout using IRF6775 DirectFET MOSFETs. The reference design contains all the required housekeeping
power supplies for ease of use. The two-channel design is scalable, for power and number of channels.
Applications
AV receivers
Home theater systems
Mini component stereos
Powered speakers
Sub-woofers
Musical Instrument amplifiers
Automotive after market amplifiers
Features
Output Power:
Residual Noise:
Distortion:
Efficiency:
Multiple Protection Features:
PWM Modulator:
300W x 2 channels (4Ω, THD+N=1%)
or 370W x 2 channels (4Ω, THD+N=10%)
220V, IHF-A weighted, AES-17 filter
0.008% THD+N @ 100W, 4Ω
90% @ 300W, 4Ω, single-channel driven, Class D stage
Over-current protection (OCP), high side and low side
Over-voltage protection (OVP),
Under-voltage protection (UVP), high side and low side
Over-temperature protection (OTP)
Self-oscillating half-bridge topology with optional clock synchronization
Specifications
General Test Conditions (unless otherwise noted)
Supply Voltages
±50V
Load Impedance
4Ω
Self-Oscillating Frequency
500kHz
Gain Setting
30.8dB
Notes / Conditions
No input signal, Adjustable
1Vrms input yields rated power
Electrical Data
IR Devices Used
Typical
Notes / Conditions
IRS2052M Audio Controller and Gate-Driver,
IRF6775 DirectFET MOSFETs
Modulator
Self-oscillating, second order sigma-delta modulation, analog input
Power Supply Range
± 25V to ±50V
Bipolar power supply
Output Power CH1-2: (1% THD+N)
300W
1kHz, ±50V
Output Power CH1-2: (10% THD+N)
370W
1kHz, ±50V
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IRAUDAMP10 REV 1.1
Page 3 of 34
Rated Load Impedance
Standby Supply Current
Total Idle Power Consumption
Channel Efficiency
8-4Ω
+45/-95mA
7W
90%
Resistive load
No input signal
No input signal
Single-channel driven,
300W, Class D stage
.
Audio Performance
Class D
Output
THD+N, 1W
THD+N, 20W
THD+N, 100W
THD+N, 200W
0.015%
0.009%
0.008%
0.015%
Dynamic Range
100dB
Residual Noise, 22Hz - 20kHzAES17
220V
Damping Factor
Channel Separation
51
74dB
74dB
70dB
±1dB
±3dB
Frequency Response : 20Hz-20kHz
: 20Hz-35kHz
Physical Specifications
Dimensions
Notes / Conditions
1kHz, Single-channel driven
A-weighted, AES-17 filter,
Single-channel operation
Self-oscillating – 500kHz
1kHz, relative to 4Ω load
100Hz
1kHz
10kHz
1W, 4Ω - 8Ω Load
Weight
3.94”(L) x 2.83”(W) x 0.85”(H)
100 mm (L) x 72 mm (W) x 21.5 mm(H)
0.130kgm
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IRAUDAMP10 REV 1.1
Page 4 of 34
Connection Setup
Fig 1 Typical Test Setup
Connector Description
CN1
P1
P2
P3
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Pin #
1
2
3
4
1
2
3
1
2
1
2
Pin Name
CH1 INPUT
GND
GND
CH2 INPUT
-B
GND
+B
CH2 OUTPUT
GND
GND
CH1 OUTPUT
Pin Description
Analog input for CH1
Floating ground of Channel 1 input
Floating ground of Channel 2 input
Analog input for CH2
-50V supply referenced to GND.
Ground signal from MB.
+50V supply referenced to GND.
Output of Channel 2
Floating ground of Channel 2 output
Floating ground of Channel 1 output
Output of Channel 1
IRAUDAMP10 REV 1.1
Page 5 of 34
Test Procedures
Test Setup:
1. Connect 4-200 W dummy loads to 2 output connectors (P2 and P3 as shown on Fig 1)
and an Audio Precision analyzer (AP).
2. Connect the Audio Signal Generator to CN1 for CH1~CH2 respectively (AP).
3. Set up the dual power supply with voltages of ±50V; current limit to 5A.
4. TURN OFF the dual power supply before connecting to On of the unit under test (UUT).
5. Connect the dual power supply to P1. as shown on Fig 1
Power up:
6. Turn ON the dual power supply. The ±B supplies must be applied and removed at the
same time.
7. One orange and two blue LED should turn ON immediately and stay ON
8. Quiescent current for the positive supply should be 45mA 10mA at +50V.
9. Quiescent current for the negative supply should be 95mA 10mA at –50V.
Switching Frequency test
10. With an Oscilloscope, monitor the switching waveform at test points VS1~VS2. Adjust
VR1A and VR1B to set the self oscillating frequency to 500 kHz 25 kHz when DUT in
free oscillating mode.
Functionality Audio Tests:
11. Set the signal generator to 1kHz, 20 mVRMS output.
12. Connect the audio signal generator to CN1(Input of CH1,CH2,CH3)
13. Sweep the audio signal voltage from 15 mVRMS to 1 VRMS.
14. Monitor the output signals at P2/P3 with an oscilloscope. The waveform must be a non
distorted sinusoidal signal.
15. Observe that a 1 VRMS input generates an output voltage of 34.88 VRMS(CH1/CH2). The
ratio, R4x/(R3x) and R30x/(R31x), determines the voltage gain of IRAUDAMP10.
Test Setup using Audio Precision (Ap):
16. Use an unbalanced-floating signal from the generator outputs.
17. Use balanced inputs taken across output terminals, P2 and P3.
18. Connect Ap frame ground to GND at terminal P1.
19. Select the AES-17 filter(pull-down menu) for all the testing except frequency response.
20. Use a signal voltage sweep range from 15 mVRMS to 1.5 VRMS.
21. Run Ap test programs for all subsequent tests as shown in Fig 2- Fig 7below.
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IRAUDAMP10 REV 1.1
Page 6 of 34
Performance and test graphs
10
5
2
1
0 .5
0 .2
%
0 .1
0.05
0.02
0.01
0.005
0.002
0.001
100m
200m
500m
1
2
5
10
20
50
100
200
500
W
S w eep
Tra c e
C o lo r
L in e S t y le
Th ic k
D ata
A x is
C om m ent
1
1
1
3
B lu e
M agenta
S o lid
S o lid
2
2
A n lr. TH D + N R a t io
A n lr. TH D + N R a t io
L e ft
L e ft
CH2
CH1
±B Supply = ±50V, 4 Ω Resistive Load
Fig 2 IRAUDAMP10, THD+N versus Power, Stereo, 4 Ω
.
+4
T
+2
+0
d
B
r
-2
-4
A
-6
-8
-10
20
50
100
200
500
1k
2k
5k
10k
20k
50k
100k 200k
Hz
Sweep
Trace
Color
Line Style
Thick
Data
Axis
Comment
1
1
1
2
Blue
Magenta
Solid
Solid
2
2
Anlr.Level B
Anlr.Level A
Left
Left
CH2
CH1
±B Supply = ±50V, 4 Ω Resistive Load
Fig 3 IRAUDAMP10, Frequency response
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IRAUDAMP10 REV 1.1
Page 7 of 34
100
10
1
0.1
%
0.01
0.001
0.0001
20
50
100
200
500
1k
2k
5k
10k
20k
10k
20k
Hz
Sweep
Trace
Color
Line Style
Thick
Data
Axis
Comment
1
2
3
1
1
1
Green
Yellow
Red
Solid
Solid
Solid
2
2
2
Anlr.THD+N Ratio
Anlr.THD+N Ratio
Anlr.THD+N Ratio
Left
Left
Left
10W
50W
100W
Fig 4 THD+N Ratio vs. Frequency
+0
-10
-20
-30
-40
d
B
V
-50
-60
-70
-80
-90
-100
-110
10
20
50
100
200
500
1k
2k
5k
Hz
S weep
Trac e
Color
Line S ty le
Thic k
Data
A x is
Com m ent
1
1
1
2
B lue
M agenta
S olid
S olid
2
2
F ft.Ch.1 A m pl
F ft.Ch.2 A m pl
Left
Left
CH2
CH1
Fig 5, 1V output Frequency Spectrum
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IRAUDAMP10 REV 1.1
Page 8 of 34
+20
+0
-20
-40
d
B
V
-60
-80
-100
-120
-140
10
20
50
100
200
500
1k
2k
5k
10k
20k
Hz
Sweep
Trace
Color
Line Style
Thick
Data
Axis
Comment
1
1
1
2
Blue
Magenta
Solid
Solid
2
2
Fft.Ch.1 Ampl
Fft.Ch.2 Ampl
Left
Left
CH2
CH1
No signal, Self Oscillator @ 500kHz
Fig 6, IRAUDAMP10 Noise Floor
.
+0
-10
-20
-30
d
B
r
A
-40
-50
-60
-70
-80
-90
-100
20
50
100
200
500
1k
2k
5k
10k
20k
Hz
S weep
Trac e
Color
Line S ty le
Thic k
Data
A x is
Com m ent
1
1
1
2
B lue
M agenta
S olid
S olid
2
2
A nlr.A m pl
A nlr.A m pl
Left
Left
CH2-CH1
CH1-CH2
Fig 7, Channel separation vs. frequency
.
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IRAUDAMP10 REV 1.1
Page 9 of 34
Soft Clipping
IRS2052M has Clipping detection function, it monitors error voltage in COMP pin with a window
comparator and pull an open drain nmos referenced to GND. Threshold to detect is at 10% and
90% of VAA-VSS. Each channel has independent CLIP outputs. Once IRS2052M detects
Clipping, the CLIP pin can generate pulses to trigger soft clipping circuit, which can limit output’s
maximum power as Fig 9(soft clipping circuit is not available on AMP10 reference board).
Soft Clipping
R28A
1K
C15A
10uF, 16V
R29A
220K
D3A
1N4148
Audio signal INPUT
R27A
C6A
1uF,50V
R5A
47K
GND
R6A
47K
CLIP Detection
D
C0A
R7A
470K
Q5
VAA
DTA144EKA
10uF,50V 3.3K
S
G
Q6
MMBFJ112
R3A
1K
IN-
C5A
10uF, 50V
VSS
GND
Fig 9 Soft Clipping Circuit
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IRAUDAMP10 REV 1.1
Page 10 of 34
Efficiency
Fig 10 shows efficiency characteristics of the IRAUDAMP10. The high efficiency is achieved by
following major factors:
1) Low conduction loss due to the DirectFETs offering low RDS(ON)
2) Low switching loss due to the DirectFETs offering low input capacitance for fast rise and
fall times
Secure dead-time provided by the IRS2052M, avoiding cross-conduction.
Efficiency (%)
100%
90%
Efficiency (%)
80%
70%
60%
AMP10 50V 4ohms
50%
40%
30%
20%
10%
0%
0
50
100
150
200
250
Output power (W)
300
350
Fig 10, IRAUDAMP10 4 ohms load Stereo, ±B supply = ±50V
Thermal Considerations
With this high efficiency, the IRAUDAMP10 design can handle one-eighth of the continuous rated
power, which is generally considered to be a normal operating condition for safety standards,
without additional heatsinks or forced air-cooling.
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IRAUDAMP10 REV 1.1
Page 11 of 34
Thermal Interface Material’s Pressure Control
The pressure between DirectFET & TIM (Thermal Interface Material) is controlled by depth of Heat
Spreader’s groove. Choose TIM which is recommended by IR. (Refer to AN-1035 for more
details). TIM’s manufacturer thickness, conductivity, & etc. determine pressure requirement.
Below shows selection options recommended:
Fig 11 TIM Information
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IRAUDAMP10 REV 1.1
Page 12 of 34
Check the TIM’s compression deflection with constant rate of strain (example as Fig.12) base on
manufacturer’s datasheet. According to the stress requirement, find strain range for the TIM. Then,
calculate heat spreader groove depth as below:
Groove Depth=DirectFET’s Height +TIM’s Thickness*strain
**DirectFET’s height should be measured from PCB to the top of DirectFET after reflow. The
average height of IRF6775 is 0.6mm.
Fig 12 compression deflection with constant rate of strain
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IRAUDAMP10 REV 1.1
Page 13 of 34
Power Supply Rejection Ratio (PSRR)
The IRAUDAMP10 obtains good power supply rejection ratio of -60 dB at 1kHz shown in Fig 13.
With this high PSRR, IRAUDAMP10 accepts any power supply topology when the supply voltages
fit between the min and max range.
+0
-10
-20
-30
d
B
-40
-50
-60
-70
-80
-90
20
50
100
200
500
1k
2k
5k
10k
20k
40k
Hz
Sweep
Trace
Color
Line Style
Thick
Data
Axis
2
1
Red
Solid
2
Anlr.Ratio
Left
Comment
Fig 13 Power Supply Rejection Ratio (PSRR)
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IRAUDAMP10 REV 1.1
Page 14 of 34
Short Circuit Protection Response
Figs 14-15 show over current protection reaction time of the IRAUDAMP10 in a short circuit event.
As soon as the IRS2052M detects an over current condition, it shuts down PWM. After one
second, the IRS2052M tries to resume the PWM. If the short circuit persists, the IRS2052M
repeats try and fail sequences until the short circuit is removed.
Short Circuit in Positive and Negative Load Current
CSD pin
CSD pin
VS pin
VS pin
Load current
Load current
Positive OCP
Negative OCP
Fig 14 Positive and Negative OCP Waveforms
.
OCP Waveforms Showing CSD Trip and Hiccup
CSD pin
CSD pin
VS pin
VS pin
Load current
Load current
Fig 15 OCP Response with Continuous Short Circuit
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IRAUDAMP10 REV 1.1
Page 15 of 34
IRAUDAMP10 Overview
The IRAUDAMP10 features a 2CH self-oscillating type PWM modulator for the smallest space,
highest performance and robust design. This topology represents an analog version of a secondorder sigma-delta modulation having a Class D switching stage inside the loop. The benefit of the
sigma-delta modulation, in comparison to the carrier-signal based modulation, is that all the error
in the audible frequency range is shifted to the inaudible upper-frequency range by nature of its
operation. Also, sigma-delta modulation allows a designer to apply a sufficient amount of error
correction.
The IRAUDAMP10 self-oscillating topology consists of following essential functional blocks.
Front-end integrator
PWM comparator
Level shifters
Gate drivers and MOSFETs
Output LPF
Integrator
Referring to Fig 16 below, the input operational amplifier of the IRS2052M forms a front-end
second-order integrator with R3x, C2x, C3x, and R2x. The integrator that receives a rectangular
feedback signal from the PWM output via R4x and audio input signal via R3x generates a
quadratic carrier signal at the COMP pin. The analog input signal shifts the average value of the
quadratic waveform such that the duty cycle varies according to the instantaneous voltage of the
analog input signal.
PWM Comparator
The carrier signal at the COMP pin is converted to a PWM signal by an internal comparator that
has a threshold at middle point between VAA and VSS. The comparator has no hysteresis in its
input threshold.
Level Shifters
The internal input level-shifter transfers the PWM signal down to the low-side gate driver section.
The gate driver section has another level-shifter that level shifts up the high-side gate signal to the
high-side gate driver section.
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IRAUDAMP10 REV 1.1
Page 16 of 34
Gate Drivers and DirectFETs
The received PWM signal is sent to the dead-time generation block where a programmable
amount of dead time is added into the PWM signal between the two gate output signals of LO and
HO to prevent potential cross conduction across the output power DirectFETs. The high-side levelshifter shifts up the high-side gate drive signal out of the dead-time block.
Each channel of the IRS2052M’s drives two DirectFETs, high- and low-sides, in the power stage
providing the amplified PWM waveform.
Output LPF
The amplified PWM output is reconstructed back to an analog signal by the output LC LPF.
Demodulation LC low-pass filter (LPF) formed by L1 and C13, filters out the Class D switching
carrier signal leaving the audio output at the speaker load. A single stage output filter can be used
with switching frequencies of 500 kHz and greater; a design with a lower switching frequency may
require an additional stage of LPF.
Fig 16 Simplified Block Diagram of IRAUDAMP10 Class D Amplifier
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IRAUDAMP10 REV 1.1
Page 17 of 34
Functional Descriptions
IRS2052M Gate Driver IC
The IRAUDAMP10 uses the IRS2052M, a 2 Channel high-voltage (up to 200 V), high-speed
power MOSFET driver with internal dead-time and protection functions specifically designed for
Class D audio amplifier applications. These functions include OCP and UVP. The IRS2052M
integrates bi-directional over current protection for both high-side and low-side MOSFETs. The
dead-time can be selected for optimized performance according to the size of the MOSFET,
minimizing dead-time while preventing shoot-through. As a result, there is no gate-timing
adjustment required externally. Selectable dead-time through the DT pin voltage is an easy and
reliable function which requires only two external resistors, R12 and R13 as shown on Fig 17 or
Fig 23 below.
The IRS2052M offers the following functions.
PWM modulator
Dead-time insertion
Over current protection
Under voltage protection
Level shifters
Refer to IRS2052M datasheet and AN-1159 for more details.
L1A
CH3 OUTPUT
18
C14A
0.1uF, 63V
C14B
R21B
10R,1W
2.2K
CH1 OUTPUT
4.7R
R17B
R15B 10K
***
R71B
10K
Q1B,D
IRF6665/6775M
+B
C19B
1k
R9B
S1
3way SW
C15
N/A
XTAL
C17A
470uF,63V
GND
R23B
100k
C17D
0.1uF,100V
C17B
470uF,63V
-B
10R
Q2B,D
IRF6665/6775M
VSS
R23A
100k
C17C
0.1uF,100V
1R
22uF,16V
3.9K
13
R19B
R16B
14
0.1uF,100V
15
10R
C11 C12 C13 C14
330pF 330pF 330pF 330pF
R24B
22uH
DS5
XTAL
VAA VAA
GND
L1B
RF071M2STR
R18B
D2B
16
NC
R106
2
0.47uF, 400V
C13B
C9B
10uF,16V
R14B 4.7R
19
17
12
9
11
R52
1K
2
1R
4.7R
D2A
RF071M2STR
21
Y2
Y1
C19A R19A
DS4
R18A
0.1uF,100V
D1A
RF071M2STR
Q2A,C
IRF6665/6775M
20
R22B
***
R51
1K
R21A
0.1uF, 63V 10R,1W
C10A
22uF,16V
3.9K
22
C10B
27
25
NC
28
26
NC
NC
OTP
VS2
VS1
NC
XSL
X2A
23
R71A
10K
R12B
N/A
R107
3.9K
DS2
SD
GND
10R
R15A
*** R17A
10K
R16A
R20B
1
D4
1N4148
10R
D1B
RF071M2STR
8.2K
0
-B
NC
1
0.47uF, 400V
C13A
R22A
***
2.2K
R12
C16A
0.01uF
29
COM
30
31
34
33
HO1
NC
R12A
N/A
R20A
R9A
24
R108
3.9K
C8
10uF, 16V
R14
10R
D3
CSD
32
35
VB1
CSD
R22
10R
R4B
100K
DT
CSH1
NC
4.7uF,10V
R15
10R
LO1
CLIP1
1N4148
4.7uF,10V GND
VCC2
COMP1
C9
GND
LO2
COM2
IN1
10
47
DSB
-B
VAA
R104
C10
C12B
220pF
VSS
X2B
46
R26B 10K
48
R0B
100K
CSH2
IRS2052M
8
C2B
2.2nF,50V
45
VCC
R11 ***
44
IC1
GND
7
R27B
VAA
43
VB2
IN2
X1A
VR1B
200R
3.3K
VSS
42
4.7uF,10V
RpA 90C
HO2
COMP2
6
15K
4.7uF,10V
C7
C3B
2.2nF,50V
R32A 10R
CLIP2
X1B
R30B
10K
C6
1nF,50V C4B
R2B 120R
GND
NC
5
R7 10R
41
NC
NC
36
R3B
1K
NE5532AN
R31B
39
CKO
C5B
10uF, 50V
R6 10R
FAULT
R3A
1K
OTW
5
6
7
8
GND 2IN+
1IN+
2IN1IN- 2OUT
1OUT VDD
C0B
10uF,50V
38
C4A
1nF,50V
40
C5A
10uF, 50V
1
4
3
2
1
GND
4
3
2
1
VR1A
200R
R2A 120R
GND
NC
10K 2
CH2
GND
GND
CH1
C8B
470pF
IC3
37
DSA
C3A 2.2nF,50V
4
C8A
470pF
3.3K
C0A
10uF,50V
CN1
10K
10K 3
C2A
2.2nF,50V
R27A
R30A 15K
VREF
R26A
R31A 10K
R105
R0A
100K
OCSET
R4A
100K
C12A
220pF
DS3
GND
R24A 2.2K
Q1A,C
IRF6665/6775M
R13
1K
C9A 10uF,16V
R10
22uH
R14A 4.7R
VAA
P2
CH2 OUTPUT
GND
C62
+5v
R45
10k
0.01uF, 50V
R43
470R,1W
CH2
P1
R47
470R,1W
-B
GND
+B
R62 10k
C40
220uF/10V
GND
1
2
Q8 MJD44H11T4G
Z5
5.6V
1
2
3
GND
R54
10k
For EMI
R57
47k
P3
R50
47k
R36
100R,1W
GND
CH1 OUTPUT
R56
47k
S2
Z6
5.6V
C41
220uF/10V
Q9
-5v
R46
10k
MJD45H11T4G
Z3
***
R53
10k
Q4
MMBT5551
Q3
MMBT5551
R44
R48
470R,1W
470R,1W
Z4
24V
R58
47k
R55
47k
OVP
R31
10k
Q1
MJD44H11T4G
R39
100R,1W
CH1
DS1
C32
100uF, 25V
Z1
12V
R41 10k
R40 10k
UVP
D1A, D1B
D1C, D1D
R11
R15A, R15B
R22A, R22B
Z3
IRF6665 Version
Q1A, Q1B, Q1A, Q1B
1N4148
8.2k
10k
22k
39V
IRF6775M Version
Q1C, Q1D, Q2C, Q2D
RF071M2
5.6k
5.6k
33k
51V
Fig 17 System-level View of IRAUDAMP10
www.irf.com
1
2
R37
100R,1W
R38
100R,1W
IRAUDAMP10 REV 1.1
Page 18 of 34
Self-Oscillating Frequency
Self-oscillating frequency is determined by the total delay time along the control loop of the
system; the propagation delay of the IRS2052M, the DirectFETs switching speed, the timeconstant of front-end integrator (R2x, R3x, R4x, Vr1x, C2x, C3x ). Variations in +B and –B supply
voltages also affect the self-oscillating frequency.
The self-oscillating frequency changes with the duty ratio. The frequency is highest at idling. It
drops as duty cycle varies away from 50%.
Adjustments of Self-Oscillating Frequency
Use VR1x to set different self-oscillating frequencies. The PWM switching frequency in this type of
self-oscillating switching scheme greatly impacts the audio performance, both in absolute
frequency and frequency relative to the other channels. In absolute terms, at higher frequencies,
distortion due to switching-time becomes significant, while at lower frequencies, the bandwidth of
the amplifier suffers. In relative terms, interference between channels is most significant if the
relative frequency difference is within the audible range.
Normally, when adjusting the self-oscillating frequency of the different channels, it is suggested to
either match the frequencies accurately, or have them separated by at least 25kHz. Under the
normal operating condition with no audio input signal, the switching-frequency is set around
500kHz in the IRAUDAMP10.
Internal Clock Oscillator
The IRS2052M integrates two clock oscillators and synchronization networks for each PWM
channel. To prevent AM radio reception interference, two PWM frequencies are selectable via XSL
pin. As shown in Table 2, when XSL is bias to VAA, X1A and X1B are active. When XSL is GND
X2A and X2B are active. When XSL is VSS, both clock oscillators are disabled.
XSL pin
VAA
GND
VSS
X1A/B
Activated
Disabled
Disabled
X2A/B
Disabled
Activated
Disabled
CKO outputs internal clock with VAA/VSS amplitude. The CKO can distribute clock signal to
multiple IRS2052 devices to synchronize PWM switching timing.
www.irf.com
IRAUDAMP10 REV 1.1
Page 19 of 34
Selectable Dead-time
The dead-time of the IRS2052 is set based on the voltage applied to the DT pin. Fig 18 lists the
suggested component value for each programmable dead-time between 45 and 105 ns.
All the IRAUDAMP10 models use DT1 (45ns) dead-time.
Dead-time Mode
DT1
DT2
DT3
DT4
R1
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