IRFB3307

PD - 95706D IRFB3307PbF IRFS3307PbF IRFSL3307PbF Applications l High Efficiency Synchronous Rectification in SMPS l Uninterruptible Power Supply l High Speed Power Switching l Hard Switched and High Frequency Circuits HEXFET® Power MOSFET D G S Benefits l Improved Gate, Avalanche and Dynamic dV/dt Ruggedness l Fully Characterized Capacitance and Avalanche SOA l Enhanced body diode dV/dt and dI/dt Capability l Lead-Free VDSS RDS(on) typ. max. ID 75V 5.0m: 6.3m: 120A S D G S D G S D G D2Pak IRFS3307PbF TO-220AB IRFB3307PbF TO-262 IRFSL3307PbF Absolute Maximum Ratings Symbol ID @ TC = 25°C ID @ TC = 100°C Parameter Max. Units cl cl 120 84 Continuous Drain Current, VGS @ 10V Continuous Drain Current, VGS @ 10V d A 510 IDM Pulsed Drain Current PD @TC = 25°C Maximum Power Dissipation 200 W l l Linear Derating Factor 1.3 VGS Gate-to-Source Voltage ± 20 W/°C V TJ TSTG Operating Junction and Storage Temperature Range -55 to + 175 °C 300 Soldering Temperature, for 10 seconds (1.6mm from case) x Avalanche Characteristics EAS (Thermally limited) IAR Single Pulse Avalanche Energy Avalanche Current EAR Repetitive Avalanche Energy c x 10lb in (1.1N m) Mounting torque, 6-32 or M3 screw e 270 See Fig. 14, 15, 16a, 16b g mJ A mJ Thermal Resistance Symbol Parameter k Typ. Max. ––– 0.61 l R JC Junction-to-Case R CS R JA Case-to-Sink, Flat Greased Surface , TO-220 Junction-to-Ambient, TO-220 0.50 ––– ––– 62 R JA Junction-to-Ambient (PCB Mount) , D 2Pak ––– 40 www.irf.com k jk Units °C/W 1 01/20/12 IRFB/S/SL3307PbF Static @ TJ = 25°C (unless otherwise specified) Symbol Parameter V(BR)DSS V(BR)DSS/TJ R DS(on) VGS(th) IDSS Drain-to-Source Breakdown Voltage Breakdown Voltage Temp. Coefficient Static Drain-to-Source On-Resistance Gate Threshold Voltage Drain-to-Source Leakage Current IGSS Gate-to-Source Forward Leakage Gate-to-Source Reverse Leakage Gate Input Resistance RG Min. Typ. Max. Units 75 ––– ––– ––– 0.069 ––– ––– 5.0 6.3 2.0 ––– 4.0 ––– ––– 20 ––– ––– 250 ––– ––– 200 ––– ––– -200 ––– 1.5 ––– V V/°C m V μA nA  Conditions VGS = 0V, ID = 250μA Reference to 25°C, ID = 1mA VGS = 10V, ID = 75A VDS = VGS, ID = 150μA VDS = 75V, VGS = 0V VDS = 75V, VGS = 0V, TJ = 125°C VGS = 20V VGS = -20V f = 1MHz, open drain d g Dynamic @ TJ = 25°C (unless otherwise specified) Symbol gfs Qg Qgs Qgd td(on) tr td(off) tf C iss C oss C rss C oss eff. (ER) C oss eff. (TR) Parameter Min. Typ. Max. Units Forward Transconductance Total Gate Charge Gate-to-Source Charge Gate-to-Drain ("Miller") Charge Turn-On Delay Time Rise Time Turn-Off Delay Time Fall Time Input Capacitance Output Capacitance Reverse Transfer Capacitance Effective Output Capacitance (Energy Related) Effective Output Capacitance (Time Related) 98 ––– ––– ––– ––– ––– ––– ––– ––– ––– ––– ––– ––– h ––– 120 35 46 26 120 51 63 5150 460 250 570 700 ––– 180 ––– ––– ––– ––– ––– ––– ––– ––– ––– ––– ––– S nC ns pF Conditions VDS = 50V, ID = 75A ID = 75A VDS = 60V VGS = 10V VDD = 48V ID = 75A RG = 3.9 VGS = 10V VGS = 0V VDS = 50V ƒ = 1.0MHz VGS = 0V, VDS = 0V to 60V , See Fig.11 VGS = 0V, VDS = 0V to 60V , See Fig. 5 g g i h Diode Characteristics Symbol IS Parameter Min. Typ. Max. Units Continuous Source Current VSD dv/dt trr (Body Diode) Pulsed Source Current (Body Diode) Diode Forward Voltage Peak Diode Recovery Reverse Recovery Time Qrr Reverse Recovery Charge IRRM ton Reverse Recovery Current Forward Turn-On Time ISM d ––– 130 c A Conditions MOSFET symbol D showing the G integral reverse S p-n junction diode. ––– ––– 1.3 V TJ = 25°C, IS = 75A, VGS = 0V ––– 11 ––– V/ns TJ = 175°C, IS = 75A, VDS = 75V ––– 38 57 ns TJ = 25°C VR = 64V, ––– 46 69 TJ = 125°C IF = 75A di/dt = 100A/μs ––– 65 98 nC TJ = 25°C ––– 86 130 TJ = 125°C ––– 2.8 ––– A TJ = 25°C Intrinsic turn-on time is negligible (turn-on is dominated by LS+LD) Notes:  Calculated continuous current based on maximum allowable junction temperature. Package limitation current is 75A. ‚ Repetitive rating; pulse width limited by max. junction temperature. ƒ Limited by TJmax, starting TJ = 25°C, L = 0.096mH RG = 25, IAS = 75A, VGS =10V. Part not recommended for use above this value. „ ISD  75A, di/dt  530A/μs, VDD V(BR)DSS, TJ  175°C. … Pulse width  400μs; duty cycle  2%. 2 ––– ––– ––– 510 A g f g † Coss eff. (TR) is a fixed capacitance that gives the same charging time as Coss while VDS is rising from 0 to 80% VDSS . ‡ Coss eff. (ER) is a fixed capacitance that gives the same energy as Coss while VDS is rising from 0 to 80% VDSS. ˆ When mounted on 1" square PCB (FR-4 or G-10 Material). For recom mended footprint and soldering techniques refer to application note #AN-994. ‰ R is measured at TJ approximately 90°C. Š RJC (end of life) for D2Pak and TO-262 = 0.75°C/W. Note: This is the maximum measured value after 1000 temperature cycles from -55 to 150°C and is accounted for by the physical wearout of the die attach medium. www.irf.com IRFB/S/SL3307PbF 1000 1000 ID, Drain-to-Source Current (A) 100 BOTTOM 10 TOP ID, Drain-to-Source Current (A) TOP VGS 15V 10V 8.0V 6.0V 5.5V 5.0V 4.8V 4.5V 100 1 4.5V 0.1 BOTTOM 4.5V 10 60μs PULSE WIDTH 60μs PULSE WIDTH Tj = 175°C Tj = 25°C 0.01 0.1 1 10 1 100 0.1 1000 Fig 1. Typical Output Characteristics 10 100 1000 Fig 2. Typical Output Characteristics 1000 2.5 RDS(on) , Drain-to-Source On Resistance (Normalized) ID, Drain-to-Source Current ) 1 V DS, Drain-to-Source Voltage (V) V DS, Drain-to-Source Voltage (V) 100 T J = 175°C 10 T J = 25°C 1 VDS = 25V 60μs PULSE WIDTH 0.1 ID = 75A VGS = 10V 2.0 1.5 1.0 0.5 2 4 6 8 10 -60 -40 -20 0 Fig 4. Normalized On-Resistance vs. Temperature Fig 3. Typical Transfer Characteristics 100000 12.0 VGS = 0V, f = 1 MHZ C iss = C gs + C gd, C ds SHORTED C rss = C gd VGS, Gate-to-Source Voltage (V) ID= 75A C oss = C ds + C gd 10000 Ciss Coss 1000 20 40 60 80 100 120 140 160 180 T J , Junction Temperature (°C) VGS, Gate-to-Source Voltage (V) C, Capacitance(pF) VGS 15V 10V 8.0V 6.0V 5.5V 5.0V 4.8V 4.5V Crss 10.0 VDS= 60V VDS= 38V VDS= 15V 8.0 6.0 4.0 2.0 0.0 100 1 10 100 VDS, Drain-to-Source Voltage (V) Fig 5. Typical Capacitance vs. Drain-to-Source Voltage www.irf.com 0 20 40 60 80 100 120 140 QG Total Gate Charge (nC) Fig 6. Typical Gate Charge vs. Gate-to-Source Voltage 3 IRFB/S/SL3307PbF 10000 ID, Drain-to-Source Current (A) ISD, Reverse Drain Current (A) 1000 OPERATION IN THIS AREA LIMITED BY R DS(on) 1000 T J = 175°C 100 T J = 25°C 10 100μsec 100 1msec 10 10msec 1 VGS = 0V 0.1 1 1 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 V(BR)DSS , Drain-to-Source Breakdown Voltage (V) 140 Limited By Package ID, Drain Current (A) 100 80 60 40 20 0 25 50 75 100 125 150 175 100 95 90 85 80 75 70 -60 -40 -20 0 20 40 60 80 100 120 140 160 180 T J , Temperature ( °C ) T C , Case Temperature (°C) Fig 10. Drain-to-Source Breakdown Voltage Fig 9. Maximum Drain Current vs. Case Temperature 1.4 EAS , Single Pulse Avalanche Energy (mJ) 1200 1.2 1.0 Energy (μJ) 100 Fig 8. Maximum Safe Operating Area Fig 7. Typical Source-Drain Diode Forward Voltage 120 10 VDS, Drain-to-Source Voltage (V) VSD, Source-to-Drain Voltage (V) 0.8 0.6 0.4 0.2 0.0 ID 8.6A 12A BOTTOM 75A TOP 1000 800 600 400 200 0 0 10 20 30 40 50 60 70 VDS, Drain-to-Source Voltage (V) 4 DC Tc = 25°C Tj = 175°C Single Pulse Fig 11. Typical COSS Stored Energy 80 25 50 75 100 125 150 175 Starting T J , Junction Temperature (°C) Fig 12. Maximum Avalanche Energy vs. DrainCurrent www.irf.com IRFB/S/SL3307PbF 1 Thermal Response ( Z thJC ) D = 0.50 0.20 0.1 0.10 0.05 0.02 0.01 0.01 J SINGLE PULSE ( THERMAL RESPONSE ) 0.001 R1 R1 J 1 R2 R2 C 2 1 Ri (°C/W) i (sec) 0.2911 0.000484 0.3196 0.005529  2 Ci= iRi Ci iRi Notes: 1. Duty Factor D = t1/t2 2. Peak Tj = P dm x Zthjc + Tc 0.0001 1E-006 1E-005 0.0001 0.001 0.01 0.1 1 t1 , Rectangular Pulse Duration (sec) Fig 13. Maximum Effective Transient Thermal Impedance, Junction-to-Case 100 Allowed avalanche Current vs avalanche pulsewidth, tav, assuming Tj = 150°C and Tstart =25°C (Single Pulse) Avalanche Current (A) Duty Cycle = Single Pulse 0.01 0.05 10 0.10 1 Allowed avalanche Current vs avalanche pulsewidth, tav, assuming  j = 25°C and Tstart = 150°C. 0.1 1.0E-06 1.0E-05 1.0E-04 1.0E-03 1.0E-02 1.0E-01 tav (sec) Fig 14. Typical Avalanche Current vs.Pulsewidth EAR , Avalanche Energy (mJ) 300 Notes on Repetitive Avalanche Curves , Figures 14, 15: (For further info, see AN-1005 at www.irf.com) 1. Avalanche failures assumption: Purely a thermal phenomenon and failure occurs at a temperature far in excess of Tjmax. This is validated for every part type. 2. Safe operation in Avalanche is allowed as long as neither Tjmax nor Iav (max) is exceeded. 3. Equation below based on circuit and waveforms shown in Figures 16a, 16b. 4. PD (ave) = Average power dissipation per single avalanche pulse. 5. BV = Rated breakdown voltage (1.3 factor accounts for voltage increase during avalanche). 6. Iav = Allowable avalanche current. 7. T = Allowable rise in junction temperature, not to exceed Tjmax (assumed as 25°C in Figure 14, 15). tav = Average time in avalanche. D = Duty cycle in avalanche = tav ·f ZthJC(D, tav) = Transient thermal resistance, see Figures 13) TOP Single Pulse BOTTOM 1% Duty Cycle ID = 75A 250 200 150 100 50 0 25 50 75 100 125 150 175 Starting T J , Junction Temperature (°C) Fig 15. Maximum Avalanche Energy vs. Temperature www.irf.com PD (ave) = 1/2 ( 1.3·BV·Iav) = DT/ ZthJC Iav = 2DT/ [1.3·BV·Zth] EAS (AR) = PD (ave)·tav 5 IRFB/S/SL3307PbF 20 VGS(th) Gate threshold Voltage (V) 5.0 4.5 15 4.0 3.0 ID = 150μA 2.5 ID = 1.0mA IRRM (A) 3.5 ID = 250μA 10 ID = 1.0A IF = 30A V = 64V R T = 25°C _____ J TJ = 125°C ---------- 5 2.0 1.5 -75 -50 -25 0 25 50 0 75 100 125 150 175 200 100 200 300 400 500 600 700 800 900 1000 T J , Temperature ( °C ) dif/dt (A/μs) Fig 16. Threshold Voltage vs. Temperature Fig. 17 - Typical Recovery Current vs. dif/dt 400 20 350 300 15 Qrr (nC) IRRM (A) 250 10 200 150 IF = 45A VR = 64V 5 I = 30A F V = 64V R TJ = 25°C _____ 100 T = 25°C _____ J T = 125°C ---------J 50 TJ = 125°C ---------- 0 0 100 200 300 400 500 600 700 800 900 1000 100 200 300 400 500 600 700 800 900 1000 dif/dt (A/μs) dif/dt (A/μs) Fig. 19 - Typical Stored Charge vs. dif/dt Fig. 18 - Typical Recovery Current vs. dif/dt 400 350 300 Qrr (nC) 250 200 150 IF = 45A VR = 64V 100 T = 25°C _____ J T = 125°C ---------J 50 0 100 200 300 400 500 600 700 800 900 1000 dif/dt (A/μs) 6 Fig. 20 - Typical Stored Charge vs. dif/dt www.irf.com IRFB/S/SL3307PbF D.U.T Driver Gate Drive ƒ - ‚ „ - - * D.U.T. ISD Waveform Reverse Recovery Current +  RG dv/dt controlled by RG Driver same type as D.U.T. I SD controlled by Duty Factor "D" D.U.T. - Device Under Test VDD P.W. Period VGS=10V Circuit Layout Considerations  Low Stray Inductance Ground Plane Low Leakage Inductance Current Transformer + D= Period P.W. + + - Body Diode Forward Current di/dt D.U.T. VDS Waveform Diode Recovery dv/dt Re-Applied Voltage Body Diode VDD Forward Drop Inductor Current Inductor Curent ISD Ripple  5% * VGS = 5V for Logic Level Devices Fig 20. Peak Diode Recovery dv/dt Test Circuit for N-Channel HEXFET® Power MOSFETs V(BR)DSS 15V D.U.T RG VGS 20V DRIVER L VDS tp + V - DD IAS tp A 0.01 I AS Fig 21a. Unclamped Inductive Test Circuit LD Fig 21b. Unclamped Inductive Waveforms VDS VDS 90% + VDD - 10% D.U.T VGS VGS Pulse Width < 1μs Duty Factor < 0.1% td(on) Fig 22a. Switching Time Test Circuit tr td(off) tf Fig 22b. Switching Time Waveforms Id Vds Vgs L DUT 0 VCC Vgs(th) 1K Qgs1 Qgs2 Fig 23a. Gate Charge Test Circuit www.irf.com Qgd Qgodr Fig 23b. Gate Charge Waveform 7 IRFB/S/SL3307PbF TO-220AB Package Outline Dimensions are shown in millimeters (inches) TO-220AB Part Marking Information (;$03/( 7+,6,6$1,5) /27&2'( $66(0%/('21:: ,17+($66(0%/